History

Merge tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM driver updates from Arnd Bergmann: "There are a few separately maintained driver subsystems that we merge through the SoC tree, notable changes are: - Memory controller updates, mainly for Tegra and Mediatek SoCs, and clarifications for the memory controller DT bindings - SCMI firmware interface updates, in particular a new transport based on OPTEE and support for atomic operations. - Cleanups to the TEE subsystem, refactoring its memory management For SoC specific drivers without a separate subsystem, changes include - Smaller updates and fixes for TI, AT91/SAMA5, Qualcomm and NXP Layerscape SoCs. - Driver support for Microchip SAMA5D29, Tesla FSD, Renesas RZ/G2L, and Qualcomm SM8450. - Better power management on Mediatek MT81xx, NXP i.MX8MQ and older NVIDIA Tegra chips" * tag 'arm-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (154 commits) ARM: spear: fix typos in comments soc/microchip: fix invalid free in mpfs_sys_controller_delete soc: s4: Add support for power domains controller dt-bindings: power: add Amlogic s4 power domains bindings ARM: at91: add support in soc driver for new SAMA5D29 soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver data dt-bindings: memory: renesas,rpc-if: Document RZ/V2L SoC memory: emif: check the pointer temp in get_device_details() memory: emif: Add check for setup_interrupts dt-bindings: arm: mediatek: mmsys: add support for MT8186 dt-bindings: mediatek: add compatible for MT8186 pwrap soc: mediatek: pwrap: add pwrap driver for MT8186 SoC soc: mediatek: mmsys: add mmsys reset control for MT8186 soc: mediatek: mtk-infracfg: Disable ACP on MT8192 soc: ti: k3-socinfo: Add AM62x JTAG ID soc: mediatek: add MTK mutex support for MT8186 soc: mediatek: mmsys: add mt8186 mmsys routing table soc: mediatek: pm-domains: Add support for mt8186 dt-bindings: power: Add MT8186 power domains soc: mediatek: pm-domains: Add support for mt8195 ...

Linus Torvalds committed 4 years ago

Commit b4bc93b2 parents baaa68a 339ac71124 files · +7628 −1419Browse files

Showing the changes to include (16 of 124 files). Show all

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16 files
  1. include/dt-bindings/clock/fsd-clk.h +150 −0
  2. include/dt-bindings/power/imx8mq-power.h +3 −0
  3. include/dt-bindings/power/meson-s4-power.h +19 −0
  4. include/dt-bindings/power/mt8186-power.h +32 −0
  5. include/dt-bindings/power/mt8195-power.h +46 −0
  6. include/dt-bindings/power/qcom-rpmpd.h +5 −0
  7. include/linux/firmware/imx/svc/rm.h +5 −0
  8. include/linux/qcom_scm.h +13 −3
  9. include/linux/scmi_protocol.h +15 −0
  10. include/linux/soc/mediatek/infracfg.h +133 −0
  11. include/linux/soc/qcom/llcc-qcom.h +7 −2
  12. include/linux/soc/qcom/mdt_loader.h +15 −2
  13. include/linux/soc/ti/ti_sci_protocol.h +1 −1
  14. include/linux/tee_drv.h +31 −107
  15. include/soc/tegra/bpmp-abi.h +1 −1
  16. include/trace/events/scmi.h +28 −0
include/dt-bindings/clock/fsd-clk.h+150−0
@@ -0,0 +1,150 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd.
4 * https://www.samsung.com
5 * Copyright (c) 2017-2022 Tesla, Inc.
6 * https://www.tesla.com
7 *
8 * The constants defined in this header are being used in dts
9 * and fsd platform driver.
10 */
11
12#ifndef _DT_BINDINGS_CLOCK_FSD_H
13#define _DT_BINDINGS_CLOCK_FSD_H
14
15/* CMU */
16#define DOUT_CMU_PLL_SHARED0_DIV4 1
17#define DOUT_CMU_PERIC_SHARED1DIV36 2
18#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3
19#define DOUT_CMU_PERIC_SHARED0DIV20 4
20#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5
21#define DOUT_CMU_PLL_SHARED0_DIV6 6
22#define DOUT_CMU_FSYS0_SHARED1DIV4 7
23#define DOUT_CMU_FSYS0_SHARED0DIV4 8
24#define DOUT_CMU_FSYS1_SHARED0DIV8 9
25#define DOUT_CMU_FSYS1_SHARED0DIV4 10
26#define CMU_CPUCL_SWITCH_GATE 11
27#define DOUT_CMU_IMEM_TCUCLK 12
28#define DOUT_CMU_IMEM_ACLK 13
29#define DOUT_CMU_IMEM_DMACLK 14
30#define GAT_CMU_FSYS0_SHARED0DIV4 15
31#define CMU_NR_CLK 16
32
33/* PERIC */
34#define PERIC_SCLK_UART0 1
35#define PERIC_PCLK_UART0 2
36#define PERIC_SCLK_UART1 3
37#define PERIC_PCLK_UART1 4
38#define PERIC_DMA0_IPCLKPORT_ACLK 5
39#define PERIC_DMA1_IPCLKPORT_ACLK 6
40#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7
41#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8
42#define PERIC_PCLK_SPI0 9
43#define PERIC_SCLK_SPI0 10
44#define PERIC_PCLK_SPI1 11
45#define PERIC_SCLK_SPI1 12
46#define PERIC_PCLK_SPI2 13
47#define PERIC_SCLK_SPI2 14
48#define PERIC_PCLK_TDM0 15
49#define PERIC_PCLK_HSI2C0 16
50#define PERIC_PCLK_HSI2C1 17
51#define PERIC_PCLK_HSI2C2 18
52#define PERIC_PCLK_HSI2C3 19
53#define PERIC_PCLK_HSI2C4 20
54#define PERIC_PCLK_HSI2C5 21
55#define PERIC_PCLK_HSI2C6 22
56#define PERIC_PCLK_HSI2C7 23
57#define PERIC_MCAN0_IPCLKPORT_CCLK 24
58#define PERIC_MCAN0_IPCLKPORT_PCLK 25
59#define PERIC_MCAN1_IPCLKPORT_CCLK 26
60#define PERIC_MCAN1_IPCLKPORT_PCLK 27
61#define PERIC_MCAN2_IPCLKPORT_CCLK 28
62#define PERIC_MCAN2_IPCLKPORT_PCLK 29
63#define PERIC_MCAN3_IPCLKPORT_CCLK 30
64#define PERIC_MCAN3_IPCLKPORT_PCLK 31
65#define PERIC_PCLK_ADCIF 32
66#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33
67#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34
68#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35
69#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36
70#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37
71#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38
72#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39
73#define PERIC_HCLK_TDM0 40
74#define PERIC_PCLK_TDM1 41
75#define PERIC_HCLK_TDM1 42
76#define PERIC_EQOS_PHYRXCLK_MUX 43
77#define PERIC_EQOS_PHYRXCLK 44
78#define PERIC_DOUT_RGMII_CLK 45
79#define PERIC_NR_CLK 46
80
81/* FSYS0 */
82#define UFS0_MPHY_REFCLK_IXTAL24 1
83#define UFS0_MPHY_REFCLK_IXTAL26 2
84#define UFS1_MPHY_REFCLK_IXTAL24 3
85#define UFS1_MPHY_REFCLK_IXTAL26 4
86#define UFS0_TOP0_HCLK_BUS 5
87#define UFS0_TOP0_ACLK 6
88#define UFS0_TOP0_CLK_UNIPRO 7
89#define UFS0_TOP0_FMP_CLK 8
90#define UFS1_TOP1_HCLK_BUS 9
91#define UFS1_TOP1_ACLK 10
92#define UFS1_TOP1_CLK_UNIPRO 11
93#define UFS1_TOP1_FMP_CLK 12
94#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13
95#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14
96#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15
97#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16
98#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17
99#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18
100#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19
101#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20
102#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21
103#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22
104#define FSYS0_NR_CLK 23
105
106/* FSYS1 */
107#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1
108#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2
109#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3
110#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4
111#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5
112#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6
113#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7
114#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8
115#define FSYS1_NR_CLK 9
116
117/* IMEM */
118#define IMEM_DMA0_IPCLKPORT_ACLK 1
119#define IMEM_DMA1_IPCLKPORT_ACLK 2
120#define IMEM_WDT0_IPCLKPORT_PCLK 3
121#define IMEM_WDT1_IPCLKPORT_PCLK 4
122#define IMEM_WDT2_IPCLKPORT_PCLK 5
123#define IMEM_MCT_PCLK 6
124#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7
125#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8
126#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9
127#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10
128#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11
129#define IMEM_NR_CLK 12
130
131/* MFC */
132#define MFC_MFC_IPCLKPORT_ACLK 1
133#define MFC_NR_CLK 2
134
135/* CAM_CSI */
136#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1
137#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2
138#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3
139#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4
140#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5
141#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6
142#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7
143#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8
144#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9
145#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
146#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
147#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
148#define CAM_CSI_NR_CLK 13
149
150#endif /*_DT_BINDINGS_CLOCK_FSD_H */
include/dt-bindings/power/imx8mq-power.h+3−0
@@ -18,4 +18,7 @@ · 17 unmodified lines
18#define IMX8M_POWER_DOMAIN_MIPI_CSI2 918#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9
19#define IMX8M_POWER_DOMAIN_PCIE2 1019#define IMX8M_POWER_DOMAIN_PCIE2 10
20 20
21#define IMX8MQ_VPUBLK_PD_G1 0
22#define IMX8MQ_VPUBLK_PD_G2 1
23
21#endif24#endif
include/dt-bindings/power/meson-s4-power.h+19−0
@@ -0,0 +1,19 @@
1/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2/*
3 * Copyright (c) 2021 Amlogic, Inc.
4 * Author: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
5 */
6
7#ifndef _DT_BINDINGS_MESON_S4_POWER_H
8#define _DT_BINDINGS_MESON_S4_POWER_H
9
10#define PWRC_S4_DOS_HEVC_ID 0
11#define PWRC_S4_DOS_VDEC_ID 1
12#define PWRC_S4_VPU_HDMI_ID 2
13#define PWRC_S4_USB_COMB_ID 3
14#define PWRC_S4_GE2D_ID 4
15#define PWRC_S4_ETH_ID 5
16#define PWRC_S4_DEMOD_ID 6
17#define PWRC_S4_AUDIO_ID 7
18
19#endif
include/dt-bindings/power/mt8186-power.h+32−0
@@ -0,0 +1,32 @@
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_POWER_MT8186_POWER_H
8#define _DT_BINDINGS_POWER_MT8186_POWER_H
9
10#define MT8186_POWER_DOMAIN_MFG0 0
11#define MT8186_POWER_DOMAIN_MFG1 1
12#define MT8186_POWER_DOMAIN_MFG2 2
13#define MT8186_POWER_DOMAIN_MFG3 3
14#define MT8186_POWER_DOMAIN_SSUSB 4
15#define MT8186_POWER_DOMAIN_SSUSB_P1 5
16#define MT8186_POWER_DOMAIN_DIS 6
17#define MT8186_POWER_DOMAIN_IMG 7
18#define MT8186_POWER_DOMAIN_IMG2 8
19#define MT8186_POWER_DOMAIN_IPE 9
20#define MT8186_POWER_DOMAIN_CAM 10
21#define MT8186_POWER_DOMAIN_CAM_RAWA 11
22#define MT8186_POWER_DOMAIN_CAM_RAWB 12
23#define MT8186_POWER_DOMAIN_VENC 13
24#define MT8186_POWER_DOMAIN_VDEC 14
25#define MT8186_POWER_DOMAIN_WPE 15
26#define MT8186_POWER_DOMAIN_CONN_ON 16
27#define MT8186_POWER_DOMAIN_CSIRX_TOP 17
28#define MT8186_POWER_DOMAIN_ADSP_AO 18
29#define MT8186_POWER_DOMAIN_ADSP_INFRA 19
30#define MT8186_POWER_DOMAIN_ADSP_TOP 20
31
32#endif /* _DT_BINDINGS_POWER_MT8186_POWER_H */
include/dt-bindings/power/mt8195-power.h+46−0
@@ -0,0 +1,46 @@
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Copyright (c) 2021 MediaTek Inc.
4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H
8#define _DT_BINDINGS_POWER_MT8195_POWER_H
9
10#define MT8195_POWER_DOMAIN_PCIE_MAC_P0 0
11#define MT8195_POWER_DOMAIN_PCIE_MAC_P1 1
12#define MT8195_POWER_DOMAIN_PCIE_PHY 2
13#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 3
14#define MT8195_POWER_DOMAIN_CSI_RX_TOP 4
15#define MT8195_POWER_DOMAIN_ETHER 5
16#define MT8195_POWER_DOMAIN_ADSP 6
17#define MT8195_POWER_DOMAIN_AUDIO 7
18#define MT8195_POWER_DOMAIN_MFG0 8
19#define MT8195_POWER_DOMAIN_MFG1 9
20#define MT8195_POWER_DOMAIN_MFG2 10
21#define MT8195_POWER_DOMAIN_MFG3 11
22#define MT8195_POWER_DOMAIN_MFG4 12
23#define MT8195_POWER_DOMAIN_MFG5 13
24#define MT8195_POWER_DOMAIN_MFG6 14
25#define MT8195_POWER_DOMAIN_VPPSYS0 15
26#define MT8195_POWER_DOMAIN_VDOSYS0 16
27#define MT8195_POWER_DOMAIN_VPPSYS1 17
28#define MT8195_POWER_DOMAIN_VDOSYS1 18
29#define MT8195_POWER_DOMAIN_DP_TX 19
30#define MT8195_POWER_DOMAIN_EPD_TX 20
31#define MT8195_POWER_DOMAIN_HDMI_TX 21
32#define MT8195_POWER_DOMAIN_WPESYS 22
33#define MT8195_POWER_DOMAIN_VDEC0 23
34#define MT8195_POWER_DOMAIN_VDEC1 24
35#define MT8195_POWER_DOMAIN_VDEC2 25
36#define MT8195_POWER_DOMAIN_VENC 26
37#define MT8195_POWER_DOMAIN_VENC_CORE1 27
38#define MT8195_POWER_DOMAIN_IMG 28
39#define MT8195_POWER_DOMAIN_DIP 29
40#define MT8195_POWER_DOMAIN_IPE 30
41#define MT8195_POWER_DOMAIN_CAM 31
42#define MT8195_POWER_DOMAIN_CAM_RAWA 32
43#define MT8195_POWER_DOMAIN_CAM_RAWB 33
44#define MT8195_POWER_DOMAIN_CAM_MRAW 34
45
46#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */
include/dt-bindings/power/qcom-rpmpd.h+5−0
@@ -139,6 +139,11 @@ · 138 unmodified lines
139#define MDM9607_VDDMX_AO 4139#define MDM9607_VDDMX_AO 4
140#define MDM9607_VDDMX_VFL 5140#define MDM9607_VDDMX_VFL 5
141 141
142/* MSM8226 Power Domain Indexes */
143#define MSM8226_VDDCX 0
144#define MSM8226_VDDCX_AO 1
145#define MSM8226_VDDCX_VFC 2
146
142/* MSM8939 Power Domains */147/* MSM8939 Power Domains */
143#define MSM8939_VDDMDCX 0148#define MSM8939_VDDMDCX 0
144#define MSM8939_VDDMDCX_AO 1149#define MSM8939_VDDMDCX_AO 1
include/linux/firmware/imx/svc/rm.h+5−0
@@ -59,11 +59,16 @@ enum imx_sc_rm_func { · 58 unmodified lines
59 59
60#if IS_ENABLED(CONFIG_IMX_SCU)60#if IS_ENABLED(CONFIG_IMX_SCU)
61bool imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource);61bool imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource);
62int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt);
62#else63#else
63static inline bool64static inline bool
64imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource)65imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource)
65{66{
66 return true;67 return true;
67}68}
69static inline int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt)
70{
71 return -EOPNOTSUPP;
72}
68#endif73#endif
69#endif74#endif
include/linux/qcom_scm.h+13−3
@@ -63,13 +63,21 @@ enum qcom_scm_ice_cipher { · 62 unmodified lines
63 63
64extern bool qcom_scm_is_available(void);64extern bool qcom_scm_is_available(void);
65 65
66extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);66extern int qcom_scm_set_cold_boot_addr(void *entry);
67extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);67extern int qcom_scm_set_warm_boot_addr(void *entry);
68extern void qcom_scm_cpu_power_down(u32 flags);68extern void qcom_scm_cpu_power_down(u32 flags);
69extern int qcom_scm_set_remote_state(u32 state, u32 id);69extern int qcom_scm_set_remote_state(u32 state, u32 id);
70 70
71struct qcom_scm_pas_metadata {
72 void *ptr;
73 dma_addr_t phys;
74 ssize_t size;
75};
76
71extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,77extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
72 size_t size);78 size_t size,
79 struct qcom_scm_pas_metadata *ctx);
80void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
73extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,81extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
74 phys_addr_t size);82 phys_addr_t size);
75extern int qcom_scm_pas_auth_and_reset(u32 peripheral);83extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
@@ -83,6 +91,7 @@ extern bool qcom_scm_restore_sec_cfg_available(void); · 7 unmodified lines
83extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);91extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
84extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);92extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
85extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);93extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
94extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
86extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,95extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
87 u32 cp_nonpixel_start,96 u32 cp_nonpixel_start,
88 u32 cp_nonpixel_size);97 u32 cp_nonpixel_size);
@@ -107,6 +116,7 @@ extern bool qcom_scm_hdcp_available(void); · 18 unmodified lines
107extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,116extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
108 u32 *resp);117 u32 *resp);
109 118
119extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
110extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);120extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
111 121
112extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,122extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
include/linux/scmi_protocol.h+15−0
@@ -42,6 +42,7 @@ struct scmi_revision_info { · 41 unmodified lines
42 42
43struct scmi_clock_info {43struct scmi_clock_info {
44 char name[SCMI_MAX_STR_SIZE];44 char name[SCMI_MAX_STR_SIZE];
45 unsigned int enable_latency;
45 bool rate_discrete;46 bool rate_discrete;
46 union {47 union {
47 struct {48 struct {
@@ -82,6 +83,9 @@ struct scmi_clk_proto_ops { · 34 unmodified lines
82 u64 rate);83 u64 rate);
83 int (*enable)(const struct scmi_protocol_handle *ph, u32 clk_id);84 int (*enable)(const struct scmi_protocol_handle *ph, u32 clk_id);
84 int (*disable)(const struct scmi_protocol_handle *ph, u32 clk_id);85 int (*disable)(const struct scmi_protocol_handle *ph, u32 clk_id);
86 int (*enable_atomic)(const struct scmi_protocol_handle *ph, u32 clk_id);
87 int (*disable_atomic)(const struct scmi_protocol_handle *ph,
88 u32 clk_id);
85};89};
86 90
87/**91/**
@@ -612,6 +616,15 @@ struct scmi_notify_ops { · 524 unmodified lines
612 * @devm_protocol_get: devres managed method to acquire a protocol and get specific616 * @devm_protocol_get: devres managed method to acquire a protocol and get specific
613 * operations and a dedicated protocol handler617 * operations and a dedicated protocol handler
614 * @devm_protocol_put: devres managed method to release a protocol618 * @devm_protocol_put: devres managed method to release a protocol
619 * @is_transport_atomic: method to check if the underlying transport for this
620 * instance handle is configured to support atomic
621 * transactions for commands.
622 * Some users of the SCMI stack in the upper layers could
623 * be interested to know if they can assume SCMI
624 * command transactions associated to this handle will
625 * never sleep and act accordingly.
626 * An optional atomic threshold value could be returned
627 * where configured.
615 * @notify_ops: pointer to set of notifications related operations628 * @notify_ops: pointer to set of notifications related operations
616 */629 */
617struct scmi_handle {630struct scmi_handle {
@@ -622,6 +635,8 @@ struct scmi_handle { · 4 unmodified lines
622 (*devm_protocol_get)(struct scmi_device *sdev, u8 proto,635 (*devm_protocol_get)(struct scmi_device *sdev, u8 proto,
623 struct scmi_protocol_handle **ph);636 struct scmi_protocol_handle **ph);
624 void (*devm_protocol_put)(struct scmi_device *sdev, u8 proto);637 void (*devm_protocol_put)(struct scmi_device *sdev, u8 proto);
638 bool (*is_transport_atomic)(const struct scmi_handle *handle,
639 unsigned int *atomic_threshold);
625 640
626 const struct scmi_notify_ops *notify_ops;641 const struct scmi_notify_ops *notify_ops;
627};642};
include/linux/soc/mediatek/infracfg.h+133−0
@@ -2,6 +2,88 @@ · 1 unmodified line
2#ifndef __SOC_MEDIATEK_INFRACFG_H2#ifndef __SOC_MEDIATEK_INFRACFG_H
3#define __SOC_MEDIATEK_INFRACFG_H3#define __SOC_MEDIATEK_INFRACFG_H
4 4
5#define MT8195_TOP_AXI_PROT_EN_STA1 0x228
6#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258
7#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0
8#define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4
9#define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8
10#define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac
11#define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4
12#define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8
13#define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec
14#define MT8195_TOP_AXI_PROT_EN_2_SET 0x714
15#define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718
16#define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724
17#define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84
18#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88
19#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90
20#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4
21#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8
22#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0
23#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8
24#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc
25#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4
26#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc
27#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0
28#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8
29#define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc
30#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0
31#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8
32
33#define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6)
34#define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10)
35#define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11)
36#define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, 21)
37#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23)
38#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, 19)
39#define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22)
40#define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0)
41#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5)
42#define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7)
43#define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11))
44#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14))
45#define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2) | BIT(4))
46#define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1)
47#define MT8195_TOP_AXI_PROT_EN_MM_IMG BIT(3)
48#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 GENMASK(21, 17)
49#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5)
50#define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) | BIT(11))
51#define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10) | BIT(12))
52#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13)
53#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14)
54#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22)
55#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23)
56#define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24)
57#define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25)
58#define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26)
59#define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27)
60#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28)
61#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29)
62#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, 30)
63#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(1, 0) | BIT(4) | BIT(11))
64#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2)
65#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) | BIT(15))
66#define MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) | BIT(17))
67#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, 6) | BIT(18))
68#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 GENMASK(9, 8)
69#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10)
70#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12)
71#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13)
72#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14)
73#define MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16)
74#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21)
75#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22)
76#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, 23)
77#define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1)
78#define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2)
79#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11) | BIT(28))
80#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12) | BIT(29))
81#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13)
82#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14)
83#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | BIT(19))
84#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20)
85#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21)
86
5#define MT8192_TOP_AXI_PROT_EN_STA1 0x22887#define MT8192_TOP_AXI_PROT_EN_STA1 0x228
6#define MT8192_TOP_AXI_PROT_EN_1_STA1 0x25888#define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258
7#define MT8192_TOP_AXI_PROT_EN_SET 0x2a089#define MT8192_TOP_AXI_PROT_EN_SET 0x2a0
@@ -58,6 +140,54 @@ · 50 unmodified lines
58#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)140#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
59#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)141#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
60 142
143#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
144#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
145#define MT8186_TOP_AXI_PROT_EN_STA (0x228)
146#define MT8186_TOP_AXI_PROT_EN_1_SET (0x2A8)
147#define MT8186_TOP_AXI_PROT_EN_1_CLR (0x2AC)
148#define MT8186_TOP_AXI_PROT_EN_1_STA (0x258)
149#define MT8186_TOP_AXI_PROT_EN_2_SET (0x2B0)
150#define MT8186_TOP_AXI_PROT_EN_2_CLR (0x2B4)
151#define MT8186_TOP_AXI_PROT_EN_2_STA (0x26C)
152#define MT8186_TOP_AXI_PROT_EN_3_SET (0x2B8)
153#define MT8186_TOP_AXI_PROT_EN_3_CLR (0x2BC)
154#define MT8186_TOP_AXI_PROT_EN_3_STA (0x2C8)
155
156/* MFG1 */
157#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1 (GENMASK(28, 27))
158#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP2 (GENMASK(22, 21))
159#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP3 (BIT(25))
160#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4 (BIT(29))
161/* DIS */
162#define MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1 (GENMASK(12, 11))
163#define MT8186_TOP_AXI_PROT_EN_DIS_STEP2 (GENMASK(2, 1) | GENMASK(11, 10))
164/* IMG */
165#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1 (BIT(23))
166#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2 (BIT(15))
167/* IPE */
168#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1 (BIT(24))
169#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2 (BIT(16))
170/* CAM */
171#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1 (GENMASK(22, 21))
172#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2 (GENMASK(14, 13))
173/* VENC */
174#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1 (BIT(31))
175#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2 (BIT(19))
176/* VDEC */
177#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1 (BIT(30))
178#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2 (BIT(17))
179/* WPE */
180#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1 (BIT(17))
181#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2 (BIT(16))
182/* CONN_ON */
183#define MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1 (BIT(18))
184#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2 (BIT(14))
185#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3 (BIT(13))
186#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4 (BIT(16))
187/* ADSP_TOP */
188#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1 (GENMASK(12, 11))
189#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2 (GENMASK(1, 0))
190
61#define MT8183_TOP_AXI_PROT_EN_STA1 0x228191#define MT8183_TOP_AXI_PROT_EN_STA1 0x228
62#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258192#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258
63#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0193#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0
@@ -147,6 +277,9 @@ · 83 unmodified lines
147#define INFRA_TOPAXI_PROTECTEN_SET 0x0260277#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
148#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264278#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
149 279
280#define MT8192_INFRA_CTRL 0x290
281#define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9)
282
150#define REG_INFRA_MISC 0xf00283#define REG_INFRA_MISC 0xf00
151#define F_DDR_4GB_SUPPORT_EN BIT(13)284#define F_DDR_4GB_SUPPORT_EN BIT(13)
152 285
include/linux/soc/qcom/llcc-qcom.h+7−2
@@ -35,7 +35,12 @@ · 34 unmodified lines
35#define LLCC_WRCACHE 3135#define LLCC_WRCACHE 31
36#define LLCC_CVPFW 3236#define LLCC_CVPFW 32
37#define LLCC_CPUSS1 3337#define LLCC_CPUSS1 33
38#define LLCC_CAMEXP0 34
39#define LLCC_CPUMTE 35
38#define LLCC_CPUHWT 3640#define LLCC_CPUHWT 36
41#define LLCC_MDMCLAD2 37
42#define LLCC_CAMEXP1 38
43#define LLCC_AENPU 45
39 44
40/**45/**
41 * struct llcc_slice_desc - Cache slice descriptor46 * struct llcc_slice_desc - Cache slice descriptor
@@ -83,7 +88,7 @@ struct llcc_edac_reg_data { · 41 unmodified lines
83 * @bitmap: Bit map to track the active slice ids88 * @bitmap: Bit map to track the active slice ids
84 * @offsets: Pointer to the bank offsets array89 * @offsets: Pointer to the bank offsets array
85 * @ecc_irq: interrupt for llcc cache error detection and reporting90 * @ecc_irq: interrupt for llcc cache error detection and reporting
86 * @major_version: Indicates the LLCC major version91 * @version: Indicates the LLCC version
87 */92 */
88struct llcc_drv_data {93struct llcc_drv_data {
89 struct regmap *regmap;94 struct regmap *regmap;
@@ -96,7 +101,7 @@ struct llcc_drv_data { · 6 unmodified lines
96 unsigned long *bitmap;101 unsigned long *bitmap;
97 u32 *offsets;102 u32 *offsets;
98 int ecc_irq;103 int ecc_irq;
99 u32 major_version;104 u32 version;
100};105};
101 106
102#if IS_ENABLED(CONFIG_QCOM_LLCC)107#if IS_ENABLED(CONFIG_QCOM_LLCC)
include/linux/soc/qcom/mdt_loader.h+15−2
@@ -10,10 +10,14 @@ · 9 unmodified lines
10 10
11struct device;11struct device;
12struct firmware;12struct firmware;
13struct qcom_scm_pas_metadata;
13 14
14#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER)15#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER)
15 16
16ssize_t qcom_mdt_get_size(const struct firmware *fw);17ssize_t qcom_mdt_get_size(const struct firmware *fw);
18int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
19 const char *fw_name, int pas_id, phys_addr_t mem_phys,
20 struct qcom_scm_pas_metadata *pas_metadata_ctx);
17int qcom_mdt_load(struct device *dev, const struct firmware *fw,21int qcom_mdt_load(struct device *dev, const struct firmware *fw,
18 const char *fw_name, int pas_id, void *mem_region,22 const char *fw_name, int pas_id, void *mem_region,
19 phys_addr_t mem_phys, size_t mem_size,23 phys_addr_t mem_phys, size_t mem_size,
@@ -23,7 +27,8 @@ int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw, · 3 unmodified lines
23 const char *fw_name, int pas_id, void *mem_region,27 const char *fw_name, int pas_id, void *mem_region,
24 phys_addr_t mem_phys, size_t mem_size,28 phys_addr_t mem_phys, size_t mem_size,
25 phys_addr_t *reloc_base);29 phys_addr_t *reloc_base);
26void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len);30void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len,
31 const char *fw_name, struct device *dev);
27 32
28#else /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */33#else /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */
29 34
@@ -32,6 +37,13 @@ static inline ssize_t qcom_mdt_get_size(const struct firmware *fw) · 2 unmodified lines
32 return -ENODEV;37 return -ENODEV;
33}38}
34 39
40static inline int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
41 const char *fw_name, int pas_id, phys_addr_t mem_phys,
42 struct qcom_scm_pas_metadata *pas_metadata_ctx)
43{
44 return -ENODEV;
45}
46
35static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw,47static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw,
36 const char *fw_name, int pas_id,48 const char *fw_name, int pas_id,
37 void *mem_region, phys_addr_t mem_phys,49 void *mem_region, phys_addr_t mem_phys,
@@ -51,7 +63,8 @@ static inline int qcom_mdt_load_no_init(struct device *dev, · 13 unmodified lines
51}63}
52 64
53static inline void *qcom_mdt_read_metadata(const struct firmware *fw,65static inline void *qcom_mdt_read_metadata(const struct firmware *fw,
54 size_t *data_len)66 size_t *data_len, const char *fw_name,
67 struct device *dev)
55{68{
56 return ERR_PTR(-ENODEV);69 return ERR_PTR(-ENODEV);
57}70}
include/linux/soc/ti/ti_sci_protocol.h+1−1
@@ -645,7 +645,7 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle, · 644 unmodified lines
645 645
646static inline struct ti_sci_resource *646static inline struct ti_sci_resource *
647devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,647devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
648 u32 dev_id, u32 sub_type);648 u32 dev_id, u32 sub_type)
649{649{
650 return ERR_PTR(-EINVAL);650 return ERR_PTR(-EINVAL);
651}651}
include/linux/tee_drv.h+31−107
@@ -1,6 +1,6 @@
1/* SPDX-License-Identifier: GPL-2.0-only */1/* SPDX-License-Identifier: GPL-2.0-only */
2/*2/*
3 * Copyright (c) 2015-2016, Linaro Limited3 * Copyright (c) 2015-2022 Linaro Limited
4 */4 */
5 5
6#ifndef __TEE_DRV_H6#ifndef __TEE_DRV_H
@@ -20,14 +20,11 @@ · 13 unmodified lines
20 * specific TEE driver.20 * specific TEE driver.
21 */21 */
22 22
23#define TEE_SHM_MAPPED BIT(0) /* Memory mapped by the kernel */23#define TEE_SHM_DYNAMIC BIT(0) /* Dynamic shared memory registered */
24#define TEE_SHM_DMA_BUF BIT(1) /* Memory with dma-buf handle */24 /* in secure world */
25#define TEE_SHM_EXT_DMA_BUF BIT(2) /* Memory with dma-buf handle */25#define TEE_SHM_USER_MAPPED BIT(1) /* Memory mapped in user space */
26#define TEE_SHM_REGISTER BIT(3) /* Memory registered in secure world */26#define TEE_SHM_POOL BIT(2) /* Memory allocated from pool */
27#define TEE_SHM_USER_MAPPED BIT(4) /* Memory mapped in user space */27#define TEE_SHM_PRIV BIT(3) /* Memory private to TEE driver */
28#define TEE_SHM_POOL BIT(5) /* Memory allocated from pool */
29#define TEE_SHM_KERNEL_MAPPED BIT(6) /* Memory mapped in kernel space */
30#define TEE_SHM_PRIV BIT(7) /* Memory private to TEE driver */
31 28
32struct device;29struct device;
33struct tee_device;30struct tee_device;
@@ -221,92 +218,39 @@ struct tee_shm { · 187 unmodified lines
221};218};
222 219
223/**220/**
224 * struct tee_shm_pool_mgr - shared memory manager221 * struct tee_shm_pool - shared memory pool
225 * @ops: operations222 * @ops: operations
226 * @private_data: private data for the shared memory manager223 * @private_data: private data for the shared memory manager
227 */224 */
228struct tee_shm_pool_mgr {225struct tee_shm_pool {
229 const struct tee_shm_pool_mgr_ops *ops;226 const struct tee_shm_pool_ops *ops;
230 void *private_data;227 void *private_data;
231};228};
232 229
233/**230/**
234 * struct tee_shm_pool_mgr_ops - shared memory pool manager operations231 * struct tee_shm_pool_ops - shared memory pool operations
235 * @alloc: called when allocating shared memory232 * @alloc: called when allocating shared memory
236 * @free: called when freeing shared memory233 * @free: called when freeing shared memory
237 * @destroy_poolmgr: called when destroying the pool manager234 * @destroy_pool: called when destroying the pool
238 */235 */
239struct tee_shm_pool_mgr_ops {236struct tee_shm_pool_ops {
240 int (*alloc)(struct tee_shm_pool_mgr *poolmgr, struct tee_shm *shm,237 int (*alloc)(struct tee_shm_pool *pool, struct tee_shm *shm,
241 size_t size);238 size_t size, size_t align);
242 void (*free)(struct tee_shm_pool_mgr *poolmgr, struct tee_shm *shm);239 void (*free)(struct tee_shm_pool *pool, struct tee_shm *shm);
243 void (*destroy_poolmgr)(struct tee_shm_pool_mgr *poolmgr);240 void (*destroy_pool)(struct tee_shm_pool *pool);
244};241};
245 242
246/**
247 * tee_shm_pool_alloc() - Create a shared memory pool from shm managers
248 * @priv_mgr: manager for driver private shared memory allocations
249 * @dmabuf_mgr: manager for dma-buf shared memory allocations
250 *
251 * Allocation with the flag TEE_SHM_DMA_BUF set will use the range supplied
252 * in @dmabuf, others will use the range provided by @priv.
253 *
254 * @returns pointer to a 'struct tee_shm_pool' or an ERR_PTR on failure.
255 */
256struct tee_shm_pool *tee_shm_pool_alloc(struct tee_shm_pool_mgr *priv_mgr,
257 struct tee_shm_pool_mgr *dmabuf_mgr);
258
259/*243/*
260 * tee_shm_pool_mgr_alloc_res_mem() - Create a shm manager for reserved244 * tee_shm_pool_alloc_res_mem() - Create a shm manager for reserved memory
261 * memory
262 * @vaddr: Virtual address of start of pool245 * @vaddr: Virtual address of start of pool
263 * @paddr: Physical address of start of pool246 * @paddr: Physical address of start of pool
264 * @size: Size in bytes of the pool247 * @size: Size in bytes of the pool
265 *248 *
266 * @returns pointer to a 'struct tee_shm_pool_mgr' or an ERR_PTR on failure.
267 */
268struct tee_shm_pool_mgr *tee_shm_pool_mgr_alloc_res_mem(unsigned long vaddr,
269 phys_addr_t paddr,
270 size_t size,
271 int min_alloc_order);
272
273/**
274 * tee_shm_pool_mgr_destroy() - Free a shared memory manager
275 */
276static inline void tee_shm_pool_mgr_destroy(struct tee_shm_pool_mgr *poolm)
277{
278 poolm->ops->destroy_poolmgr(poolm);
279}
280
281/**
282 * struct tee_shm_pool_mem_info - holds information needed to create a shared
283 * memory pool
284 * @vaddr: Virtual address of start of pool
285 * @paddr: Physical address of start of pool
286 * @size: Size in bytes of the pool
287 */
288struct tee_shm_pool_mem_info {
289 unsigned long vaddr;
290 phys_addr_t paddr;
291 size_t size;
292};
293
294/**
295 * tee_shm_pool_alloc_res_mem() - Create a shared memory pool from reserved
296 * memory range
297 * @priv_info: Information for driver private shared memory pool
298 * @dmabuf_info: Information for dma-buf shared memory pool
299 *
300 * Start and end of pools will must be page aligned.
301 *
302 * Allocation with the flag TEE_SHM_DMA_BUF set will use the range supplied
303 * in @dmabuf, others will use the range provided by @priv.
304 *
305 * @returns pointer to a 'struct tee_shm_pool' or an ERR_PTR on failure.249 * @returns pointer to a 'struct tee_shm_pool' or an ERR_PTR on failure.
306 */250 */
307struct tee_shm_pool *251struct tee_shm_pool *tee_shm_pool_alloc_res_mem(unsigned long vaddr,
308tee_shm_pool_alloc_res_mem(struct tee_shm_pool_mem_info *priv_info,252 phys_addr_t paddr, size_t size,
309 struct tee_shm_pool_mem_info *dmabuf_info);253 int min_alloc_order);
310 254
311/**255/**
312 * tee_shm_pool_free() - Free a shared memory pool256 * tee_shm_pool_free() - Free a shared memory pool
@@ -315,7 +259,10 @@ tee_shm_pool_alloc_res_mem(struct tee_shm_pool_mem_info *priv_info, · 2 unmodified lines
315 * The must be no remaining shared memory allocated from this pool when259 * The must be no remaining shared memory allocated from this pool when
316 * this function is called.260 * this function is called.
317 */261 */
318void tee_shm_pool_free(struct tee_shm_pool *pool);262static inline void tee_shm_pool_free(struct tee_shm_pool *pool)
263{
264 pool->ops->destroy_pool(pool);
265}
319 266
320/**267/**
321 * tee_get_drvdata() - Return driver_data pointer268 * tee_get_drvdata() - Return driver_data pointer
@@ -323,43 +270,20 @@ void tee_shm_pool_free(struct tee_shm_pool *pool); · 1 unmodified line
323 */270 */
324void *tee_get_drvdata(struct tee_device *teedev);271void *tee_get_drvdata(struct tee_device *teedev);
325 272
326/**273struct tee_shm *tee_shm_alloc_priv_buf(struct tee_context *ctx, size_t size);
327 * tee_shm_alloc() - Allocate shared memory
328 * @ctx: Context that allocates the shared memory
329 * @size: Requested size of shared memory
330 * @flags: Flags setting properties for the requested shared memory.
331 *
332 * Memory allocated as global shared memory is automatically freed when the
333 * TEE file pointer is closed. The @flags field uses the bits defined by
334 * TEE_SHM_* above. TEE_SHM_MAPPED must currently always be set. If
335 * TEE_SHM_DMA_BUF global shared memory will be allocated and associated
336 * with a dma-buf handle, else driver private memory.
337 *
338 * @returns a pointer to 'struct tee_shm'
339 */
340struct tee_shm *tee_shm_alloc(struct tee_context *ctx, size_t size, u32 flags);
341struct tee_shm *tee_shm_alloc_kernel_buf(struct tee_context *ctx, size_t size);274struct tee_shm *tee_shm_alloc_kernel_buf(struct tee_context *ctx, size_t size);
342 275
343/**276struct tee_shm *tee_shm_register_kernel_buf(struct tee_context *ctx,
344 * tee_shm_register() - Register shared memory buffer277 void *addr, size_t length);
345 * @ctx: Context that registers the shared memory
346 * @addr: Address is userspace of the shared buffer
347 * @length: Length of the shared buffer
348 * @flags: Flags setting properties for the requested shared memory.
349 *
350 * @returns a pointer to 'struct tee_shm'
351 */
352struct tee_shm *tee_shm_register(struct tee_context *ctx, unsigned long addr,
353 size_t length, u32 flags);
354 278
355/**279/**
356 * tee_shm_is_registered() - Check if shared memory object in registered in TEE280 * tee_shm_is_dynamic() - Check if shared memory object is of the dynamic kind
357 * @shm: Shared memory handle281 * @shm: Shared memory handle
358 * @returns true if object is registered in TEE282 * @returns true if object is dynamic shared memory
359 */283 */
360static inline bool tee_shm_is_registered(struct tee_shm *shm)284static inline bool tee_shm_is_dynamic(struct tee_shm *shm)
361{285{
362 return shm && (shm->flags & TEE_SHM_REGISTER);286 return shm && (shm->flags & TEE_SHM_DYNAMIC);
363}287}
364 288
365/**289/**
include/soc/tegra/bpmp-abi.h+1−1
@@ -931,7 +931,7 @@ enum mrq_reset_commands { · 930 unmodified lines
931 * @brief Request with MRQ_RESET931 * @brief Request with MRQ_RESET
932 *932 *
933 * Used by the sender of an #MRQ_RESET message to request BPMP to933 * Used by the sender of an #MRQ_RESET message to request BPMP to
934 * assert or or deassert a given reset line.934 * assert or deassert a given reset line.
935 */935 */
936struct mrq_reset_request {936struct mrq_reset_request {
937 /** @brief Reset action to perform (@ref mrq_reset_commands) */937 /** @brief Reset action to perform (@ref mrq_reset_commands) */
include/trace/events/scmi.h+28−0
@@ -33,6 +33,34 @@ TRACE_EVENT(scmi_xfer_begin, · 32 unmodified lines
33 __entry->seq, __entry->poll)33 __entry->seq, __entry->poll)
34);34);
35 35
36TRACE_EVENT(scmi_xfer_response_wait,
37 TP_PROTO(int transfer_id, u8 msg_id, u8 protocol_id, u16 seq,
38 u32 timeout, bool poll),
39 TP_ARGS(transfer_id, msg_id, protocol_id, seq, timeout, poll),
40
41 TP_STRUCT__entry(
42 __field(int, transfer_id)
43 __field(u8, msg_id)
44 __field(u8, protocol_id)
45 __field(u16, seq)
46 __field(u32, timeout)
47 __field(bool, poll)
48 ),
49
50 TP_fast_assign(
51 __entry->transfer_id = transfer_id;
52 __entry->msg_id = msg_id;
53 __entry->protocol_id = protocol_id;
54 __entry->seq = seq;
55 __entry->timeout = timeout;
56 __entry->poll = poll;
57 ),
58
59 TP_printk("transfer_id=%d msg_id=%u protocol_id=%u seq=%u tmo_ms=%u poll=%u",
60 __entry->transfer_id, __entry->msg_id, __entry->protocol_id,
61 __entry->seq, __entry->timeout, __entry->poll)
62);
63
36TRACE_EVENT(scmi_xfer_end,64TRACE_EVENT(scmi_xfer_end,
37 TP_PROTO(int transfer_id, u8 msg_id, u8 protocol_id, u16 seq,65 TP_PROTO(int transfer_id, u8 msg_id, u8 protocol_id, u16 seq,
38 int status),66 int status),

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