History

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd: "This is the first batch of clk driver fixes for this release. We have a handful of fixes for the uniphier clk driver that was introduced recently, as well as Kconfig option hiding, module autoloading markings, and a few fixes for clk_hw based registration patches that went in this merge window" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: at91: Fix a return value in case of error clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs clk: uniphier: fix memory overrun bug clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init clk: mvebu: armada-37xx-periph: Fix the clock gate flag clk: bcm2835: Clamp the PLL's requested rate to the hardware limits. clk: max77686: fix number of clocks setup for clk_hw based registration clk: mvebu: armada-37xx-periph: Fix the clock provider registration clk: core: add __init decoration for CLK_OF_DECLARE_DRIVER function clk: mediatek: Add hardware dependency clk: samsung: clk-exynos-audss: Fix module autoload clk: uniphier: fix type of variable passed to regmap_read() clk: uniphier: add system clock support for sLD3 SoC

Linus Torvalds committed 10 years ago

Commit b5cd8912 parents 1ce5bdb 91bbc1713 files · +41 −35Browse files

Unified · Split

13 files
  1. Documentation/devicetree/bindings/clock/uniphier-clock.txt +8 −8
  2. drivers/clk/at91/clk-programmable.c +1 −1
  3. drivers/clk/bcm/clk-bcm2835.c +4 −7
  4. drivers/clk/clk-max77686.c +1 −0
  5. drivers/clk/hisilicon/clk-hi6220.c +2 −2
  6. drivers/clk/mediatek/Kconfig +2 −0
  7. drivers/clk/mvebu/armada-37xx-periph.c +6 −5
  8. drivers/clk/samsung/clk-exynos-audss.c +1 −0
  9. drivers/clk/uniphier/clk-uniphier-core.c +12 −8
  10. drivers/clk/uniphier/clk-uniphier-mio.c +1 −1
  11. drivers/clk/uniphier/clk-uniphier-mux.c +1 −1
  12. drivers/clk/uniphier/clk-uniphier.h +1 −1
  13. include/linux/clk-provider.h +1 −1
Documentation/devicetree/bindings/clock/uniphier-clock.txt+8−8
@@ -24,7 +24,7 @@ Example: · 23 unmodified lines
24 reg = <0x61840000 0x4000>;24 reg = <0x61840000 0x4000>;
25 25
26 clock {26 clock {
27 compatible = "socionext,uniphier-ld20-clock";27 compatible = "socionext,uniphier-ld11-clock";
28 #clock-cells = <1>;28 #clock-cells = <1>;
29 };29 };
30 30
@@ -43,8 +43,8 @@ Provided clocks: · 12 unmodified lines
4321: USB3 ch1 PHY14321: USB3 ch1 PHY1
44 44
45 45
46Media I/O (MIO) clock46Media I/O (MIO) clock, SD clock
47---------------------47-------------------------------
48 48
49Required properties:49Required properties:
50- compatible: should be one of the following:50- compatible: should be one of the following:
@@ -52,10 +52,10 @@ Required properties: · 1 unmodified line
52 "socionext,uniphier-ld4-mio-clock" - for LD4 SoC.52 "socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
53 "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.53 "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
54 "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.54 "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
55 "socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.55 "socionext,uniphier-pro5-sd-clock" - for Pro5 SoC.
56 "socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.56 "socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
57 "socionext,uniphier-ld11-mio-clock" - for LD11 SoC.57 "socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
58 "socionext,uniphier-ld20-mio-clock" - for LD20 SoC.58 "socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
59- #clock-cells: should be 1.59- #clock-cells: should be 1.
60 60
61Example:61Example:
@@ -66,7 +66,7 @@ Example: · 4 unmodified lines
66 reg = <0x59810000 0x800>;66 reg = <0x59810000 0x800>;
67 67
68 clock {68 clock {
69 compatible = "socionext,uniphier-ld20-mio-clock";69 compatible = "socionext,uniphier-ld11-mio-clock";
70 #clock-cells = <1>;70 #clock-cells = <1>;
71 };71 };
72 72
@@ -112,7 +112,7 @@ Example: · 39 unmodified lines
112 reg = <0x59820000 0x200>;112 reg = <0x59820000 0x200>;
113 113
114 clock {114 clock {
115 compatible = "socionext,uniphier-ld20-peri-clock";115 compatible = "socionext,uniphier-ld11-peri-clock";
116 #clock-cells = <1>;116 #clock-cells = <1>;
117 };117 };
118 118
drivers/clk/at91/clk-programmable.c+1−1
@@ -203,7 +203,7 @@ at91_clk_register_programmable(struct regmap *regmap, · 202 unmodified lines
203 ret = clk_hw_register(NULL, &prog->hw);203 ret = clk_hw_register(NULL, &prog->hw);
204 if (ret) {204 if (ret) {
205 kfree(prog);205 kfree(prog);
206 hw = &prog->hw;206 hw = ERR_PTR(ret);
207 }207 }
208 208
209 return hw;209 return hw;
drivers/clk/bcm/clk-bcm2835.c+4−7
@@ -502,8 +502,12 @@ static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, · 501 unmodified lines
502static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,502static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
503 unsigned long *parent_rate)503 unsigned long *parent_rate)
504{504{
505 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
506 const struct bcm2835_pll_data *data = pll->data;
505 u32 ndiv, fdiv;507 u32 ndiv, fdiv;
506 508
509 rate = clamp(rate, data->min_rate, data->max_rate);
510
507 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);511 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
508 512
509 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);513 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
@@ -608,13 +612,6 @@ static int bcm2835_pll_set_rate(struct clk_hw *hw, · 98 unmodified lines
608 u32 ana[4];612 u32 ana[4];
609 int i;613 int i;
610 614
611 if (rate < data->min_rate || rate > data->max_rate) {
612 dev_err(cprman->dev, "%s: rate out of spec: %lu vs (%lu, %lu)\n",
613 clk_hw_get_name(hw), rate,
614 data->min_rate, data->max_rate);
615 return -EINVAL;
616 }
617
618 if (rate > data->max_fb_rate) {615 if (rate > data->max_fb_rate) {
619 use_fb_prediv = true;616 use_fb_prediv = true;
620 rate /= 2;617 rate /= 2;
drivers/clk/clk-max77686.c+1−0
@@ -216,6 +216,7 @@ static int max77686_clk_probe(struct platform_device *pdev) · 215 unmodified lines
216 return -EINVAL;216 return -EINVAL;
217 }217 }
218 218
219 drv_data->num_clks = num_clks;
219 drv_data->max_clk_data = devm_kcalloc(dev, num_clks,220 drv_data->max_clk_data = devm_kcalloc(dev, num_clks,
220 sizeof(*drv_data->max_clk_data),221 sizeof(*drv_data->max_clk_data),
221 GFP_KERNEL);222 GFP_KERNEL);
drivers/clk/hisilicon/clk-hi6220.c+2−2
@@ -195,7 +195,7 @@ static void __init hi6220_clk_sys_init(struct device_node *np) · 194 unmodified lines
195 hi6220_clk_register_divider(hi6220_div_clks_sys,195 hi6220_clk_register_divider(hi6220_div_clks_sys,
196 ARRAY_SIZE(hi6220_div_clks_sys), clk_data);196 ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
197}197}
198CLK_OF_DECLARE(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);198CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);
199 199
200 200
201/* clocks in media controller */201/* clocks in media controller */
@@ -252,7 +252,7 @@ static void __init hi6220_clk_media_init(struct device_node *np) · 50 unmodified lines
252 hi6220_clk_register_divider(hi6220_div_clks_media,252 hi6220_clk_register_divider(hi6220_div_clks_media,
253 ARRAY_SIZE(hi6220_div_clks_media), clk_data);253 ARRAY_SIZE(hi6220_div_clks_media), clk_data);
254}254}
255CLK_OF_DECLARE(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);255CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);
256 256
257 257
258/* clocks in pmctrl */258/* clocks in pmctrl */
drivers/clk/mediatek/Kconfig+2−0
@@ -8,6 +8,7 @@ config COMMON_CLK_MEDIATEK · 7 unmodified lines
8 8
9config COMMON_CLK_MT81359config COMMON_CLK_MT8135
10 bool "Clock driver for Mediatek MT8135"10 bool "Clock driver for Mediatek MT8135"
11 depends on ARCH_MEDIATEK || COMPILE_TEST
11 select COMMON_CLK_MEDIATEK12 select COMMON_CLK_MEDIATEK
12 default ARCH_MEDIATEK13 default ARCH_MEDIATEK
13 ---help---14 ---help---
@@ -15,6 +16,7 @@ config COMMON_CLK_MT8135 · 1 unmodified line
15 16
16config COMMON_CLK_MT817317config COMMON_CLK_MT8173
17 bool "Clock driver for Mediatek MT8173"18 bool "Clock driver for Mediatek MT8173"
19 depends on ARCH_MEDIATEK || COMPILE_TEST
18 select COMMON_CLK_MEDIATEK20 select COMMON_CLK_MEDIATEK
19 default ARCH_MEDIATEK21 default ARCH_MEDIATEK
20 ---help---22 ---help---
drivers/clk/mvebu/armada-37xx-periph.c+6−5
@@ -305,7 +305,7 @@ static const struct of_device_id armada_3700_periph_clock_of_match[] = { · 304 unmodified lines
305};305};
306static int armada_3700_add_composite_clk(const struct clk_periph_data *data,306static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
307 void __iomem *reg, spinlock_t *lock,307 void __iomem *reg, spinlock_t *lock,
308 struct device *dev, struct clk_hw *hw)308 struct device *dev, struct clk_hw **hw)
309{309{
310 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,310 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
311 *rate_ops = NULL;311 *rate_ops = NULL;
@@ -329,6 +329,7 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data, · 17 unmodified lines
329 gate->lock = lock;329 gate->lock = lock;
330 gate_ops = gate_hw->init->ops;330 gate_ops = gate_hw->init->ops;
331 gate->reg = reg + (u64)gate->reg;331 gate->reg = reg + (u64)gate->reg;
332 gate->flags = CLK_GATE_SET_TO_DISABLE;
332 }333 }
333 334
334 if (data->rate_hw) {335 if (data->rate_hw) {
@@ -353,13 +354,13 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data, · 18 unmodified lines
353 }354 }
354 }355 }
355 356
356 hw = clk_hw_register_composite(dev, data->name, data->parent_names,357 *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
357 data->num_parents, mux_hw,358 data->num_parents, mux_hw,
358 mux_ops, rate_hw, rate_ops,359 mux_ops, rate_hw, rate_ops,
359 gate_hw, gate_ops, CLK_IGNORE_UNUSED);360 gate_hw, gate_ops, CLK_IGNORE_UNUSED);
360 361
361 if (IS_ERR(hw))362 if (IS_ERR(*hw))
362 return PTR_ERR(hw);363 return PTR_ERR(*hw);
363 364
364 return 0;365 return 0;
365}366}
@@ -400,7 +401,7 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev) · 34 unmodified lines
400 spin_lock_init(&driver_data->lock);401 spin_lock_init(&driver_data->lock);
401 402
402 for (i = 0; i < num_periph; i++) {403 for (i = 0; i < num_periph; i++) {
403 struct clk_hw *hw = driver_data->hw_data->hws[i];404 struct clk_hw **hw = &driver_data->hw_data->hws[i];
404 405
405 if (armada_3700_add_composite_clk(&data[i], reg,406 if (armada_3700_add_composite_clk(&data[i], reg,
406 &driver_data->lock, dev, hw))407 &driver_data->lock, dev, hw))
drivers/clk/samsung/clk-exynos-audss.c+1−0
@@ -106,6 +106,7 @@ static const struct of_device_id exynos_audss_clk_of_match[] = { · 105 unmodified lines
106 },106 },
107 { },107 { },
108};108};
109MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
109 110
110static void exynos_audss_clk_teardown(void)111static void exynos_audss_clk_teardown(void)
111{112{
drivers/clk/uniphier/clk-uniphier-core.c+12−8
@@ -79,7 +79,7 @@ static int uniphier_clk_probe(struct platform_device *pdev) · 78 unmodified lines
79 hw_data->num = clk_num;79 hw_data->num = clk_num;
80 80
81 /* avoid returning NULL for unused idx */81 /* avoid returning NULL for unused idx */
82 for (; clk_num >= 0; clk_num--)82 while (--clk_num >= 0)
83 hw_data->hws[clk_num] = ERR_PTR(-EINVAL);83 hw_data->hws[clk_num] = ERR_PTR(-EINVAL);
84 84
85 for (p = data; p->name; p++) {85 for (p = data; p->name; p++) {
@@ -110,6 +110,10 @@ static int uniphier_clk_remove(struct platform_device *pdev) · 24 unmodified lines
110 110
111static const struct of_device_id uniphier_clk_match[] = {111static const struct of_device_id uniphier_clk_match[] = {
112 /* System clock */112 /* System clock */
113 {
114 .compatible = "socionext,uniphier-sld3-clock",
115 .data = uniphier_sld3_sys_clk_data,
116 },
113 {117 {
114 .compatible = "socionext,uniphier-ld4-clock",118 .compatible = "socionext,uniphier-ld4-clock",
115 .data = uniphier_ld4_sys_clk_data,119 .data = uniphier_ld4_sys_clk_data,
@@ -138,7 +142,7 @@ static const struct of_device_id uniphier_clk_match[] = { · 22 unmodified lines
138 .compatible = "socionext,uniphier-ld20-clock",142 .compatible = "socionext,uniphier-ld20-clock",
139 .data = uniphier_ld20_sys_clk_data,143 .data = uniphier_ld20_sys_clk_data,
140 },144 },
141 /* Media I/O clock */145 /* Media I/O clock, SD clock */
142 {146 {
143 .compatible = "socionext,uniphier-sld3-mio-clock",147 .compatible = "socionext,uniphier-sld3-mio-clock",
144 .data = uniphier_sld3_mio_clk_data,148 .data = uniphier_sld3_mio_clk_data,
@@ -156,20 +160,20 @@ static const struct of_device_id uniphier_clk_match[] = { · 11 unmodified lines
156 .data = uniphier_sld3_mio_clk_data,160 .data = uniphier_sld3_mio_clk_data,
157 },161 },
158 {162 {
159 .compatible = "socionext,uniphier-pro5-mio-clock",163 .compatible = "socionext,uniphier-pro5-sd-clock",
160 .data = uniphier_pro5_mio_clk_data,164 .data = uniphier_pro5_sd_clk_data,
161 },165 },
162 {166 {
163 .compatible = "socionext,uniphier-pxs2-mio-clock",167 .compatible = "socionext,uniphier-pxs2-sd-clock",
164 .data = uniphier_pro5_mio_clk_data,168 .data = uniphier_pro5_sd_clk_data,
165 },169 },
166 {170 {
167 .compatible = "socionext,uniphier-ld11-mio-clock",171 .compatible = "socionext,uniphier-ld11-mio-clock",
168 .data = uniphier_sld3_mio_clk_data,172 .data = uniphier_sld3_mio_clk_data,
169 },173 },
170 {174 {
171 .compatible = "socionext,uniphier-ld20-mio-clock",175 .compatible = "socionext,uniphier-ld20-sd-clock",
172 .data = uniphier_pro5_mio_clk_data,176 .data = uniphier_pro5_sd_clk_data,
173 },177 },
174 /* Peripheral clock */178 /* Peripheral clock */
175 {179 {
drivers/clk/uniphier/clk-uniphier-mio.c+1−1
@@ -93,7 +93,7 @@ const struct uniphier_clk_data uniphier_sld3_mio_clk_data[] = { · 92 unmodified lines
93 { /* sentinel */ }93 { /* sentinel */ }
94};94};
95 95
96const struct uniphier_clk_data uniphier_pro5_mio_clk_data[] = {96const struct uniphier_clk_data uniphier_pro5_sd_clk_data[] = {
97 UNIPHIER_MIO_CLK_SD_FIXED,97 UNIPHIER_MIO_CLK_SD_FIXED,
98 UNIPHIER_MIO_CLK_SD(0, 0),98 UNIPHIER_MIO_CLK_SD(0, 0),
99 UNIPHIER_MIO_CLK_SD(1, 1),99 UNIPHIER_MIO_CLK_SD(1, 1),
drivers/clk/uniphier/clk-uniphier-mux.c+1−1
@@ -42,7 +42,7 @@ static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw) · 41 unmodified lines
42 struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);42 struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
43 int num_parents = clk_hw_get_num_parents(hw);43 int num_parents = clk_hw_get_num_parents(hw);
44 int ret;44 int ret;
45 u32 val;45 unsigned int val;
46 u8 i;46 u8 i;
47 47
48 ret = regmap_read(mux->regmap, mux->reg, &val);48 ret = regmap_read(mux->regmap, mux->reg, &val);
drivers/clk/uniphier/clk-uniphier.h+1−1
@@ -115,7 +115,7 @@ extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[]; · 114 unmodified lines
115extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];115extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
116extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];116extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
117extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];117extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
118extern const struct uniphier_clk_data uniphier_pro5_mio_clk_data[];118extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
119extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];119extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
120extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];120extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
121 121
include/linux/clk-provider.h+1−1
@@ -785,7 +785,7 @@ extern struct of_device_id __clk_of_table; · 784 unmodified lines
785 * routines, one at of_clk_init(), and one at platform device probe785 * routines, one at of_clk_init(), and one at platform device probe
786 */786 */
787#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \787#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
788 static void name##_of_clk_init_driver(struct device_node *np) \788 static void __init name##_of_clk_init_driver(struct device_node *np) \
789 { \789 { \
790 of_node_clear_flag(np, OF_POPULATED); \790 of_node_clear_flag(np, OF_POPULATED); \
791 fn(np); \791 fn(np); \