* for-next/perf: (25 commits) perf/marvell: Fix !CONFIG_OF build for CN10K DDR PMU driver drivers/perf: Add Apple icestorm/firestorm CPU PMU driver drivers/perf: arm_pmu: Handle 47 bit counters arm64: perf: Consistently make all event numbers as 16-bits arm64: perf: Expose some Armv9 common events under sysfs perf/marvell: cn10k DDR perf event core ownership perf/marvell: cn10k DDR perfmon event overflow handling perf/marvell: CN10k DDR performance monitor support dt-bindings: perf: marvell: cn10k ddr performance monitor perf/arm-cmn: Update watchpoint format perf/arm-cmn: Hide XP PUB events for CMN-600 perf: replace bitmap_weight with bitmap_empty where appropriate perf: Replace acpi_bus_get_device() perf/marvell_cn10k: Fix unused variable warning when W=1 and CONFIG_OF=n perf/arm-cmn: Make arm_cmn_debugfs static perf: MARVELL_CN10K_TAD_PMU should depend on ARCH_THUNDER perf/arm-ccn: Use platform_get_irq() to get the interrupt irqchip/apple-aic: Move PMU-specific registers to their own include file arm64: dts: apple: Add t8303 PMU nodes arm64: dts: apple: Add t8103 PMU interrupt affinities ...
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| @@ -11,5 +11,7 @@ · 10 unmodified lines | ||
| 11 | 11 | #define AIC_TMR_HV_VIRT 1 |
| 12 | 12 | #define AIC_TMR_GUEST_PHYS 2 |
| 13 | 13 | #define AIC_TMR_GUEST_VIRT 3 |
| 14 | +#define AIC_CPU_PMU_E 4 | |
| 15 | +#define AIC_CPU_PMU_P 5 | |
| 14 | 16 | |
| 15 | 17 | #endif |
| @@ -231,6 +231,7 @@ enum cpuhp_state { · 230 unmodified lines | ||
| 231 | 231 | CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE, |
| 232 | 232 | CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE, |
| 233 | 233 | CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE, |
| 234 | + CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE, | |
| 234 | 235 | CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE, |
| 235 | 236 | CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE, |
| 236 | 237 | CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE, |
| @@ -26,6 +26,8 @@ · 25 unmodified lines | ||
| 26 | 26 | */ |
| 27 | 27 | /* Event uses a 64bit counter */ |
| 28 | 28 | #define ARMPMU_EVT_64BIT 1 |
| 29 | +/* Event uses a 47bit counter */ | |
| 30 | +#define ARMPMU_EVT_47BIT 2 | |
| 29 | 31 | |
| 30 | 32 | #define HW_OP_UNSUPPORTED 0xFFFF |
| 31 | 33 | #define C(_x) PERF_COUNT_HW_CACHE_##_x |