5709 A0 copper devices will not link up with some link partners without this workaround. Update driver to 1.5.5.
Unified · Split
| @@ -57,8 +57,8 @@ · 56 unmodified lines | ||
| 57 | 57 | |
| 58 | 58 | #define DRV_MODULE_NAME "bnx2" |
| 59 | 59 | #define PFX DRV_MODULE_NAME ": " |
| 60 | −#define DRV_MODULE_VERSION "1.5.4" | |
| 61 | −#define DRV_MODULE_RELDATE "January 24, 2007" | |
| 60 | +#define DRV_MODULE_VERSION "1.5.5" | |
| 61 | +#define DRV_MODULE_RELDATE "February 1, 2007" | |
| 62 | 62 | |
| 63 | 63 | #define RUN_AT(x) (jiffies + (x)) |
| 64 | 64 | |
| @@ -1356,6 +1356,14 @@ bnx2_init_copper_phy(struct bnx2 *bp) · 1291 unmodified lines | ||
| 1356 | 1356 | bnx2_write_phy(bp, 0x18, 0x0400); |
| 1357 | 1357 | } |
| 1358 | 1358 | |
| 1359 | + if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) { | |
| 1360 | + bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, | |
| 1361 | + MII_BNX2_DSP_EXPAND_REG | 0x8); | |
| 1362 | + bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); | |
| 1363 | + val &= ~(1 << 8); | |
| 1364 | + bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); | |
| 1365 | + } | |
| 1366 | + | |
| 1359 | 1367 | if (bp->dev->mtu > 1500) { |
| 1360 | 1368 | /* Set extended packet length bit */ |
| 1361 | 1369 | bnx2_write_phy(bp, 0x18, 0x7); |
| @@ -5918,6 +5926,8 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) · 4556 unmodified lines | ||
| 5918 | 5926 | } else if (CHIP_NUM(bp) == CHIP_NUM_5706 || |
| 5919 | 5927 | CHIP_NUM(bp) == CHIP_NUM_5708) |
| 5920 | 5928 | bp->phy_flags |= PHY_CRC_FIX_FLAG; |
| 5929 | + else if (CHIP_ID(bp) == CHIP_ID_5709_A0) | |
| 5930 | + bp->phy_flags |= PHY_DIS_EARLY_DAC_FLAG; | |
| 5921 | 5931 | |
| 5922 | 5932 | if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || |
| 5923 | 5933 | (CHIP_ID(bp) == CHIP_ID_5708_B0) || |
| @@ -6288,6 +6288,10 @@ struct l2_fhdr { · 6287 unmodified lines | ||
| 6288 | 6288 | |
| 6289 | 6289 | #define BCM5708S_TX_ACTL3 0x17 |
| 6290 | 6290 | |
| 6291 | +#define MII_BNX2_DSP_RW_PORT 0x15 | |
| 6292 | +#define MII_BNX2_DSP_ADDRESS 0x17 | |
| 6293 | +#define MII_BNX2_DSP_EXPAND_REG 0x0f00 | |
| 6294 | + | |
| 6291 | 6295 | #define MIN_ETHERNET_PACKET_SIZE 60 |
| 6292 | 6296 | #define MAX_ETHERNET_PACKET_SIZE 1514 |
| 6293 | 6297 | #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014 |
| @@ -6489,6 +6493,7 @@ struct bnx2 { · 195 unmodified lines | ||
| 6489 | 6493 | #define PHY_INT_MODE_MASK_FLAG 0x300 |
| 6490 | 6494 | #define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 |
| 6491 | 6495 | #define PHY_INT_MODE_LINK_READY_FLAG 0x200 |
| 6496 | +#define PHY_DIS_EARLY_DAC_FLAG 0x400 | |
| 6492 | 6497 | |
| 6493 | 6498 | u32 chip_id; |
| 6494 | 6499 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
| @@ -6512,6 +6517,7 @@ struct bnx2 { · 17 unmodified lines | ||
| 6512 | 6517 | #define CHIP_ID_5708_A0 0x57080000 |
| 6513 | 6518 | #define CHIP_ID_5708_B0 0x57081000 |
| 6514 | 6519 | #define CHIP_ID_5708_B1 0x57081010 |
| 6520 | +#define CHIP_ID_5709_A0 0x57090000 | |
| 6515 | 6521 | |
| 6516 | 6522 | #define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf) |
| 6517 | 6523 | |