Merge tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar: - qcom: - enable support for ipq8074, sm1850 and sm7180 - add child device node for qcs404 - misc fixes - mediatek: - enable support for mt8183 - misc rejig of cmdq driver - new client-reg dt property - armada: - use device-managed registration api * tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: qcom-apcs: fix max_register value mailbox: qcom: Add support for IPQ8074 APCS dt-bindings: mailbox: qom: Add ipq8074 APPS compatible mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs mbox: qcom: replace integer with valid macro mbox: qcom: add APCS child device for QCS404 mailbox: mediatek: cmdq: clear the event in cmdq initial flow mailbox: mediatek: cmdq: support mt8183 gce function mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data dt-binding: gce: add binding for gce client reg property dt-binding: gce: add gce header file for mt8183 dt-binding: gce: remove thread-num property mailbox: armada-37xx-rwtm: Use device-managed registration API

Linus Torvalds committed 7 years ago

Commit b6822422 parents e3a008a 556a0968 files · +222 −33Browse files

Unified · Split

8 files

Documentation/devicetree/bindings/mailbox/mtk-gce.txt +15 −8
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +3 −0
drivers/mailbox/armada-37xx-rwtm-mailbox.c +1 −13
drivers/mailbox/mtk-cmdq-mailbox.c +13 −5
drivers/mailbox/qcom-apcs-ipc-mailbox.c +12 −4
include/dt-bindings/gce/mt8183-gce.h +175 −0
include/linux/mailbox/mtk-cmdq-mailbox.h +3 −0
include/linux/soc/mediatek/mtk-cmdq.h +0 −3

Documentation/devicetree/bindings/mailbox/mtk-gce.txt+15−8

@@ -9,7 +9,7 @@ CMDQ driver uses mailbox framework for communication. Please refer to · 8 unmodified lines
9	9	mailbox.txt for generic information about mailbox device-tree bindings.
10	10
11	11	Required properties:
12		−- compatible: Must be "mediatek,mt8173-gce"
	12	+- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"
13	13	- reg: Address range of the GCE unit
14	14	- interrupts: The interrupt signal from the GCE block
15	15	- clock: Clocks according to the common clock binding
@@ -25,11 +25,19 @@ Required properties: · 9 unmodified lines
25	25	Required properties for a client device:
26	26	- mboxes: Client use mailbox to communicate with GCE, it should have this
27	27	property and list of phandle, mailbox specifiers.
28		−- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding
29		− to the register address.
	28	+Optional properties for a client device:
	29	+- mediatek,gce-client-reg: Specify the sub-system id which is corresponding
	30	+ to the register address, it should have this property and list of phandle,
	31	+ sub-system specifiers.
	32	+ <&phandle subsys_number start_offset size>
	33	+ phandle: Label name of a gce node.
	34	+ subsys_number: specify the sub-system id which is corresponding
	35	+ to the register address.
	36	+ start_offset: the start offset of register address that GCE can access.
	37	+ size: the total size of register address that GCE can access.
30	38
31		−Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as
32		−sub-system ids, thread priority, event ids.
	39	+Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
	40	+or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.
33	41
34	42	Example:
35	43
@@ -39,7 +47,6 @@ Example: · 3 unmodified lines
39	47	interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
40	48	clocks = <&infracfg CLK_INFRA_GCE>;
41	49	clock-names = "gce";
42		− thread-num = CMDQ_THR_MAX_COUNT;
43	50	#mbox-cells = <3>;
44	51	};
45	52
@@ -49,9 +56,9 @@ Example for a client device: · 3 unmodified lines
49	56	compatible = "mediatek,mt8173-mmsys";
50	57	mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,
51	58	<&gce 1 CMDQ_THR_PRIO_LOWEST 1>;
52		− mediatek,gce-subsys = <SUBSYS_1400XXXX>;
53	59	mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
54	60	CMDQ_EVENT_MUTEX1_STREAM_EOF>;
55		−
	61	+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,
	62	+ <&gce SUBSYS_1401XXXX 0x2000 0x100>;
56	63	...
57	64	};

Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt+3−0

@@ -12,7 +12,10 @@ platforms. · 11 unmodified lines
12	12	"qcom,msm8996-apcs-hmss-global"
13	13	"qcom,msm8998-apcs-hmss-global"
14	14	"qcom,qcs404-apcs-apps-global"
	15	+ "qcom,sc7180-apss-shared"
15	16	"qcom,sdm845-apss-shared"
	17	+ "qcom,sm8150-apss-shared"
	18	+ "qcom,ipq8074-apcs-apps-global"
16	19
17	20	- reg:
18	21	Usage: required

drivers/mailbox/armada-37xx-rwtm-mailbox.c+1−13

@@ -180,7 +180,7 @@ static int armada_37xx_mbox_probe(struct platform_device *pdev) · 179 unmodified lines
180	180	mbox->controller.ops = &a37xx_mbox_ops;
181	181	mbox->controller.txdone_irq = true;
182	182
183		− ret = mbox_controller_register(&mbox->controller);
	183	+ ret = devm_mbox_controller_register(mbox->dev, &mbox->controller);
184	184	if (ret) {
185	185	dev_err(&pdev->dev, "Could not register mailbox controller\n");
186	186	return ret;
@@ -190,17 +190,6 @@ static int armada_37xx_mbox_probe(struct platform_device *pdev) · 3 unmodified lines
190	190	return ret;
191	191	}
192	192
193		−static int armada_37xx_mbox_remove(struct platform_device *pdev)
194		−{
195		− struct a37xx_mbox *mbox = platform_get_drvdata(pdev);
196		−
197		− if (!mbox)
198		− return -EINVAL;
199		−
200		− mbox_controller_unregister(&mbox->controller);
201		−
202		− return 0;
203		−}
204	193
205	194	static const struct of_device_id armada_37xx_mbox_match[] = {
206	195	{ .compatible = "marvell,armada-3700-rwtm-mailbox" },
@@ -211,7 +200,6 @@ MODULE_DEVICE_TABLE(of, armada_37xx_mbox_match); · 4 unmodified lines
211	200
212	201	static struct platform_driver armada_37xx_mbox_driver = {
213	202	.probe = armada_37xx_mbox_probe,
214		− .remove = armada_37xx_mbox_remove,
215	203	.driver = {
216	204	.name = DRIVER_NAME,
217	205	.of_match_table = armada_37xx_mbox_match,

drivers/mailbox/mtk-cmdq-mailbox.c+13−5

@@ -18,10 +18,10 @@ · 17 unmodified lines
18	18	#include <linux/of_device.h>
19	19
20	20	#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
21		−#define CMDQ_IRQ_MASK 0xffff
22	21	#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
23	22
24	23	#define CMDQ_CURR_IRQ_STATUS 0x10
	24	+#define CMDQ_SYNC_TOKEN_UPDATE 0x68
25	25	#define CMDQ_THR_SLOT_CYCLES 0x30
26	26	#define CMDQ_THR_BASE 0x100
27	27	#define CMDQ_THR_SIZE 0x80
@@ -72,6 +72,7 @@ struct cmdq { · 44 unmodified lines
72	72	void __iomem *base;
73	73	u32 irq;
74	74	u32 thread_nr;
	75	+ u32 irq_mask;
75	76	struct cmdq_thread *thread;
76	77	struct clk *clock;
77	78	bool suspended;
@@ -104,8 +105,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread) · 26 unmodified lines
104	105
105	106	static void cmdq_init(struct cmdq *cmdq)
106	107	{
	108	+ int i;
	109	+
107	110	WARN_ON(clk_enable(cmdq->clock) < 0);
108	111	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
	112	+ for (i = 0; i <= CMDQ_MAX_EVENT; i++)
	113	+ writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
109	114	clk_disable(cmdq->clock);
110	115	}
111	116
@@ -285,11 +290,11 @@ static irqreturn_t cmdq_irq_handler(int irq, void *dev) · 173 unmodified lines
285	290	unsigned long irq_status, flags = 0L;
286	291	int bit;
287	292
288		− irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK;
289		− if (!(irq_status ^ CMDQ_IRQ_MASK))
	293	+ irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
	294	+ if (!(irq_status ^ cmdq->irq_mask))
290	295	return IRQ_NONE;
291	296
292		− for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) {
	297	+ for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
293	298	struct cmdq_thread *thread = &cmdq->thread[bit];
294	299
295	300	spin_lock_irqsave(&thread->chan->lock, flags);
@@ -473,6 +478,9 @@ static int cmdq_probe(struct platform_device *pdev) · 177 unmodified lines
473	478	dev_err(dev, "failed to get irq\n");
474	479	return -EINVAL;
475	480	}
	481	+
	482	+ cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
	483	+ cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
476	484	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
477	485	"mtk_cmdq", cmdq);
478	486	if (err < 0) {
@@ -489,7 +497,6 @@ static int cmdq_probe(struct platform_device *pdev) · 10 unmodified lines
489	497	return PTR_ERR(cmdq->clock);
490	498	}
491	499
492		− cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
493	500	cmdq->mbox.dev = dev;
494	501	cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
495	502	sizeof(*cmdq->mbox.chans), GFP_KERNEL);
@@ -537,6 +544,7 @@ static const struct dev_pm_ops cmdq_pm_ops = { · 41 unmodified lines
537	544
538	545	static const struct of_device_id cmdq_of_ids[] = {
539	546	{.compatible = "mediatek,mt8173-gce", .data = (void *)16},
	547	+ {.compatible = "mediatek,mt8183-gce", .data = (void *)24},
540	548	{}
541	549	};
542	550

drivers/mailbox/qcom-apcs-ipc-mailbox.c+12−4

@@ -28,7 +28,7 @@ static const struct regmap_config apcs_regmap_config = { · 27 unmodified lines
28	28	.reg_bits = 32,
29	29	.reg_stride = 4,
30	30	.val_bits = 32,
31		− .max_register = 0x1000,
	31	+ .max_register = 0xFFC,
32	32	.fast_io = true,
33	33	};
34	34
@@ -47,7 +47,6 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = { · 12 unmodified lines
47	47
48	48	static int qcom_apcs_ipc_probe(struct platform_device *pdev)
49	49	{
50		− struct device_node *np = pdev->dev.of_node;
51	50	struct qcom_apcs_ipc *apcs;
52	51	struct regmap *regmap;
53	52	struct resource *res;
@@ -55,6 +54,11 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) · 1 unmodified line
55	54	void __iomem *base;
56	55	unsigned long i;
57	56	int ret;
	57	+ const struct of_device_id apcs_clk_match_table[] = {
	58	+ { .compatible = "qcom,msm8916-apcs-kpss-global", },
	59	+ { .compatible = "qcom,qcs404-apcs-apps-global", },
	60	+ {}
	61	+ };
58	62
59	63	apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL);
60	64	if (!apcs)
@@ -89,10 +93,11 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) · 28 unmodified lines
89	93	return ret;
90	94	}
91	95
92		− if (of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global")) {
	96	+ if (of_match_device(apcs_clk_match_table, &pdev->dev)) {
93	97	apcs->clk = platform_device_register_data(&pdev->dev,
94	98	"qcom-apcs-msm8916-clk",
95		− -1, NULL, 0);
	99	+ PLATFORM_DEVID_NONE,
	100	+ NULL, 0);
96	101	if (IS_ERR(apcs->clk))
97	102	dev_err(&pdev->dev, "failed to register APCS clk\n");
98	103	}
@@ -118,7 +123,10 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { · 19 unmodified lines
118	123	{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
119	124	{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = (void *)8 },
120	125	{ .compatible = "qcom,qcs404-apcs-apps-global", .data = (void *)8 },
	126	+ { .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },
121	127	{ .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
	128	+ { .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
	129	+ { .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 },
122	130	{}
123	131	};
124	132	MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);

include/dt-bindings/gce/mt8183-gce.h+175−0

@@ -0,0 +1,175 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright (c) 2019 MediaTek Inc.
	4	+ * Author: Bibby Hsieh <bibby.hsieh@mediatek.com>
	5	+ *
	6	+ */
	7	+
	8	+#ifndef _DT_BINDINGS_GCE_MT8183_H
	9	+#define _DT_BINDINGS_GCE_MT8183_H
	10	+
	11	+#define CMDQ_NO_TIMEOUT 0xffffffff
	12	+
	13	+/* GCE HW thread priority */
	14	+#define CMDQ_THR_PRIO_LOWEST 0
	15	+#define CMDQ_THR_PRIO_HIGHEST 1
	16	+
	17	+/* GCE SUBSYS */
	18	+#define SUBSYS_1300XXXX 0
	19	+#define SUBSYS_1400XXXX 1
	20	+#define SUBSYS_1401XXXX 2
	21	+#define SUBSYS_1402XXXX 3
	22	+#define SUBSYS_1502XXXX 4
	23	+#define SUBSYS_1880XXXX 5
	24	+#define SUBSYS_1881XXXX 6
	25	+#define SUBSYS_1882XXXX 7
	26	+#define SUBSYS_1883XXXX 8
	27	+#define SUBSYS_1884XXXX 9
	28	+#define SUBSYS_1000XXXX 10
	29	+#define SUBSYS_1001XXXX 11
	30	+#define SUBSYS_1002XXXX 12
	31	+#define SUBSYS_1003XXXX 13
	32	+#define SUBSYS_1004XXXX 14
	33	+#define SUBSYS_1005XXXX 15
	34	+#define SUBSYS_1020XXXX 16
	35	+#define SUBSYS_1028XXXX 17
	36	+#define SUBSYS_1700XXXX 18
	37	+#define SUBSYS_1701XXXX 19
	38	+#define SUBSYS_1702XXXX 20
	39	+#define SUBSYS_1703XXXX 21
	40	+#define SUBSYS_1800XXXX 22
	41	+#define SUBSYS_1801XXXX 23
	42	+#define SUBSYS_1802XXXX 24
	43	+#define SUBSYS_1804XXXX 25
	44	+#define SUBSYS_1805XXXX 26
	45	+#define SUBSYS_1808XXXX 27
	46	+#define SUBSYS_180aXXXX 28
	47	+#define SUBSYS_180bXXXX 29
	48	+
	49	+#define CMDQ_EVENT_DISP_RDMA0_SOF 0
	50	+#define CMDQ_EVENT_DISP_RDMA1_SOF 1
	51	+#define CMDQ_EVENT_MDP_RDMA0_SOF 2
	52	+#define CMDQ_EVENT_MDP_RSZ0_SOF 4
	53	+#define CMDQ_EVENT_MDP_RSZ1_SOF 5
	54	+#define CMDQ_EVENT_MDP_TDSHP_SOF 6
	55	+#define CMDQ_EVENT_MDP_WROT0_SOF 7
	56	+#define CMDQ_EVENT_MDP_WDMA0_SOF 8
	57	+#define CMDQ_EVENT_DISP_OVL0_SOF 9
	58	+#define CMDQ_EVENT_DISP_OVL0_2L_SOF 10
	59	+#define CMDQ_EVENT_DISP_OVL1_2L_SOF 11
	60	+#define CMDQ_EVENT_DISP_WDMA0_SOF 12
	61	+#define CMDQ_EVENT_DISP_COLOR0_SOF 13
	62	+#define CMDQ_EVENT_DISP_CCORR0_SOF 14
	63	+#define CMDQ_EVENT_DISP_AAL0_SOF 15
	64	+#define CMDQ_EVENT_DISP_GAMMA0_SOF 16
	65	+#define CMDQ_EVENT_DISP_DITHER0_SOF 17
	66	+#define CMDQ_EVENT_DISP_PWM0_SOF 18
	67	+#define CMDQ_EVENT_DISP_DSI0_SOF 19
	68	+#define CMDQ_EVENT_DISP_DPI0_SOF 20
	69	+#define CMDQ_EVENT_DISP_RSZ_SOF 22
	70	+#define CMDQ_EVENT_MDP_AAL_SOF 23
	71	+#define CMDQ_EVENT_MDP_CCORR_SOF 24
	72	+#define CMDQ_EVENT_DISP_DBI_SOF 25
	73	+#define CMDQ_EVENT_DISP_RDMA0_EOF 26
	74	+#define CMDQ_EVENT_DISP_RDMA1_EOF 27
	75	+#define CMDQ_EVENT_MDP_RDMA0_EOF 28
	76	+#define CMDQ_EVENT_MDP_RSZ0_EOF 30
	77	+#define CMDQ_EVENT_MDP_RSZ1_EOF 31
	78	+#define CMDQ_EVENT_MDP_TDSHP_EOF 32
	79	+#define CMDQ_EVENT_MDP_WROT0_EOF 33
	80	+#define CMDQ_EVENT_MDP_WDMA0_EOF 34
	81	+#define CMDQ_EVENT_DISP_OVL0_EOF 35
	82	+#define CMDQ_EVENT_DISP_OVL0_2L_EOF 36
	83	+#define CMDQ_EVENT_DISP_OVL1_2L_EOF 37
	84	+#define CMDQ_EVENT_DISP_WDMA0_EOF 38
	85	+#define CMDQ_EVENT_DISP_COLOR0_EOF 39
	86	+#define CMDQ_EVENT_DISP_CCORR0_EOF 40
	87	+#define CMDQ_EVENT_DISP_AAL0_EOF 41
	88	+#define CMDQ_EVENT_DISP_GAMMA0_EOF 42
	89	+#define CMDQ_EVENT_DISP_DITHER0_EOF 43
	90	+#define CMDQ_EVENT_DSI0_EOF 44
	91	+#define CMDQ_EVENT_DPI0_EOF 45
	92	+#define CMDQ_EVENT_DISP_RSZ_EOF 47
	93	+#define CMDQ_EVENT_MDP_AAL_EOF 48
	94	+#define CMDQ_EVENT_MDP_CCORR_EOF 49
	95	+#define CMDQ_EVENT_DBI_EOF 50
	96	+#define CMDQ_EVENT_MUTEX_STREAM_DONE0 130
	97	+#define CMDQ_EVENT_MUTEX_STREAM_DONE1 131
	98	+#define CMDQ_EVENT_MUTEX_STREAM_DONE2 132
	99	+#define CMDQ_EVENT_MUTEX_STREAM_DONE3 133
	100	+#define CMDQ_EVENT_MUTEX_STREAM_DONE4 134
	101	+#define CMDQ_EVENT_MUTEX_STREAM_DONE5 135
	102	+#define CMDQ_EVENT_MUTEX_STREAM_DONE6 136
	103	+#define CMDQ_EVENT_MUTEX_STREAM_DONE7 137
	104	+#define CMDQ_EVENT_MUTEX_STREAM_DONE8 138
	105	+#define CMDQ_EVENT_MUTEX_STREAM_DONE9 139
	106	+#define CMDQ_EVENT_MUTEX_STREAM_DONE10 140
	107	+#define CMDQ_EVENT_MUTEX_STREAM_DONE11 141
	108	+#define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142
	109	+#define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143
	110	+#define CMDQ_EVENT_DSI0_TE_EVENT 144
	111	+#define CMDQ_EVENT_DSI0_IRQ_EVENT 145
	112	+#define CMDQ_EVENT_DSI0_DONE_EVENT 146
	113	+#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150
	114	+#define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151
	115	+#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152
	116	+#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154
	117	+#define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155
	118	+#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156
	119	+#define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157
	120	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257
	121	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258
	122	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259
	123	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260
	124	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261
	125	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262
	126	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263
	127	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264
	128	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265
	129	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266
	130	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267
	131	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268
	132	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269
	133	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270
	134	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271
	135	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272
	136	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273
	137	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274
	138	+#define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275
	139	+#define CMDQ_EVENT_AMD_FRAME_DONE 276
	140	+#define CMDQ_EVENT_DVE_DONE 277
	141	+#define CMDQ_EVENT_WMFE_DONE 278
	142	+#define CMDQ_EVENT_RSC_DONE 279
	143	+#define CMDQ_EVENT_MFB_DONE 280
	144	+#define CMDQ_EVENT_WPE_A_DONE 281
	145	+#define CMDQ_EVENT_SPE_B_DONE 282
	146	+#define CMDQ_EVENT_OCC_DONE 283
	147	+#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289
	148	+#define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290
	149	+#define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291
	150	+#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292
	151	+#define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293
	152	+#define CMDQ_EVENT_ISP_FRAME_DONE_A 321
	153	+#define CMDQ_EVENT_ISP_FRAME_DONE_B 322
	154	+#define CMDQ_EVENT_CAMSV0_PASS1_DONE 323
	155	+#define CMDQ_EVENT_CAMSV1_PASS1_DONE 324
	156	+#define CMDQ_EVENT_CAMSV2_PASS1_DONE 325
	157	+#define CMDQ_EVENT_TSF_DONE 326
	158	+#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327
	159	+#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328
	160	+#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329
	161	+#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330
	162	+#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331
	163	+#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332
	164	+#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333
	165	+#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334
	166	+#define CMDQ_EVENT_IPU_CORE0_DONE0 353
	167	+#define CMDQ_EVENT_IPU_CORE0_DONE1 354
	168	+#define CMDQ_EVENT_IPU_CORE0_DONE2 355
	169	+#define CMDQ_EVENT_IPU_CORE0_DONE3 356
	170	+#define CMDQ_EVENT_IPU_CORE1_DONE0 385
	171	+#define CMDQ_EVENT_IPU_CORE1_DONE1 386
	172	+#define CMDQ_EVENT_IPU_CORE1_DONE2 387
	173	+#define CMDQ_EVENT_IPU_CORE1_DONE3 388
	174	+
	175	+#endif

include/linux/mailbox/mtk-cmdq-mailbox.h+3−0

@@ -20,6 +20,9 @@ · 19 unmodified lines
20	20	#define CMDQ_WFE_WAIT BIT(15)
21	21	#define CMDQ_WFE_WAIT_VALUE 0x1
22	22
	23	+/** cmdq event maximum */
	24	+#define CMDQ_MAX_EVENT 0x3ff
	25	+
23	26	/*
24	27	* CMDQ_CODE_MASK:
25	28	* set write mask

include/linux/soc/mediatek/mtk-cmdq.h+0−3

@@ -13,9 +13,6 @@ · 12 unmodified lines
13	13
14	14	#define CMDQ_NO_TIMEOUT 0xffffffffu
15	15
16		−/** cmdq event maximum */
17		−#define CMDQ_MAX_EVENT 0x3ff
18		−
19	16	struct cmdq_pkt;
20	17
21	18	struct cmdq_client {

Merge tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration

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