The DCC_MAX_COMPRESSED_BLOCK has to contain one of AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't fit in 1 bit. Fix this cleanly while it is only in drm-next.
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| @@ -1168,7 +1168,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 1167 unmodified lines | ||
| 1168 | 1168 | #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 |
| 1169 | 1169 | #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 |
| 1170 | 1170 | #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 |
| 1171 | −#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1 | |
| 1171 | +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 | |
| 1172 | 1172 | |
| 1173 | 1173 | /* |
| 1174 | 1174 | * DCC supports embedding some clear colors directly in the DCC surface. |
| @@ -1179,7 +1179,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 4 unmodified lines | ||
| 1179 | 1179 | * If this bit is set that means the fastclear eliminate is not needed for these |
| 1180 | 1180 | * embeddable colors. |
| 1181 | 1181 | */ |
| 1182 | −#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19 | |
| 1182 | +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 | |
| 1183 | 1183 | #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 |
| 1184 | 1184 | |
| 1185 | 1185 | /* |
| @@ -1192,15 +1192,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 6 unmodified lines | ||
| 1192 | 1192 | * RB = only for TILE_VER_GFX9 & DCC |
| 1193 | 1193 | * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) |
| 1194 | 1194 | */ |
| 1195 | −#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20 | |
| 1195 | +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 | |
| 1196 | 1196 | #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 |
| 1197 | −#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23 | |
| 1197 | +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 | |
| 1198 | 1198 | #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 |
| 1199 | −#define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */ | |
| 1199 | +#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */ | |
| 1200 | 1200 | #define AMD_FMT_MOD_PACKERS_MASK 0x7 |
| 1201 | −#define AMD_FMT_MOD_RB_SHIFT 29 | |
| 1201 | +#define AMD_FMT_MOD_RB_SHIFT 30 | |
| 1202 | 1202 | #define AMD_FMT_MOD_RB_MASK 0x7 |
| 1203 | −#define AMD_FMT_MOD_PIPE_SHIFT 32 | |
| 1203 | +#define AMD_FMT_MOD_PIPE_SHIFT 33 | |
| 1204 | 1204 | #define AMD_FMT_MOD_PIPE_MASK 0x7 |
| 1205 | 1205 | |
| 1206 | 1206 | #define AMD_FMT_MOD_SET(field, value) \ |