History

Merge tag 'amd-drm-fixes-6.7-2023-12-20' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes

amd-drm-fixes-6.7-2023-12-20: amdgpu: - DCN 3.5 fixes - DCN 3.2 SubVP fix - GPUVM fix amdkfd: - SVM fix for APUs Signed-off-by: Dave Airlie <airlied@redhat.com>

Dave Airlie committed 2 years ago

Commit b7ef7ca2 parents ceb6a6f 4a0057a7 files · +55 −27Browse files

Unified · Split

7 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +1 −0
  2. drivers/gpu/drm/amd/amdkfd/kfd_svm.c +12 −6
  3. drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +15 −12
  4. drivers/gpu/drm/amd/display/dc/core/dc.c +18 −8
  5. drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c +1 −1
  6. drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +6 −0
  7. drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +2 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+1−0
@@ -285,6 +285,7 @@ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm) · 284 unmodified lines
285 list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {285 list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
286 struct amdgpu_bo *bo = vm_bo->bo;286 struct amdgpu_bo *bo = vm_bo->bo;
287 287
288 vm_bo->moved = true;
288 if (!bo || bo->tbo.type != ttm_bo_type_kernel)289 if (!bo || bo->tbo.type != ttm_bo_type_kernel)
289 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);290 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
290 else if (bo->parent)291 else if (bo->parent)
drivers/gpu/drm/amd/amdkfd/kfd_svm.c+12−6
@@ -1653,18 +1653,24 @@ static int svm_range_validate_and_map(struct mm_struct *mm, · 1652 unmodified lines
1653 if (test_bit(gpuidx, prange->bitmap_access))1653 if (test_bit(gpuidx, prange->bitmap_access))
1654 bitmap_set(ctx->bitmap, gpuidx, 1);1654 bitmap_set(ctx->bitmap, gpuidx, 1);
1655 }1655 }
1656
1657 /*
1658 * If prange is already mapped or with always mapped flag,
1659 * update mapping on GPUs with ACCESS attribute
1660 */
1661 if (bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
1662 if (prange->mapped_to_gpu ||
1663 prange->flags & KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED)
1664 bitmap_copy(ctx->bitmap, prange->bitmap_access, MAX_GPU_INSTANCE);
1665 }
1656 } else {1666 } else {
1657 bitmap_or(ctx->bitmap, prange->bitmap_access,1667 bitmap_or(ctx->bitmap, prange->bitmap_access,
1658 prange->bitmap_aip, MAX_GPU_INSTANCE);1668 prange->bitmap_aip, MAX_GPU_INSTANCE);
1659 }1669 }
1660 1670
1661 if (bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {1671 if (bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
1662 bitmap_copy(ctx->bitmap, prange->bitmap_access, MAX_GPU_INSTANCE);1672 r = 0;
1663 if (!prange->mapped_to_gpu ||1673 goto free_ctx;
1664 bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
1665 r = 0;
1666 goto free_ctx;
1667 }
1668 }1674 }
1669 1675
1670 if (prange->actual_loc && !prange->ttm_res) {1676 if (prange->actual_loc && !prange->ttm_res) {
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c+15−12
@@ -1014,13 +1014,20 @@ static enum bp_result get_ss_info_v4_5( · 1013 unmodified lines
1014 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);1014 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1015 break;1015 break;
1016 case AS_SIGNAL_TYPE_DISPLAY_PORT:1016 case AS_SIGNAL_TYPE_DISPLAY_PORT:
1017 ss_info->spread_spectrum_percentage =1017 if (bp->base.integrated_info) {
1018 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage);
1019 ss_info->spread_spectrum_percentage =
1020 bp->base.integrated_info->gpuclk_ss_percentage;
1021 ss_info->type.CENTER_MODE =
1022 bp->base.integrated_info->gpuclk_ss_type;
1023 } else {
1024 ss_info->spread_spectrum_percentage =
1018 disp_cntl_tbl->dp_ss_percentage;1025 disp_cntl_tbl->dp_ss_percentage;
1019 ss_info->spread_spectrum_range =1026 ss_info->spread_spectrum_range =
1020 disp_cntl_tbl->dp_ss_rate_10hz * 10;1027 disp_cntl_tbl->dp_ss_rate_10hz * 10;
1021 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)1028 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1022 ss_info->type.CENTER_MODE = true;1029 ss_info->type.CENTER_MODE = true;
1023 1030 }
1024 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);1031 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1025 break;1032 break;
1026 case AS_SIGNAL_TYPE_GPU_PLL:1033 case AS_SIGNAL_TYPE_GPU_PLL:
@@ -2386,13 +2393,7 @@ static enum bp_result get_vram_info_v30( · 1359 unmodified lines
2386 return BP_RESULT_BADBIOSTABLE;2393 return BP_RESULT_BADBIOSTABLE;
2387 2394
2388 info->num_chans = info_v30->channel_num;2395 info->num_chans = info_v30->channel_num;
2389 /* As suggested by VBIOS we should always use2396 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
2390 * dram_channel_width_bytes = 2 when using VRAM
2391 * table version 3.0. This is because the channel_width
2392 * param in the VRAM info table is changed in 7000 series and
2393 * no longer represents the memory channel width.
2394 */
2395 info->dram_channel_width_bytes = 2;
2396 2397
2397 return result;2398 return result;
2398}2399}
@@ -2820,6 +2821,8 @@ static enum bp_result get_integrated_info_v2_2( · 421 unmodified lines
2820 info->ma_channel_number = info_v2_2->umachannelnumber;2821 info->ma_channel_number = info_v2_2->umachannelnumber;
2821 info->dp_ss_control =2822 info->dp_ss_control =
2822 le16_to_cpu(info_v2_2->reserved1);2823 le16_to_cpu(info_v2_2->reserved1);
2824 info->gpuclk_ss_percentage = info_v2_2->gpuclk_ss_percentage;
2825 info->gpuclk_ss_type = info_v2_2->gpuclk_ss_type;
2823 2826
2824 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {2827 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2825 info->ext_disp_conn_info.gu_id[i] =2828 info->ext_disp_conn_info.gu_id[i] =
drivers/gpu/drm/amd/display/dc/core/dc.c+18−8
@@ -5095,18 +5095,28 @@ void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc) · 5094 unmodified lines
5095 */5095 */
5096bool dc_is_dmub_outbox_supported(struct dc *dc)5096bool dc_is_dmub_outbox_supported(struct dc *dc)
5097{5097{
5098 /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */5098 switch (dc->ctx->asic_id.chip_family) {
5099 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
5100 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
5101 !dc->debug.dpia_debug.bits.disable_dpia)
5102 return true;
5103 5099
5104 if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1 &&5100 case FAMILY_YELLOW_CARP:
5105 !dc->debug.dpia_debug.bits.disable_dpia)5101 /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
5106 return true;5102 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
5103 !dc->debug.dpia_debug.bits.disable_dpia)
5104 return true;
5105 break;
5106
5107 case AMDGPU_FAMILY_GC_11_0_1:
5108 case AMDGPU_FAMILY_GC_11_5_0:
5109 if (!dc->debug.dpia_debug.bits.disable_dpia)
5110 return true;
5111 break;
5112
5113 default:
5114 break;
5115 }
5107 5116
5108 /* dmub aux needs dmub notifications to be enabled */5117 /* dmub aux needs dmub notifications to be enabled */
5109 return dc->debug.enable_dmub_aux_for_legacy_ddc;5118 return dc->debug.enable_dmub_aux_for_legacy_ddc;
5119
5110}5120}
5111 5121
5112/**5122/**
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c+1−1
@@ -5420,7 +5420,7 @@ static void CalculateOutputLink( · 5419 unmodified lines
5420 *OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,5420 *OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,
5421 OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);5421 OutputFormat, DSCInputBitPerComponent, NumberOfDSCSlices, (dml_uint_t)AudioSampleRate, AudioSampleLayout, ODMModeNoDSC, ODMModeDSC, RequiredSlots);
5422 5422
5423 if (OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {5423 if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {
5424 *RequiresDSC = true;5424 *RequiresDSC = true;
5425 LinkDSCEnable = true;5425 LinkDSCEnable = true;
5426 *OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,5426 *OutBpp = TruncToValidBPP((1 - Downspreading / 100) * 13500, OutputLinkDPLanes, HTotal, HActive, PixelClockBackEnd, ForcedOutputLinkBPP, LinkDSCEnable, Output,
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c+6−0
@@ -960,6 +960,12 @@ void dcn32_init_hw(struct dc *dc) · 959 unmodified lines
960 dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;960 dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;
961 dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;961 dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;
962 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;962 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
963
964 if (dc->ctx->dmub_srv->dmub->fw_version <
965 DMUB_FW_VERSION(7, 0, 35)) {
966 dc->debug.force_disable_subvp = true;
967 dc->debug.disable_fpo_optimizations = true;
968 }
963 }969 }
964}970}
965 971
drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h+2−0
@@ -417,6 +417,8 @@ struct integrated_info { · 416 unmodified lines
417 /* V2.1 */417 /* V2.1 */
418 struct edp_info edp1_info;418 struct edp_info edp1_info;
419 struct edp_info edp2_info;419 struct edp_info edp2_info;
420 uint32_t gpuclk_ss_percentage;
421 uint32_t gpuclk_ss_type;
420};422};
421 423
422/*424/*