lael-labs/linux

Documentation/devicetree/bindings/arm/tegra.yaml+39−9

               - toradex,colibri_t20-iris
           - const: toradex,colibri_t20
           - const: nvidia,tegra20
+      - items:
+          - const: asus,tf101
+          - const: nvidia,tegra20
       - items:
           - const: acer,picasso
           - const: nvidia,tegra20
               - nvidia,cardhu-a04
           - const: nvidia,cardhu
           - const: nvidia,tegra30
+      - items:
+          - const: asus,tf201
+          - const: nvidia,tegra30
+      - items:
+          - const: asus,tf300t
+          - const: nvidia,tegra30
+      - items:
+          - const: asus,tf300tg
+          - const: nvidia,tegra30
+      - items:
+          - const: asus,tf700t
+          - const: nvidia,tegra30
       - items:
           - const: toradex,apalis_t30-eval
           - const: toradex,apalis_t30
       - items:
           - const: ouya,ouya
           - const: nvidia,tegra30
+      - items:
+          - const: pegatron,chagall
+          - const: nvidia,tegra30
       - items:
           - enum:
+              - asus,tf701t
               - nvidia,dalmore
               - nvidia,roth
               - nvidia,tn7
               - nvidia,p2571
               - nvidia,p2894-0050-a08
           - const: nvidia,tegra210
-      - items:
+      - description: Jetson TX2 Developer Kit
-          - enum:
+        items:
-              - nvidia,p2771-0000
+          - const: nvidia,p2771-0000
-              - nvidia,p3509-0000+p3636-0001
           - const: nvidia,tegra186
-      - items:
+      - description: Jetson TX2 NX Developer Kit
-          - enum:
+        items:
-              - nvidia,p2972-0000
+          - const: nvidia,p3509-0000+p3636-0001
+          - const: nvidia,tegra186
+      - description: Jetson AGX Xavier Developer Kit
+        items:
+          - const: nvidia,p2972-0000
           - const: nvidia,tegra194
       - description: Jetson Xavier NX
         items:
           - const: nvidia,p3509-0000+p3668-0001
           - const: nvidia,tegra194
       - items:
-          - enum:
+          - const: nvidia,tegra234-vdk
-              - nvidia,tegra234-vdk
+          - const: nvidia,tegra234
+      - description: Jetson AGX Orin
+        items:
+          - const: nvidia,p3701-0000
+          - const: nvidia,tegra234
+      - description: Jetson AGX Orin Developer Kit
+        items:
+          - const: nvidia,p3737-0000+p3701-0000
+          - const: nvidia,p3701-0000
           - const: nvidia,tegra234
 additionalProperties: true

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt+0−133

@@ -1,133 +0,0 @@
1	NVIDIA Tegra Power Management Controller (PMC)
2
3	Required properties:
4	- compatible: Should contain one of the following:
5	- "nvidia,tegra186-pmc": for Tegra186
6	- "nvidia,tegra194-pmc": for Tegra194
7	- "nvidia,tegra234-pmc": for Tegra234
8	- reg: Must contain an (offset, length) pair of the register set for each
9	entry in reg-names.
10	- reg-names: Must include the following entries:
11	- "pmc"
12	- "wake"
13	- "aotag"
14	- "scratch"
15	- "misc" (Only for Tegra194 and later)
16
17	Optional properties:
18	- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
19	- interrupt-controller: Identifies the node as an interrupt controller.
20	- #interrupt-cells: Specifies the number of cells needed to encode an
21	interrupt source. The value must be 2.
22
23	Example:
24
25	SoC DTSI:
26
27	pmc@c3600000 {
28	compatible = "nvidia,tegra186-pmc";
29	reg = <0 0x0c360000 0 0x10000>,
30	<0 0x0c370000 0 0x10000>,
31	<0 0x0c380000 0 0x10000>,
32	<0 0x0c390000 0 0x10000>;
33	reg-names = "pmc", "wake", "aotag", "scratch";
34	};
35
36	Board DTS:
37
38	pmc@c360000 {
39	nvidia,invert-interrupt;
40	};
41
42	== Pad Control ==
43
44	On Tegra SoCs a pad is a set of pins which are configured as a group.
45	The pin grouping is a fixed attribute of the hardware. The PMC can be
46	used to set pad power state and signaling voltage. A pad can be either
47	in active or power down mode. The support for power state and signaling
48	voltage configuration varies depending on the pad in question. 3.3 V and
49	1.8 V signaling voltages are supported on pins where software
50	controllable signaling voltage switching is available.
51
52	Pad configurations are described with pin configuration nodes which
53	are placed under the pmc node and they are referred to by the pinctrl
54	client properties. For more information see
55	Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
56
57	The following pads are present on Tegra186:
58	csia csib dsi mipi-bias
59	pex-clk-bias pex-clk3 pex-clk2 pex-clk1
60	usb0 usb1 usb2 usb-bias
61	uart audio hsic dbg
62	hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
63	sdmmc4 cam dsib dsic
64	dsid csic csid csie
65	dsif spi ufs dmic-hv
66	edp sdmmc1-hv sdmmc3-hv conn
67	audio-hv ao-hv
68
69	Required pin configuration properties:
70	- pins: A list of strings, each of which contains the name of a pad
71	to be configured.
72
73	Optional pin configuration properties:
74	- low-power-enable: Configure the pad into power down mode
75	- low-power-disable: Configure the pad into active mode
76	- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
77	TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
78	The values are defined in
79	include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
80
81	Note: The power state can be configured on all of the above pads except
82	for ao-hv. Following pads have software configurable signaling
83	voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
84	ao-hv.
85
86	Pad configuration state example:
87	pmc: pmc@7000e400 {
88	compatible = "nvidia,tegra186-pmc";
89	reg = <0 0x0c360000 0 0x10000>,
90	<0 0x0c370000 0 0x10000>,
91	<0 0x0c380000 0 0x10000>,
92	<0 0x0c390000 0 0x10000>;
93	reg-names = "pmc", "wake", "aotag", "scratch";
94
95	...
96
97	sdmmc1_3v3: sdmmc1-3v3 {
98	pins = "sdmmc1-hv";
99	power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
100	};
101
102	sdmmc1_1v8: sdmmc1-1v8 {
103	pins = "sdmmc1-hv";
104	power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
105	};
106
107	hdmi_off: hdmi-off {
108	pins = "hdmi";
109	low-power-enable;
110	}
111
112	hdmi_on: hdmi-on {
113	pins = "hdmi";
114	low-power-disable;
115	}
116	};
117
118	Pinctrl client example:
119	sdmmc1: sdhci@3400000 {
120	...
121	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
122	pinctrl-0 = <&sdmmc1_3v3>;
123	pinctrl-1 = <&sdmmc1_1v8>;
124	};
125
126	...
127
128	sor0: sor@15540000 {
129	...
130	pinctrl-0 = <&hdmi_off>;
131	pinctrl-1 = <&hdmi_on>;
132	pinctrl-names = "hdmi-on", "hdmi-off";
133	};

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml+198−0

@@ -0,0 +1,198 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra Power Management Controller (PMC)
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	properties:
	14	compatible:
	15	enum:
	16	- nvidia,tegra186-pmc
	17	- nvidia,tegra194-pmc
	18	- nvidia,tegra234-pmc
	19
	20	reg:
	21	minItems: 4
	22	maxItems: 5
	23
	24	reg-names:
	25	minItems: 4
	26	items:
	27	- const: pmc
	28	- const: wake
	29	- const: aotag
	30	- const: scratch
	31	- const: misc
	32
	33	interrupt-controller: true
	34
	35	"#interrupt-cells":
	36	description: Specifies the number of cells needed to encode an
	37	interrupt source. The value must be 2.
	38	const: 2
	39
	40	nvidia,invert-interrupt:
	41	description: If present, inverts the PMU interrupt signal.
	42	$ref: /schemas/types.yaml#/definitions/flag
	43
	44	if:
	45	properties:
	46	compatible:
	47	contains:
	48	const: nvidia,tegra186-pmc
	49	then:
	50	properties:
	51	reg:
	52	maxItems: 4
	53
	54	reg-names:
	55	maxItems: 4
	56	else:
	57	properties:
	58	reg:
	59	minItems: 5
	60
	61	reg-names:
	62	minItems: 5
	63
	64	patternProperties:
	65	"^[a-z0-9]+-[a-z0-9]+$":
	66	if:
	67	type: object
	68	then:
	69	description: \|
	70	These are pad configuration nodes. On Tegra SoCs a pad is a set of
	71	pins which are configured as a group. The pin grouping is a fixed
	72	attribute of the hardware. The PMC can be used to set pad power
	73	state and signaling voltage. A pad can be either in active or
	74	power down mode. The support for power state and signaling voltage
	75	configuration varies depending on the pad in question. 3.3 V and
	76	1.8 V signaling voltages are supported on pins where software
	77	controllable signaling voltage switching is available.
	78
	79	Pad configurations are described with pin configuration nodes
	80	which are placed under the pmc node and they are referred to by
	81	the pinctrl client properties. For more information see
	82
	83	Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
	84
	85	The following pads are present on Tegra186:
	86
	87	csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
	88	pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
	89	hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
	90	dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
	91	sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
	92
	93	The following pads are present on Tegra194:
	94
	95	csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
	96	pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
	97	pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
	98	soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
	99	hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
	100	pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
	101	spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
	102	audio-hv, ao-hv
	103
	104	properties:
	105	pins:
	106	$ref: /schemas/types.yaml#/definitions/string
	107	description: Must contain the name of the pad(s) to be
	108	configured.
	109
	110	low-power-enable:
	111	description: Configure the pad into power down mode.
	112	$ref: /schemas/types.yaml#/definitions/flag
	113
	114	low-power-disable:
	115	description: Configure the pad into active mode.
	116	$ref: /schemas/types.yaml#/definitions/flag
	117
	118	power-source:
	119	$ref: /schemas/types.yaml#/definitions/uint32
	120	description: \|
	121	Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
	122	TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
	123	voltages.
	124
	125	The values are defined in
	126
	127	include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
	128
	129	The power state can be configured on all of the above pads
	130	except for ao-hv. Following pads have software configurable
	131	signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
	132	audio-hv, ao-hv.
	133
	134	phandle: true
	135
	136	required:
	137	- pins
	138
	139	additionalProperties: false
	140
	141	required:
	142	- compatible
	143	- reg
	144	- reg-names
	145
	146	additionalProperties: false
	147
	148	dependencies:
	149	interrupt-controller: ['#interrupt-cells']
	150	"#interrupt-cells":
	151	required:
	152	- interrupt-controller
	153
	154	examples:
	155	- \|
	156	#include <dt-bindings/clock/tegra186-clock.h>
	157	#include <dt-bindings/interrupt-controller/arm-gic.h>
	158	#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
	159	#include <dt-bindings/memory/tegra186-mc.h>
	160	#include <dt-bindings/reset/tegra186-reset.h>
	161
	162	pmc@c3600000 {
	163	compatible = "nvidia,tegra186-pmc";
	164	reg = <0x0c360000 0x10000>,
	165	<0x0c370000 0x10000>,
	166	<0x0c380000 0x10000>,
	167	<0x0c390000 0x10000>;
	168	reg-names = "pmc", "wake", "aotag", "scratch";
	169	nvidia,invert-interrupt;
	170
	171	sdmmc1_3v3: sdmmc1-3v3 {
	172	pins = "sdmmc1-hv";
	173	power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
	174	};
	175
	176	sdmmc1_1v8: sdmmc1-1v8 {
	177	pins = "sdmmc1-hv";
	178	power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
	179	};
	180	};
	181
	182	sdmmc1: mmc@3400000 {
	183	compatible = "nvidia,tegra186-sdhci";
	184	reg = <0x03400000 0x10000>;
	185	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	186	clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
	187	<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
	188	clock-names = "sdhci", "tmclk";
	189	resets = <&bpmp TEGRA186_RESET_SDMMC1>;
	190	reset-names = "sdhci";
	191	interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
	192	<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
	193	interconnect-names = "dma-mem", "write";
	194	iommus = <&smmu TEGRA186_SID_SDMMC1>;
	195	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
	196	pinctrl-0 = <&sdmmc1_3v3>;
	197	pinctrl-1 = <&sdmmc1_1v8>;
	198	};

Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml+37−0

@@ -42,6 +42,36 @@ properties: · 41 unmodified lines
42	"#reset-cells":	42	"#reset-cells":
43	const: 1	43	const: 1
44		44
		45	patternProperties:
		46	"^(sclk)\|(pll-[cem])$":
		47	type: object
		48	properties:
		49	compatible:
		50	enum:
		51	- nvidia,tegra20-sclk
		52	- nvidia,tegra30-sclk
		53	- nvidia,tegra30-pllc
		54	- nvidia,tegra30-plle
		55	- nvidia,tegra30-pllm
		56
		57	operating-points-v2: true
		58
		59	clocks:
		60	items:
		61	- description: node's clock
		62
		63	power-domains:
		64	maxItems: 1
		65	description: phandle to the core SoC power domain
		66
		67	required:
		68	- compatible
		69	- operating-points-v2
		70	- clocks
		71	- power-domains
		72
		73	additionalProperties: false
		74
45	required:	75	required:
46	- compatible	76	- compatible
47	- reg	77	- reg
@@ -59,6 +89,13 @@ examples: · 11 unmodified lines
59	reg = <0x60006000 0x1000>;	89	reg = <0x60006000 0x1000>;
60	#clock-cells = <1>;	90	#clock-cells = <1>;
61	#reset-cells = <1>;	91	#reset-cells = <1>;
		92
		93	sclk {
		94	compatible = "nvidia,tegra20-sclk";
		95	operating-points-v2 = <&opp_table>;
		96	clocks = <&tegra_car TEGRA20_CLK_SCLK>;
		97	power-domains = <&domain>;
		98	};
62	};	99	};
63		100
64	usb-controller@c5004000 {	101	usb-controller@c5004000 {

Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt+53−0

   See ../reset/reset.txt for details.
 - reset-names: Must include the following entries:
   - host1x
+  - mc
+Optional properties:
+- operating-points-v2: See ../bindings/opp/opp.txt for details.
+  - power-domains: Phandle to HEG or core power domain.
+For each opp entry in 'operating-points-v2' table of host1x and its modules:
+- opp-supported-hw: One bitfield indicating:
+	On Tegra20: SoC process ID mask
+	On Tegra30+: SoC speedo ID mask
+	A bitwise AND is performed against the value and if any bit
+	matches, the OPP gets enabled.
 Each host1x client module having to perform DMA through the Memory Controller
 should have the interconnect endpoints set to the Memory Client and External
   - interconnect-names: Must include name of the interconnect path for each
     interconnect entry. Consult TRM documentation for information about
     available memory clients, see MEMORY CONTROLLER section.
+  - operating-points-v2: See ../bindings/opp/opp.txt for details.
+  - power-domains: Phandle to MPE power domain.
 - vi: video input
   - interconnect-names: Must include name of the interconnect path for each
     interconnect entry. Consult TRM documentation for information about
     available memory clients, see MEMORY CONTROLLER section.
+  - operating-points-v2: See ../bindings/opp/opp.txt for details.
+  - power-domains: Phandle to VENC power domain.
 - epp: encoder pre-processor
   - interconnect-names: Must include name of the interconnect path for each
     interconnect entry. Consult TRM documentation for information about
     available memory clients, see MEMORY CONTROLLER section.
+  - operating-points-v2: See ../bindings/opp/opp.txt for details.
+  - power-domains: Phandle to HEG or core power domain.
 - isp: image signal processor
   - interconnect-names: Must include name of the interconnect path for each
     interconnect entry. Consult TRM documentation for information about
     available memory clients, see MEMORY CONTROLLER section.
+  - power-domains: Phandle to VENC or core power domain.
 - gr2d: 2D graphics engine
     See ../reset/reset.txt for details.
   - reset-names: Must include the following entries:
     - 2d
+    - mc
   Optional properties:
   - interconnects: Must contain entry for the GR2D memory clients.
   - interconnect-names: Must include name of the interconnect path for each
     interconnect entry. Consult TRM documentation for information about
     available memory clients, see MEMORY CONTROLLER section.
+  - operating-points-v2: See ../bindings/opp/opp.txt for details.
+  - power-domains: Phandle to HEG or core power domain.
 - gr3d: 3D graphics engine
   - reset-names: Must include the following entries:
     - 3d
     - 3d2 (Only required on SoCs with two 3D clocks)
+    - mc
+    - mc2 (Only required on SoCs with two 3D clocks)
   Optional properties:
   - interconnects: Must contain entry for the GR3D memory clients.
   - interconnect-names: Must include name of the interconnect path for each
     interconnect entry. Consult TRM documentation for information about
     available memory clients, see MEMORY CONTROLLER section.
+  - operating-points-v2: See ../bindings/opp/opp.txt for details.
+  - power-domains: Phandles to 3D or core power domain.
 - dc: display controller
   - interconnect-names: Must include name of the interconnect path for each
     interconnect entry. Consult TRM documentation for information about
     available memory clients, see MEMORY CONTROLLER section.
+  - operating-points-v2: See ../bindings/opp/opp.txt for details.
+  - power-domains: Phandle to core power domain.
 - hdmi: High Definition Multimedia Interface
   - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
   - nvidia,edid: supplies a binary EDID blob
   - nvidia,panel: phandle of a display panel
+  - operating-points-v2: See ../bindings/opp/opp.txt for details.
 - tvo: TV encoder output
   - clocks: Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  Optional properties:
+  - operating-points-v2: See ../bindings/opp/opp.txt for details.
+  - power-domains: Phandle to core power domain.
 - dsi: display serial interface
   Required properties:
   - nvidia,panel: phandle of a display panel
   - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
     up with in order to support up to 8 data lanes
+  - operating-points-v2: See ../bindings/opp/opp.txt for details.
 - sor: serial output resource
 		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
 		resets = <&tegra_car 28>;
 		reset-names = "host1x";
+		operating-points-v2 = <&dvfs_opp_table>;
+		power-domains = <&domain>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 			clocks = <&tegra_car TEGRA20_CLK_MPE>;
 			resets = <&tegra_car 60>;
 			reset-names = "mpe";
+			operating-points-v2 = <&dvfs_opp_table>;
+			power-domains = <&domain>;
 		};
 		vi@54080000 {
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
 			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+			operating-points-v2 = <&dvfs_opp_table>;
 			clocks = <&tegra_car TEGRA210_CLK_VI>;
 			power-domains = <&pd_venc>;
 			clocks = <&tegra_car TEGRA20_CLK_EPP>;
 			resets = <&tegra_car 19>;
 			reset-names = "epp";
+			operating-points-v2 = <&dvfs_opp_table>;
+			power-domains = <&domain>;
 		};
 		isp {
 			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
 			resets = <&tegra_car 21>;
 			reset-names = "2d";
+			operating-points-v2 = <&dvfs_opp_table>;
+			power-domains = <&domain>;
 		};
 		gr3d {
 			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
 			resets = <&tegra_car 24>;
 			reset-names = "3d";
+			operating-points-v2 = <&dvfs_opp_table>;
+			power-domains = <&domain>;
 		};
 		dc@54200000 {
 			clock-names = "dc", "parent";
 			resets = <&tegra_car 27>;
 			reset-names = "dc";
+			operating-points-v2 = <&dvfs_opp_table>;
+			power-domains = <&domain>;
 			interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
 					<&mc TEGRA20_MC_DISPLAY0B &emc>,
 			clock-names = "dc", "parent";
 			resets = <&tegra_car 26>;
 			reset-names = "dc";
+			operating-points-v2 = <&dvfs_opp_table>;
+			power-domains = <&domain>;
 			interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
 					<&mc TEGRA20_MC_DISPLAY0BB &emc>,
 			resets = <&tegra_car 51>;
 			reset-names = "hdmi";
 			status = "disabled";
+			operating-points-v2 = <&dvfs_opp_table>;
 		};
 		tvo {
 			interrupts = <0 76 0x04>;
 			clocks = <&tegra_car TEGRA20_CLK_TVO>;
 			status = "disabled";
+			operating-points-v2 = <&dvfs_opp_table>;
 		};
 		dsi {
 			resets = <&tegra_car 48>;
 			reset-names = "dsi";
 			status = "disabled";
+			operating-points-v2 = <&dvfs_opp_table>;
 		};
 	};

Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt+0−107

@@ -1,107 +0,0 @@
1	NVIDIA Tegra Boot and Power Management Processor (BPMP)
2
3	The BPMP is a specific processor in Tegra chip, which is designed for
4	booting process handling and offloading the power management, clock
5	management, and reset control tasks from the CPU. The binding document
6	defines the resources that would be used by the BPMP firmware driver,
7	which can create the interprocessor communication (IPC) between the CPU
8	and BPMP.
9
10	Required properties:
11	- compatible
12	Array of strings
13	One of:
14	- "nvidia,tegra186-bpmp"
15	- mboxes : The phandle of mailbox controller and the mailbox specifier.
16	- shmem : List of the phandle of the TX and RX shared memory area that
17	the IPC between CPU and BPMP is based on.
18	- #clock-cells : Should be 1.
19	- #power-domain-cells : Should be 1.
20	- #reset-cells : Should be 1.
21
22	This node is a mailbox consumer. See the following files for details of
23	the mailbox subsystem, and the specifiers implemented by the relevant
24	provider(s):
25
26	- .../mailbox/mailbox.txt
27	- .../mailbox/nvidia,tegra186-hsp.txt
28
29	This node is a clock, power domain, and reset provider. See the following
30	files for general documentation of those features, and the specifiers
31	implemented by this node:
32
33	- .../clock/clock-bindings.txt
34	- <dt-bindings/clock/tegra186-clock.h>
35	- ../power/power-domain.yaml
36	- <dt-bindings/power/tegra186-powergate.h>
37	- .../reset/reset.txt
38	- <dt-bindings/reset/tegra186-reset.h>
39
40	The BPMP implements some services which must be represented by separate nodes.
41	For example, it can provide access to certain I2C controllers, and the I2C
42	bindings represent each I2C controller as a device tree node. Such nodes should
43	be nested directly inside the main BPMP node.
44
45	Software can determine whether a child node of the BPMP node represents a device
46	by checking for a compatible property. Any node with a compatible property
47	represents a device that can be instantiated. Nodes without a compatible
48	property may be used to provide configuration information regarding the BPMP
49	itself, although no such configuration nodes are currently defined by this
50	binding.
51
52	The BPMP firmware defines no single global name-/numbering-space for such
53	services. Put another way, the numbering scheme for I2C buses is distinct from
54	the numbering scheme for any other service the BPMP may provide (e.g. a future
55	hypothetical SPI bus service). As such, child device nodes will have no reg
56	property, and the BPMP node will have no #address-cells or #size-cells property.
57
58	The shared memory bindings for BPMP
59	-----------------------------------
60
61	The shared memory area for the IPC TX and RX between CPU and BPMP are
62	predefined and work on top of sysram, which is an SRAM inside the chip.
63
64	See ".../sram/sram.txt" for the bindings.
65
66	Example:
67
68	hsp_top0: hsp@3c00000 {
69	...
70	#mbox-cells = <2>;
71	};
72
73	sysram@30000000 {
74	compatible = "nvidia,tegra186-sysram", "mmio-sram";
75	reg = <0x0 0x30000000 0x0 0x50000>;
76	#address-cells = <2>;
77	#size-cells = <2>;
78	ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
79
80	cpu_bpmp_tx: shmem@4e000 {
81	compatible = "nvidia,tegra186-bpmp-shmem";
82	reg = <0x0 0x4e000 0x0 0x1000>;
83	label = "cpu-bpmp-tx";
84	pool;
85	};
86
87	cpu_bpmp_rx: shmem@4f000 {
88	compatible = "nvidia,tegra186-bpmp-shmem";
89	reg = <0x0 0x4f000 0x0 0x1000>;
90	label = "cpu-bpmp-rx";
91	pool;
92	};
93	};
94
95	bpmp {
96	compatible = "nvidia,tegra186-bpmp";
97	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
98	shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
99	#clock-cells = <1>;
100	#power-domain-cells = <1>;
101	#reset-cells = <1>;
102
103	i2c {
104	compatible = "...";
105	...
106	};
107	};

Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml+186−0

@@ -0,0 +1,186 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	description: \|
	14	The BPMP is a specific processor in Tegra chip, which is designed for
	15	booting process handling and offloading the power management, clock
	16	management, and reset control tasks from the CPU. The binding document
	17	defines the resources that would be used by the BPMP firmware driver,
	18	which can create the interprocessor communication (IPC) between the
	19	CPU and BPMP.
	20
	21	This node is a mailbox consumer. See the following files for details
	22	of the mailbox subsystem, and the specifiers implemented by the
	23	relevant provider(s):
	24
	25	- .../mailbox/mailbox.txt
	26	- .../mailbox/nvidia,tegra186-hsp.yaml
	27
	28	This node is a clock, power domain, and reset provider. See the
	29	following files for general documentation of those features, and the
	30	specifiers implemented by this node:
	31
	32	- .../clock/clock-bindings.txt
	33	- <dt-bindings/clock/tegra186-clock.h>
	34	- ../power/power-domain.yaml
	35	- <dt-bindings/power/tegra186-powergate.h>
	36	- .../reset/reset.txt
	37	- <dt-bindings/reset/tegra186-reset.h>
	38
	39	The BPMP implements some services which must be represented by
	40	separate nodes. For example, it can provide access to certain I2C
	41	controllers, and the I2C bindings represent each I2C controller as a
	42	device tree node. Such nodes should be nested directly inside the main
	43	BPMP node.
	44
	45	Software can determine whether a child node of the BPMP node
	46	represents a device by checking for a compatible property. Any node
	47	with a compatible property represents a device that can be
	48	instantiated. Nodes without a compatible property may be used to
	49	provide configuration information regarding the BPMP itself, although
	50	no such configuration nodes are currently defined by this binding.
	51
	52	The BPMP firmware defines no single global name-/numbering-space for
	53	such services. Put another way, the numbering scheme for I2C buses is
	54	distinct from the numbering scheme for any other service the BPMP may
	55	provide (e.g. a future hypothetical SPI bus service). As such, child
	56	device nodes will have no reg property, and the BPMP node will have no
	57	"#address-cells" or "#size-cells" property.
	58
	59	The shared memory area for the IPC TX and RX between CPU and BPMP are
	60	predefined and work on top of sysram, which is an SRAM inside the
	61	chip. See ".../sram/sram.yaml" for the bindings.
	62
	63	properties:
	64	compatible:
	65	oneOf:
	66	- items:
	67	- enum:
	68	- nvidia,tegra194-bpmp
	69	- nvidia,tegra234-bpmp
	70	- const: nvidia,tegra186-bpmp
	71	- const: nvidia,tegra186-bpmp
	72
	73	mboxes:
	74	description: A phandle and channel specifier for the mailbox used to
	75	communicate with the BPMP.
	76	maxItems: 1
	77
	78	shmem:
	79	description: List of the phandle to the TX and RX shared memory area
	80	that the IPC between CPU and BPMP is based on.
	81	minItems: 2
	82	maxItems: 2
	83
	84	"#clock-cells":
	85	const: 1
	86
	87	"#power-domain-cells":
	88	const: 1
	89
	90	"#reset-cells":
	91	const: 1
	92
	93	interconnects:
	94	items:
	95	- description: memory read client
	96	- description: memory write client
	97	- description: DMA read client
	98	- description: DMA write client
	99
	100	interconnect-names:
	101	items:
	102	- const: read
	103	- const: write
	104	- const: dma-mem # dma-read
	105	- const: dma-write
	106
	107	iommus:
	108	maxItems: 1
	109
	110	i2c:
	111	type: object
	112
	113	thermal:
	114	type: object
	115
	116	additionalProperties: false
	117
	118	required:
	119	- compatible
	120	- mboxes
	121	- shmem
	122	- "#clock-cells"
	123	- "#power-domain-cells"
	124	- "#reset-cells"
	125
	126	examples:
	127	- \|
	128	#include <dt-bindings/interrupt-controller/arm-gic.h>
	129	#include <dt-bindings/mailbox/tegra186-hsp.h>
	130	#include <dt-bindings/memory/tegra186-mc.h>
	131
	132	hsp_top0: hsp@3c00000 {
	133	compatible = "nvidia,tegra186-hsp";
	134	reg = <0x03c00000 0xa0000>;
	135	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	136	interrupt-names = "doorbell";
	137	#mbox-cells = <2>;
	138	};
	139
	140	sram@30000000 {
	141	compatible = "nvidia,tegra186-sysram", "mmio-sram";
	142	reg = <0x30000000 0x50000>;
	143	#address-cells = <1>;
	144	#size-cells = <1>;
	145	ranges = <0x0 0x30000000 0x50000>;
	146
	147	cpu_bpmp_tx: sram@4e000 {
	148	reg = <0x4e000 0x1000>;
	149	label = "cpu-bpmp-tx";
	150	pool;
	151	};
	152
	153	cpu_bpmp_rx: sram@4f000 {
	154	reg = <0x4f000 0x1000>;
	155	label = "cpu-bpmp-rx";
	156	pool;
	157	};
	158	};
	159
	160	bpmp {
	161	compatible = "nvidia,tegra186-bpmp";
	162	interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
	163	<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
	164	<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
	165	<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
	166	interconnect-names = "read", "write", "dma-mem", "dma-write";
	167	iommus = <&smmu TEGRA186_SID_BPMP>;
	168	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
	169	TEGRA_HSP_DB_MASTER_BPMP>;
	170	shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
	171	#clock-cells = <1>;
	172	#power-domain-cells = <1>;
	173	#reset-cells = <1>;
	174
	175	i2c {
	176	compatible = "nvidia,tegra186-bpmp-i2c";
	177	nvidia,bpmp-bus-id = <5>;
	178	#address-cells = <1>;
	179	#size-cells = <0>;
	180	};
	181
	182	thermal {
	183	compatible = "nvidia,tegra186-bpmp-thermal";
	184	#thermal-sensor-cells = <1>;
	185	};
	186	};

Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt+0−42

@@ -1,42 +0,0 @@
1	NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
2
3	Required properties:
4	- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
5	must contain "nvidia,tegra30-efuse". For Tegra114, must contain
6	"nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
7	For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
8	For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
9	"nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
10	For Tegra234 must contain "nvidia,tegra234-efuse".
11	Details:
12	nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
13	due to a hardware bug. Tegra20 also lacks certain information which is
14	available in later generations such as fab code, lot code, wafer id,..
15	nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
16	The differences between these SoCs are the size of the efuse array,
17	the location of the spare (OEM programmable) bits and the location of
18	the speedo data.
19	- reg: Should contain 1 entry: the entry gives the physical address and length
20	of the fuse registers.
21	- clocks: Must contain an entry for each entry in clock-names.
22	See ../clocks/clock-bindings.txt for details.
23	- clock-names: Must include the following entries:
24	- fuse
25	- resets: Must contain an entry for each entry in reset-names.
26	See ../reset/reset.txt for details.
27	- reset-names: Must include the following entries:
28	- fuse
29
30	Example:
31
32	fuse@7000f800 {
33	compatible = "nvidia,tegra20-efuse";
34	reg = <0x7000f800 0x400>,
35	<0x70000000 0x400>;
36	clocks = <&tegra_car TEGRA20_CLK_FUSE>;
37	clock-names = "fuse";
38	resets = <&tegra_car 39>;
39	reset-names = "fuse";
40	};
41
42

Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml+89−0

@@ -0,0 +1,89 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra FUSE block
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	properties:
	14	compatible:
	15	oneOf:
	16	- enum:
	17	- nvidia,tegra20-efuse
	18	- nvidia,tegra30-efuse
	19	- nvidia,tegra114-efuse
	20	- nvidia,tegra124-efuse
	21	- nvidia,tegra210-efuse
	22	- nvidia,tegra186-efuse
	23	- nvidia,tegra194-efuse
	24	- nvidia,tegra234-efuse
	25
	26	- items:
	27	- const: nvidia,tegra132-efuse
	28	- const: nvidia,tegra124-efuse
	29
	30	reg:
	31	maxItems: 1
	32
	33	clocks:
	34	maxItems: 1
	35
	36	clock-names:
	37	items:
	38	- const: fuse
	39
	40	resets:
	41	maxItems: 1
	42
	43	reset-names:
	44	items:
	45	- const: fuse
	46
	47	operating-points-v2:
	48	$ref: "/schemas/types.yaml#/definitions/phandle"
	49
	50	power-domains:
	51	items:
	52	- description: phandle to the core power domain
	53
	54	additionalProperties: false
	55
	56	required:
	57	- compatible
	58	- reg
	59	- clocks
	60	- clock-names
	61
	62	if:
	63	properties:
	64	compatible:
	65	contains:
	66	enum:
	67	- nvidia,tegra20-efuse
	68	- nvidia,tegra30-efuse
	69	- nvidia,tegra114-efuse
	70	- nvidia,tegra124-efuse
	71	- nvidia,tegra132-efuse
	72	- nvidia,tegra210-efuse
	73	then:
	74	required:
	75	- resets
	76	- reset-names
	77
	78	examples:
	79	- \|
	80	#include <dt-bindings/clock/tegra20-car.h>
	81
	82	fuse@7000f800 {
	83	compatible = "nvidia,tegra20-efuse";
	84	reg = <0x7000f800 0x400>;
	85	clocks = <&tegra_car TEGRA20_CLK_FUSE>;
	86	clock-names = "fuse";
	87	resets = <&tegra_car 39>;
	88	reset-names = "fuse";
	89	};

Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml+135−0

@@ -0,0 +1,135 @@
	1	# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#"
	5	$schema: "http://devicetree.org/meta-schemas/core.yaml#"
	6
	7	title: Device tree binding for NVIDIA Tegra NVENC
	8
	9	description: \|
	10	NVENC is the hardware video encoder present on NVIDIA Tegra210
	11	and newer chips. It is located on the Host1x bus and typically
	12	programmed through Host1x channels.
	13
	14	maintainers:
	15	- Thierry Reding <treding@gmail.com>
	16	- Mikko Perttunen <mperttunen@nvidia.com>
	17
	18	properties:
	19	$nodename:
	20	pattern: "^nvenc@[0-9a-f]*$"
	21
	22	compatible:
	23	enum:
	24	- nvidia,tegra210-nvenc
	25	- nvidia,tegra186-nvenc
	26	- nvidia,tegra194-nvenc
	27
	28	reg:
	29	maxItems: 1
	30
	31	clocks:
	32	maxItems: 1
	33
	34	clock-names:
	35	items:
	36	- const: nvenc
	37
	38	resets:
	39	maxItems: 1
	40
	41	reset-names:
	42	items:
	43	- const: nvenc
	44
	45	power-domains:
	46	maxItems: 1
	47
	48	iommus:
	49	maxItems: 1
	50
	51	dma-coherent: true
	52
	53	interconnects:
	54	minItems: 2
	55	maxItems: 3
	56
	57	interconnect-names:
	58	minItems: 2
	59	maxItems: 3
	60
	61	nvidia,host1x-class:
	62	description: \|
	63	Host1x class of the engine, used to specify the targeted engine
	64	when programming the engine through Host1x channels or when
	65	configuring engine-specific behavior in Host1x.
	66	default: 0x21
	67	$ref: /schemas/types.yaml#/definitions/uint32
	68
	69	required:
	70	- compatible
	71	- reg
	72	- clocks
	73	- clock-names
	74	- resets
	75	- reset-names
	76	- power-domains
	77
	78	allOf:
	79	- if:
	80	properties:
	81	compatible:
	82	enum:
	83	- nvidia,tegra210-nvenc
	84	- nvidia,tegra186-nvenc
	85	then:
	86	properties:
	87	interconnects:
	88	items:
	89	- description: DMA read memory client
	90	- description: DMA write memory client
	91	interconnect-names:
	92	items:
	93	- const: dma-mem
	94	- const: write
	95	- if:
	96	properties:
	97	compatible:
	98	enum:
	99	- nvidia,tegra194-nvenc
	100	then:
	101	properties:
	102	interconnects:
	103	items:
	104	- description: DMA read memory client
	105	- description: DMA read 2 memory client
	106	- description: DMA write memory client
	107	interconnect-names:
	108	items:
	109	- const: dma-mem
	110	- const: read-1
	111	- const: write
	112
	113	additionalProperties: false
	114
	115	examples:
	116	- \|
	117	#include <dt-bindings/clock/tegra186-clock.h>
	118	#include <dt-bindings/memory/tegra186-mc.h>
	119	#include <dt-bindings/power/tegra186-powergate.h>
	120	#include <dt-bindings/reset/tegra186-reset.h>
	121
	122	nvenc@154c0000 {
	123	compatible = "nvidia,tegra186-nvenc";
	124	reg = <0x154c0000 0x40000>;
	125	clocks = <&bpmp TEGRA186_CLK_NVENC>;
	126	clock-names = "nvenc";
	127	resets = <&bpmp TEGRA186_RESET_NVENC>;
	128	reset-names = "nvenc";
	129
	130	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
	131	interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
	132	<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
	133	interconnect-names = "dma-mem", "write";
	134	iommus = <&smmu TEGRA186_SID_NVENC>;
	135	};

Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml+94−0

@@ -0,0 +1,94 @@
	1	# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#"
	5	$schema: "http://devicetree.org/meta-schemas/core.yaml#"
	6
	7	title: Device tree binding for NVIDIA Tegra NVJPG
	8
	9	description: \|
	10	NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210
	11	and newer chips. It is located on the Host1x bus and typically programmed
	12	through Host1x channels.
	13
	14	maintainers:
	15	- Thierry Reding <treding@gmail.com>
	16	- Mikko Perttunen <mperttunen@nvidia.com>
	17
	18	properties:
	19	$nodename:
	20	pattern: "^nvjpg@[0-9a-f]*$"
	21
	22	compatible:
	23	enum:
	24	- nvidia,tegra210-nvjpg
	25	- nvidia,tegra186-nvjpg
	26	- nvidia,tegra194-nvjpg
	27
	28	reg:
	29	maxItems: 1
	30
	31	clocks:
	32	maxItems: 1
	33
	34	clock-names:
	35	items:
	36	- const: nvjpg
	37
	38	resets:
	39	maxItems: 1
	40
	41	reset-names:
	42	items:
	43	- const: nvjpg
	44
	45	power-domains:
	46	maxItems: 1
	47
	48	iommus:
	49	maxItems: 1
	50
	51	dma-coherent: true
	52
	53	interconnects:
	54	items:
	55	- description: DMA read memory client
	56	- description: DMA write memory client
	57
	58	interconnect-names:
	59	items:
	60	- const: dma-mem
	61	- const: write
	62
	63	required:
	64	- compatible
	65	- reg
	66	- clocks
	67	- clock-names
	68	- resets
	69	- reset-names
	70	- power-domains
	71
	72	additionalProperties: false
	73
	74	examples:
	75	- \|
	76	#include <dt-bindings/clock/tegra186-clock.h>
	77	#include <dt-bindings/memory/tegra186-mc.h>
	78	#include <dt-bindings/power/tegra186-powergate.h>
	79	#include <dt-bindings/reset/tegra186-reset.h>
	80
	81	nvjpg@15380000 {
	82	compatible = "nvidia,tegra186-nvjpg";
	83	reg = <0x15380000 0x40000>;
	84	clocks = <&bpmp TEGRA186_CLK_NVJPG>;
	85	clock-names = "nvjpg";
	86	resets = <&bpmp TEGRA186_RESET_NVJPG>;
	87	reset-names = "nvjpg";
	88
	89	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
	90	interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
	91	<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
	92	interconnect-names = "dma-mem", "write";
	93	iommus = <&smmu TEGRA186_SID_NVJPG>;
	94	};

Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt+0−72

@@ -1,72 +0,0 @@
1	NVIDIA Tegra Hardware Synchronization Primitives (HSP)
2
3	The HSP modules are used for the processors to share resources and communicate
4	together. It provides a set of hardware synchronization primitives for
5	interprocessor communication. So the interprocessor communication (IPC)
6	protocols can use hardware synchronization primitives, when operating between
7	two processors not in an SMP relationship.
8
9	The features that HSP supported are shared mailboxes, shared semaphores,
10	arbitrated semaphores and doorbells.
11
12	Required properties:
13	- name : Should be hsp
14	- compatible
15	Array of strings.
16	one of:
17	- "nvidia,tegra186-hsp"
18	- "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"
19	- reg : Offset and length of the register set for the device.
20	- interrupt-names
21	Array of strings.
22	Contains a list of names for the interrupts described by the interrupt
23	property. May contain the following entries, in any order:
24	- "doorbell"
25	- "sharedN", where 'N' is a number from zero up to the number of
26	external interrupts supported by the HSP instance minus one.
27	Users of this binding MUST look up entries in the interrupt property
28	by name, using this interrupt-names property to do so.
29	- interrupts
30	Array of interrupt specifiers.
31	Must contain one entry per entry in the interrupt-names property,
32	in a matching order.
33	- #mbox-cells : Should be 2.
34
35	The mbox specifier of the "mboxes" property in the client node should contain
36	two cells. The first cell determines the HSP type and the second cell is used
37	to identify the mailbox that the client is going to use.
38
39	For doorbells, the second cell specifies the index of the doorbell to use.
40
41	For shared mailboxes, the second cell is composed of two fields:
42	- bits 31..24:
43	A bit mask of flags that further specify how the shared mailbox will be
44	used. Valid flags are:
45	- bit 31:
46	Defines the direction of the mailbox. If set, the mailbox will be used
47	as a producer (i.e. used to send data). If cleared, the mailbox is the
48	consumer of data sent by a producer.
49
50	- bits 23.. 0:
51	The index of the shared mailbox to use. The number of available mailboxes
52	may vary by instance of the HSP block and SoC generation.
53
54	The following file contains definitions that can be used to construct mailbox
55	specifiers:
56
57	<dt-bindings/mailbox/tegra186-hsp.h>
58
59	Example:
60
61	hsp_top0: hsp@3c00000 {
62	compatible = "nvidia,tegra186-hsp";
63	reg = <0x0 0x03c00000 0x0 0xa0000>;
64	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
65	interrupt-names = "doorbell";
66	#mbox-cells = <2>;
67	};
68
69	client {
70	...
71	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>;
72	};

Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml+114−0

@@ -0,0 +1,114 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra Hardware Synchronization Primitives (HSP)
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	description: \|
	14	The HSP modules are used for the processors to share resources and
	15	communicate together. It provides a set of hardware synchronization
	16	primitives for interprocessor communication. So the interprocessor
	17	communication (IPC) protocols can use hardware synchronization
	18	primitives, when operating between two processors not in an SMP
	19	relationship.
	20
	21	The features that HSP supported are shared mailboxes, shared
	22	semaphores, arbitrated semaphores and doorbells.
	23
	24	The mbox specifier of the "mboxes" property in the client node should
	25	contain two cells. The first cell determines the HSP type and the
	26	second cell is used to identify the mailbox that the client is going
	27	to use.
	28
	29	For doorbells, the second cell specifies the index of the doorbell to
	30	use.
	31
	32	For shared mailboxes, the second cell is composed of two fields:
	33	- bits 31..24:
	34	A bit mask of flags that further specify how the shared mailbox
	35	will be used. Valid flags are:
	36	- bit 31:
	37	Defines the direction of the mailbox. If set, the mailbox
	38	will be used as a producer (i.e. used to send data). If
	39	cleared, the mailbox is the consumer of data sent by a
	40	producer.
	41
	42	- bits 23..0:
	43	The index of the shared mailbox to use. The number of available
	44	mailboxes may vary by instance of the HSP block and SoC
	45	generation.
	46
	47	The following file contains definitions that can be used to
	48	construct mailbox specifiers:
	49
	50	<dt-bindings/mailbox/tegra186-hsp.h>
	51
	52	properties:
	53	$nodename:
	54	pattern: "^hsp@[0-9a-f]+$"
	55
	56	compatible:
	57	oneOf:
	58	- const: nvidia,tegra186-hsp
	59	- const: nvidia,tegra194-hsp
	60	- items:
	61	- const: nvidia,tegra234-hsp
	62	- const: nvidia,tegra194-hsp
	63
	64	reg:
	65	maxItems: 1
	66
	67	interrupts:
	68	minItems: 1
	69	maxItems: 9
	70
	71	interrupt-names:
	72	oneOf:
	73	# shared interrupts are optional
	74	- items:
	75	- const: doorbell
	76
	77	- items:
	78	- const: doorbell
	79	- pattern: "^shared[0-7]$"
	80	- pattern: "^shared[0-7]$"
	81	- pattern: "^shared[0-7]$"
	82	- pattern: "^shared[0-7]$"
	83	- pattern: "^shared[0-7]$"
	84	- pattern: "^shared[0-7]$"
	85	- pattern: "^shared[0-7]$"
	86	- pattern: "^shared[0-7]$"
	87
	88	- items:
	89	- pattern: "^shared[0-7]$"
	90	- pattern: "^shared[0-7]$"
	91	- pattern: "^shared[0-7]$"
	92	- pattern: "^shared[0-7]$"
	93
	94	"#mbox-cells":
	95	const: 2
	96
	97	additionalProperties: false
	98
	99	examples:
	100	- \|
	101	#include <dt-bindings/interrupt-controller/arm-gic.h>
	102	#include <dt-bindings/mailbox/tegra186-hsp.h>
	103
	104	hsp_top0: hsp@3c00000 {
	105	compatible = "nvidia,tegra186-hsp";
	106	reg = <0x03c00000 0xa0000>;
	107	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	108	interrupt-names = "doorbell";
	109	#mbox-cells = <2>;
	110	};
	111
	112	client {
	113	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>;
	114	};

Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt+0−64

@@ -1,64 +0,0 @@
1	NVIDIA Tegra Video Decoder Engine
2
3	Required properties:
4	- compatible : Must contain one of the following values:
5	- "nvidia,tegra20-vde"
6	- "nvidia,tegra30-vde"
7	- "nvidia,tegra114-vde"
8	- "nvidia,tegra124-vde"
9	- "nvidia,tegra132-vde"
10	- reg : Must contain an entry for each entry in reg-names.
11	- reg-names : Must include the following entries:
12	- sxe
13	- bsev
14	- mbe
15	- ppe
16	- mce
17	- tfe
18	- ppb
19	- vdma
20	- frameid
21	- iram : Must contain phandle to the mmio-sram device node that represents
22	IRAM region used by VDE.
23	- interrupts : Must contain an entry for each entry in interrupt-names.
24	- interrupt-names : Must include the following entries:
25	- sync-token
26	- bsev
27	- sxe
28	- clocks : Must include the following entries:
29	- vde
30	- resets : Must contain an entry for each entry in reset-names.
31	- reset-names : Should include the following entries:
32	- vde
33
34	Optional properties:
35	- resets : Must contain an entry for each entry in reset-names.
36	- reset-names : Must include the following entries:
37	- mc
38	- iommus: Must contain phandle to the IOMMU device node.
39
40	Example:
41
42	video-codec@6001a000 {
43	compatible = "nvidia,tegra20-vde";
44	reg = <0x6001a000 0x1000 /* Syntax Engine */
45	0x6001b000 0x1000 /* Video Bitstream Engine */
46	0x6001c000 0x100 /* Macroblock Engine */
47	0x6001c200 0x100 /* Post-processing Engine */
48	0x6001c400 0x100 /* Motion Compensation Engine */
49	0x6001c600 0x100 /* Transform Engine */
50	0x6001c800 0x100 /* Pixel prediction block */
51	0x6001ca00 0x100 /* Video DMA */
52	0x6001d800 0x300 /* Video frame controls */>;
53	reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
54	"tfe", "ppb", "vdma", "frameid";
55	iram = <&vde_pool>; /* IRAM region */
56	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
57	<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
58	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
59	interrupt-names = "sync-token", "bsev", "sxe";
60	clocks = <&tegra_car TEGRA20_CLK_VDE>;
61	reset-names = "vde", "mc";
62	resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
63	iommus = <&mc TEGRA_SWGROUP_VDE>;
64	};

Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml+119−0

@@ -0,0 +1,119 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra Video Decoder Engine
	8
	9	maintainers:
	10	- Dmitry Osipenko <digetx@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12	- Thierry Reding <thierry.reding@gmail.com>
	13
	14	properties:
	15	compatible:
	16	oneOf:
	17	- items:
	18	- enum:
	19	- nvidia,tegra132-vde
	20	- nvidia,tegra124-vde
	21	- nvidia,tegra114-vde
	22	- items:
	23	- const: nvidia,tegra30-vde
	24	- const: nvidia,tegra20-vde
	25	- items:
	26	- const: nvidia,tegra20-vde
	27
	28	reg:
	29	maxItems: 9
	30
	31	reg-names:
	32	items:
	33	- const: sxe
	34	- const: bsev
	35	- const: mbe
	36	- const: ppe
	37	- const: mce
	38	- const: tfe
	39	- const: ppb
	40	- const: vdma
	41	- const: frameid
	42
	43	clocks:
	44	maxItems: 1
	45
	46	resets:
	47	maxItems: 2
	48
	49	reset-names:
	50	items:
	51	- const: vde
	52	- const: mc
	53
	54	interrupts:
	55	maxItems: 3
	56
	57	interrupt-names:
	58	items:
	59	- const: sync-token
	60	- const: bsev
	61	- const: sxe
	62
	63	iommus:
	64	maxItems: 1
	65
	66	iram:
	67	$ref: /schemas/types.yaml#/definitions/phandle
	68	description:
	69	Phandle of the SRAM MMIO node.
	70
	71	operating-points-v2:
	72	description:
	73	Should contain freqs and voltages and opp-supported-hw property,
	74	which is a bitfield indicating SoC speedo or process ID mask.
	75
	76	power-domains:
	77	maxItems: 1
	78	description:
	79	Phandle to the SoC core power domain.
	80
	81	required:
	82	- compatible
	83	- reg
	84	- reg-names
	85	- clocks
	86	- resets
	87	- reset-names
	88	- interrupts
	89	- interrupt-names
	90
	91	additionalProperties: false
	92
	93	examples:
	94	- \|
	95	video-codec@6001a000 {
	96	compatible = "nvidia,tegra20-vde";
	97	reg = <0x6001a000 0x1000>, /* Syntax Engine */
	98	<0x6001b000 0x1000>, /* Video Bitstream Engine */
	99	<0x6001c000 0x100>, /* Macroblock Engine */
	100	<0x6001c200 0x100>, /* Post-processing Engine */
	101	<0x6001c400 0x100>, /* Motion Compensation Engine */
	102	<0x6001c600 0x100>, /* Transform Engine */
	103	<0x6001c800 0x100>, /* Pixel prediction block */
	104	<0x6001ca00 0x100>, /* Video DMA */
	105	<0x6001d800 0x300>; /* Video frame controls */
	106	reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
	107	"tfe", "ppb", "vdma", "frameid";
	108	iram = <&iram>; /* IRAM MMIO region */
	109	interrupts = <0 9 4>, /* Sync token */
	110	<0 10 4>, /* BSE-V */
	111	<0 12 4>; /* SXE */
	112	interrupt-names = "sync-token", "bsev", "sxe";
	113	clocks = <&clk 61>;
	114	reset-names = "vde", "mc";
	115	resets = <&rst 61>, <&mem 13>;
	116	iommus = <&mem 15>;
	117	operating-points-v2 = <&dvfs_opp_table>;
	118	power-domains = <&domain>;
	119	};

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml+87−11

@@ -31,12 +31,15 @@ properties: · 30 unmodified lines
31	- enum:	31	- enum:
32	- nvidia,tegra186-mc	32	- nvidia,tegra186-mc
33	- nvidia,tegra194-mc	33	- nvidia,tegra194-mc
		34	- nvidia,tegra234-mc
34		35
35	reg:	36	reg:
36	maxItems: 1	37	minItems: 1
		38	maxItems: 3
37		39
38	interrupts:	40	interrupts:
39	maxItems: 1	41	items:
		42	- description: MC general interrupt
40		43
41	"#address-cells":	44	"#address-cells":
42	const: 2	45	const: 2
@@ -48,6 +51,9 @@ properties: · 5 unmodified lines
48		51
49	dma-ranges: true	52	dma-ranges: true
50		53
		54	"#interconnect-cells":
		55	const: 1
		56
51	patternProperties:	57	patternProperties:
52	"^external-memory-controller@[0-9a-f]+$":	58	"^external-memory-controller@[0-9a-f]+$":
53	description:	59	description:
@@ -63,12 +69,15 @@ patternProperties: · 9 unmodified lines
63	- enum:	69	- enum:
64	- nvidia,tegra186-emc	70	- nvidia,tegra186-emc
65	- nvidia,tegra194-emc	71	- nvidia,tegra194-emc
		72	- nvidia,tegra234-emc
66		73
67	reg:	74	reg:
68	maxItems: 1	75	minItems: 1
		76	maxItems: 2
69		77
70	interrupts:	78	interrupts:
71	maxItems: 1	79	items:
		80	- description: EMC general interrupt
72		81
73	clocks:	82	clocks:
74	items:	83	items:
@@ -78,11 +87,83 @@ patternProperties: · 3 unmodified lines
78	items:	87	items:
79	- const: emc	88	- const: emc
80		89
		90	"#interconnect-cells":
		91	const: 0
		92
81	nvidia,bpmp:	93	nvidia,bpmp:
82	$ref: /schemas/types.yaml#/definitions/phandle	94	$ref: /schemas/types.yaml#/definitions/phandle
83	description:	95	description:
84	phandle of the node representing the BPMP	96	phandle of the node representing the BPMP
85		97
		98	allOf:
		99	- if:
		100	properties:
		101	compatible:
		102	const: nvidia,tegra186-emc
		103	then:
		104	properties:
		105	reg:
		106	maxItems: 1
		107
		108	- if:
		109	properties:
		110	compatible:
		111	const: nvidia,tegra194-emc
		112	then:
		113	properties:
		114	reg:
		115	minItems: 2
		116
		117	- if:
		118	properties:
		119	compatible:
		120	const: nvidia,tegra234-emc
		121	then:
		122	properties:
		123	reg:
		124	minItems: 2
		125
		126	additionalProperties: false
		127
		128	required:
		129	- compatible
		130	- reg
		131	- interrupts
		132	- clocks
		133	- clock-names
		134	- "#interconnect-cells"
		135	- nvidia,bpmp
		136
		137	allOf:
		138	- if:
		139	properties:
		140	compatible:
		141	const: nvidia,tegra186-mc
		142	then:
		143	properties:
		144	reg:
		145	maxItems: 1
		146
		147	- if:
		148	properties:
		149	compatible:
		150	const: nvidia,tegra194-mc
		151	then:
		152	properties:
		153	reg:
		154	minItems: 3
		155
		156	- if:
		157	properties:
		158	compatible:
		159	const: nvidia,tegra234-mc
		160	then:
		161	properties:
		162	reg:
		163	minItems: 3
		164
		165	additionalProperties: false
		166
86	required:	167	required:
87	- compatible	168	- compatible
88	- reg	169	- reg
@@ -90,8 +171,6 @@ required: · 1 unmodified line
90	- "#address-cells"	171	- "#address-cells"
91	- "#size-cells"	172	- "#size-cells"
92		173
93	additionalProperties: false
94
95	examples:	174	examples:
96	- \|	175	- \|
97	#include <dt-bindings/clock/tegra186-clock.h>	176	#include <dt-bindings/clock/tegra186-clock.h>
@@ -124,12 +203,9 @@ examples: · 26 unmodified lines
124	clocks = <&bpmp TEGRA186_CLK_EMC>;	203	clocks = <&bpmp TEGRA186_CLK_EMC>;
125	clock-names = "emc";	204	clock-names = "emc";
126		205
		206	#interconnect-cells = <0>;
		207
127	nvidia,bpmp = <&bpmp>;	208	nvidia,bpmp = <&bpmp>;
128	};	209	};
129	};	210	};
130	};	211	};
131
132	bpmp: bpmp {
133	compatible = "nvidia,tegra186-bpmp";
134	#clock-cells = <1>;
135	};

Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt+0−14

@@ -1,14 +0,0 @@
1	NVIDIA Tegra186 (and later) MISC register block
2
3	The MISC register block found on Tegra186 and later SoCs contains registers
4	that can be used to identify a given chip and various strapping options.
5
6	Required properties:
7	- compatible: Must be:
8	- Tegra186: "nvidia,tegra186-misc"
9	- Tegra194: "nvidia,tegra194-misc"
10	- Tegra234: "nvidia,tegra234-misc"
11	- reg: Should contain 2 entries: The first entry gives the physical address
12	and length of the register region which contains revision and debug
13	features. The second entry specifies the physical address and length
14	of the register region indicating the strapping options.

Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml+43−0

@@ -0,0 +1,43 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra186 (and later) MISC register block
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	description: The MISC register block found on Tegra186 and later SoCs contains
	14	registers that can be used to identify a given chip and various strapping
	15	options.
	16
	17	properties:
	18	compatible:
	19	enum:
	20	- nvidia,tegra186-misc
	21	- nvidia,tegra194-misc
	22	- nvidia,tegra234-misc
	23
	24	reg:
	25	items:
	26	- description: physical address and length of the registers which
	27	contain revision and debug features
	28	- description: physical address and length of the registers which
	29	indicate strapping options
	30
	31	additionalProperties: false
	32
	33	required:
	34	- compatible
	35	- reg
	36
	37	examples:
	38	- \|
	39	misc@100000 {
	40	compatible = "nvidia,tegra186-misc";
	41	reg = <0x00100000 0xf000>,
	42	<0x0010f000 0x1000>;
	43	};

Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt+0−17

@@ -1,17 +0,0 @@
1	NVIDIA Tegra APBMISC block
2
3	Required properties:
4	- compatible: Must be:
5	- Tegra20: "nvidia,tegra20-apbmisc"
6	- Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"
7	- Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"
8	- Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
9	- Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
10	- Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"
11	- reg: Should contain 2 entries: the first entry gives the physical address
12	and length of the registers which contain revision and debug features.
13	The second entry gives the physical address and length of the
14	registers indicating the strapping options.
15
16	Optional properties:
17	- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).

Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml+51−0

@@ -0,0 +1,51 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra APBMISC block
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	properties:
	14	compatible:
	15	oneOf:
	16	- items:
	17	- enum:
	18	- nvidia,tegra210-apbmisc
	19	- nvidia,tegra124-apbmisc
	20	- nvidia,tegra114-apbmisc
	21	- nvidia,tegra30-apbmisc
	22	- const: nvidia,tegra20-apbmisc
	23
	24	- items:
	25	- const: nvidia,tegra20-apbmisc
	26
	27	reg:
	28	items:
	29	- description: physical address and length of the registers which
	30	contain revision and debug features
	31	- description: physical address and length of the registers which
	32	indicate strapping options
	33
	34	nvidia,long-ram-code:
	35	description: If present, the RAM code is long (4 bit). If not, short
	36	(2 bit).
	37	type: boolean
	38
	39	additionalProperties: false
	40
	41	required:
	42	- compatible
	43	- reg
	44
	45	examples:
	46	- \|
	47	apbmisc@70000800 {
	48	compatible = "nvidia,tegra20-apbmisc";
	49	reg = <0x70000800 0x64>, /* Chip revision */
	50	<0x70000008 0x04>; /* Strapping options */
	51	};

Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt+0−143

@@ -1,143 +0,0 @@
1	* NVIDIA Tegra Secure Digital Host Controller
2
3	This controller on Tegra family SoCs provides an interface for MMC, SD,
4	and SDIO types of memory cards.
5
6	This file documents differences between the core properties described
7	by mmc.txt and the properties used by the sdhci-tegra driver.
8
9	Required properties:
10	- compatible : should be one of:
11	- "nvidia,tegra20-sdhci": for Tegra20
12	- "nvidia,tegra30-sdhci": for Tegra30
13	- "nvidia,tegra114-sdhci": for Tegra114
14	- "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
15	- "nvidia,tegra210-sdhci": for Tegra210
16	- "nvidia,tegra186-sdhci": for Tegra186
17	- "nvidia,tegra194-sdhci": for Tegra194
18	- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
19	One for the module clock and one for the timeout clock.
20	For all other Tegra devices, must contain a single entry for
21	the module clock. See ../clocks/clock-bindings.txt for details.
22	- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the
23	strings 'sdhci' and 'tmclk' to represent the module and
24	the timeout clocks, respectively.
25	For all other Tegra devices must contain the string 'sdhci'
26	to represent the module clock.
27	- resets : Must contain an entry for each entry in reset-names.
28	See ../reset/reset.txt for details.
29	- reset-names : Must include the following entries:
30	- sdhci
31
32	Optional properties:
33	- power-gpios : Specify GPIOs for power control
34
35	Example:
36
37	sdhci@c8000200 {
38	compatible = "nvidia,tegra20-sdhci";
39	reg = <0xc8000200 0x200>;
40	interrupts = <47>;
41	clocks = <&tegra_car 14>;
42	resets = <&tegra_car 14>;
43	reset-names = "sdhci";
44	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
45	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
46	power-gpios = <&gpio 155 0>; /* gpio PT3 */
47	bus-width = <8>;
48	};
49
50	Optional properties for Tegra210, Tegra186 and Tegra194:
51	- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
52	configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
53	for controllers supporting multiple voltage levels. The order of names
54	should correspond to the pin configuration states in pinctrl-0 and
55	pinctrl-1.
56	- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
57	Tegra210 where pad config registers are in the pinmux register domain
58	for pull-up-strength and pull-down-strength values configuration when
59	using pads at 3V3 and 1V8 levels.
60	- nvidia,only-1-8-v : The presence of this property indicates that the
61	controller operates at a 1.8 V fixed I/O voltage.
62	- nvidia,pad-autocal-pull-up-offset-3v3,
63	nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
64	calibration offsets for 3.3 V signaling modes.
65	- nvidia,pad-autocal-pull-up-offset-1v8,
66	nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
67	calibration offsets for 1.8 V signaling modes.
68	- nvidia,pad-autocal-pull-up-offset-3v3-timeout,
69	nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
70	strength used as a fallback in case the automatic calibration times
71	out on a 3.3 V signaling mode.
72	- nvidia,pad-autocal-pull-up-offset-1v8-timeout,
73	nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
74	strength used as a fallback in case the automatic calibration times
75	out on a 1.8 V signaling mode.
76	- nvidia,pad-autocal-pull-up-offset-sdr104,
77	nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength
78	calibration offsets for SDR104 mode.
79	- nvidia,pad-autocal-pull-up-offset-hs400,
80	nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
81	calibration offsets for HS400 mode.
82	- nvidia,default-tap : Specify the default inbound sampling clock
83	trimmer value for non-tunable modes.
84	- nvidia,default-trim : Specify the default outbound clock trimmer
85	value.
86	- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
87
88	Notes on the pad calibration pull up and pulldown offset values:
89	- The property values are drive codes which are programmed into the
90	PD_OFFSET and PU_OFFSET sections of the
91	SDHCI_TEGRA_AUTO_CAL_CONFIG register.
92	- A higher value corresponds to higher drive strength. Please refer
93	to the reference manual of the SoC for correct values.
94	- The SDR104 and HS400 timing specific values are used in
95	corresponding modes if specified.
96
97	Notes on tap and trim values:
98	- The values are used for compensating trace length differences
99	by adjusting the sampling point.
100	- The values are programmed to the Vendor Clock Control Register.
101	Please refer to the reference manual of the SoC for correct
102	values.
103	- The DQS trim values are only used on controllers which support
104	HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
105	HS400.
106
107	Example:
108	sdhci@700b0000 {
109	compatible = "nvidia,tegra124-sdhci";
110	reg = <0x0 0x700b0000 0x0 0x200>;
111	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
112	clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
113	clock-names = "sdhci";
114	resets = <&tegra_car 14>;
115	reset-names = "sdhci";
116	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
117	pinctrl-0 = <&sdmmc1_3v3>;
118	pinctrl-1 = <&sdmmc1_1v8>;
119	nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
120	nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
121	nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
122	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
123	status = "disabled";
124	};
125
126	sdhci@700b0000 {
127	compatible = "nvidia,tegra210-sdhci";
128	reg = <0x0 0x700b0000 0x0 0x200>;
129	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
130	clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
131	<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
132	clock-names = "sdhci", "tmclk";
133	resets = <&tegra_car 14>;
134	reset-names = "sdhci";
135	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
136	pinctrl-0 = <&sdmmc1_3v3>;
137	pinctrl-1 = <&sdmmc1_1v8>;
138	nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
139	nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
140	nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
141	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
142	status = "disabled";
143	};

Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml+317−0

@@ -0,0 +1,317 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra Secure Digital Host Controller
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	description: \|
	14	This controller on Tegra family SoCs provides an interface for MMC, SD, and
	15	SDIO types of memory cards.
	16
	17	This file documents differences between the core properties described by
	18	mmc-controller.yaml and the properties for the Tegra SDHCI controller.
	19
	20	properties:
	21	compatible:
	22	oneOf:
	23	- enum:
	24	- nvidia,tegra20-sdhci
	25	- nvidia,tegra30-sdhci
	26	- nvidia,tegra114-sdhci
	27	- nvidia,tegra124-sdhci
	28	- nvidia,tegra210-sdhci
	29	- nvidia,tegra186-sdhci
	30	- nvidia,tegra194-sdhci
	31
	32	- items:
	33	- const: nvidia,tegra132-sdhci
	34	- const: nvidia,tegra124-sdhci
	35
	36	- items:
	37	- enum:
	38	- nvidia,tegra194-sdhci
	39	- nvidia,tegra234-sdhci
	40	- const: nvidia,tegra186-sdhci
	41
	42	reg:
	43	maxItems: 1
	44
	45	interrupts:
	46	maxItems: 1
	47
	48	assigned-clocks: true
	49	assigned-clock-parents: true
	50	assigned-clock-rates: true
	51
	52	clocks:
	53	minItems: 1
	54	maxItems: 2
	55
	56	clock-names:
	57	minItems: 1
	58	maxItems: 2
	59
	60	resets:
	61	items:
	62	- description: module reset
	63
	64	reset-names:
	65	items:
	66	- const: sdhci
	67
	68	power-gpios:
	69	description: specify GPIOs for power control
	70	maxItems: 1
	71
	72	interconnects:
	73	items:
	74	- description: memory read client
	75	- description: memory write client
	76
	77	interconnect-names:
	78	items:
	79	- const: dma-mem # read
	80	- const: write
	81
	82	iommus:
	83	maxItems: 1
	84
	85	operating-points-v2:
	86	$ref: "/schemas/types.yaml#/definitions/phandle"
	87
	88	power-domains:
	89	items:
	90	- description: phandle to the core power domain
	91
	92	nvidia,default-tap:
	93	description: Specify the default inbound sampling clock trimmer value for
	94	non-tunable modes.
	95
	96	The values are used for compensating trace length differences by
	97	adjusting the sampling point. The values are programmed to the Vendor
	98	Clock Control Register. Please refer to the reference manual of the SoC
	99	for correct values.
	100
	101	The DQS trim values are only used on controllers which support HS400
	102	timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
	103	$ref: "/schemas/types.yaml#/definitions/uint32"
	104
	105	nvidia,default-trim:
	106	description: Specify the default outbound clock trimmer value.
	107	$ref: "/schemas/types.yaml#/definitions/uint32"
	108
	109	nvidia,dqs-trim:
	110	description: Specify DQS trim value for HS400 timing.
	111	$ref: "/schemas/types.yaml#/definitions/uint32"
	112
	113	nvidia,pad-autocal-pull-down-offset-1v8:
	114	description: Specify drive strength calibration offsets for 1.8 V
	115	signaling modes.
	116	$ref: "/schemas/types.yaml#/definitions/uint32"
	117
	118	nvidia,pad-autocal-pull-down-offset-1v8-timeout:
	119	description: Specify drive strength used as a fallback in case the
	120	automatic calibration times out on a 1.8 V signaling mode.
	121	$ref: "/schemas/types.yaml#/definitions/uint32"
	122
	123	nvidia,pad-autocal-pull-down-offset-3v3:
	124	description: Specify drive strength calibration offsets for 3.3 V
	125	signaling modes.
	126	$ref: "/schemas/types.yaml#/definitions/uint32"
	127
	128	nvidia,pad-autocal-pull-down-offset-3v3-timeout:
	129	description: Specify drive strength used as a fallback in case the
	130	automatic calibration times out on a 3.3 V signaling mode.
	131	$ref: "/schemas/types.yaml#/definitions/uint32"
	132
	133	nvidia,pad-autocal-pull-down-offset-sdr104:
	134	description: Specify drive strength calibration offsets for SDR104 mode.
	135	$ref: "/schemas/types.yaml#/definitions/uint32"
	136
	137	nvidia,pad-autocal-pull-down-offset-hs400:
	138	description: Specify drive strength calibration offsets for HS400 mode.
	139	$ref: "/schemas/types.yaml#/definitions/uint32"
	140
	141	nvidia,pad-autocal-pull-up-offset-1v8:
	142	description: Specify drive strength calibration offsets for 1.8 V
	143	signaling modes.
	144	$ref: "/schemas/types.yaml#/definitions/uint32"
	145
	146	nvidia,pad-autocal-pull-up-offset-1v8-timeout:
	147	description: Specify drive strength used as a fallback in case the
	148	automatic calibration times out on a 1.8 V signaling mode.
	149	$ref: "/schemas/types.yaml#/definitions/uint32"
	150
	151	nvidia,pad-autocal-pull-up-offset-3v3:
	152	description: Specify drive strength calibration offsets for 3.3 V
	153	signaling modes.
	154
	155	The property values are drive codes which are programmed into the
	156	PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG
	157	register. A higher value corresponds to higher drive strength. Please
	158	refer to the reference manual of the SoC for correct values. The SDR104
	159	and HS400 timing specific values are used in corresponding modes if
	160	specified.
	161	$ref: "/schemas/types.yaml#/definitions/uint32"
	162
	163	nvidia,pad-autocal-pull-up-offset-3v3-timeout:
	164	description: Specify drive strength used as a fallback in case the
	165	automatic calibration times out on a 3.3 V signaling mode.
	166	$ref: "/schemas/types.yaml#/definitions/uint32"
	167
	168	nvidia,pad-autocal-pull-up-offset-sdr104:
	169	description: Specify drive strength calibration offsets for SDR104 mode.
	170	$ref: "/schemas/types.yaml#/definitions/uint32"
	171
	172	nvidia,pad-autocal-pull-up-offset-hs400:
	173	description: Specify drive strength calibration offsets for HS400 mode.
	174	$ref: "/schemas/types.yaml#/definitions/uint32"
	175
	176	nvidia,only-1-8v:
	177	description: The presence of this property indicates that the controller
	178	operates at a 1.8 V fixed I/O voltage.
	179	$ref: "/schemas/types.yaml#/definitions/flag"
	180
	181	required:
	182	- compatible
	183	- reg
	184	- interrupts
	185	- clocks
	186	- resets
	187	- reset-names
	188
	189	allOf:
	190	- $ref: "mmc-controller.yaml"
	191	- if:
	192	properties:
	193	compatible:
	194	contains:
	195	enum:
	196	- nvidia,tegra20-sdhci
	197	- nvidia,tegra30-sdhci
	198	- nvidia,tegra114-sdhci
	199	- nvidia,tegra124-sdhci
	200	clocks:
	201	items:
	202	- description: module clock
	203	minItems: 1
	204	maxItems: 1
	205	else:
	206	properties:
	207	clocks:
	208	items:
	209	- description: module clock
	210	- description: timeout clock
	211	minItems: 2
	212	maxItems: 2
	213	clock-names:
	214	items:
	215	- const: sdhci
	216	- const: tmclk
	217	minItems: 2
	218	maxItems: 2
	219	required:
	220	- clock-names
	221
	222	- if:
	223	properties:
	224	compatible:
	225	contains:
	226	const: nvidia,tegra210-sdhci
	227	then:
	228	properties:
	229	pinctrl-names:
	230	oneOf:
	231	- items:
	232	- const: sdmmc-3v3
	233	description: pad configuration for 3.3 V
	234	- const: sdmmc-1v8
	235	description: pad configuration for 1.8 V
	236	- const: sdmmc-3v3-drv
	237	description: pull-up/down configuration for 3.3 V
	238	- const: sdmmc-1v8-drv
	239	description: pull-up/down configuration for 1.8 V
	240	- items:
	241	- const: sdmmc-3v3-drv
	242	description: pull-up/down configuration for 3.3 V
	243	- const: sdmmc-1v8-drv
	244	description: pull-up/down configuration for 1.8 V
	245	- items:
	246	- const: sdmmc-1v8-drv
	247	description: pull-up/down configuration for 1.8 V
	248	required:
	249	- clock-names
	250	- if:
	251	properties:
	252	compatible:
	253	contains:
	254	enum:
	255	- nvidia,tegra186-sdhci
	256	- nvidia,tegra194-sdhci
	257	then:
	258	properties:
	259	pinctrl-names:
	260	items:
	261	- const: sdmmc-3v3
	262	description: pad configuration for 3.3 V
	263	- const: sdmmc-1v8
	264	description: pad configuration for 1.8 V
	265	required:
	266	- clock-names
	267
	268	unevaluatedProperties: false
	269
	270	examples:
	271	- \|
	272	#include <dt-bindings/interrupt-controller/arm-gic.h>
	273
	274	mmc@c8000200 {
	275	compatible = "nvidia,tegra20-sdhci";
	276	reg = <0xc8000200 0x200>;
	277	interrupts = <47>;
	278	clocks = <&tegra_car 14>;
	279	resets = <&tegra_car 14>;
	280	reset-names = "sdhci";
	281	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
	282	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
	283	power-gpios = <&gpio 155 0>; /* gpio PT3 */
	284	bus-width = <8>;
	285	};
	286
	287	- \|
	288	#include <dt-bindings/clock/tegra210-car.h>
	289	#include <dt-bindings/interrupt-controller/arm-gic.h>
	290
	291	mmc@700b0000 {
	292	compatible = "nvidia,tegra210-sdhci";
	293	reg = <0x700b0000 0x200>;
	294	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	295	clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
	296	<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
	297	clock-names = "sdhci", "tmclk";
	298	resets = <&tegra_car 14>;
	299	reset-names = "sdhci";
	300	pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
	301	"sdmmc-3v3-drv", "sdmmc-1v8-drv";
	302	pinctrl-0 = <&sdmmc1_3v3>;
	303	pinctrl-1 = <&sdmmc1_1v8>;
	304	pinctrl-2 = <&sdmmc1_3v3_drv>;
	305	pinctrl-3 = <&sdmmc1_1v8_drv>;
	306	nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
	307	nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
	308	nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
	309	nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
	310	nvidia,default-tap = <0x2>;
	311	nvidia,default-trim = <0x4>;
	312	assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
	313	<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
	314	<&tegra_car TEGRA210_CLK_PLL_C4>;
	315	assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
	316	assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
	317	};

Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt+0−24

@@ -1,24 +0,0 @@
1	NVIDIA Tegra20 real-time clock
2
3	The Tegra RTC maintains seconds and milliseconds counters, and five alarm
4	registers. The alarms and other interrupts may wake the system from low-power
5	state.
6
7	Required properties:
8
9	- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise,
10	must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip>
11	can be tegra30, tegra114, tegra124, or tegra132.
12	- reg : Specifies base physical address and size of the registers.
13	- interrupts : A single interrupt specifier.
14	- clocks : Must contain one entry, for the module clock.
15	See ../clocks/clock-bindings.txt for details.
16
17	Example:
18
19	timer {
20	compatible = "nvidia,tegra20-rtc";
21	reg = <0x7000e000 0x100>;
22	interrupts = <0 2 0x04>;
23	clocks = <&tegra_car 4>;
24	};

Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml+61−0

@@ -0,0 +1,61 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra real-time clock
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	description: \|
	14	The Tegra RTC maintains seconds and milliseconds counters, and five
	15	alarm registers. The alarms and other interrupts may wake the system
	16	from low-power state.
	17
	18	properties:
	19	compatible:
	20	oneOf:
	21	- const: nvidia,tegra20-rtc
	22	- items:
	23	- enum:
	24	- nvidia,tegra30-rtc
	25	- nvidia,tegra114-rtc
	26	- nvidia,tegra124-rtc
	27	- nvidia,tegra210-rtc
	28	- nvidia,tegra186-rtc
	29	- nvidia,tegra194-rtc
	30	- nvidia,tegra234-rtc
	31	- const: nvidia,tegra20-rtc
	32
	33	reg:
	34	maxItems: 1
	35
	36	interrupts:
	37	maxItems: 1
	38
	39	clocks:
	40	maxItems: 1
	41
	42	clock-names:
	43	items:
	44	- const: rtc
	45
	46	additionalProperties: false
	47
	48	required:
	49	- compatible
	50	- reg
	51	- interrupts
	52	- clocks
	53
	54	examples:
	55	- \|
	56	timer@7000e000 {
	57	compatible = "nvidia,tegra20-rtc";
	58	reg = <0x7000e000 0x100>;
	59	interrupts = <0 2 0x04>;
	60	clocks = <&tegra_car 4>;
	61	};

Documentation/devicetree/bindings/serial/8250.yaml+2−1

               - nvidia,tegra30-uart
               - nvidia,tegra114-uart
               - nvidia,tegra124-uart
+              - nvidia,tegra210-uart
               - nvidia,tegra186-uart
               - nvidia,tegra194-uart
-              - nvidia,tegra210-uart
+              - nvidia,tegra234-uart
           - const: nvidia,tegra20-uart
   reg:

Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt+0−35

@@ -1,35 +0,0 @@
1	NVIDIA Tegra Combined UART (TCU)
2
3	The TCU is a system for sharing a hardware UART instance among multiple
4	systems within the Tegra SoC. It is implemented through a mailbox-
5	based protocol where each "virtual UART" has a pair of mailboxes, one
6	for transmitting and one for receiving, that is used to communicate
7	with the hardware implementing the TCU.
8
9	Required properties:
10	- name : Should be tcu
11	- compatible
12	Array of strings
13	One of:
14	- "nvidia,tegra194-tcu"
15	- mbox-names:
16	"rx" - Mailbox for receiving data from hardware UART
17	"tx" - Mailbox for transmitting data to hardware UART
18	- mboxes: Mailboxes corresponding to the mbox-names.
19
20	This node is a mailbox consumer. See the following files for details of
21	the mailbox subsystem, and the specifiers implemented by the relevant
22	provider(s):
23
24	- .../mailbox/mailbox.txt
25	- .../mailbox/nvidia,tegra186-hsp.txt
26
27	Example bindings:
28	-----------------
29
30	tcu: tcu {
31	compatible = "nvidia,tegra194-tcu";
32	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
33	<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
34	mbox-names = "rx", "tx";
35	};

Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml+61−0

@@ -0,0 +1,61 @@
	1	# SPDX-License-Identifier: GPL-2.0
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra Combined UART (TCU)
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jonathan Hunter <jonathanh@nvidia.com>
	12
	13	description:
	14	The TCU is a system for sharing a hardware UART instance among multiple
	15	systems within the Tegra SoC. It is implemented through a mailbox-
	16	based protocol where each "virtual UART" has a pair of mailboxes, one
	17	for transmitting and one for receiving, that is used to communicate
	18	with the hardware implementing the TCU.
	19
	20	properties:
	21	$nodename:
	22	pattern: "^serial(@.*)?$"
	23
	24	compatible:
	25	oneOf:
	26	- const: nvidia,tegra194-tcu
	27	- items:
	28	- enum:
	29	- nvidia,tegra234-tcu
	30	- const: nvidia,tegra194-tcu
	31
	32	mbox-names:
	33	items:
	34	- const: rx
	35	- const: tx
	36
	37	mboxes:
	38	description: \|
	39	List of phandles to mailbox channels used for receiving and
	40	transmitting data from and to the hardware UART.
	41	items:
	42	- description: mailbox for receiving data from hardware UART
	43	- description: mailbox for transmitting data to hardware UART
	44
	45	required:
	46	- compatible
	47	- mbox-names
	48	- mboxes
	49
	50	additionalProperties: false
	51
	52	examples:
	53	- \|
	54	#include <dt-bindings/mailbox/tegra186-hsp.h>
	55
	56	tcu: serial {
	57	compatible = "nvidia,tegra194-tcu";
	58	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
	59	<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
	60	mbox-names = "rx", "tx";
	61	};

Documentation/devicetree/bindings/sram/sram.yaml+3−0

         - amlogic,meson-gxbb-sram
         - arm,juno-sram-ns
         - atmel,sama5d2-securam
+        - nvidia,tegra186-sysram
+        - nvidia,tegra194-sysram
+        - nvidia,tegra234-sysram
         - qcom,rpm-msg-ram
         - rockchip,rk3288-pmu-sram

Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt+0−33

@@ -1,33 +0,0 @@
1	NVIDIA Tegra186 BPMP thermal sensor
2
3	In Tegra186, the BPMP (Boot and Power Management Processor) implements an
4	interface that is used to read system temperatures, including CPU cluster
5	and GPU temperatures. This binding describes the thermal sensor that is
6	exposed by BPMP.
7
8	The BPMP thermal node must be located directly inside the main BPMP node. See
9	../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
10
11	This node represents a thermal sensor. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details of the
12	core thermal binding.
13
14	Required properties:
15	- compatible:
16	Array of strings.
17	One of:
18	- "nvidia,tegra186-bpmp-thermal"
19	- "nvidia,tegra194-bpmp-thermal"
20	- #thermal-sensor-cells: Cell for sensor index.
21	Single-cell integer.
22	Must be <1>.
23
24	Example:
25
26	bpmp {
27	...
28
29	bpmp_thermal: thermal {
30	compatible = "nvidia,tegra186-bpmp-thermal";
31	#thermal-sensor-cells = <1>;
32	};
33	};

Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml+42−0

@@ -0,0 +1,42 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: NVIDIA Tegra186 (and later) BPMP thermal sensor
	8
	9	maintainers:
	10	- Thierry Reding <thierry.reding@gmail.com>
	11	- Jon Hunter <jonathanh@nvidia.com>
	12
	13	description: \|
	14	In Tegra186, the BPMP (Boot and Power Management Processor) implements
	15	an interface that is used to read system temperatures, including CPU
	16	cluster and GPU temperatures. This binding describes the thermal
	17	sensor that is exposed by BPMP.
	18
	19	The BPMP thermal node must be located directly inside the main BPMP
	20	node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the
	21	BPMP binding.
	22
	23	This node represents a thermal sensor. See
	24
	25	Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
	26
	27	for details of the core thermal binding.
	28
	29	properties:
	30	compatible:
	31	enum:
	32	- nvidia,tegra186-bpmp-thermal
	33	- nvidia,tegra194-bpmp-thermal
	34
	35	'#thermal-sensor-cells':
	36	$ref: /schemas/types.yaml#/definitions/uint32
	37	description: Number of cells needed in the phandle specifier to
	38	identify a given sensor. Must be 1 and the single cell specifies
	39	the sensor index.
	40	const: 1
	41
	42	additionalProperties: false

Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml+13−0

@@ -59,6 +59,19 @@ properties: · 58 unmodified lines
59	- const: fs_src	59	- const: fs_src
60	- const: hs_src	60	- const: hs_src
61		61
		62	interconnects:
		63	items:
		64	- description: memory read client
		65	- description: memory write client
		66
		67	interconnect-names:
		68	items:
		69	- const: dma-mem # read
		70	- const: write
		71
		72	iommus:
		73	maxItems: 1
		74
62	power-domains:	75	power-domains:
63	items:	76	items:
64	- description: XUSBB(device) power-domain	77	- description: XUSBB(device) power-domain

include/dt-bindings/clock/tegra234-clock.h+23−3

@@ -4,11 +4,31 @@ · 3 unmodified lines
4	#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H	4	#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
5	#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H	5	#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
6		6
		7	/**
		8	* @file
		9	* @defgroup bpmp_clock_ids Clock ID's
		10	* @{
		11	*/
		12	/**
		13	* @brief controls the EMC clock frequency.
		14	* @details Doing a clk_set_rate on this clock will select the
		15	* appropriate clock source, program the source rate and execute a
		16	* specific sequence to switch to the new clock source for both memory
		17	* controllers. This can be used to control the balance between memory
		18	* throughput and memory controller power.
		19	*/
		20	#define TEGRA234_CLK_EMC 31U
7	/** @brief output of gate CLK_ENB_FUSE */	21	/** @brief output of gate CLK_ENB_FUSE */
8	#define TEGRA234_CLK_FUSE 40	22	#define TEGRA234_CLK_FUSE 40U
9	/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */	23	/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
10	#define TEGRA234_CLK_SDMMC4 123	24	#define TEGRA234_CLK_SDMMC4 123U
11	/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */	25	/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
12	#define TEGRA234_CLK_UARTA 155	26	#define TEGRA234_CLK_UARTA 155U
		27	/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
		28	#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
		29	/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
		30	#define TEGRA234_CLK_PLLC4 237U
		31	/** @brief 32K input clock provided by PMIC */
		32	#define TEGRA234_CLK_CLK_32K 289U
13		33
14	#endif	34	#endif

include/dt-bindings/memory/tegra234-mc.h+32−0

@@ -0,0 +1,32 @@
	1	/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
	2
	3	#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
	4	#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
	5
	6	/* special clients */
	7	#define TEGRA234_SID_INVALID 0x00
	8	#define TEGRA234_SID_PASSTHROUGH 0x7f
	9
	10
	11	/* NISO1 stream IDs */
	12	#define TEGRA234_SID_SDMMC4 0x02
	13	#define TEGRA234_SID_BPMP 0x10
	14
	15	/*
	16	* memory client IDs
	17	*/
	18
	19	/* sdmmcd memory read client */
	20	#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
	21	/* sdmmcd memory write client */
	22	#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
	23	/* BPMP read client */
	24	#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
	25	/* BPMP write client */
	26	#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94
	27	/* BPMPDMA read client */
	28	#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
	29	/* BPMPDMA write client */
	30	#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
	31
	32	#endif

include/dt-bindings/reset/tegra234-reset.h+10−2

@@ -4,7 +4,15 @@ · 3 unmodified lines
4	#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H	4	#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
5	#define DT_BINDINGS_RESET_TEGRA234_RESET_H	5	#define DT_BINDINGS_RESET_TEGRA234_RESET_H
6		6
7	#define TEGRA234_RESET_SDMMC4 85	7	/**
8	#define TEGRA234_RESET_UARTA 100	8	* @file
		9	* @defgroup bpmp_reset_ids Reset ID's
		10	* @brief Identifiers for Resets controllable by firmware
		11	* @{
		12	*/
		13	#define TEGRA234_RESET_SDMMC4 85U
		14	#define TEGRA234_RESET_UARTA 100U
		15
		16	/** @} */
9		17
10	#endif	18	#endif

Merge tag 'tegra-for-5.17-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

Keyboard shortcuts

General

Issues and pull requests

Issues, pull requests and Inbox

Repository code