dt-bindings: Changes for v5.17-rc1 This contains a bunch of json-schema conversions for various Tegra- related DT bindings and additions for new SoC and board support. * tag 'tegra-for-5.17-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits) media: dt: bindings: tegra-vde: Document OPP and power domain media: dt: bindings: tegra-vde: Convert to schema dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D dt-bindings: host1x: Document OPP and power domain properties dt-bindings: clock: tegra-car: Document new clock sub-nodes dt-bindings: ARM: tegra: Document Pegatron Chagall dt-bindings: ARM: tegra: Document ASUS Transformers dt-bindings: usb: tegra-xudc: Document interconnects and iommus properties dt-bindings: serial: Document Tegra234 TCU dt-bindings: serial: tegra-tcu: Convert to json-schema dt-bindings: thermal: tegra186-bpmp: Convert to json-schema dt-bindings: firmware: tegra: Convert to json-schema dt-bindings: tegra: pmc: Convert to json-schema dt-bindings: serial: 8250: Document Tegra234 UART dt-bindings: mmc: tegra: Document Tegra234 SDHCI dt-bindings: fuse: tegra: Document Tegra234 FUSE dt-bindings: fuse: tegra: Convert to json-schema dt-bindings: rtc: tegra: Document Tegra234 RTC dt-bindings: rtc: tegra: Convert to json-schema dt-bindings: mailbox: tegra: Document Tegra234 HSP ...
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| @@ -4,11 +4,31 @@ · 3 unmodified lines | |||
| 4 | #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H | 4 | #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H |
| 5 | #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H | 5 | #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H |
| 6 | 6 | ||
| 7 | /** | ||
| 8 | * @file | ||
| 9 | * @defgroup bpmp_clock_ids Clock ID's | ||
| 10 | * @{ | ||
| 11 | */ | ||
| 12 | /** | ||
| 13 | * @brief controls the EMC clock frequency. | ||
| 14 | * @details Doing a clk_set_rate on this clock will select the | ||
| 15 | * appropriate clock source, program the source rate and execute a | ||
| 16 | * specific sequence to switch to the new clock source for both memory | ||
| 17 | * controllers. This can be used to control the balance between memory | ||
| 18 | * throughput and memory controller power. | ||
| 19 | */ | ||
| 20 | #define TEGRA234_CLK_EMC 31U | ||
| 7 | /** @brief output of gate CLK_ENB_FUSE */ | 21 | /** @brief output of gate CLK_ENB_FUSE */ |
| 8 | #define TEGRA234_CLK_FUSE 40 | 22 | #define TEGRA234_CLK_FUSE 40U |
| 9 | /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ | 23 | /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ |
| 10 | #define TEGRA234_CLK_SDMMC4 123 | 24 | #define TEGRA234_CLK_SDMMC4 123U |
| 11 | /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ | 25 | /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ |
| 12 | #define TEGRA234_CLK_UARTA 155 | 26 | #define TEGRA234_CLK_UARTA 155U |
| 27 | /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ | ||
| 28 | #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U | ||
| 29 | /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ | ||
| 30 | #define TEGRA234_CLK_PLLC4 237U | ||
| 31 | /** @brief 32K input clock provided by PMIC */ | ||
| 32 | #define TEGRA234_CLK_CLK_32K 289U | ||
| 13 | 33 | ||
| 14 | #endif | 34 | #endif |
| @@ -0,0 +1,32 @@ | |||
| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ | ||
| 2 | |||
| 3 | #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H | ||
| 4 | #define DT_BINDINGS_MEMORY_TEGRA234_MC_H | ||
| 5 | |||
| 6 | /* special clients */ | ||
| 7 | #define TEGRA234_SID_INVALID 0x00 | ||
| 8 | #define TEGRA234_SID_PASSTHROUGH 0x7f | ||
| 9 | |||
| 10 | |||
| 11 | /* NISO1 stream IDs */ | ||
| 12 | #define TEGRA234_SID_SDMMC4 0x02 | ||
| 13 | #define TEGRA234_SID_BPMP 0x10 | ||
| 14 | |||
| 15 | /* | ||
| 16 | * memory client IDs | ||
| 17 | */ | ||
| 18 | |||
| 19 | /* sdmmcd memory read client */ | ||
| 20 | #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 | ||
| 21 | /* sdmmcd memory write client */ | ||
| 22 | #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 | ||
| 23 | /* BPMP read client */ | ||
| 24 | #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 | ||
| 25 | /* BPMP write client */ | ||
| 26 | #define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 | ||
| 27 | /* BPMPDMA read client */ | ||
| 28 | #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 | ||
| 29 | /* BPMPDMA write client */ | ||
| 30 | #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 | ||
| 31 | |||
| 32 | #endif | ||
| @@ -4,7 +4,15 @@ · 3 unmodified lines | |||
| 4 | #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H | 4 | #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H |
| 5 | #define DT_BINDINGS_RESET_TEGRA234_RESET_H | 5 | #define DT_BINDINGS_RESET_TEGRA234_RESET_H |
| 6 | 6 | ||
| 7 | #define TEGRA234_RESET_SDMMC4 85 | 7 | /** |
| 8 | #define TEGRA234_RESET_UARTA 100 | 8 | * @file |
| 9 | * @defgroup bpmp_reset_ids Reset ID's | ||
| 10 | * @brief Identifiers for Resets controllable by firmware | ||
| 11 | * @{ | ||
| 12 | */ | ||
| 13 | #define TEGRA234_RESET_SDMMC4 85U | ||
| 14 | #define TEGRA234_RESET_UARTA 100U | ||
| 15 | |||
| 16 | /** @} */ | ||
| 9 | 17 | ||
| 10 | #endif | 18 | #endif |