According to the PCIe 3.0 spec, PCI_EXP_LNKCAP2_SLS_2_5GB is 1st bit of PCI_EXP_LNKCAP2 register, not 0th bit. So, the bit definition of supported link speed vector should be fixed. [bhelgaas: change "Current" to "Supported"] Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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| @@ -544,9 +544,9 @@ · 543 unmodified lines | |||
| 544 | #define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ | 544 | #define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ |
| 545 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ | 545 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ |
| 546 | #define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ | 546 | #define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ |
| 547 | #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */ | 547 | #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ |
| 548 | #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */ | 548 | #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ |
| 549 | #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */ | 549 | #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ |
| 550 | #define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */ | 550 | #define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */ |
| 551 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ | 551 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
| 552 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ | 552 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ |