main pull request for v6.4 Core Display: ============ * Bugfixes for error handling during probe * rework UBWC decoder programming * prepare_commit cleanup * bindings for SM8550 (MDSS, DPU), SM8450 (DP) * timeout calculation fixup * atomic: use drm_crtc_next_vblank_start() instead of our own custom thing to calculate the start of next vblank DP: == * interrupts cleanup DPU: === * DSPP sub-block flush on sc7280 * support AR30 in addition to XR30 format * Allow using REC_0 and REC_1 to handle wide (4k) RGB planes * Split the HW catalog into individual per-SoC files DSI: === * rework DSI instance ID detection on obscure platforms GPU: === * uapi C++ compatibility fix * a6xx: More robust gdsc reset * a3xx and a4xx devfreq support * update generated headers * various cleanups and fixes * GPU and GEM updates to avoid allocations which could trigger reclaim (shrinker) in fence signaling path * dma-fence deadline hint support and wait-boost * a640 speedbin support * a650 speedbin support Conflicts in drivers/gpu/drm/msm/adreno/adreno_gpu.c: Conflict between the 7fa5047a436b ("drm: Use of_property_present() for testing DT property presence") and 9f251f934012 ("drm/msm/adreno: Use OPP for every GPU generation"). The latter removed the of_ function call outright, so I went with what's in the PR unchanged.
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| @@ -151,8 +151,13 @@ struct drm_msm_gem_info { · 150 unmodified lines | ||
| 151 | 151 | #define MSM_PREP_READ 0x01 |
| 152 | 152 | #define MSM_PREP_WRITE 0x02 |
| 153 | 153 | #define MSM_PREP_NOSYNC 0x04 |
| 154 | +#define MSM_PREP_BOOST 0x08 | |
| 154 | 155 | |
| 155 | −#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) | |
| 156 | +#define MSM_PREP_FLAGS (MSM_PREP_READ | \ | |
| 157 | + MSM_PREP_WRITE | \ | |
| 158 | + MSM_PREP_NOSYNC | \ | |
| 159 | + MSM_PREP_BOOST | \ | |
| 160 | + 0) | |
| 156 | 161 | |
| 157 | 162 | struct drm_msm_gem_cpu_prep { |
| 158 | 163 | __u32 handle; /* in */ |
| @@ -181,7 +186,11 @@ struct drm_msm_gem_cpu_fini { · 22 unmodified lines | ||
| 181 | 186 | */ |
| 182 | 187 | struct drm_msm_gem_submit_reloc { |
| 183 | 188 | __u32 submit_offset; /* in, offset from submit_bo */ |
| 189 | +#ifdef __cplusplus | |
| 190 | + __u32 _or; /* in, value OR'd with result */ | |
| 191 | +#else | |
| 184 | 192 | __u32 or; /* in, value OR'd with result */ |
| 193 | +#endif | |
| 185 | 194 | __s32 shift; /* in, amount of left shift (can be negative) */ |
| 186 | 195 | __u32 reloc_idx; /* in, index of reloc_bo buffer */ |
| 187 | 196 | __u64 reloc_offset; /* in, offset from start of reloc_bo */ |
| @@ -286,6 +295,11 @@ struct drm_msm_gem_submit { · 98 unmodified lines | ||
| 286 | 295 | |
| 287 | 296 | }; |
| 288 | 297 | |
| 298 | +#define MSM_WAIT_FENCE_BOOST 0x00000001 | |
| 299 | +#define MSM_WAIT_FENCE_FLAGS ( \ | |
| 300 | + MSM_WAIT_FENCE_BOOST | \ | |
| 301 | + 0) | |
| 302 | + | |
| 289 | 303 | /* The normal way to synchronize with the GPU is just to CPU_PREP on |
| 290 | 304 | * a buffer if you need to access it from the CPU (other cmdstream |
| 291 | 305 | * submission from same or other contexts, PAGE_FLIP ioctl, etc, all |
| @@ -295,7 +309,7 @@ struct drm_msm_gem_submit { · 3 unmodified lines | ||
| 295 | 309 | */ |
| 296 | 310 | struct drm_msm_wait_fence { |
| 297 | 311 | __u32 fence; /* in */ |
| 298 | − __u32 pad; | |
| 312 | + __u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */ | |
| 299 | 313 | struct drm_msm_timespec timeout; /* in */ |
| 300 | 314 | __u32 queueid; /* in, submitqueue id */ |
| 301 | 315 | }; |