Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie: "Nothing too major, radeon still has some dpm changes for off by default. Radeon, intel, msm: - radeon: a few more dpm fixes (still off by default), uvd fixes - i915: runtime warn backtrace and regression fix - msm: iommu changes fallout" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (27 commits) drm/msm: use drm_gem_dumb_destroy helper drm/msm: deal with mach/iommu.h removal drm/msm: Remove iommu include from mdp4_kms.c drm/msm: Odd PTR_ERR usage drm/i915: Fix up usage of SHRINK_STOP drm/radeon: fix hdmi audio on DCE3.0/3.1 asics drm/i915: preserve pipe A quirk in i9xx_set_pipeconf drm/i915/tv: clear adjusted_mode.flags drm/i915/dp: increase i2c-over-aux retry interval on AUX DEFER drm/radeon/cik: fix overflow in vram fetch drm/radeon: add missing hdmi callbacks for rv6xx drm/i915: Use a temporary va_list for two-pass string handling drm/radeon/uvd: lower msg&fb buffer requirements on UVD3 drm/radeon: disable tests/benchmarks if accel is disabled drm/radeon: don't set default clocks for SI when DPM is disabled drm/radeon/dpm/ci: filter clocks based on voltage/clk dep tables drm/radeon/dpm/si: filter clocks based on voltage/clk dep tables drm/radeon/dpm/ni: filter clocks based on voltage/clk dep tables drm/radeon/dpm/btc: filter clocks based on voltage/clk dep tables drm/radeon/dpm: fetch the max clk from voltage dep tables helper ...

Linus Torvalds committed 13 years ago

Commit b97b8692 parents 669fc2f 665441726 files · +266 −77Browse files

Unified · Split

26 files

drivers/gpu/drm/i915/i915_gem.c +4 −4
drivers/gpu/drm/i915/i915_gpu_error.c +4 −2
drivers/gpu/drm/i915/intel_display.c +4 −0
drivers/gpu/drm/i915/intel_dp.c +12 −1
drivers/gpu/drm/i915/intel_tv.c +8 −0
drivers/gpu/drm/msm/mdp4/mdp4_kms.c +0 −2
drivers/gpu/drm/msm/msm_drv.c +4 −4
drivers/gpu/drm/msm/msm_gem.c +0 −7
drivers/gpu/drm/radeon/btc_dpm.c +51 −0
drivers/gpu/drm/radeon/btc_dpm.h +2 −0
drivers/gpu/drm/radeon/ci_dpm.c +26 −0
drivers/gpu/drm/radeon/cik.c +8 −9
drivers/gpu/drm/radeon/ni_dpm.c +24 −0
drivers/gpu/drm/radeon/r100.c +5 −3
drivers/gpu/drm/radeon/r600_dpm.c +1 −1
drivers/gpu/drm/radeon/r600_hdmi.c +15 −5
drivers/gpu/drm/radeon/radeon_asic.c +2 −0
drivers/gpu/drm/radeon/radeon_atombios.c +43 −23
drivers/gpu/drm/radeon/radeon_cs.c +3 −2
drivers/gpu/drm/radeon/radeon_device.c +12 −3
drivers/gpu/drm/radeon/radeon_pm.c +4 −4
drivers/gpu/drm/radeon/radeon_ring.c +5 −3
drivers/gpu/drm/radeon/radeon_uvd.c +1 −2
drivers/gpu/drm/radeon/si_dpm.c +24 −0
drivers/gpu/drm/radeon/uvd_v1_0.c +2 −2
include/uapi/drm/radeon_drm.h +2 −0

drivers/gpu/drm/i915/i915_gem.c+4−4

@@ -4800,10 +4800,10 @@ i915_gem_inactive_count(struct shrinker shrinker, struct shrink_control sc) · 4799 unmodified lines
4800	4800
4801	4801	if (!mutex_trylock(&dev->struct_mutex)) {
4802	4802	if (!mutex_is_locked_by(&dev->struct_mutex, current))
4803		− return SHRINK_STOP;
	4803	+ return 0;
4804	4804
4805	4805	if (dev_priv->mm.shrinker_no_lock_stealing)
4806		− return SHRINK_STOP;
	4806	+ return 0;
4807	4807
4808	4808	unlock = false;
4809	4809	}
@@ -4901,10 +4901,10 @@ i915_gem_inactive_scan(struct shrinker shrinker, struct shrink_control sc) · 91 unmodified lines
4901	4901
4902	4902	if (!mutex_trylock(&dev->struct_mutex)) {
4903	4903	if (!mutex_is_locked_by(&dev->struct_mutex, current))
4904		− return 0;
	4904	+ return SHRINK_STOP;
4905	4905
4906	4906	if (dev_priv->mm.shrinker_no_lock_stealing)
4907		− return 0;
	4907	+ return SHRINK_STOP;
4908	4908
4909	4909	unlock = false;
4910	4910	}

drivers/gpu/drm/i915/i915_gpu_error.c+4−2

@@ -143,8 +143,10 @@ static void i915_error_vprintf(struct drm_i915_error_state_buf *e, · 142 unmodified lines
143	143
144	144	/* Seek the first printf which is hits start position */
145	145	if (e->pos < e->start) {
146		− len = vsnprintf(NULL, 0, f, args);
147		− if (!__i915_error_seek(e, len))
	146	+ va_list tmp;
	147	+
	148	+ va_copy(tmp, args);
	149	+ if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp)))
148	150	return;
149	151	}
150	152

drivers/gpu/drm/i915/intel_display.c+4−0

@@ -4775,6 +4775,10 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) · 4774 unmodified lines
4775	4775
4776	4776	pipeconf = 0;
4777	4777
	4778	+ if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
	4779	+ I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
	4780	+ pipeconf \|= PIPECONF_ENABLE;
	4781	+
4778	4782	if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4779	4783	/* Enable pixel doubling when the dot clock is > 90% of the (display)
4780	4784	* core speed.

drivers/gpu/drm/i915/intel_dp.c+12−1

@@ -588,7 +588,18 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, · 587 unmodified lines
588	588	DRM_DEBUG_KMS("aux_ch native nack\n");
589	589	return -EREMOTEIO;
590	590	case AUX_NATIVE_REPLY_DEFER:
591		− udelay(100);
	591	+ /*
	592	+ * For now, just give more slack to branch devices. We
	593	+ * could check the DPCD for I2C bit rate capabilities,
	594	+ * and if available, adjust the interval. We could also
	595	+ * be more careful with DP-to-Legacy adapters where a
	596	+ * long legacy cable may force very low I2C bit rates.
	597	+ */
	598	+ if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	599	+ DP_DWN_STRM_PORT_PRESENT)
	600	+ usleep_range(500, 600);
	601	+ else
	602	+ usleep_range(300, 400);
592	603	continue;
593	604	default:
594	605	DRM_ERROR("aux_ch invalid native reply 0x%02x\n",

drivers/gpu/drm/i915/intel_tv.c+8−0

@@ -916,6 +916,14 @@ intel_tv_compute_config(struct intel_encoder *encoder, · 915 unmodified lines
916	916	DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
917	917	pipe_config->pipe_bpp = 8*3;
918	918
	919	+ /* TV has it's own notion of sync and other mode flags, so clear them. */
	920	+ pipe_config->adjusted_mode.flags = 0;
	921	+
	922	+ /*
	923	+ * FIXME: We don't check whether the input mode is actually what we want
	924	+ * or whether userspace is doing something stupid.
	925	+ */
	926	+
919	927	return true;
920	928	}
921	929

drivers/gpu/drm/msm/mdp4/mdp4_kms.c+0−2

@@ -19,8 +19,6 @@ · 18 unmodified lines
19	19	#include "msm_drv.h"
20	20	#include "mdp4_kms.h"
21	21
22		−#include <mach/iommu.h>
23		−
24	22	static struct mdp4_platform_config mdp4_get_config(struct platform_device dev);
25	23
26	24	static int mdp4_hw_init(struct msm_kms *kms)

drivers/gpu/drm/msm/msm_drv.c+4−4

@@ -18,8 +18,6 @@ · 17 unmodified lines
18	18	#include "msm_drv.h"
19	19	#include "msm_gpu.h"
20	20
21		−#include <mach/iommu.h>
22		−
23	21	static void msm_fb_output_poll_changed(struct drm_device *dev)
24	22	{
25	23	struct msm_drm_private *priv = dev->dev_private;
@@ -62,6 +60,8 @@ int msm_iommu_attach(struct drm_device dev, struct iommu_domain iommu, · 36 unmodified lines
62	60	int i, ret;
63	61
64	62	for (i = 0; i < cnt; i++) {
	63	+ /* TODO maybe some day msm iommu won't require this hack: */
	64	+ struct device msm_iommu_get_ctx(const char ctx_name);
65	65	struct device *ctx = msm_iommu_get_ctx(names[i]);
66	66	if (!ctx)
67	67	continue;
@@ -199,7 +199,7 @@ static int msm_load(struct drm_device *dev, unsigned long flags) · 131 unmodified lines
199	199	* imx drm driver on iMX5
200	200	*/
201	201	dev_err(dev->dev, "failed to load kms\n");
202		− ret = PTR_ERR(priv->kms);
	202	+ ret = PTR_ERR(kms);
203	203	goto fail;
204	204	}
205	205
@@ -697,7 +697,7 @@ static struct drm_driver msm_driver = { · 491 unmodified lines
697	697	.gem_vm_ops = &vm_ops,
698	698	.dumb_create = msm_gem_dumb_create,
699	699	.dumb_map_offset = msm_gem_dumb_map_offset,
700		− .dumb_destroy = msm_gem_dumb_destroy,
	700	+ .dumb_destroy = drm_gem_dumb_destroy,
701	701	#ifdef CONFIG_DEBUG_FS
702	702	.debugfs_init = msm_debugfs_init,
703	703	.debugfs_cleanup = msm_debugfs_cleanup,

drivers/gpu/drm/msm/msm_gem.c+0−7

@@ -319,13 +319,6 @@ int msm_gem_dumb_create(struct drm_file file, struct drm_device dev, · 318 unmodified lines
319	319	MSM_BO_SCANOUT \| MSM_BO_WC, &args->handle);
320	320	}
321	321
322		−int msm_gem_dumb_destroy(struct drm_file file, struct drm_device dev,
323		− uint32_t handle)
324		−{
325		− /* No special work needed, drop the reference and see what falls out */
326		− return drm_gem_handle_delete(file, handle);
327		−}
328		−
329	322	int msm_gem_dumb_map_offset(struct drm_file file, struct drm_device dev,
330	323	uint32_t handle, uint64_t *offset)
331	324	{

drivers/gpu/drm/radeon/btc_dpm.c+51−0

@@ -1168,6 +1168,23 @@ static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = · 1167 unmodified lines
1168	1168	{ 25000, 30000, RADEON_SCLK_UP }
1169	1169	};
1170	1170
	1171	+void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
	1172	+ u32 *max_clock)
	1173	+{
	1174	+ u32 i, clock = 0;
	1175	+
	1176	+ if ((table == NULL) \|\| (table->count == 0)) {
	1177	+ *max_clock = clock;
	1178	+ return;
	1179	+ }
	1180	+
	1181	+ for (i = 0; i < table->count; i++) {
	1182	+ if (clock < table->entries[i].clk)
	1183	+ clock = table->entries[i].clk;
	1184	+ }
	1185	+ *max_clock = clock;
	1186	+}
	1187	+
1171	1188	void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,
1172	1189	u32 clock, u16 max_voltage, u16 *voltage)
1173	1190	{
@@ -2080,6 +2097,7 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev, · 906 unmodified lines
2080	2097	bool disable_mclk_switching;
2081	2098	u32 mclk, sclk;
2082	2099	u16 vddc, vddci;
	2100	+ u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2083	2101
2084	2102	if ((rdev->pm.dpm.new_active_crtc_count > 1) \|\|
2085	2103	btc_dpm_vblank_too_short(rdev))
@@ -2121,6 +2139,39 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev, · 35 unmodified lines
2121	2139	ps->low.vddci = max_limits->vddci;
2122	2140	}
2123	2141
	2142	+ /* limit clocks to max supported clocks based on voltage dependency tables */
	2143	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
	2144	+ &max_sclk_vddc);
	2145	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
	2146	+ &max_mclk_vddci);
	2147	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
	2148	+ &max_mclk_vddc);
	2149	+
	2150	+ if (max_sclk_vddc) {
	2151	+ if (ps->low.sclk > max_sclk_vddc)
	2152	+ ps->low.sclk = max_sclk_vddc;
	2153	+ if (ps->medium.sclk > max_sclk_vddc)
	2154	+ ps->medium.sclk = max_sclk_vddc;
	2155	+ if (ps->high.sclk > max_sclk_vddc)
	2156	+ ps->high.sclk = max_sclk_vddc;
	2157	+ }
	2158	+ if (max_mclk_vddci) {
	2159	+ if (ps->low.mclk > max_mclk_vddci)
	2160	+ ps->low.mclk = max_mclk_vddci;
	2161	+ if (ps->medium.mclk > max_mclk_vddci)
	2162	+ ps->medium.mclk = max_mclk_vddci;
	2163	+ if (ps->high.mclk > max_mclk_vddci)
	2164	+ ps->high.mclk = max_mclk_vddci;
	2165	+ }
	2166	+ if (max_mclk_vddc) {
	2167	+ if (ps->low.mclk > max_mclk_vddc)
	2168	+ ps->low.mclk = max_mclk_vddc;
	2169	+ if (ps->medium.mclk > max_mclk_vddc)
	2170	+ ps->medium.mclk = max_mclk_vddc;
	2171	+ if (ps->high.mclk > max_mclk_vddc)
	2172	+ ps->high.mclk = max_mclk_vddc;
	2173	+ }
	2174	+
2124	2175	/* XXX validate the min clocks required for display */
2125	2176
2126	2177	if (disable_mclk_switching) {

drivers/gpu/drm/radeon/btc_dpm.h+2−0

@@ -46,6 +46,8 @@ void btc_adjust_clock_combinations(struct radeon_device *rdev, · 45 unmodified lines
46	46	struct rv7xx_pl *pl);
47	47	void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,
48	48	u32 clock, u16 max_voltage, u16 *voltage);
	49	+void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
	50	+ u32 *max_clock);
49	51	void btc_apply_voltage_delta_rules(struct radeon_device *rdev,
50	52	u16 max_vddc, u16 max_vddci,
51	53	u16 vddc, u16 vddci);

drivers/gpu/drm/radeon/ci_dpm.c+26−0

@@ -146,6 +146,8 @@ static const struct ci_pt_config_reg didt_config_ci[] = · 145 unmodified lines
146	146	};
147	147
148	148	extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
	149	+extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
	150	+ u32 *max_clock);
149	151	extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
150	152	u32 arb_freq_src, u32 arb_freq_dest);
151	153	extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
@@ -712,6 +714,7 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev, · 560 unmodified lines
712	714	struct radeon_clock_and_voltage_limits *max_limits;
713	715	bool disable_mclk_switching;
714	716	u32 sclk, mclk;
	717	+ u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
715	718	int i;
716	719
717	720	if ((rdev->pm.dpm.new_active_crtc_count > 1) \|\|
@@ -739,6 +742,29 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev, · 21 unmodified lines
739	742	}
740	743	}
741	744
	745	+ /* limit clocks to max supported clocks based on voltage dependency tables */
	746	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
	747	+ &max_sclk_vddc);
	748	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
	749	+ &max_mclk_vddci);
	750	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
	751	+ &max_mclk_vddc);
	752	+
	753	+ for (i = 0; i < ps->performance_level_count; i++) {
	754	+ if (max_sclk_vddc) {
	755	+ if (ps->performance_levels[i].sclk > max_sclk_vddc)
	756	+ ps->performance_levels[i].sclk = max_sclk_vddc;
	757	+ }
	758	+ if (max_mclk_vddci) {
	759	+ if (ps->performance_levels[i].mclk > max_mclk_vddci)
	760	+ ps->performance_levels[i].mclk = max_mclk_vddci;
	761	+ }
	762	+ if (max_mclk_vddc) {
	763	+ if (ps->performance_levels[i].mclk > max_mclk_vddc)
	764	+ ps->performance_levels[i].mclk = max_mclk_vddc;
	765	+ }
	766	+ }
	767	+
742	768	/* XXX validate the min clocks required for display */
743	769
744	770	if (disable_mclk_switching) {

drivers/gpu/drm/radeon/cik.c+8−9

@@ -2845,10 +2845,8 @@ static void cik_gpu_init(struct radeon_device *rdev) · 2844 unmodified lines
2845	2845	rdev->config.cik.tile_config \|= (3 << 0);
2846	2846	break;
2847	2847	}
2848		− if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
2849		− rdev->config.cik.tile_config \|= 1 << 4;
2850		− else
2851		− rdev->config.cik.tile_config \|= 0 << 4;
	2848	+ rdev->config.cik.tile_config \|=
	2849	+ ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2852	2850	rdev->config.cik.tile_config \|=
2853	2851	((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
2854	2852	rdev->config.cik.tile_config \|=
@@ -4456,8 +4454,8 @@ static int cik_mc_init(struct radeon_device *rdev) · 1601 unmodified lines
4456	4454	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
4457	4455	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
4458	4456	/* size in MB on si */
4459		− rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
4460		− rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
	4457	+ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
	4458	+ rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
4461	4459	rdev->mc.visible_vram_size = rdev->mc.aper_size;
4462	4460	si_vram_gtt_location(rdev, &rdev->mc);
4463	4461	radeon_update_bandwidth_info(rdev);
@@ -4735,12 +4733,13 @@ static void cik_vm_decode_fault(struct radeon_device *rdev, · 271 unmodified lines
4735	4733	u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
4736	4734	u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
4737	4735	u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
4738		− char block = (char )&mc_client;
	4736	+ char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
	4737	+ (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
4739	4738
4740		− printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
	4739	+ printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
4741	4740	protections, vmid, addr,
4742	4741	(status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
4743		− block, mc_id);
	4742	+ block, mc_client, mc_id);
4744	4743	}
4745	4744
4746	4745	/**

drivers/gpu/drm/radeon/ni_dpm.c+24−0

@@ -787,6 +787,7 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev, · 786 unmodified lines
787	787	bool disable_mclk_switching;
788	788	u32 mclk, sclk;
789	789	u16 vddc, vddci;
	790	+ u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
790	791	int i;
791	792
792	793	if ((rdev->pm.dpm.new_active_crtc_count > 1) \|\|
@@ -813,6 +814,29 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev, · 20 unmodified lines
813	814	}
814	815	}
815	816
	817	+ /* limit clocks to max supported clocks based on voltage dependency tables */
	818	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
	819	+ &max_sclk_vddc);
	820	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
	821	+ &max_mclk_vddci);
	822	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
	823	+ &max_mclk_vddc);
	824	+
	825	+ for (i = 0; i < ps->performance_level_count; i++) {
	826	+ if (max_sclk_vddc) {
	827	+ if (ps->performance_levels[i].sclk > max_sclk_vddc)
	828	+ ps->performance_levels[i].sclk = max_sclk_vddc;
	829	+ }
	830	+ if (max_mclk_vddci) {
	831	+ if (ps->performance_levels[i].mclk > max_mclk_vddci)
	832	+ ps->performance_levels[i].mclk = max_mclk_vddci;
	833	+ }
	834	+ if (max_mclk_vddc) {
	835	+ if (ps->performance_levels[i].mclk > max_mclk_vddc)
	836	+ ps->performance_levels[i].mclk = max_mclk_vddc;
	837	+ }
	838	+ }
	839	+
816	840	/* XXX validate the min clocks required for display */
817	841
818	842	if (disable_mclk_switching) {

drivers/gpu/drm/radeon/r100.c+5−3

@@ -2933,9 +2933,11 @@ static int r100_debugfs_cp_ring_info(struct seq_file m, void data) · 2932 unmodified lines
2933	2933	seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2934	2934	seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2935	2935	seq_printf(m, "%u dwords in ring\n", count);
2936		− for (j = 0; j <= count; j++) {
2937		− i = (rdp + j) & ring->ptr_mask;
2938		− seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
	2936	+ if (ring->ready) {
	2937	+ for (j = 0; j <= count; j++) {
	2938	+ i = (rdp + j) & ring->ptr_mask;
	2939	+ seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
	2940	+ }
2939	2941	}
2940	2942	return 0;
2941	2943	}

drivers/gpu/drm/radeon/r600_dpm.c+1−1

@@ -1084,7 +1084,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev) · 1083 unmodified lines
1084	1084	rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
1085	1085	le16_to_cpu(uvd_clk->usDClkLow) \| (uvd_clk->ucDClkHigh << 16);
1086	1086	rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =
1087		− le16_to_cpu(limits->entries[i].usVoltage);
	1087	+ le16_to_cpu(entry->usVoltage);
1088	1088	entry = (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record *)
1089	1089	((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record));
1090	1090	}

drivers/gpu/drm/radeon/r600_hdmi.c+15−5

@@ -257,10 +257,7 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) · 256 unmodified lines
257	257	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
258	258	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
259	259	*/
260		− if (ASIC_IS_DCE3(rdev)) {
261		− /* according to the reg specs, this should DCE3.2 only, but in
262		− * practice it seems to cover DCE3.0 as well.
263		− */
	260	+ if (ASIC_IS_DCE32(rdev)) {
264	261	if (dig->dig_encoder == 0) {
265	262	dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
266	263	dto_cntl \|= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
@@ -276,8 +273,21 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) · 9 unmodified lines
276	273	WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
277	274	WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
278	275	}
	276	+ } else if (ASIC_IS_DCE3(rdev)) {
	277	+ /* according to the reg specs, this should DCE3.2 only, but in
	278	+ * practice it seems to cover DCE3.0/3.1 as well.
	279	+ */
	280	+ if (dig->dig_encoder == 0) {
	281	+ WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
	282	+ WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
	283	+ WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
	284	+ } else {
	285	+ WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);
	286	+ WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
	287	+ WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
	288	+ }
279	289	} else {
280		− /* according to the reg specs, this should be DCE2.0 and DCE3.0 */
	290	+ /* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */
281	291	WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) \|
282	292	AUDIO_DTO_MODULE(clock / 10));
283	293	}

drivers/gpu/drm/radeon/radeon_asic.c+2−0

@@ -1004,6 +1004,8 @@ static struct radeon_asic rv6xx_asic = { · 1003 unmodified lines
1004	1004	.wait_for_vblank = &avivo_wait_for_vblank,
1005	1005	.set_backlight_level = &atombios_set_backlight_level,
1006	1006	.get_backlight_level = &atombios_get_backlight_level,
	1007	+ .hdmi_enable = &r600_hdmi_enable,
	1008	+ .hdmi_setmode = &r600_hdmi_setmode,
1007	1009	},
1008	1010	.copy = {
1009	1011	.blit = &r600_copy_cpdma,

drivers/gpu/drm/radeon/radeon_atombios.c+43−23

@@ -1367,6 +1367,7 @@ bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, · 1366 unmodified lines
1367	1367	int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1368	1368	uint16_t data_offset, size;
1369	1369	struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
	1370	+ struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1370	1371	uint8_t frev, crev;
1371	1372	int i, num_indices;
1372	1373
@@ -1378,18 +1379,21 @@ bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, · 5 unmodified lines
1378	1379
1379	1380	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1380	1381	sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1381		−
	1382	+ ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
	1383	+ ((u8 *)&ss_info->asSS_Info[0]);
1382	1384	for (i = 0; i < num_indices; i++) {
1383		− if (ss_info->asSS_Info[i].ucSS_Id == id) {
	1385	+ if (ss_assign->ucSS_Id == id) {
1384	1386	ss->percentage =
1385		− le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1386		− ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1387		− ss->step = ss_info->asSS_Info[i].ucSS_Step;
1388		− ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1389		− ss->range = ss_info->asSS_Info[i].ucSS_Range;
1390		− ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
	1387	+ le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
	1388	+ ss->type = ss_assign->ucSpreadSpectrumType;
	1389	+ ss->step = ss_assign->ucSS_Step;
	1390	+ ss->delay = ss_assign->ucSS_Delay;
	1391	+ ss->range = ss_assign->ucSS_Range;
	1392	+ ss->refdiv = ss_assign->ucRecommendedRef_Div;
1391	1393	return true;
1392	1394	}
	1395	+ ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
	1396	+ ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1393	1397	}
1394	1398	}
1395	1399	return false;
@@ -1477,6 +1481,12 @@ union asic_ss_info { · 81 unmodified lines
1477	1481	struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1478	1482	};
1479	1483
	1484	+union asic_ss_assignment {
	1485	+ struct _ATOM_ASIC_SS_ASSIGNMENT v1;
	1486	+ struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
	1487	+ struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
	1488	+};
	1489	+
1480	1490	bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1481	1491	struct radeon_atom_ss *ss,
1482	1492	int id, u32 clock)
@@ -1485,6 +1495,7 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, · 2 unmodified lines
1485	1495	int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1486	1496	uint16_t data_offset, size;
1487	1497	union asic_ss_info *ss_info;
	1498	+ union asic_ss_assignment *ss_assign;
1488	1499	uint8_t frev, crev;
1489	1500	int i, num_indices;
1490	1501
@@ -1509,45 +1520,52 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, · 18 unmodified lines
1509	1520	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1510	1521	sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1511	1522
	1523	+ ss_assign = (union asic_ss_assignment )((u8 )&ss_info->info.asSpreadSpectrum[0]);
1512	1524	for (i = 0; i < num_indices; i++) {
1513		− if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1514		− (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
	1525	+ if ((ss_assign->v1.ucClockIndication == id) &&
	1526	+ (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1515	1527	ss->percentage =
1516		− le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1517		− ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1518		− ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
	1528	+ le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
	1529	+ ss->type = ss_assign->v1.ucSpreadSpectrumMode;
	1530	+ ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1519	1531	return true;
1520	1532	}
	1533	+ ss_assign = (union asic_ss_assignment *)
	1534	+ ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1521	1535	}
1522	1536	break;
1523	1537	case 2:
1524	1538	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1525	1539	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
	1540	+ ss_assign = (union asic_ss_assignment )((u8 )&ss_info->info_2.asSpreadSpectrum[0]);
1526	1541	for (i = 0; i < num_indices; i++) {
1527		− if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1528		− (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
	1542	+ if ((ss_assign->v2.ucClockIndication == id) &&
	1543	+ (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1529	1544	ss->percentage =
1530		− le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1531		− ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1532		− ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
	1545	+ le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
	1546	+ ss->type = ss_assign->v2.ucSpreadSpectrumMode;
	1547	+ ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1533	1548	if ((crev == 2) &&
1534	1549	((id == ASIC_INTERNAL_ENGINE_SS) \|\|
1535	1550	(id == ASIC_INTERNAL_MEMORY_SS)))
1536	1551	ss->rate /= 100;
1537	1552	return true;
1538	1553	}
	1554	+ ss_assign = (union asic_ss_assignment *)
	1555	+ ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1539	1556	}
1540	1557	break;
1541	1558	case 3:
1542	1559	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1543	1560	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
	1561	+ ss_assign = (union asic_ss_assignment )((u8 )&ss_info->info_3.asSpreadSpectrum[0]);
1544	1562	for (i = 0; i < num_indices; i++) {
1545		− if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1546		− (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
	1563	+ if ((ss_assign->v3.ucClockIndication == id) &&
	1564	+ (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1547	1565	ss->percentage =
1548		− le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1549		− ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1550		− ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
	1566	+ le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
	1567	+ ss->type = ss_assign->v3.ucSpreadSpectrumMode;
	1568	+ ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1551	1569	if ((id == ASIC_INTERNAL_ENGINE_SS) \|\|
1552	1570	(id == ASIC_INTERNAL_MEMORY_SS))
1553	1571	ss->rate /= 100;
@@ -1555,6 +1573,8 @@ bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, · 1 unmodified line
1555	1573	radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1556	1574	return true;
1557	1575	}
	1576	+ ss_assign = (union asic_ss_assignment *)
	1577	+ ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1558	1578	}
1559	1579	break;
1560	1580	default:

drivers/gpu/drm/radeon/radeon_cs.c+3−2

@@ -85,8 +85,9 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) · 84 unmodified lines
85	85	VRAM, also but everything into VRAM on AGP cards to avoid
86	86	image corruptions */
87	87	if (p->ring == R600_RING_TYPE_UVD_INDEX &&
88		− (i == 0 \|\| p->rdev->flags & RADEON_IS_AGP)) {
89		− /* TODO: is this still needed for NI+ ? */
	88	+ p->rdev->family < CHIP_PALM &&
	89	+ (i == 0 \|\| drm_pci_device_is_agp(p->rdev->ddev))) {
	90	+
90	91	p->relocs[i].lobj.domain =
91	92	RADEON_GEM_DOMAIN_VRAM;
92	93

drivers/gpu/drm/radeon/radeon_device.c+12−3

@@ -1320,13 +1320,22 @@ int radeon_device_init(struct radeon_device *rdev, · 1319 unmodified lines
1320	1320	return r;
1321	1321	}
1322	1322	if ((radeon_testing & 1)) {
1323		− radeon_test_moves(rdev);
	1323	+ if (rdev->accel_working)
	1324	+ radeon_test_moves(rdev);
	1325	+ else
	1326	+ DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1324	1327	}
1325	1328	if ((radeon_testing & 2)) {
1326		− radeon_test_syncing(rdev);
	1329	+ if (rdev->accel_working)
	1330	+ radeon_test_syncing(rdev);
	1331	+ else
	1332	+ DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1327	1333	}
1328	1334	if (radeon_benchmarking) {
1329		− radeon_benchmark(rdev, radeon_benchmarking);
	1335	+ if (rdev->accel_working)
	1336	+ radeon_benchmark(rdev, radeon_benchmarking);
	1337	+ else
	1338	+ DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1330	1339	}
1331	1340	return 0;
1332	1341	}

drivers/gpu/drm/radeon/radeon_pm.c+4−4

@@ -1002,7 +1002,7 @@ static void radeon_pm_resume_old(struct radeon_device *rdev) · 1001 unmodified lines
1002	1002	{
1003	1003	/* set up the default clocks if the MC ucode is loaded */
1004	1004	if ((rdev->family >= CHIP_BARTS) &&
1005		− (rdev->family <= CHIP_HAINAN) &&
	1005	+ (rdev->family <= CHIP_CAYMAN) &&
1006	1006	rdev->mc_fw) {
1007	1007	if (rdev->pm.default_vddc)
1008	1008	radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
@@ -1046,7 +1046,7 @@ static void radeon_pm_resume_dpm(struct radeon_device *rdev) · 37 unmodified lines
1046	1046	if (ret) {
1047	1047	DRM_ERROR("radeon: dpm resume failed\n");
1048	1048	if ((rdev->family >= CHIP_BARTS) &&
1049		− (rdev->family <= CHIP_HAINAN) &&
	1049	+ (rdev->family <= CHIP_CAYMAN) &&
1050	1050	rdev->mc_fw) {
1051	1051	if (rdev->pm.default_vddc)
1052	1052	radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
@@ -1097,7 +1097,7 @@ static int radeon_pm_init_old(struct radeon_device *rdev) · 44 unmodified lines
1097	1097	radeon_pm_init_profile(rdev);
1098	1098	/* set up the default clocks if the MC ucode is loaded */
1099	1099	if ((rdev->family >= CHIP_BARTS) &&
1100		− (rdev->family <= CHIP_HAINAN) &&
	1100	+ (rdev->family <= CHIP_CAYMAN) &&
1101	1101	rdev->mc_fw) {
1102	1102	if (rdev->pm.default_vddc)
1103	1103	radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
@@ -1183,7 +1183,7 @@ static int radeon_pm_init_dpm(struct radeon_device *rdev) · 79 unmodified lines
1183	1183	if (ret) {
1184	1184	rdev->pm.dpm_enabled = false;
1185	1185	if ((rdev->family >= CHIP_BARTS) &&
1186		− (rdev->family <= CHIP_HAINAN) &&
	1186	+ (rdev->family <= CHIP_CAYMAN) &&
1187	1187	rdev->mc_fw) {
1188	1188	if (rdev->pm.default_vddc)
1189	1189	radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,

drivers/gpu/drm/radeon/radeon_ring.c+5−3

@@ -839,9 +839,11 @@ static int radeon_debugfs_ring_info(struct seq_file m, void data) · 838 unmodified lines
839	839	* packet that is the root issue
840	840	*/
841	841	i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
842		− for (j = 0; j <= (count + 32); j++) {
843		− seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
844		− i = (i + 1) & ring->ptr_mask;
	842	+ if (ring->ready) {
	843	+ for (j = 0; j <= (count + 32); j++) {
	844	+ seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
	845	+ i = (i + 1) & ring->ptr_mask;
	846	+ }
845	847	}
846	848	return 0;
847	849	}

drivers/gpu/drm/radeon/radeon_uvd.c+1−2

@@ -476,8 +476,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, · 475 unmodified lines
476	476	return -EINVAL;
477	477	}
478	478
479		− /* TODO: is this still necessary on NI+ ? */
480		− if ((cmd == 0 \|\| cmd == 0x3) &&
	479	+ if (p->rdev->family < CHIP_PALM && (cmd == 0 \|\| cmd == 0x3) &&
481	480	(start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
482	481	DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
483	482	start, end);

drivers/gpu/drm/radeon/si_dpm.c+24−0

@@ -2910,6 +2910,7 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, · 2909 unmodified lines
2910	2910	bool disable_sclk_switching = false;
2911	2911	u32 mclk, sclk;
2912	2912	u16 vddc, vddci;
	2913	+ u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2913	2914	int i;
2914	2915
2915	2916	if ((rdev->pm.dpm.new_active_crtc_count > 1) \|\|
@@ -2943,6 +2944,29 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev, · 27 unmodified lines
2943	2944	}
2944	2945	}
2945	2946
	2947	+ /* limit clocks to max supported clocks based on voltage dependency tables */
	2948	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
	2949	+ &max_sclk_vddc);
	2950	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
	2951	+ &max_mclk_vddci);
	2952	+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
	2953	+ &max_mclk_vddc);
	2954	+
	2955	+ for (i = 0; i < ps->performance_level_count; i++) {
	2956	+ if (max_sclk_vddc) {
	2957	+ if (ps->performance_levels[i].sclk > max_sclk_vddc)
	2958	+ ps->performance_levels[i].sclk = max_sclk_vddc;
	2959	+ }
	2960	+ if (max_mclk_vddci) {
	2961	+ if (ps->performance_levels[i].mclk > max_mclk_vddci)
	2962	+ ps->performance_levels[i].mclk = max_mclk_vddci;
	2963	+ }
	2964	+ if (max_mclk_vddc) {
	2965	+ if (ps->performance_levels[i].mclk > max_mclk_vddc)
	2966	+ ps->performance_levels[i].mclk = max_mclk_vddc;
	2967	+ }
	2968	+ }
	2969	+
2946	2970	/* XXX validate the min clocks required for display */
2947	2971
2948	2972	if (disable_mclk_switching) {

drivers/gpu/drm/radeon/uvd_v1_0.c+2−2

@@ -212,8 +212,8 @@ int uvd_v1_0_start(struct radeon_device *rdev) · 211 unmodified lines
212	212	/* enable VCPU clock */
213	213	WREG32(UVD_VCPU_CNTL, 1 << 9);
214	214
215		− /* enable UMC */
216		− WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
	215	+ /* enable UMC and NC0 */
	216	+ WREG32_P(UVD_LMI_CTRL2, 1 << 13, ~((1 << 8) \| (1 << 13)));
217	217
218	218	/* boot up the VCPU */
219	219	WREG32(UVD_SOFT_RESET, 0);

include/uapi/drm/radeon_drm.h+2−0

@@ -1007,4 +1007,6 @@ struct drm_radeon_info { · 1006 unmodified lines
1007	1007	#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
1008	1008	#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
1009	1009
	1010	+#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
	1011	+
1010	1012	#endif

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

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