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drm/i915: use REG_FIELD_PREP() to define register bitfield values

Slightly verbose, but does away with hand rolled shifts. Ties the field values with the mask defining the field. Unfortunately we have to make a local copy of FIELD_PREP() to evaluate to a integer constant expression. But with this, we can ensure the mask is non-zero, power of 2, fits u32, and the value fits the mask (when the value is a constant expression). Convert power sequencer registers as an example. v4: - rebase v3: - rename the macro to REG_FIELD_PREP to avoid underscore prefix and to be in line with kernel macros (Chris) - rename power of 2 check macro (Chris) v2: - add build-time checks with BUILD_BUG_ON_ZERO() - rename to just _FIELD() due to regmap.h REG_FIELD() clash

Jani Nikula committed 7 years ago

Commit baa09e71 parent 78b36b11 file · +39 −30Browse files

Unified · Split

drivers/gpu/drm/i915/i915_reg.h+39−30
@@ -62,11 +62,11 @@ · 61 unmodified lines
6262 * significant to least significant bit. Indent the register content macros
6363 * using two extra spaces between ``#define`` and the macro name.
6464 *
65− * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents so
66− * that they are already shifted in place, and can be directly OR'd. For
67− * convenience, function-like macros may be used to define bit fields, but do
68− * note that the macros may be needed to read as well as write the register
69− * contents.
65+ * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66+ * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67+ * shifted in place, so they can be directly OR'd together. For convenience,
68+ * function-like macros may be used to define bit fields, but do note that the
69+ * macros may be needed to read as well as write the register contents.
7070 *
7171 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
7272 *
@@ -108,9 +108,9 @@ · 35 unmodified lines
108108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109109 * #define FOO_ENABLE REG_BIT(31)
110110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111− * #define FOO_MODE_BAR (0 << 16)
112− * #define FOO_MODE_BAZ (1 << 16)
113− * #define FOO_MODE_QUX_SNB (2 << 16)
111+ * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112+ * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113+ * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
114114 *
115115 * #define BAR _MMIO(0xb000)
116116 * #define GEN8_BAR _MMIO(0xb888)
@@ -144,17 +144,27 @@ · 27 unmodified lines
144144 __builtin_constant_p(__low) && \
145145 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
146146
147+/*
148+ * Local integer constant expression version of is_power_of_2().
149+ */
150+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
151+
147152 /**
148153 * REG_FIELD_PREP() - Prepare a u32 bitfield value
149154 * @__mask: shifted mask defining the field's length and position
150155 * @__val: value to put in the field
151156
152− * Local wrapper for FIELD_PREP() to force u32 and for consistency with
153− * REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
157+ * Local copy of FIELD_PREP() to generate an integer constant expression, force
158+ * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
154159 *
155160 * @return: @__val masked and shifted into the field defined by @__mask.
156161 */
157−#define REG_FIELD_PREP(__mask, __val) ((u32)FIELD_PREP(__mask, __val))
162+#define REG_FIELD_PREP(__mask, __val) \
163+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
164+ BUILD_BUG_ON_ZERO(!__builtin_constant_p(__mask)) + \
165+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
166+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
167+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
158168
159169 /**
160170 * REG_FIELD_GET() - Extract a u32 bitfield value
@@ -4764,27 +4774,26 @@ enum { · 4603 unmodified lines
47644774 */
47654775 #define PP_READY REG_BIT(30)
47664776 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28)
4767−#define PP_SEQUENCE_NONE (0 << 28)
4768−#define PP_SEQUENCE_POWER_UP (1 << 28)
4769−#define PP_SEQUENCE_POWER_DOWN (2 << 28)
4777+#define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
4778+#define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
4779+#define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
47704780 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
47714781 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0)
4772−#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
4773−#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
4774−#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
4775−#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
4776−#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
4777−#define PP_SEQUENCE_STATE_ON_S1_1 (0x9 << 0)
4778−#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
4779−#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
4780−#define PP_SEQUENCE_STATE_RESET (0xf << 0)
4782+#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
4783+#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
4784+#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
4785+#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
4786+#define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
4787+#define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
4788+#define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
4789+#define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
4790+#define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
47814791
47824792 #define _PP_CONTROL 0x61204
47834793 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
47844794 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16)
4785−#define PANEL_UNLOCK_REGS (0xabcd << 16)
4795+#define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
47864796 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4)
4787−#define BXT_POWER_CYCLE_DELAY_SHIFT 4
47884797 #define EDP_FORCE_VDD REG_BIT(3)
47894798 #define EDP_BLC_ENABLE REG_BIT(2)
47904799 #define PANEL_POWER_RESET REG_BIT(1)
@@ -4793,11 +4802,11 @@ enum { · 2 unmodified lines
47934802 #define _PP_ON_DELAYS 0x61208
47944803 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
47954804 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30)
4796−#define PANEL_PORT_SELECT_LVDS (0 << 30)
4797−#define PANEL_PORT_SELECT_DPA (1 << 30)
4798−#define PANEL_PORT_SELECT_DPC (2 << 30)
4799−#define PANEL_PORT_SELECT_DPD (3 << 30)
4800−#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
4805+#define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
4806+#define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1)
4807+#define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2)
4808+#define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3)
4809+#define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)
48014810 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16)
48024811 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0)
48034812