History

Merge tag 'fpga-for-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga into char-misc-next

Moritz writes: FPGA Manager changes for 5.19-rc1 FPGA Manager - My change moves the linux-fpga repository to a shared location w/ shared responsibilities between maintainers - Nava's changes fix coding style and kernel-docs DFL - Matthew's change allows ports to be linked to FMEs. - Tianfei's changes clean up some documentation and ensure the feature type is checked before parsing IRQs All patches have been reviewed on the mailing list, and have been in the last linux-next releases (as part of our for-next branch). Signed-off-by: Moritz Fischer <mdf@kernel.org> * tag 'fpga-for-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga: fpga: dfl: Allow Port to be linked to FME's DFL Documentation: fpga: dfl: add link address of feature id table fpga: dfl: check feature type before parse irq info fpga: fpga-region: fix kernel-doc formatting issues fpga: Use tab instead of space indentation fpga: fpga-mgr: fix kernel-doc warnings fpga: fix for coding style issues MAINTAINERS: Update linux-fpga repository location

Greg Kroah-Hartman committed 4 years ago

Commit bab6ffa2 parents 9c518db ae23f7410 files · +68 −40Browse files

Unified · Split

10 files
  1. Documentation/fpga/dfl.rst +5 −0
  2. MAINTAINERS +1 −1
  3. drivers/fpga/Makefile +3 −3
  4. drivers/fpga/dfl-pci.c +9 −0
  5. drivers/fpga/dfl.c +22 −16
  6. drivers/fpga/dfl.h +1 −0
  7. drivers/fpga/fpga-mgr.c +9 −4
  8. drivers/fpga/fpga-region.c +3 −3
  9. drivers/fpga/of-fpga-region.c +12 −10
  10. include/linux/fpga/fpga-region.h +3 −3
Documentation/fpga/dfl.rst+5−0
@@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id. · 501 unmodified lines
502FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)502FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
503could be a reference.503could be a reference.
504 504
505Please refer to below link to existing feature id table and guide for new feature
506ids application.
507https://github.com/OPAE/dfl-feature-id
508
509
505Location of DFLs on a PCI Device510Location of DFLs on a PCI Device
506================================511================================
507The original method for finding a DFL on a PCI device assumed the start of the512The original method for finding a DFL on a PCI device assumed the start of the
MAINTAINERS+1−1
@@ -7732,7 +7732,7 @@ R: Tom Rix <trix@redhat.com> · 7731 unmodified lines
7732L: linux-fpga@vger.kernel.org7732L: linux-fpga@vger.kernel.org
7733S: Maintained7733S: Maintained
7734Q: http://patchwork.kernel.org/project/linux-fpga/list/7734Q: http://patchwork.kernel.org/project/linux-fpga/list/
7735T: git git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga.git7735T: git git://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga.git
7736F: Documentation/devicetree/bindings/fpga/7736F: Documentation/devicetree/bindings/fpga/
7737F: Documentation/driver-api/fpga/7737F: Documentation/driver-api/fpga/
7738F: Documentation/fpga/7738F: Documentation/fpga/
drivers/fpga/Makefile+3−3
@@ -18,9 +18,9 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o · 17 unmodified lines
18obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o18obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
19obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o19obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
20obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o20obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
21obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o21obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
22obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o22obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
23obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o23obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
24 24
25# FPGA Bridge Drivers25# FPGA Bridge Drivers
26obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o26obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
drivers/fpga/dfl-pci.c+9−0
@@ -259,6 +259,15 @@ static int find_dfls_by_default(struct pci_dev *pcidev, · 258 unmodified lines
259 */259 */
260 bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);260 bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
261 offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);261 offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
262 if (bar == FME_PORT_OFST_BAR_SKIP) {
263 continue;
264 } else if (bar >= PCI_STD_NUM_BARS) {
265 dev_err(&pcidev->dev, "bad BAR %d for port %d\n",
266 bar, i);
267 ret = -EINVAL;
268 break;
269 }
270
262 start = pci_resource_start(pcidev, bar) + offset;271 start = pci_resource_start(pcidev, bar) + offset;
263 len = pci_resource_len(pcidev, bar) - offset;272 len = pci_resource_len(pcidev, bar) - offset;
264 273
drivers/fpga/dfl.c+22−16
@@ -940,9 +940,12 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, · 939 unmodified lines
940{940{
941 void __iomem *base = binfo->ioaddr + ofst;941 void __iomem *base = binfo->ioaddr + ofst;
942 unsigned int i, ibase, inr = 0;942 unsigned int i, ibase, inr = 0;
943 enum dfl_id_type type;
943 int virq;944 int virq;
944 u64 v;945 u64 v;
945 946
947 type = feature_dev_id_type(binfo->feature_dev);
948
946 /*949 /*
947 * Ideally DFL framework should only read info from DFL header, but950 * Ideally DFL framework should only read info from DFL header, but
948 * current version DFL only provides mmio resources information for951 * current version DFL only provides mmio resources information for
@@ -957,22 +960,25 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, · 8 unmodified lines
957 * code will be added. But in order to be compatible to old version960 * code will be added. But in order to be compatible to old version
958 * DFL, the driver may still fall back to these quirks.961 * DFL, the driver may still fall back to these quirks.
959 */962 */
960 switch (fid) {963 if (type == PORT_ID) {
961 case PORT_FEATURE_ID_UINT:964 switch (fid) {
962 v = readq(base + PORT_UINT_CAP);965 case PORT_FEATURE_ID_UINT:
963 ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v);966 v = readq(base + PORT_UINT_CAP);
964 inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v);967 ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
965 break;968 inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
966 case PORT_FEATURE_ID_ERROR:969 break;
967 v = readq(base + PORT_ERROR_CAP);970 case PORT_FEATURE_ID_ERROR:
968 ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);971 v = readq(base + PORT_ERROR_CAP);
969 inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);972 ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
970 break;973 inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
971 case FME_FEATURE_ID_GLOBAL_ERR:974 break;
972 v = readq(base + FME_ERROR_CAP);975 }
973 ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);976 } else if (type == FME_ID) {
974 inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);977 if (fid == FME_FEATURE_ID_GLOBAL_ERR) {
975 break;978 v = readq(base + FME_ERROR_CAP);
979 ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
980 inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
981 }
976 }982 }
977 983
978 if (!inr) {984 if (!inr) {
drivers/fpga/dfl.h+1−0
@@ -89,6 +89,7 @@ · 88 unmodified lines
89#define FME_HDR_NEXT_AFU NEXT_AFU89#define FME_HDR_NEXT_AFU NEXT_AFU
90#define FME_HDR_CAP 0x3090#define FME_HDR_CAP 0x30
91#define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))91#define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))
92#define FME_PORT_OFST_BAR_SKIP 7
92#define FME_HDR_BITSTREAM_ID 0x6093#define FME_HDR_BITSTREAM_ID 0x60
93#define FME_HDR_BITSTREAM_MD 0x6894#define FME_HDR_BITSTREAM_MD 0x68
94 95
drivers/fpga/fpga-mgr.c+9−4
@@ -148,11 +148,12 @@ static int fpga_mgr_write_init_buf(struct fpga_manager *mgr, · 147 unmodified lines
148 int ret;148 int ret;
149 149
150 mgr->state = FPGA_MGR_STATE_WRITE_INIT;150 mgr->state = FPGA_MGR_STATE_WRITE_INIT;
151 if (!mgr->mops->initial_header_size)151 if (!mgr->mops->initial_header_size) {
152 ret = fpga_mgr_write_init(mgr, info, NULL, 0);152 ret = fpga_mgr_write_init(mgr, info, NULL, 0);
153 else153 } else {
154 ret = fpga_mgr_write_init(154 count = min(mgr->mops->initial_header_size, count);
155 mgr, info, buf, min(mgr->mops->initial_header_size, count));155 ret = fpga_mgr_write_init(mgr, info, buf, count);
156 }
156 157
157 if (ret) {158 if (ret) {
158 dev_err(&mgr->dev, "Error preparing FPGA for writing\n");159 dev_err(&mgr->dev, "Error preparing FPGA for writing\n");
@@ -730,6 +731,8 @@ static void devm_fpga_mgr_unregister(struct device *dev, void *res) · 571 unmodified lines
730 * @parent: fpga manager device from pdev731 * @parent: fpga manager device from pdev
731 * @info: parameters for fpga manager732 * @info: parameters for fpga manager
732 *733 *
734 * Return: fpga manager pointer on success, negative error code otherwise.
735 *
733 * This is the devres variant of fpga_mgr_register_full() for which the unregister736 * This is the devres variant of fpga_mgr_register_full() for which the unregister
734 * function will be called automatically when the managing device is detached.737 * function will be called automatically when the managing device is detached.
735 */738 */
@@ -763,6 +766,8 @@ EXPORT_SYMBOL_GPL(devm_fpga_mgr_register_full); · 27 unmodified lines
763 * @mops: pointer to structure of fpga manager ops766 * @mops: pointer to structure of fpga manager ops
764 * @priv: fpga manager private data767 * @priv: fpga manager private data
765 *768 *
769 * Return: fpga manager pointer on success, negative error code otherwise.
770 *
766 * This is the devres variant of fpga_mgr_register() for which the771 * This is the devres variant of fpga_mgr_register() for which the
767 * unregister function will be called automatically when the managing772 * unregister function will be called automatically when the managing
768 * device is detached.773 * device is detached.
drivers/fpga/fpga-region.c+3−3
@@ -18,9 +18,9 @@ · 17 unmodified lines
18static DEFINE_IDA(fpga_region_ida);18static DEFINE_IDA(fpga_region_ida);
19static struct class *fpga_region_class;19static struct class *fpga_region_class;
20 20
21struct fpga_region *fpga_region_class_find(21struct fpga_region *
22 struct device *start, const void *data,22fpga_region_class_find(struct device *start, const void *data,
23 int (*match)(struct device *, const void *))23 int (*match)(struct device *, const void *))
24{24{
25 struct device *dev;25 struct device *dev;
26 26
drivers/fpga/of-fpga-region.c+12−10
@@ -28,7 +28,7 @@ MODULE_DEVICE_TABLE(of, fpga_region_of_match); · 27 unmodified lines
28 *28 *
29 * Caller will need to put_device(&region->dev) when done.29 * Caller will need to put_device(&region->dev) when done.
30 *30 *
31 * Returns FPGA Region struct or NULL31 * Return: FPGA Region struct or NULL
32 */32 */
33static struct fpga_region *of_fpga_region_find(struct device_node *np)33static struct fpga_region *of_fpga_region_find(struct device_node *np)
34{34{
@@ -80,7 +80,7 @@ static struct fpga_manager *of_fpga_region_get_mgr(struct device_node *np) · 45 unmodified lines
80 * Caller should call fpga_bridges_put(&region->bridge_list) when80 * Caller should call fpga_bridges_put(&region->bridge_list) when
81 * done with the bridges.81 * done with the bridges.
82 *82 *
83 * Return 0 for success (even if there are no bridges specified)83 * Return: 0 for success (even if there are no bridges specified)
84 * or -EBUSY if any of the bridges are in use.84 * or -EBUSY if any of the bridges are in use.
85 */85 */
86static int of_fpga_region_get_bridges(struct fpga_region *region)86static int of_fpga_region_get_bridges(struct fpga_region *region)
@@ -139,13 +139,13 @@ static int of_fpga_region_get_bridges(struct fpga_region *region) · 52 unmodified lines
139}139}
140 140
141/**141/**
142 * child_regions_with_firmware142 * child_regions_with_firmware - Used to check the child region info.
143 * @overlay: device node of the overlay143 * @overlay: device node of the overlay
144 *144 *
145 * If the overlay adds child FPGA regions, they are not allowed to have145 * If the overlay adds child FPGA regions, they are not allowed to have
146 * firmware-name property.146 * firmware-name property.
147 *147 *
148 * Return 0 for OK or -EINVAL if child FPGA region adds firmware-name.148 * Return: 0 for OK or -EINVAL if child FPGA region adds firmware-name.
149 */149 */
150static int child_regions_with_firmware(struct device_node *overlay)150static int child_regions_with_firmware(struct device_node *overlay)
151{151{
@@ -184,14 +184,14 @@ static int child_regions_with_firmware(struct device_node *overlay) · 32 unmodified lines
184 * Given an overlay applied to an FPGA region, parse the FPGA image specific184 * Given an overlay applied to an FPGA region, parse the FPGA image specific
185 * info in the overlay and do some checking.185 * info in the overlay and do some checking.
186 *186 *
187 * Returns:187 * Return:
188 * NULL if overlay doesn't direct us to program the FPGA.188 * NULL if overlay doesn't direct us to program the FPGA.
189 * fpga_image_info struct if there is an image to program.189 * fpga_image_info struct if there is an image to program.
190 * error code for invalid overlay.190 * error code for invalid overlay.
191 */191 */
192static struct fpga_image_info *of_fpga_region_parse_ov(192static struct fpga_image_info *
193 struct fpga_region *region,193of_fpga_region_parse_ov(struct fpga_region *region,
194 struct device_node *overlay)194 struct device_node *overlay)
195{195{
196 struct device *dev = &region->dev;196 struct device *dev = &region->dev;
197 struct fpga_image_info *info;197 struct fpga_image_info *info;
@@ -279,7 +279,7 @@ ret_no_info: · 81 unmodified lines
279 * If the checks fail, overlay is rejected and does not get added to the279 * If the checks fail, overlay is rejected and does not get added to the
280 * live tree.280 * live tree.
281 *281 *
282 * Returns 0 for success or negative error code for failure.282 * Return: 0 for success or negative error code for failure.
283 */283 */
284static int of_fpga_region_notify_pre_apply(struct fpga_region *region,284static int of_fpga_region_notify_pre_apply(struct fpga_region *region,
285 struct of_overlay_notify_data *nd)285 struct of_overlay_notify_data *nd)
@@ -339,7 +339,7 @@ static void of_fpga_region_notify_post_remove(struct fpga_region *region, · 53 unmodified lines
339 * This notifier handles programming an FPGA when a "firmware-name" property is339 * This notifier handles programming an FPGA when a "firmware-name" property is
340 * added to an fpga-region.340 * added to an fpga-region.
341 *341 *
342 * Returns NOTIFY_OK or error if FPGA programming fails.342 * Return: NOTIFY_OK or error if FPGA programming fails.
343 */343 */
344static int of_fpga_region_notify(struct notifier_block *nb,344static int of_fpga_region_notify(struct notifier_block *nb,
345 unsigned long action, void *arg)345 unsigned long action, void *arg)
@@ -446,6 +446,8 @@ static struct platform_driver of_fpga_region_driver = { · 100 unmodified lines
446/**446/**
447 * of_fpga_region_init - init function for fpga_region class447 * of_fpga_region_init - init function for fpga_region class
448 * Creates the fpga_region class and registers a reconfig notifier.448 * Creates the fpga_region class and registers a reconfig notifier.
449 *
450 * Return: 0 on success, negative error code otherwise.
449 */451 */
450static int __init of_fpga_region_init(void)452static int __init of_fpga_region_init(void)
451{453{
include/linux/fpga/fpga-region.h+3−3
@@ -52,9 +52,9 @@ struct fpga_region { · 51 unmodified lines
52 52
53#define to_fpga_region(d) container_of(d, struct fpga_region, dev)53#define to_fpga_region(d) container_of(d, struct fpga_region, dev)
54 54
55struct fpga_region *fpga_region_class_find(55struct fpga_region *
56 struct device *start, const void *data,56fpga_region_class_find(struct device *start, const void *data,
57 int (*match)(struct device *, const void *));57 int (*match)(struct device *, const void *));
58 58
59int fpga_region_program_fpga(struct fpga_region *region);59int fpga_region_program_fpga(struct fpga_region *region);
60 60

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