Write protect bit, when set, inhibits supervisor writes to the read-only pages. In guest supervisor shared virtual addressing (SVA), write-protect should be honored upon guest bind supervisor PASID request. This patch extends the VT-d portion of the IOMMU UAPI to include WP bit. WPE bit of the supervisor PASID entry will be set to match CPU CR0.WP bit.
Unified · Split
| @@ -732,6 +732,9 @@ intel_pasid_setup_bind_data(struct intel_iommu *iommu, struct pasid_entry *pte, · 731 unmodified lines | |||
| 732 | return -EINVAL; | 732 | return -EINVAL; |
| 733 | } | 733 | } |
| 734 | pasid_set_sre(pte); | 734 | pasid_set_sre(pte); |
| 735 | /* Enable write protect WP if guest requested */ | ||
| 736 | if (pasid_data->flags & IOMMU_SVA_VTD_GPASID_WPE) | ||
| 737 | pasid_set_wpe(pte); | ||
| 735 | } | 738 | } |
| 736 | 739 | ||
| 737 | if (pasid_data->flags & IOMMU_SVA_VTD_GPASID_EAFE) { | 740 | if (pasid_data->flags & IOMMU_SVA_VTD_GPASID_EAFE) { |
| @@ -288,7 +288,8 @@ struct iommu_gpasid_bind_data_vtd { · 287 unmodified lines | |||
| 288 | #define IOMMU_SVA_VTD_GPASID_PWT (1 << 3) /* page-level write through */ | 288 | #define IOMMU_SVA_VTD_GPASID_PWT (1 << 3) /* page-level write through */ |
| 289 | #define IOMMU_SVA_VTD_GPASID_EMTE (1 << 4) /* extended mem type enable */ | 289 | #define IOMMU_SVA_VTD_GPASID_EMTE (1 << 4) /* extended mem type enable */ |
| 290 | #define IOMMU_SVA_VTD_GPASID_CD (1 << 5) /* PASID-level cache disable */ | 290 | #define IOMMU_SVA_VTD_GPASID_CD (1 << 5) /* PASID-level cache disable */ |
| 291 | #define IOMMU_SVA_VTD_GPASID_LAST (1 << 6) | 291 | #define IOMMU_SVA_VTD_GPASID_WPE (1 << 6) /* Write protect enable */ |
| 292 | #define IOMMU_SVA_VTD_GPASID_LAST (1 << 7) | ||
| 292 | __u64 flags; | 293 | __u64 flags; |
| 293 | __u32 pat; | 294 | __u32 pat; |
| 294 | __u32 emt; | 295 | __u32 emt; |