- AMD provides custom protocol to read Processor feature capabilities and configuration information through side band. The information is accessed by providing CPUID Function, extended function and thread ID to the protocol. Undefined function returns 0.
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| @@ -25,6 +25,24 @@ struct apml_mbox_msg { · 24 unmodified lines | |||
| 25 | __u32 fw_ret_code; | 25 | __u32 fw_ret_code; |
| 26 | }; | 26 | }; |
| 27 | 27 | ||
| 28 | struct apml_cpuid_msg { | ||
| 29 | /* | ||
| 30 | * CPUID input | ||
| 31 | * [0]...[3] cpuid func, | ||
| 32 | * [4][5] cpuid: thread | ||
| 33 | * [6] cpuid: ext function & read eax/ebx or ecx/edx | ||
| 34 | * [7:0] -> bits [7:4] -> ext function & | ||
| 35 | * bit [0] read eax/ebx or ecx/edx | ||
| 36 | * CPUID output | ||
| 37 | */ | ||
| 38 | __u64 cpu_in_out; | ||
| 39 | /* | ||
| 40 | * Status code for CPUID read | ||
| 41 | */ | ||
| 42 | __u32 fw_ret_code; | ||
| 43 | __u32 pad; | ||
| 44 | }; | ||
| 45 | |||
| 28 | /* | 46 | /* |
| 29 | * AMD sideband interface base IOCTL | 47 | * AMD sideband interface base IOCTL |
| 30 | */ | 48 | */ |
| @@ -48,4 +66,23 @@ struct apml_mbox_msg { · 17 unmodified lines | |||
| 48 | */ | 66 | */ |
| 49 | #define SBRMI_IOCTL_MBOX_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_mbox_msg) | 67 | #define SBRMI_IOCTL_MBOX_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_mbox_msg) |
| 50 | 68 | ||
| 69 | /** | ||
| 70 | * DOC: SBRMI_IOCTL_CPUID_CMD | ||
| 71 | * | ||
| 72 | * @Parameters | ||
| 73 | * | ||
| 74 | * @struct apml_cpuid_msg | ||
| 75 | * Pointer to the &struct apml_cpuid_msg that will contain the protocol | ||
| 76 | * information | ||
| 77 | * | ||
| 78 | * @Description | ||
| 79 | * IOCTL command for APML messages using generic _IOWR | ||
| 80 | * The IOCTL provides userspace access to AMD sideband cpuid protocol | ||
| 81 | * - CPUID protocol to get CPU details for Function/Ext Function | ||
| 82 | * at thread level | ||
| 83 | * - returning "-EFAULT" if none of the above | ||
| 84 | * "-EPROTOTYPE" error is returned to provide additional error details | ||
| 85 | */ | ||
| 86 | #define SBRMI_IOCTL_CPUID_CMD _IOWR(SB_BASE_IOCTL_NR, 1, struct apml_cpuid_msg) | ||
| 87 | |||
| 51 | #endif /*_AMD_APML_H_*/ | 88 | #endif /*_AMD_APML_H_*/ |