Pull IOMMU updates from Joerg Roedel: - A big cleanup and optimization patch-set for the Tegra GART driver - Documentation updates and fixes for the IOMMU-API - Support for page request in Intel VT-d scalable mode - Intel VT-d dma_[un]map_resource() support - Updates to the ATS enabling code for PCI (acked by Bjorn) and Intel VT-d to align with the latest version of the ATS spec - Relaxed IRQ source checking in the Intel VT-d driver for some aliased devices, needed for future devices which send IRQ messages from more than on request-ID - IRQ remapping driver for Hyper-V - Patches to make generic IOVA and IO-Page-Table code usable outside of the IOMMU code - Various other small fixes and cleanups * tag 'iommu-updates-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (60 commits) iommu/vt-d: Get domain ID before clear pasid entry iommu/vt-d: Fix NULL pointer reference in intel_svm_bind_mm() iommu/vt-d: Set context field after value initialized iommu/vt-d: Disable ATS support on untrusted devices iommu/mediatek: Fix semicolon code style issue MAINTAINERS: Add Hyper-V IOMMU driver into Hyper-V CORE AND DRIVERS scope iommu/hyper-v: Add Hyper-V stub IOMMU driver x86/Hyper-V: Set x2apic destination mode to physical when x2apic is available PCI/ATS: Add inline to pci_prg_resp_pasid_required() iommu/vt-d: Check identity map for hot-added devices iommu: Fix IOMMU debugfs fallout iommu: Document iommu_ops.is_attach_deferred() iommu: Document iommu_ops.iotlb_sync_map() iommu/vt-d: Enable ATS only if the device uses page aligned address. PCI/ATS: Add pci_ats_page_aligned() interface iommu/vt-d: Fix PRI/PASID dependency issue. PCI/ATS: Add pci_prg_resp_pasid_required() interface. iommu/vt-d: Allow interrupts from the entire bus for aliased devices iommu/vt-d: Add helper to set an IRTE to verify only the bus number iommu: Fix flush_tlb_all typo ...
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| @@ -866,6 +866,7 @@ · 865 unmodified lines | |||
| 866 | #define PCI_ATS_CAP 0x04 /* ATS Capability Register */ | 866 | #define PCI_ATS_CAP 0x04 /* ATS Capability Register */ |
| 867 | #define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ | 867 | #define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ |
| 868 | #define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ | 868 | #define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ |
| 869 | #define PCI_ATS_CAP_PAGE_ALIGNED 0x0020 /* Page Aligned Request */ | ||
| 869 | #define PCI_ATS_CTRL 0x06 /* ATS Control Register */ | 870 | #define PCI_ATS_CTRL 0x06 /* ATS Control Register */ |
| 870 | #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ | 871 | #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ |
| 871 | #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ | 872 | #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ |
| @@ -880,6 +881,7 @@ · 8 unmodified lines | |||
| 880 | #define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ | 881 | #define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ |
| 881 | #define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ | 882 | #define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ |
| 882 | #define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ | 883 | #define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ |
| 884 | #define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */ | ||
| 883 | #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ | 885 | #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ |
| 884 | #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ | 886 | #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ |
| 885 | #define PCI_EXT_CAP_PRI_SIZEOF 16 | 887 | #define PCI_EXT_CAP_PRI_SIZEOF 16 |