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PCI: Add #defines for Enter Compliance, Transmit Margin

Add definitions for the Enter Compliance and Transmit Margin fields of the PCIe Link Control 2 register.

Bjorn Helgaas committed 7 years ago

Commit bbdb2f51 parent b7da3d41 file · +2 −0Browse files

Showing the changes to include/uapi/linux (1 of 1 file). Show all

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include/uapi/linux/pci_regs.h+2−0
@@ -673,6 +673,8 @@ · 672 unmodified lines
673#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */673#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
674#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */674#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
675#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */675#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
676#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
677#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
676#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */678#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
677#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */679#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
678#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */680#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */