SKL+ display engine can scan out certain kinds of compressed surfaces produced by the render engine. This involved telling the display engine the location of the color control surfae (CCS) which describes which parts of the main surface are compressed and which are not. The location of CCS is provided by userspace as just another plane with its own offset. By providing our own format information for the CCS formats, we should be able to make framebuffer_check() do the right thing for the CCS surface as well. Note that we'll return the same format info for both Y and Yf tiled format as that's what happens with the non-CCS Y vs. Yf as well. If desired, we could potentially return a unique pointer for each pixel_format+tiling+ccs combination, in which case we immediately be able to tell if any of that stuff changed by just comparing the pointers. But that does sound a bit wasteful space wise. v2: Drop the 'dev' argument from the hook v3: Include the description of the CCS surface layout v4: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason) v5: Re-drop 'dev', fix commit message, add missing drm_fourcc.h description of CCS layout. (daniels)
Unified · Split
| @@ -2428,6 +2428,41 @@ static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) · 2427 unmodified lines | ||
| 2428 | 2428 | } |
| 2429 | 2429 | } |
| 2430 | 2430 | |
| 2431 | +static const struct drm_format_info ccs_formats[] = { | |
| 2432 | + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
| 2433 | + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
| 2434 | + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
| 2435 | + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
| 2436 | +}; | |
| 2437 | + | |
| 2438 | +static const struct drm_format_info * | |
| 2439 | +lookup_format_info(const struct drm_format_info formats[], | |
| 2440 | + int num_formats, u32 format) | |
| 2441 | +{ | |
| 2442 | + int i; | |
| 2443 | + | |
| 2444 | + for (i = 0; i < num_formats; i++) { | |
| 2445 | + if (formats[i].format == format) | |
| 2446 | + return &formats[i]; | |
| 2447 | + } | |
| 2448 | + | |
| 2449 | + return NULL; | |
| 2450 | +} | |
| 2451 | + | |
| 2452 | +static const struct drm_format_info * | |
| 2453 | +intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) | |
| 2454 | +{ | |
| 2455 | + switch (cmd->modifier[0]) { | |
| 2456 | + case I915_FORMAT_MOD_Y_TILED_CCS: | |
| 2457 | + case I915_FORMAT_MOD_Yf_TILED_CCS: | |
| 2458 | + return lookup_format_info(ccs_formats, | |
| 2459 | + ARRAY_SIZE(ccs_formats), | |
| 2460 | + cmd->pixel_format); | |
| 2461 | + default: | |
| 2462 | + return NULL; | |
| 2463 | + } | |
| 2464 | +} | |
| 2465 | + | |
| 2431 | 2466 | static int |
| 2432 | 2467 | intel_fill_fb_info(struct drm_i915_private *dev_priv, |
| 2433 | 2468 | struct drm_framebuffer *fb) |
| @@ -13673,6 +13708,7 @@ static void intel_atomic_state_free(struct drm_atomic_state *state) · 11239 unmodified lines | ||
| 13673 | 13708 | |
| 13674 | 13709 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
| 13675 | 13710 | .fb_create = intel_user_framebuffer_create, |
| 13711 | + .get_format_info = intel_get_format_info, | |
| 13676 | 13712 | .output_poll_changed = intel_fbdev_output_poll_changed, |
| 13677 | 13713 | .atomic_check = intel_atomic_check, |
| 13678 | 13714 | .atomic_commit = intel_atomic_commit, |
| @@ -263,6 +263,26 @@ extern "C" { · 262 unmodified lines | ||
| 263 | 263 | */ |
| 264 | 264 | #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) |
| 265 | 265 | |
| 266 | +/* | |
| 267 | + * Intel color control surface (CCS) for render compression | |
| 268 | + * | |
| 269 | + * The framebuffer format must be one of the 8:8:8:8 RGB formats. | |
| 270 | + * The main surface will be plane index 0 and must be Y/Yf-tiled, | |
| 271 | + * the CCS will be plane index 1. | |
| 272 | + * | |
| 273 | + * Each CCS tile matches a 1024x512 pixel area of the main surface. | |
| 274 | + * To match certain aspects of the 3D hardware the CCS is | |
| 275 | + * considered to be made up of normal 128Bx32 Y tiles, Thus | |
| 276 | + * the CCS pitch must be specified in multiples of 128 bytes. | |
| 277 | + * | |
| 278 | + * In reality the CCS tile appears to be a 64Bx64 Y tile, composed | |
| 279 | + * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. | |
| 280 | + * But that fact is not relevant unless the memory is accessed | |
| 281 | + * directly. | |
| 282 | + */ | |
| 283 | +#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) | |
| 284 | +#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) | |
| 285 | + | |
| 266 | 286 | /* |
| 267 | 287 | * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks |
| 268 | 288 | * |