Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added yet. v2: - Fix checkpatch issues - Use 4 bits for gt id in non-engine counters. Drop FIXME. - Set MAX GTs to 4. Drop FIXME. v3: (Ashutosh, Tvrtko) - Drop BUG_ON that would never fire - Make enable u64 - Pull in some code from next patch v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko) v5: s/u64/u32 where needed (Ashutosh)
Showing the changes to include/uapi/drm (1 of 3 files). Show all
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| @@ -280,7 +280,16 @@ enum drm_i915_pmu_engine_sample { · 279 unmodified lines | ||
| 280 | 280 | #define I915_PMU_ENGINE_SEMA(class, instance) \ |
| 281 | 281 | __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) |
| 282 | 282 | |
| 283 | −#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | |
| 283 | +/* | |
| 284 | + * Top 4 bits of every non-engine counter are GT id. | |
| 285 | + */ | |
| 286 | +#define __I915_PMU_GT_SHIFT (60) | |
| 287 | + | |
| 288 | +#define ___I915_PMU_OTHER(gt, x) \ | |
| 289 | + (((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \ | |
| 290 | + ((__u64)(gt) << __I915_PMU_GT_SHIFT)) | |
| 291 | + | |
| 292 | +#define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x) | |
| 284 | 293 | |
| 285 | 294 | #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) |
| 286 | 295 | #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) |
| @@ -290,6 +299,12 @@ enum drm_i915_pmu_engine_sample { · 3 unmodified lines | ||
| 290 | 299 | |
| 291 | 300 | #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY |
| 292 | 301 | |
| 302 | +#define __I915_PMU_ACTUAL_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 0) | |
| 303 | +#define __I915_PMU_REQUESTED_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 1) | |
| 304 | +#define __I915_PMU_INTERRUPTS(gt) ___I915_PMU_OTHER(gt, 2) | |
| 305 | +#define __I915_PMU_RC6_RESIDENCY(gt) ___I915_PMU_OTHER(gt, 3) | |
| 306 | +#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt) ___I915_PMU_OTHER(gt, 4) | |
| 307 | + | |
| 293 | 308 | /* Each region is a minimum of 16k, and there are at most 255 of them. |
| 294 | 309 | */ |
| 295 | 310 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use |