lael-labs/linux

drivers/gpu/drm/amd/amdgpu/Makefile+12−1

@@ -40,7 +40,18 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ · 39 unmodified lines
40	-I$(FULL_AMD_PATH)/amdkfd	40	-I$(FULL_AMD_PATH)/amdkfd
41		41
42	subdir-ccflags-y := -Wextra	42	subdir-ccflags-y := -Wextra
43	subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)	43	subdir-ccflags-y += -Wunused
		44	subdir-ccflags-y += -Wmissing-prototypes
		45	subdir-ccflags-y += -Wmissing-declarations
		46	subdir-ccflags-y += -Wmissing-include-dirs
		47	subdir-ccflags-y += -Wold-style-definition
		48	subdir-ccflags-y += -Wmissing-format-attribute
		49	# Need this to avoid recursive variable evaluation issues
		50	cond-flags := $(call cc-option, -Wunused-but-set-variable) \
		51	$(call cc-option, -Wunused-const-variable) \
		52	$(call cc-option, -Wstringop-truncation) \
		53	$(call cc-option, -Wpacked-not-aligned)
		54	subdir-ccflags-y += $(cond-flags)
44	subdir-ccflags-y += -Wno-unused-parameter	55	subdir-ccflags-y += -Wno-unused-parameter
45	subdir-ccflags-y += -Wno-type-limits	56	subdir-ccflags-y += -Wno-type-limits
46	subdir-ccflags-y += -Wno-sign-compare	57	subdir-ccflags-y += -Wno-sign-compare

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+1−1

@@ -309,7 +309,7 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, · 308 unmodified lines
309	}	309	}
310	p->gang_leader = p->jobs[p->gang_leader_idx];	310	p->gang_leader = p->jobs[p->gang_leader_idx];
311		311
312	if (p->ctx->vram_lost_counter != p->gang_leader->vram_lost_counter) {	312	if (p->ctx->generation != p->gang_leader->generation) {
313	ret = -ECANCELED;	313	ret = -ECANCELED;
314	goto free_all_kdata;	314	goto free_all_kdata;
315	}	315	}

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c+11−3

 	ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter);
 	ctx->reset_counter_query = ctx->reset_counter;
-	ctx->vram_lost_counter = atomic_read(&mgr->adev->vram_lost_counter);
+	ctx->generation = amdgpu_vm_generation(mgr->adev, &fpriv->vm);
 	ctx->init_priority = priority;
 	ctx->override_priority = AMDGPU_CTX_PRIORITY_UNSET;
 			  u32 ring, struct drm_sched_entity **entity)
 {
 	int r;
+	struct drm_sched_entity *ctx_entity;
 	if (hw_ip >= AMDGPU_HW_IP_NUM) {
 		DRM_ERROR("unknown HW IP type: %d\n", hw_ip);
 			return r;
 	}
-	*entity = &ctx->entities[hw_ip][ring]->entity;
+	ctx_entity = &ctx->entities[hw_ip][ring]->entity;
+	r = drm_sched_entity_error(ctx_entity);
+	if (r) {
+		DRM_DEBUG("error entity %p\n", ctx_entity);
+		return r;
+	}
+	*entity = ctx_entity;
 	return 0;
 }
 	if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter))
 		out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET;
-	if (ctx->vram_lost_counter != atomic_read(&adev->vram_lost_counter))
+	if (ctx->generation != amdgpu_vm_generation(adev, &fpriv->vm))
 		out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST;
 	if (atomic_read(&ctx->guilty))

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h+1−1

@@ -47,7 +47,7 @@ struct amdgpu_ctx { · 46 unmodified lines
47	struct amdgpu_ctx_mgr *mgr;	47	struct amdgpu_ctx_mgr *mgr;
48	unsigned reset_counter;	48	unsigned reset_counter;
49	unsigned reset_counter_query;	49	unsigned reset_counter_query;
50	uint32_t vram_lost_counter;	50	uint64_t generation;
51	spinlock_t ring_lock;	51	spinlock_t ring_lock;
52	struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];	52	struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
53	bool preamble_presented;	53	bool preamble_presented;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c+3−0

 				mall_size += mall_size_per_umc;
 		}
 		adev->gmc.mall_size = mall_size;
+		adev->gmc.m_half_use = half_use;
 		break;
 	default:
 		dev_err(adev->dev,
 		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 		break;
 	case IP_VERSION(9, 4, 3):
+		if (!amdgpu_exp_hw_support)
+			return -EINVAL;
 		amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block);
 		break;
 	case IP_VERSION(10, 1, 10):

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c+25−0

@@ -691,6 +691,30 @@ void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring) · 690 unmodified lines
691	}	691	}
692	}	692	}
693		693
		694	/**
		695	* amdgpu_fence_driver_set_error - set error code on fences
		696	* @ring: the ring which contains the fences
		697	* @error: the error code to set
		698	*
		699	* Set an error code to all the fences pending on the ring.
		700	*/
		701	void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error)
		702	{
		703	struct amdgpu_fence_driver *drv = &ring->fence_drv;
		704	unsigned long flags;
		705
		706	spin_lock_irqsave(&drv->lock, flags);
		707	for (unsigned int i = 0; i <= drv->num_fences_mask; ++i) {
		708	struct dma_fence *fence;
		709
		710	fence = rcu_dereference_protected(drv->fences[i],
		711	lockdep_is_held(&drv->lock));
		712	if (fence && !dma_fence_is_signaled_locked(fence))
		713	dma_fence_set_error(fence, error);
		714	}
		715	spin_unlock_irqrestore(&drv->lock, flags);
		716	}
		717
694	/**	718	/**
695	* amdgpu_fence_driver_force_completion - force signal latest fence of ring	719	* amdgpu_fence_driver_force_completion - force signal latest fence of ring
696	*	720	*
@@ -699,6 +723,7 @@ void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring) · 2 unmodified lines
699	*/	723	*/
700	void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)	724	void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
701	{	725	{
		726	amdgpu_fence_driver_set_error(ring, -ECANCELED);
702	amdgpu_fence_write(ring, ring->fence_drv.sync_seq);	727	amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
703	amdgpu_fence_process(ring);	728	amdgpu_fence_process(ring);
704	}	729	}

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h+2−0

@@ -301,6 +301,8 @@ struct amdgpu_gmc { · 300 unmodified lines
301		301
302	/* MALL size */	302	/* MALL size */
303	u64 mall_size;	303	u64 mall_size;
		304	uint32_t m_half_use;
		305
304	/* number of UMC instances */	306	/* number of UMC instances */
305	int num_umc;	307	int num_umc;
306	/* mode2 save restore */	308	/* mode2 save restore */

drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c+2−2

@@ -190,8 +190,8 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, · 189 unmodified lines
190	pr_debug("hmm range: start = 0x%lx, end = 0x%lx",	190	pr_debug("hmm range: start = 0x%lx, end = 0x%lx",
191	hmm_range->start, hmm_range->end);	191	hmm_range->start, hmm_range->end);
192		192
193	/* Assuming 512MB takes maxmium 1 second to fault page address */	193	/* Assuming 128MB takes maximum 1 second to fault page address */
194	timeout = max((hmm_range->end - hmm_range->start) >> 29, 1UL);	194	timeout = max((hmm_range->end - hmm_range->start) >> 27, 1UL);
195	timeout *= HMM_RANGE_DEFAULT_TIMEOUT;	195	timeout *= HMM_RANGE_DEFAULT_TIMEOUT;
196	timeout = jiffies + msecs_to_jiffies(timeout);	196	timeout = jiffies + msecs_to_jiffies(timeout);
197		197

drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c+2−1

@@ -467,7 +467,8 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, · 466 unmodified lines
467	handled = true;	467	handled = true;
468		468
469	} else {	469	} else {
470	DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);	470	DRM_DEBUG("Unregistered interrupt src_id: %d of client_id:%d\n",
		471	src_id, client_id);
471	}	472	}
472		473
473	/* Send it to amdkfd as well if it isn't already handled */	474	/* Send it to amdkfd as well if it isn't already handled */

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c+14−3

 	(*job)->vm = vm;
 	amdgpu_sync_create(&(*job)->explicit_sync);
-	(*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
+	(*job)->generation = amdgpu_vm_generation(adev, vm);
 	(*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
 	if (!entity)
 	struct dma_fence *fence = NULL;
 	int r;
+	/* Ignore soft recovered fences here */
+	r = drm_sched_entity_error(s_entity);
+	if (r && r != -ENODATA)
+		goto error;
 	if (!fence && job->gang_submit)
 		fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
 	while (!fence && job->vm && !job->vmid) {
 		r = amdgpu_vmid_grab(job->vm, ring, job, &fence);
-		if (r)
+		if (r) {
 			DRM_ERROR("Error getting VM ID (%d)\n", r);
+			goto error;
+		}
 	}
 	return fence;
+error:
+	dma_fence_set_error(&job->base.s_fence->finished, r);
+	return NULL;
 }
 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
 	trace_amdgpu_sched_run_job(job);
 	/* Skip job if VRAM is lost and never resubmit gangs */
-	if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter) ||
+	if (job->generation != amdgpu_vm_generation(adev, job->vm) ||
 	    (job->job_run_counter && job->gang_submit))
 		dma_fence_set_error(finished, -ECANCELED);

drivers/gpu/drm/amd/amdgpu/amdgpu_job.h+1−1

@@ -61,7 +61,7 @@ struct amdgpu_job { · 60 unmodified lines
61	uint32_t gds_base, gds_size;	61	uint32_t gds_base, gds_size;
62	uint32_t gws_base, gws_size;	62	uint32_t gws_base, gws_size;
63	uint32_t oa_base, oa_size;	63	uint32_t oa_base, oa_size;
64	uint32_t vram_lost_counter;	64	uint64_t generation;
65		65
66	/* user fence handling */	66	/* user fence handling */
67	uint64_t uf_addr;	67	uint64_t uf_addr;

drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h+0−2

@@ -99,8 +99,6 @@ struct amdgpu_nbio_funcs { · 98 unmodified lines
99	int (get_compute_partition_mode)(struct amdgpu_device adev);	99	int (get_compute_partition_mode)(struct amdgpu_device adev);
100	u32 (get_memory_partition_mode)(struct amdgpu_device adev,	100	u32 (get_memory_partition_mode)(struct amdgpu_device adev,
101	u32 *supp_modes);	101	u32 *supp_modes);
102	void (set_compute_partition_mode)(struct amdgpu_device adev,
103	enum amdgpu_gfx_partition mode);
104	};	102	};
105		103
106	struct amdgpu_nbio {	104	struct amdgpu_nbio {

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+6−2

 		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 			places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn);
-		else if (adev->gmc.real_vram_size != adev->gmc.visible_vram_size)
+		else
 			places[c].flags |= TTM_PL_FLAG_TOPDOWN;
 		if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
 void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
 			  struct amdgpu_mem_stats *stats)
 {
-	unsigned int domain;
 	uint64_t size = amdgpu_bo_size(bo);
+	unsigned int domain;
+	/* Abort if the BO doesn't currently have a backing store */
+	if (!bo->tbo.resource)
+		return;
 	domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
 	switch (domain) {

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+22−1

@@ -569,6 +569,26 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index, · 568 unmodified lines
569	return -ETIME;	569	return -ETIME;
570	}	570	}
571		571
		572	int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
		573	uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)
		574	{
		575	uint32_t val;
		576	int i;
		577	struct amdgpu_device *adev = psp->adev;
		578
		579	if (psp->adev->no_hw_access)
		580	return 0;
		581
		582	for (i = 0; i < msec_timeout; i++) {
		583	val = RREG32(reg_index);
		584	if ((val & mask) == reg_val)
		585	return 0;
		586	msleep(1);
		587	}
		588
		589	return -ETIME;
		590	}
		591
572	static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)	592	static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
573	{	593	{
574	switch (cmd_id) {	594	switch (cmd_id) {
@@ -1653,10 +1673,11 @@ int psp_ras_initialize(struct psp_context *psp) · 1078 unmodified lines
1653		1673
1654	if (amdgpu_ras_is_poison_mode_supported(adev))	1674	if (amdgpu_ras_is_poison_mode_supported(adev))
1655	ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;	1675	ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1656	if (!adev->gmc.xgmi.connected_to_cpu)	1676	if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1657	ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;	1677	ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1658	ras_cmd->ras_in_message.init_flags.xcc_mask =	1678	ras_cmd->ras_in_message.init_flags.xcc_mask =
1659	adev->gfx.xcc_mask;	1679	adev->gfx.xcc_mask;
		1680	ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
1660		1681
1661	ret = psp_ta_load(psp, &psp->ras_context.context);	1682	ret = psp_ta_load(psp, &psp->ras_context.context);
1662		1683

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h+2−0

@@ -455,6 +455,8 @@ extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; · 454 unmodified lines
455		455
456	extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,	456	extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
457	uint32_t field_val, uint32_t mask, bool check_changed);	457	uint32_t field_val, uint32_t mask, bool check_changed);
		458	extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
		459	uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
458		460
459	int psp_gpu_reset(struct amdgpu_device *adev);	461	int psp_gpu_reset(struct amdgpu_device *adev);
460	int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,	462	int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c+8−8

 	memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 	err_data.err_addr = &err_rec;
-	amdgpu_umc_fill_error_record(&err_data, address,
+	amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
-			(address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0);
 	if (amdgpu_bad_page_threshold != 0) {
 		amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 		ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 		break;
 	case 2:
-		if ((data.inject.address >= adev->gmc.mc_vram_size) ||
+		if ((data.inject.address >= adev->gmc.mc_vram_size &&
+		    adev->gmc.mc_vram_size) ||
 		    (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 			dev_warn(adev->dev, "RAS WARN: input address "
 					"0x%llx is invalid.",
 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
 {
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
+	struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
 	struct drm_minor  *minor = adev_to_drm(adev)->primary;
 	struct dentry     *dir;
 			    &amdgpu_ras_debugfs_eeprom_ops);
 	debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
 			   &con->bad_page_cnt_threshold);
+	debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
 	debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
 	debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
 	debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
 		}
 	}
-	if (!adev->gmc.xgmi.connected_to_cpu)
+	amdgpu_umc_poison_handler(adev, false);
-		amdgpu_umc_poison_handler(adev, false);
 	if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
 		poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
 {
 	adev->ras_hw_enabled = adev->ras_enabled = 0;
-	if (!adev->is_atom_fw ||
+	if (!amdgpu_ras_asic_supported(adev))
-	    !amdgpu_ras_asic_supported(adev))
 		return;
-	if (!adev->gmc.xgmi.connected_to_cpu) {
+	if (!adev->gmc.xgmi.connected_to_cpu &&	!adev->gmc.is_app_apu) {
 		if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
 			dev_info(adev->dev, "MEM ECC is active.\n");
 			adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c+2−2

@@ -72,7 +72,7 @@ · 71 unmodified lines
72	/* Bad GPU tag ‘BADG’ */	72	/* Bad GPU tag ‘BADG’ */
73	#define RAS_TABLE_HDR_BAD 0x42414447	73	#define RAS_TABLE_HDR_BAD 0x42414447
74		74
75	/**	75	/*
76	* EEPROM Table structure v1	76	* EEPROM Table structure v1
77	* ---------------------------------	77	* ---------------------------------
78	* \| \|	78	* \| \|
@@ -94,7 +94,7 @@ · 15 unmodified lines
94	#define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \	94	#define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \
95	/ RAS_TABLE_RECORD_SIZE)	95	/ RAS_TABLE_RECORD_SIZE)
96		96
97	/**	97	/*
98	* EEPROM Table structrue v2.1	98	* EEPROM Table structrue v2.1
99	* ---------------------------------	99	* ---------------------------------
100	* \| \|	100	* \| \|

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c+23−0

 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
 			       struct dma_fence *fence)
 {
+	unsigned long flags;
 	ktime_t deadline = ktime_add_us(ktime_get(), 10000);
 	if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
 		return false;
+	spin_lock_irqsave(fence->lock, flags);
+	if (!dma_fence_is_signaled_locked(fence))
+		dma_fence_set_error(fence, -ENODATA);
+	spin_unlock_irqrestore(fence->lock, flags);
 	atomic_inc(&ring->adev->gpu_reset_counter);
 	while (!dma_fence_is_signaled(fence) &&
 	       ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
 	.llseek = default_llseek
 };
+static int amdgpu_debugfs_ring_error(void *data, u64 val)
+{
+	struct amdgpu_ring *ring = data;
+	amdgpu_fence_driver_set_error(ring, val);
+	return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL,
+				amdgpu_debugfs_ring_error, "%lld\n");
 #endif
 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
 					 &amdgpu_debugfs_mqd_fops,
 					 ring->mqd_size);
 	}
+	sprintf(name, "amdgpu_error_%s", ring->name);
+	debugfs_create_file(name, 0200, root, ring,
+			    &amdgpu_debugfs_error_fops);
 #endif
 }

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h+1−0

@@ -126,6 +126,7 @@ struct amdgpu_fence_driver { · 125 unmodified lines
126	extern const struct drm_sched_backend_ops amdgpu_sched_ops;	126	extern const struct drm_sched_backend_ops amdgpu_sched_ops;
127		127
128	void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);	128	void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
		129	void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
129	void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);	130	void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
130		131
131	int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);	132	int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+9−9

@@ -228,7 +228,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, · 227 unmodified lines
228	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);	228	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
229	num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;	229	num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
230		230
231	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,	231	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
232	AMDGPU_FENCE_OWNER_UNDEFINED,	232	AMDGPU_FENCE_OWNER_UNDEFINED,
233	num_dw * 4 + num_bytes,	233	num_dw * 4 + num_bytes,
234	AMDGPU_IB_POOL_DELAYED, &job);	234	AMDGPU_IB_POOL_DELAYED, &job);
@@ -1456,7 +1456,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, · 1221 unmodified lines
1456	memcpy(adev->mman.sdma_access_ptr, buf, len);	1456	memcpy(adev->mman.sdma_access_ptr, buf, len);
1457		1457
1458	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);	1458	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1459	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,	1459	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
1460	AMDGPU_FENCE_OWNER_UNDEFINED,	1460	AMDGPU_FENCE_OWNER_UNDEFINED,
1461	num_dw * 4, AMDGPU_IB_POOL_DELAYED,	1461	num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1462	&job);	1462	&job);
@@ -2032,7 +2032,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) · 569 unmodified lines
2032		2032
2033	ring = adev->mman.buffer_funcs_ring;	2033	ring = adev->mman.buffer_funcs_ring;
2034	sched = &ring->sched;	2034	sched = &ring->sched;
2035	r = drm_sched_entity_init(&adev->mman.entity,	2035	r = drm_sched_entity_init(&adev->mman.high_pr,
2036	DRM_SCHED_PRIORITY_KERNEL, &sched,	2036	DRM_SCHED_PRIORITY_KERNEL, &sched,
2037	1, NULL);	2037	1, NULL);
2038	if (r) {	2038	if (r) {
@@ -2041,7 +2041,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) · 2 unmodified lines
2041	return;	2041	return;
2042	}	2042	}
2043		2043
2044	r = drm_sched_entity_init(&adev->mman.delayed,	2044	r = drm_sched_entity_init(&adev->mman.low_pr,
2045	DRM_SCHED_PRIORITY_NORMAL, &sched,	2045	DRM_SCHED_PRIORITY_NORMAL, &sched,
2046	1, NULL);	2046	1, NULL);
2047	if (r) {	2047	if (r) {
@@ -2050,8 +2050,8 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) · 2 unmodified lines
2050	goto error_free_entity;	2050	goto error_free_entity;
2051	}	2051	}
2052	} else {	2052	} else {
2053	drm_sched_entity_destroy(&adev->mman.entity);	2053	drm_sched_entity_destroy(&adev->mman.high_pr);
2054	drm_sched_entity_destroy(&adev->mman.delayed);	2054	drm_sched_entity_destroy(&adev->mman.low_pr);
2055	dma_fence_put(man->move);	2055	dma_fence_put(man->move);
2056	man->move = NULL;	2056	man->move = NULL;
2057	}	2057	}
@@ -2067,7 +2067,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) · 9 unmodified lines
2067	return;	2067	return;
2068		2068
2069	error_free_entity:	2069	error_free_entity:
2070	drm_sched_entity_destroy(&adev->mman.entity);	2070	drm_sched_entity_destroy(&adev->mman.high_pr);
2071	}	2071	}
2072		2072
2073	static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,	2073	static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
@@ -2082,8 +2082,8 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, · 8 unmodified lines
2082	AMDGPU_IB_POOL_DIRECT :	2082	AMDGPU_IB_POOL_DIRECT :
2083	AMDGPU_IB_POOL_DELAYED;	2083	AMDGPU_IB_POOL_DELAYED;
2084	int r;	2084	int r;
2085	struct drm_sched_entity *entity = delayed ? &adev->mman.delayed :	2085	struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr :
2086	&adev->mman.entity;	2086	&adev->mman.high_pr;
2087	r = amdgpu_job_alloc_with_ib(adev, entity,	2087	r = amdgpu_job_alloc_with_ib(adev, entity,
2088	AMDGPU_FENCE_OWNER_UNDEFINED,	2088	AMDGPU_FENCE_OWNER_UNDEFINED,
2089	num_dw * 4, pool, job);	2089	num_dw * 4, pool, job);

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h+4−4

@@ -59,10 +59,10 @@ struct amdgpu_mman { · 58 unmodified lines
59	bool buffer_funcs_enabled;	59	bool buffer_funcs_enabled;
60		60
61	struct mutex gtt_window_lock;	61	struct mutex gtt_window_lock;
62	/* Scheduler entity for buffer moves */	62	/* High priority scheduler entity for buffer moves */
63	struct drm_sched_entity entity;	63	struct drm_sched_entity high_pr;
64	/* Scheduler entity for VRAM clearing */	64	/* Low priority scheduler entity for VRAM clearing */
65	struct drm_sched_entity delayed;	65	struct drm_sched_entity low_pr;
66		66
67	struct amdgpu_vram_mgr vram_mgr;	67	struct amdgpu_vram_mgr vram_mgr;
68	struct amdgpu_gtt_mgr gtt_mgr;	68	struct amdgpu_gtt_mgr gtt_mgr;

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c+19−15

 {
 	int ret = AMDGPU_RAS_SUCCESS;
-	if (!amdgpu_sriov_vf(adev)) {
+	if (adev->gmc.xgmi.connected_to_cpu ||
-		if (!adev->gmc.xgmi.connected_to_cpu) {
+		adev->gmc.is_app_apu) {
-			struct ras_err_data err_data = {0, 0, 0, NULL};
+		if (reset) {
-			struct ras_common_if head = {
-				.block = AMDGPU_RAS_BLOCK__UMC,
-			};
-			struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);
-			ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset);
-			if (ret == AMDGPU_RAS_SUCCESS && obj) {
-				obj->err_data.ue_count += err_data.ue_count;
-				obj->err_data.ce_count += err_data.ce_count;
-			}
-		} else if (reset) {
 			/* MCA poison handler is only responsible for GPU reset,
 			 * let MCA notifier do page retirement.
 			 */
 			kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 			amdgpu_ras_reset_gpu(adev);
 		}
+		return ret;
+	}
+	if (!amdgpu_sriov_vf(adev)) {
+		struct ras_err_data err_data = {0, 0, 0, NULL};
+		struct ras_common_if head = {
+			.block = AMDGPU_RAS_BLOCK__UMC,
+		};
+		struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);
+		ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset);
+		if (ret == AMDGPU_RAS_SUCCESS && obj) {
+			obj->err_data.ue_count += err_data.ue_count;
+			obj->err_data.ce_count += err_data.ce_count;
+		}
 	} else {
 		if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
 			adev->virt.ops->ras_poison_handler(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+130−46

@@ -266,6 +266,32 @@ static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) · 265 unmodified lines
266	spin_unlock(&vm_bo->vm->status_lock);	266	spin_unlock(&vm_bo->vm->status_lock);
267	}	267	}
268		268
		269	/**
		270	* amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
		271	* @vm: the VM which state machine to reset
		272	*
		273	* Move all vm_bo object in the VM into a state where they will be updated
		274	* again during validation.
		275	*/
		276	static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
		277	{
		278	struct amdgpu_vm_bo_base vm_bo, tmp;
		279
		280	spin_lock(&vm->status_lock);
		281	list_splice_init(&vm->done, &vm->invalidated);
		282	list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
		283	vm_bo->moved = true;
		284	list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
		285	struct amdgpu_bo *bo = vm_bo->bo;
		286
		287	if (!bo \|\| bo->tbo.type != ttm_bo_type_kernel)
		288	list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
		289	else if (bo->parent)
		290	list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
		291	}
		292	spin_unlock(&vm->status_lock);
		293	}
		294
269	/**	295	/**
270	* amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm	296	* amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
271	*	297	*
@@ -351,6 +377,58 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, · 79 unmodified lines
351	spin_unlock(&adev->mman.bdev.lru_lock);	377	spin_unlock(&adev->mman.bdev.lru_lock);
352	}	378	}
353		379
		380	/* Create scheduler entities for page table updates */
		381	static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
		382	struct amdgpu_vm *vm)
		383	{
		384	int r;
		385
		386	r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
		387	adev->vm_manager.vm_pte_scheds,
		388	adev->vm_manager.vm_pte_num_scheds, NULL);
		389	if (r)
		390	goto error;
		391
		392	return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
		393	adev->vm_manager.vm_pte_scheds,
		394	adev->vm_manager.vm_pte_num_scheds, NULL);
		395
		396	error:
		397	drm_sched_entity_destroy(&vm->immediate);
		398	return r;
		399	}
		400
		401	/* Destroy the entities for page table updates again */
		402	static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
		403	{
		404	drm_sched_entity_destroy(&vm->immediate);
		405	drm_sched_entity_destroy(&vm->delayed);
		406	}
		407
		408	/**
		409	* amdgpu_vm_generation - return the page table re-generation counter
		410	* @adev: the amdgpu_device
		411	* @vm: optional VM to check, might be NULL
		412	*
		413	* Returns a page table re-generation token to allow checking if submissions
		414	* are still valid to use this VM. The VM parameter might be NULL in which case
		415	* just the VRAM lost counter will be used.
		416	*/
		417	uint64_t amdgpu_vm_generation(struct amdgpu_device adev, struct amdgpu_vm vm)
		418	{
		419	uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
		420
		421	if (!vm)
		422	return result;
		423
		424	result += vm->generation;
		425	/* Add one if the page tables will be re-generated on next CS */
		426	if (drm_sched_entity_error(&vm->delayed))
		427	++result;
		428
		429	return result;
		430	}
		431
354	/**	432	/**
355	* amdgpu_vm_validate_pt_bos - validate the page table BOs	433	* amdgpu_vm_validate_pt_bos - validate the page table BOs
356	*	434	*
@@ -373,6 +451,15 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device adev, struct amdgpu_vm vm, · 16 unmodified lines
373	struct amdgpu_bo *bo;	451	struct amdgpu_bo *bo;
374	int r;	452	int r;
375		453
		454	if (drm_sched_entity_error(&vm->delayed)) {
		455	++vm->generation;
		456	amdgpu_vm_bo_reset_state_machine(vm);
		457	amdgpu_vm_fini_entities(vm);
		458	r = amdgpu_vm_init_entities(adev, vm);
		459	if (r)
		460	return r;
		461	}
		462
376	spin_lock(&vm->status_lock);	463	spin_lock(&vm->status_lock);
377	while (!list_empty(&vm->evicted)) {	464	while (!list_empty(&vm->evicted)) {
378	bo_base = list_first_entry(&vm->evicted,	465	bo_base = list_first_entry(&vm->evicted,
@@ -920,42 +1007,51 @@ error_unlock: · 541 unmodified lines
920	return r;	1007	return r;
921	}	1008	}
922		1009
		1010	static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
		1011	struct amdgpu_mem_stats *stats)
		1012	{
		1013	struct amdgpu_vm *vm = bo_va->base.vm;
		1014	struct amdgpu_bo *bo = bo_va->base.bo;
		1015
		1016	if (!bo)
		1017	return;
		1018
		1019	/*
		1020	* For now ignore BOs which are currently locked and potentially
		1021	* changing their location.
		1022	*/
		1023	if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv &&
		1024	!dma_resv_trylock(bo->tbo.base.resv))
		1025	return;
		1026
		1027	amdgpu_bo_get_memory(bo, stats);
		1028	if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
		1029	dma_resv_unlock(bo->tbo.base.resv);
		1030	}
		1031
923	void amdgpu_vm_get_memory(struct amdgpu_vm *vm,	1032	void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
924	struct amdgpu_mem_stats *stats)	1033	struct amdgpu_mem_stats *stats)
925	{	1034	{
926	struct amdgpu_bo_va bo_va, tmp;	1035	struct amdgpu_bo_va bo_va, tmp;
927		1036
928	spin_lock(&vm->status_lock);	1037	spin_lock(&vm->status_lock);
929	list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {	1038	list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
930	if (!bo_va->base.bo)	1039	amdgpu_vm_bo_get_memory(bo_va, stats);
931	continue;	1040
932	amdgpu_bo_get_memory(bo_va->base.bo, stats);	1041	list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
933	}	1042	amdgpu_vm_bo_get_memory(bo_va, stats);
934	list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {	1043
935	if (!bo_va->base.bo)	1044	list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
936	continue;	1045	amdgpu_vm_bo_get_memory(bo_va, stats);
937	amdgpu_bo_get_memory(bo_va->base.bo, stats);	1046
938	}	1047	list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
939	list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {	1048	amdgpu_vm_bo_get_memory(bo_va, stats);
940	if (!bo_va->base.bo)	1049
941	continue;	1050	list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
942	amdgpu_bo_get_memory(bo_va->base.bo, stats);	1051	amdgpu_vm_bo_get_memory(bo_va, stats);
943	}	1052
944	list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {	1053	list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
945	if (!bo_va->base.bo)	1054	amdgpu_vm_bo_get_memory(bo_va, stats);
946	continue;
947	amdgpu_bo_get_memory(bo_va->base.bo, stats);
948	}
949	list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
950	if (!bo_va->base.bo)
951	continue;
952	amdgpu_bo_get_memory(bo_va->base.bo, stats);
953	}
954	list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
955	if (!bo_va->base.bo)
956	continue;
957	amdgpu_bo_get_memory(bo_va->base.bo, stats);
958	}
959	spin_unlock(&vm->status_lock);	1055	spin_unlock(&vm->status_lock);
960	}	1056	}
961		1057
@@ -2039,19 +2135,10 @@ int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm) · 1077 unmodified lines
2039	INIT_LIST_HEAD(&vm->pt_freed);	2135	INIT_LIST_HEAD(&vm->pt_freed);
2040	INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);	2136	INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2041		2137
2042	/* create scheduler entities for page table updates */	2138	r = amdgpu_vm_init_entities(adev, vm);
2043	r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2044	adev->vm_manager.vm_pte_scheds,
2045	adev->vm_manager.vm_pte_num_scheds, NULL);
2046	if (r)	2139	if (r)
2047	return r;	2140	return r;
2048		2141
2049	r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2050	adev->vm_manager.vm_pte_scheds,
2051	adev->vm_manager.vm_pte_num_scheds, NULL);
2052	if (r)
2053	goto error_free_immediate;
2054
2055	vm->pte_support_ats = false;	2142	vm->pte_support_ats = false;
2056	vm->is_compute_context = false;	2143	vm->is_compute_context = false;
2057		2144
@@ -2072,6 +2159,7 @@ int amdgpu_vm_init(struct amdgpu_device adev, struct amdgpu_vm vm) · 14 unmodified lines
2072	vm->last_update = dma_fence_get_stub();	2159	vm->last_update = dma_fence_get_stub();
2073	vm->last_unlocked = dma_fence_get_stub();	2160	vm->last_unlocked = dma_fence_get_stub();
2074	vm->last_tlb_flush = dma_fence_get_stub();	2161	vm->last_tlb_flush = dma_fence_get_stub();
		2162	vm->generation = 0;
2075		2163
2076	mutex_init(&vm->eviction_lock);	2164	mutex_init(&vm->eviction_lock);
2077	vm->evicting = false;	2165	vm->evicting = false;
@@ -2112,10 +2200,7 @@ error_free_root: · 34 unmodified lines
2112	error_free_delayed:	2200	error_free_delayed:
2113	dma_fence_put(vm->last_tlb_flush);	2201	dma_fence_put(vm->last_tlb_flush);
2114	dma_fence_put(vm->last_unlocked);	2202	dma_fence_put(vm->last_unlocked);
2115	drm_sched_entity_destroy(&vm->delayed);	2203	amdgpu_vm_fini_entities(vm);
2116
2117	error_free_immediate:
2118	drm_sched_entity_destroy(&vm->immediate);
2119		2204
2120	return r;	2205	return r;
2121	}	2206	}
@@ -2268,8 +2353,7 @@ void amdgpu_vm_fini(struct amdgpu_device adev, struct amdgpu_vm vm) · 146 unmodified lines
2268	amdgpu_bo_unref(&root);	2353	amdgpu_bo_unref(&root);
2269	WARN_ON(vm->root.bo);	2354	WARN_ON(vm->root.bo);
2270		2355
2271	drm_sched_entity_destroy(&vm->immediate);	2356	amdgpu_vm_fini_entities(vm);
2272	drm_sched_entity_destroy(&vm->delayed);
2273		2357
2274	if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {	2358	if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2275	dev_err(adev->dev, "still active bo inside vm\n");	2359	dev_err(adev->dev, "still active bo inside vm\n");

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h+4−0

 	atomic64_t		tlb_seq;
 	struct dma_fence	*last_tlb_flush;
+	/* How many times we had to re-generate the page tables */
+	uint64_t		generation;
 	/* Last unlocked submission to the scheduler entities */
 	struct dma_fence	*last_unlocked;
 			 struct list_head *validated,
 			 struct amdgpu_bo_list_entry *entry);
 bool amdgpu_vm_ready(struct amdgpu_vm *vm);
+uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm);
 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 			      int (*callback)(void *p, struct amdgpu_bo *bo),
 			      void *param);

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c+46−0

@@ -325,6 +325,36 @@ static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, · 324 unmodified lines
325		325
326	}	326	}
327		327
		328	static ssize_t amdgpu_xgmi_show_num_hops(struct device *dev,
		329	struct device_attribute *attr,
		330	char *buf)
		331	{
		332	struct drm_device *ddev = dev_get_drvdata(dev);
		333	struct amdgpu_device *adev = drm_to_adev(ddev);
		334	struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
		335	int i;
		336
		337	for (i = 0; i < top->num_nodes; i++)
		338	sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_hops);
		339
		340	return sysfs_emit(buf, "%s\n", buf);
		341	}
		342
		343	static ssize_t amdgpu_xgmi_show_num_links(struct device *dev,
		344	struct device_attribute *attr,
		345	char *buf)
		346	{
		347	struct drm_device *ddev = dev_get_drvdata(dev);
		348	struct amdgpu_device *adev = drm_to_adev(ddev);
		349	struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
		350	int i;
		351
		352	for (i = 0; i < top->num_nodes; i++)
		353	sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_links);
		354
		355	return sysfs_emit(buf, "%s\n", buf);
		356	}
		357
328	#define AMDGPU_XGMI_SET_FICAA(o) ((o) \| 0x456801)	358	#define AMDGPU_XGMI_SET_FICAA(o) ((o) \| 0x456801)
329	static ssize_t amdgpu_xgmi_show_error(struct device *dev,	359	static ssize_t amdgpu_xgmi_show_error(struct device *dev,
330	struct device_attribute *attr,	360	struct device_attribute *attr,
@@ -361,6 +391,8 @@ static ssize_t amdgpu_xgmi_show_error(struct device *dev, · 30 unmodified lines
361		391
362	static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);	392	static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
363	static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);	393	static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
		394	static DEVICE_ATTR(xgmi_num_hops, S_IRUGO, amdgpu_xgmi_show_num_hops, NULL);
		395	static DEVICE_ATTR(xgmi_num_links, S_IRUGO, amdgpu_xgmi_show_num_links, NULL);
364		396
365	static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,	397	static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
366	struct amdgpu_hive_info *hive)	398	struct amdgpu_hive_info *hive)
@@ -380,6 +412,15 @@ static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev, · 13 unmodified lines
380	if (ret)	412	if (ret)
381	pr_err("failed to create xgmi_error\n");	413	pr_err("failed to create xgmi_error\n");
382		414
		415	/* Create xgmi num hops file */
		416	ret = device_create_file(adev->dev, &dev_attr_xgmi_num_hops);
		417	if (ret)
		418	pr_err("failed to create xgmi_num_hops\n");
		419
		420	/* Create xgmi num links file */
		421	ret = device_create_file(adev->dev, &dev_attr_xgmi_num_links);
		422	if (ret)
		423	pr_err("failed to create xgmi_num_links\n");
383		424
384	/* Create sysfs link to hive info folder on the first device */	425	/* Create sysfs link to hive info folder on the first device */
385	if (hive->kobj.parent != (&adev->dev->kobj)) {	426	if (hive->kobj.parent != (&adev->dev->kobj)) {
@@ -407,6 +448,9 @@ remove_link: · 21 unmodified lines
407		448
408	remove_file:	449	remove_file:
409	device_remove_file(adev->dev, &dev_attr_xgmi_device_id);	450	device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
		451	device_remove_file(adev->dev, &dev_attr_xgmi_error);
		452	device_remove_file(adev->dev, &dev_attr_xgmi_num_hops);
		453	device_remove_file(adev->dev, &dev_attr_xgmi_num_links);
410		454
411	success:	455	success:
412	return ret;	456	return ret;
@@ -420,6 +464,8 @@ static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev, · 7 unmodified lines
420		464
421	device_remove_file(adev->dev, &dev_attr_xgmi_device_id);	465	device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
422	device_remove_file(adev->dev, &dev_attr_xgmi_error);	466	device_remove_file(adev->dev, &dev_attr_xgmi_error);
		467	device_remove_file(adev->dev, &dev_attr_xgmi_num_hops);
		468	device_remove_file(adev->dev, &dev_attr_xgmi_num_links);
423		469
424	if (hive->kobj.parent != (&adev->dev->kobj))	470	if (hive->kobj.parent != (&adev->dev->kobj))
425	sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");	471	sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");

drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c+0−3

@@ -518,9 +518,6 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, · 517 unmodified lines
518	adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev,	518	adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev,
519	num_xcc_per_xcp);	519	num_xcc_per_xcp);
520		520
521	if (adev->nbio.funcs->set_compute_partition_mode)
522	adev->nbio.funcs->set_compute_partition_mode(adev, mode);
523
524	/* Init info about new xcps */	521	/* Init info about new xcps */
525	*num_xcps = num_xcc / num_xcc_per_xcp;	522	*num_xcps = num_xcc / num_xcc_per_xcp;
526	amdgpu_xcp_init(xcp_mgr, *num_xcps, mode);	523	amdgpu_xcp_init(xcp_mgr, *num_xcps, mode);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c+6−12

 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
 						int num_xccs_per_xcp)
 {
-	int i, num_xcc;
+	int ret;
-	u32 tmp = 0;
-	num_xcc = NUM_XCC(adev->gfx.xcc_mask);
-	for (i = 0; i < num_xcc; i++) {
+	ret = psp_spatial_partition(&adev->psp, NUM_XCC(adev->gfx.xcc_mask) /
-		tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
+							num_xccs_per_xcp);
-				    num_xccs_per_xcp);
+	if (ret)
-		tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
+		return ret;
-				    i % num_xccs_per_xcp);
-		WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, tmp);
-	}
 	adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;
-	return 0;
+	return ret;
 }
 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c+1−1

@@ -382,7 +382,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 381 unmodified lines
382	* translation. Avoid this by doing the invalidation from the SDMA	382	* translation. Avoid this by doing the invalidation from the SDMA
383	* itself.	383	* itself.
384	*/	384	*/
385	r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.entity,	385	r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr,
386	AMDGPU_FENCE_OWNER_UNDEFINED,	386	AMDGPU_FENCE_OWNER_UNDEFINED,
387	16 * 4, AMDGPU_IB_POOL_IMMEDIATE,	387	16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
388	&job);	388	&job);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+1−0

@@ -2107,6 +2107,7 @@ static int gmc_v9_0_sw_init(void *handle) · 2106 unmodified lines
2107	bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32);	2107	bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32);
2108		2108
2109	amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);	2109	amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
		2110	adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2110	break;	2111	break;
2111	default:	2112	default:
2112	break;	2113	break;

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c+1−17

@@ -390,22 +390,7 @@ static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev) · 389 unmodified lines
390	px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,	390	px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
391	PARTITION_MODE);	391	PARTITION_MODE);
392		392
393	return ffs(px);	393	return px;
394	}
395
396	static void nbio_v7_9_set_compute_partition_mode(struct amdgpu_device *adev,
397	enum amdgpu_gfx_partition mode)
398	{
399	u32 tmp;
400
401	/* Each bit represents DPX,TPX,QPX,CPX mode. No bit set means default
402	* SPX mode.
403	*/
404	tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
405	tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
406	PARTITION_MODE, mode ? BIT(mode - 1) : mode);
407
408	WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS, tmp);
409	}	394	}
410		395
411	static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,	396	static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,
@@ -463,7 +448,6 @@ const struct amdgpu_nbio_funcs nbio_v7_9_funcs = { · 51 unmodified lines
463	.ih_control = nbio_v7_9_ih_control,	448	.ih_control = nbio_v7_9_ih_control,
464	.remap_hdp_registers = nbio_v7_9_remap_hdp_registers,	449	.remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
465	.get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,	450	.get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
466	.set_compute_partition_mode = nbio_v7_9_set_compute_partition_mode,
467	.get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,	451	.get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
468	.init_registers = nbio_v7_9_init_registers,	452	.init_registers = nbio_v7_9_init_registers,
469	};	453	};

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c+5−4

@@ -624,10 +624,11 @@ static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) · 623 unmodified lines
624	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);	624	WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
625		625
626	if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)	626	if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
627	return 0;	627	ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
628		628	MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
629	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),	629	else
630	MBOX_READY_FLAG, MBOX_READY_MASK, false);	630	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
		631	MBOX_READY_FLAG, MBOX_READY_MASK, false);
631	if (ret) {	632	if (ret) {
632	dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);	633	dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
633	return ret;	634	return ret;

drivers/gpu/drm/amd/amdgpu/psp_v13_0.h+2−0

@@ -25,6 +25,8 @@ · 24 unmodified lines
25		25
26	#include "amdgpu_psp.h"	26	#include "amdgpu_psp.h"
27		27
		28	#define PSP_SPIROM_UPDATE_TIMEOUT 60000 /* 60s */
		29
28	void psp_v13_0_set_psp_funcs(struct psp_context *psp);	30	void psp_v13_0_set_psp_funcs(struct psp_context *psp);
29		31
30	#endif	32	#endif

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c+2−2

@@ -2312,7 +2312,7 @@ const struct amd_ip_funcs sdma_v4_0_ip_funcs = { · 2311 unmodified lines
2312		2312
2313	static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {	2313	static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2314	.type = AMDGPU_RING_TYPE_SDMA,	2314	.type = AMDGPU_RING_TYPE_SDMA,
2315	.align_mask = 0xf,	2315	.align_mask = 0xff,
2316	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),	2316	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2317	.support_64bit_ptrs = true,	2317	.support_64bit_ptrs = true,
2318	.secure_submission_supported = true,	2318	.secure_submission_supported = true,
@@ -2344,7 +2344,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { · 25 unmodified lines
2344		2344
2345	static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {	2345	static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2346	.type = AMDGPU_RING_TYPE_SDMA,	2346	.type = AMDGPU_RING_TYPE_SDMA,
2347	.align_mask = 0xf,	2347	.align_mask = 0xff,
2348	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),	2348	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2349	.support_64bit_ptrs = true,	2349	.support_64bit_ptrs = true,
2350	.secure_submission_supported = true,	2350	.secure_submission_supported = true,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c+12−8

 		return 0;
 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
-	for (i = 0; i < adev->sdma.num_instances; i++) {
+	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
-		amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
+		for (i = 0; i < adev->sdma.num_instances; i++) {
-			       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+			amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
+				       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+		}
 	}
 	sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
 	.type = AMDGPU_RING_TYPE_SDMA,
-	.align_mask = 0xf,
+	.align_mask = 0xff,
 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
 	.support_64bit_ptrs = true,
 	.get_rptr = sdma_v4_4_2_ring_get_rptr,
 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
 	.type = AMDGPU_RING_TYPE_SDMA,
-	.align_mask = 0xf,
+	.align_mask = 0xff,
 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
 	.support_64bit_ptrs = true,
 	.get_rptr = sdma_v4_4_2_ring_get_rptr,
 	uint32_t tmp_mask = inst_mask;
 	int i;
-	for_each_inst(i, tmp_mask) {
+	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
-		amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
+		for_each_inst(i, tmp_mask) {
-			       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+			amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
+				       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+		}
 	}
 	sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h+1−0

@@ -130,6 +130,7 @@ struct ta_ras_init_flags { · 129 unmodified lines
130	uint8_t poison_mode_en;	130	uint8_t poison_mode_en;
131	uint8_t dgpu_mode;	131	uint8_t dgpu_mode;
132	uint16_t xcc_mask;	132	uint16_t xcc_mask;
		133	uint8_t channel_dis_num;
133	};	134	};
134		135
135	struct ta_ras_output_flags {	136	struct ta_ras_output_flags {

drivers/gpu/drm/amd/amdgpu/umc_v8_10.h+2−1

@@ -33,7 +33,8 @@ · 32 unmodified lines
33		33
34	/* Total channel instances for all available umc nodes */	34	/* Total channel instances for all available umc nodes */
35	#define UMC_V8_10_TOTAL_CHANNEL_NUM(adev) \	35	#define UMC_V8_10_TOTAL_CHANNEL_NUM(adev) \
36	(UMC_V8_10_CHANNEL_INSTANCE_NUM * UMC_V8_10_UMC_INSTANCE_NUM * (adev)->gmc.num_umc)	36	(UMC_V8_10_CHANNEL_INSTANCE_NUM * UMC_V8_10_UMC_INSTANCE_NUM * \
		37	(adev)->gmc.num_umc - hweight32((adev)->gmc.m_half_use) * 2)
37		38
38	/* UMC regiser per channel offset */	39	/* UMC regiser per channel offset */
39	#define UMC_V8_10_PER_CHANNEL_OFFSET 0x400	40	#define UMC_V8_10_PER_CHANNEL_OFFSET 0x400

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c+5−1

 		if (adev->vcn.harvest_config & (1 << i))
 			continue;
-		atomic_set(&adev->vcn.inst[i].sched_score, 0);
+		/* Init instance 0 sched_score to 1, so it's scheduled after other instances */
+		if (i == 0)
+			atomic_set(&adev->vcn.inst[i].sched_score, 1);
+		else
+			atomic_set(&adev->vcn.inst[i].sched_score, 0);
 		/* VCN UNIFIED TRAP */
 		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],

drivers/gpu/drm/amd/amdkfd/kfd_crat.c+0−5

 #include "amdgpu.h"
 #include "amdgpu_amdkfd.h"
-/* Fixme: Fake 32GB for 1PNPS1 mode bringup */
-#define DUMMY_VRAM_SIZE 31138512896
 /* GPU Processor ID base for dGPUs for which VCRAT needs to be created.
  * GPU processor ID are expressed with Bit[31]=1.
  * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs
 			props->heap_type = heap_type;
 			props->flags = flags;
-			if (size_in_bytes == 0)
-				size_in_bytes = DUMMY_VRAM_SIZE; /* Fixme: TBD */
 			props->size_in_bytes = size_in_bytes;
 			props->width = width;

drivers/gpu/drm/amd/amdkfd/kfd_debug.c+1−1

@@ -1097,7 +1097,7 @@ void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target, · 1096 unmodified lines
1097		1097
1098	pqm = &target->pqm;	1098	pqm = &target->pqm;
1099	list_for_each_entry(pqn, &pqm->queues, process_queue_list) {	1099	list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
1100	if (!pqn)	1100	if (!pqn->q)
1101	continue;	1101	continue;
1102		1102
1103	found_mask \|= pqn->q->properties.exception_status;	1103	found_mask \|= pqn->q->properties.exception_status;

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+3−3

 	queue_input.tba_addr = qpd->tba_addr;
 	queue_input.tma_addr = qpd->tma_addr;
 	queue_input.trap_en = KFD_GC_VERSION(q->device) < IP_VERSION(11, 0, 0) ||
-			      KFD_GC_VERSION(q->device) >= IP_VERSION(12, 0, 0);
+			      KFD_GC_VERSION(q->device) > IP_VERSION(11, 0, 3);
 	queue_input.skip_process_ctx_clear = qpd->pqm->process->debug_trap_enabled;
 	queue_type = convert_to_mes_queue_type(q->properties.type);
 	q->properties.is_evicted = !!qpd->evicted;
 	q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled &&
 			KFD_GC_VERSION(q->device) >= IP_VERSION(11, 0, 0) &&
-			KFD_GC_VERSION(q->device) < IP_VERSION(12, 0, 0);
+			KFD_GC_VERSION(q->device) <= IP_VERSION(11, 0, 3);
 	if (qd)
 		mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
 	list_del(&q->list);
 	qpd->queue_count--;
 	if (q->properties.is_active) {
+		decrement_queue_count(dqm, qpd, q);
 		if (!dqm->dev->kfd->shared_resources.enable_mes) {
-			decrement_queue_count(dqm, qpd, q);
 			retval = execute_queues_cpsch(dqm,
 						      KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
 						      USE_DEFAULT_GRACE_PERIOD);

drivers/gpu/drm/amd/amdkfd/kfd_events.c+34−12

 	wait_queue_entry_t wait;
 	struct kfd_event *event; /* Event to wait for */
 	bool activated;		 /* Becomes true when event is signaled */
+	bool event_age_enabled;  /* set to true when last_event_age is non-zero */
 };
 /*
 	if (!ret) {
 		*event_id = ev->event_id;
 		*event_trigger_data = ev->event_id;
+		ev->event_age = 1;
 	} else {
 		kfree(ev);
 	}
 	 * updating the wait queues in kfd_wait_on_events.
 	 */
 	ev->signaled = !ev->auto_reset || !waitqueue_active(&ev->wq);
+	if (!(++ev->event_age)) {
+		/* Never wrap back to reserved/default event age 0/1 */
+		ev->event_age = 2;
+		WARN_ONCE(1, "event_age wrap back!");
+	}
 	list_for_each_entry(waiter, &ev->wq.head, wait.entry)
 		WRITE_ONCE(waiter->activated, true);
 static int init_event_waiter(struct kfd_process *p,
 		struct kfd_event_waiter *waiter,
-		uint32_t event_id)
+		struct kfd_event_data *event_data)
 {
-	struct kfd_event *ev = lookup_event_by_id(p, event_id);
+	struct kfd_event *ev = lookup_event_by_id(p, event_data->event_id);
 	if (!ev)
 		return -EINVAL;
 	waiter->event = ev;
 	waiter->activated = ev->signaled;
 	ev->signaled = ev->signaled && !ev->auto_reset;
+	/* last_event_age = 0 reserved for backward compatible */
+	if (waiter->event->type == KFD_EVENT_TYPE_SIGNAL &&
+		event_data->signal_event_data.last_event_age) {
+		waiter->event_age_enabled = true;
+		if (ev->event_age != event_data->signal_event_data.last_event_age)
+			waiter->activated = true;
+	}
 	if (!waiter->activated)
 		add_wait_queue(&ev->wq, &waiter->wait);
 	spin_unlock(&ev->lock);
 		struct kfd_event_waiter *event_waiters,
 		struct kfd_event_data __user *data)
 {
-	struct kfd_hsa_memory_exception_data *src;
+	void *src;
-	struct kfd_hsa_memory_exception_data __user *dst;
+	void __user *dst;
 	struct kfd_event_waiter *waiter;
 	struct kfd_event *event;
-	uint32_t i;
+	uint32_t i, size = 0;
 	for (i = 0; i < num_events; i++) {
 		waiter = &event_waiters[i];
 		event = waiter->event;
 		if (!event)
 			return -EINVAL; /* event was destroyed */
-		if (waiter->activated && event->type == KFD_EVENT_TYPE_MEMORY) {
+		if (waiter->activated) {
-			dst = &data[i].memory_exception_data;
+			if (event->type == KFD_EVENT_TYPE_MEMORY) {
-			src = &event->memory_exception_data;
+				dst = &data[i].memory_exception_data;
-			if (copy_to_user(dst, src,
+				src = &event->memory_exception_data;
-				sizeof(struct kfd_hsa_memory_exception_data)))
+				size = sizeof(struct kfd_hsa_memory_exception_data);
+			} else if (event->type == KFD_EVENT_TYPE_SIGNAL &&
+				waiter->event_age_enabled) {
+				dst = &data[i].signal_event_data.last_event_age;
+				src = &event->event_age;
+				size = sizeof(u64);
+			}
+			if (size && copy_to_user(dst, src, size))
 				return -EFAULT;
 		}
 	}
 			goto out_unlock;
 		}
-		ret = init_event_waiter(p, &event_waiters[i],
+		ret = init_event_waiter(p, &event_waiters[i], &event_data);
-					event_data.event_id);
 		if (ret)
 			goto out_unlock;
 	}

drivers/gpu/drm/amd/amdkfd/kfd_events.h+1−0

@@ -53,6 +53,7 @@ struct signal_page; · 52 unmodified lines
53		53
54	struct kfd_event {	54	struct kfd_event {
55	u32 event_id;	55	u32 event_id;
		56	u64 event_age;
56		57
57	bool signaled;	58	bool signaled;
58	bool auto_reset;	59	bool auto_reset;

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c+1−1

@@ -64,7 +64,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, uint64_t npages, · 63 unmodified lines
64	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);	64	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
65	num_bytes = npages * 8;	65	num_bytes = npages * 8;
66		66
67	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.entity,	67	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
68	AMDGPU_FENCE_OWNER_UNDEFINED,	68	AMDGPU_FENCE_OWNER_UNDEFINED,
69	num_dw * 4 + num_bytes,	69	num_dw * 4 + num_bytes,
70	AMDGPU_IB_POOL_DELAYED,	70	AMDGPU_IB_POOL_DELAYED,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+41−24

 	while (dret == dpcd_bytes_to_read &&
 		process_count < max_process_count) {
+		u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};
 		u8 retry;
 		dret = 0;
 		DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
 		/* handle HPD short pulse irq */
 		if (aconnector->mst_mgr.mst_state)
-			drm_dp_mst_hpd_irq(
+			drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr,
-				&aconnector->mst_mgr,
+							esi,
-				esi,
+							ack,
-				&new_irq_handled);
+							&new_irq_handled);
 		if (new_irq_handled) {
 			/* ACK at DPCD to notify down stream */
-			const int ack_dpcd_bytes_to_write =
-				dpcd_bytes_to_read - 1;
 			for (retry = 0; retry < 3; retry++) {
-				u8 wret;
+				ssize_t wret;
-				wret = drm_dp_dpcd_write(
+				wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
-					&aconnector->dm_dp_aux.aux,
+							  dpcd_addr + 1,
-					dpcd_addr + 1,
+							  ack[1]);
-					&esi[1],
+				if (wret == 1)
-					ack_dpcd_bytes_to_write);
-				if (wret == ack_dpcd_bytes_to_write)
 					break;
 			}
+			if (retry == 3) {
+				DRM_ERROR("Failed to ack MST event.\n");
+				return;
+			}
+			drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr);
 			/* check if there is new irq to be handled */
 			dret = drm_dp_dpcd_read(
 				&aconnector->dm_dp_aux.aux,
 				drm_add_modes_noedid(connector, 1920, 1080);
 	} else {
 		amdgpu_dm_connector_ddc_get_modes(connector, edid);
-		amdgpu_dm_connector_add_common_modes(encoder, connector);
+		/* most eDP supports only timings from its edid,
+		 * usually only detailed timings are available
+		 * from eDP edid. timings which are not from edid
+		 * may damage eDP
+		 */
+		if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+			amdgpu_dm_connector_add_common_modes(encoder, connector);
 		amdgpu_dm_connector_add_freesync_modes(connector, edid);
 	}
 	amdgpu_dm_fbc_init(connector);
 		if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
 			bundle->stream_update.abm_level = &acrtc_state->abm_level;
+		mutex_lock(&dm->dc_lock);
+		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
+				acrtc_state->stream->link->psr_settings.psr_allow_active)
+			amdgpu_dm_psr_disable(acrtc_state->stream);
+		mutex_unlock(&dm->dc_lock);
 		/*
 		 * If FreeSync state on the stream has changed then we need to
 		 * re-adjust the min/max bounds now that DC doesn't handle this
 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
 		}
 		mutex_lock(&dm->dc_lock);
-		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
-				acrtc_state->stream->link->psr_settings.psr_allow_active)
-			amdgpu_dm_psr_disable(acrtc_state->stream);
 		update_planes_and_stream_adapter(dm->dc,
 					 acrtc_state->update_type,
 					 planes_count,
 	drm_atomic_helper_cleanup_planes(dev, state);
-	/* return the stolen vga memory back to VRAM */
+	/* Don't free the memory if we are hitting this as part of suspend.
-	if (!adev->mman.keep_stolen_vga_memory)
+	 * This way we don't free any memory during suspend; see
-		amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
+	 * amdgpu_bo_free_kernel().  The memory will be freed in the first
-	amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
+	 * non-suspend modeset or when the driver is torn down.
+	 */
+	if (!adev->in_suspend) {
+		/* return the stolen vga memory back to VRAM */
+		if (!adev->mman.keep_stolen_vga_memory)
+			amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
+		amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
+	}
 	/*
 	 * Finally, drop a runtime PM reference for each newly disabled CRTC,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c+32−0

@@ -2760,6 +2760,32 @@ static int psr_read_residency(void data, u64 val) · 2759 unmodified lines
2760	return 0;	2760	return 0;
2761	}	2761	}
2762		2762
		2763	/* read allow_edp_hotplug_detection */
		2764	static int allow_edp_hotplug_detection_get(void data, u64 val)
		2765	{
		2766	struct amdgpu_dm_connector *aconnector = data;
		2767	struct drm_connector *connector = &aconnector->base;
		2768	struct drm_device *dev = connector->dev;
		2769	struct amdgpu_device *adev = drm_to_adev(dev);
		2770
		2771	*val = adev->dm.dc->config.allow_edp_hotplug_detection;
		2772
		2773	return 0;
		2774	}
		2775
		2776	/* set allow_edp_hotplug_detection */
		2777	static int allow_edp_hotplug_detection_set(void *data, u64 val)
		2778	{
		2779	struct amdgpu_dm_connector *aconnector = data;
		2780	struct drm_connector *connector = &aconnector->base;
		2781	struct drm_device *dev = connector->dev;
		2782	struct amdgpu_device *adev = drm_to_adev(dev);
		2783
		2784	adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
		2785
		2786	return 0;
		2787	}
		2788
2763	/*	2789	/*
2764	* Set dmcub trace event IRQ enable or disable.	2790	* Set dmcub trace event IRQ enable or disable.
2765	* Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en	2791	* Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
@@ -2798,6 +2824,10 @@ DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); · 32 unmodified lines
2798	DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,	2824	DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
2799	"%llu\n");	2825	"%llu\n");
2800		2826
		2827	DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
		2828	allow_edp_hotplug_detection_get,
		2829	allow_edp_hotplug_detection_set, "%llu\n");
		2830
2801	DEFINE_SHOW_ATTRIBUTE(current_backlight);	2831	DEFINE_SHOW_ATTRIBUTE(current_backlight);
2802	DEFINE_SHOW_ATTRIBUTE(target_backlight);	2832	DEFINE_SHOW_ATTRIBUTE(target_backlight);
2803		2833
@@ -2968,6 +2998,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) · 164 unmodified lines
2968	&target_backlight_fops);	2998	&target_backlight_fops);
2969	debugfs_create_file("ilr_setting", 0644, dir, connector,	2999	debugfs_create_file("ilr_setting", 0644, dir, connector,
2970	&edp_ilr_debugfs_fops);	3000	&edp_ilr_debugfs_fops);
		3001	debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
		3002	&allow_edp_hotplug_detection_fops);
2971	}	3003	}
2972		3004
2973	for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {	3005	for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c+3−3

 #include "dm_helpers.h"
 #include "ddc_service_types.h"
-/* MST Dock */
-static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
 /* dm_helpers_parse_edid_caps
  *
  * Parse edid caps
 	DC_LOG_DC("Done apply_synaptics_fifo_reset_wa\n");
 }
+/* MST Dock */
+static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 		struct drm_dp_aux *aux,
 		const struct dc_stream_state *stream,

drivers/gpu/drm/amd/display/dc/core/dc.c+16−20

 					if (pix_clk_100hz != requested_pix_clk_100hz) {
 						dc->link_srv->set_dpms_off(pipe);
-						pipe->stream->dpms_off = true;
+						pipe->stream->dpms_off = false;
 					}
 				}
 			}
 /**
- * ************************************************************************************************
+ * build_dmub_cmd_list() - Build an array of DMCUB commands to be sent to DMCUB
- * build_dmub_cmd_list: Build an array of DMCUB commands to be sent to DMCUB
  *
- * @param [in]: dc: Current DC state
+ * @dc: Current DC state
- * @param [in]: srf_updates: Array of surface updates
+ * @srf_updates: Array of surface updates
- * @param [in]: surface_count: Number of surfaces that have an updated
+ * @surface_count: Number of surfaces that have an updated
- * @param [in]: stream: Correponding stream to be updated in the current flip
+ * @stream: Corresponding stream to be updated in the current flip
- * @param [in]: context: New DC state to be programmed
+ * @context: New DC state to be programmed
  *
- * @param [out]: dc_dmub_cmd: Array of DMCUB commands to be sent to DMCUB
+ * @dc_dmub_cmd: Array of DMCUB commands to be sent to DMCUB
- * @param [out]: dmub_cmd_count: Count indicating the number of DMCUB commands in dc_dmub_cmd array
+ * @dmub_cmd_count: Count indicating the number of DMCUB commands in dc_dmub_cmd array
  *
  * This function builds an array of DMCUB commands to be sent to DMCUB. This function is required
  * to build an array of commands and have them sent while the OTG lock is acquired.
  *
- * @return: void
+ * Return: void
- * ************************************************************************************************
  */
 static void build_dmub_cmd_list(struct dc *dc,
 		struct dc_surface_update *srf_updates,
 }
 /**
- * *******************************************************************************
+ * update_seamless_boot_flags() - Helper function for updating seamless boot flags
- * update_seamless_boot_flags: Helper function for updating seamless boot flags
  *
- * @param [in]: dc: Current DC state
+ * @dc: Current DC state
- * @param [in]: context: New DC state to be programmed
+ * @context: New DC state to be programmed
- * @param [in]: surface_count: Number of surfaces that have an updated
+ * @surface_count: Number of surfaces that have an updated
- * @param [in]: stream: Correponding stream to be updated in the current flip
+ * @stream: Corresponding stream to be updated in the current flip
  *
  * Updating seamless boot flags do not need to be part of the commit sequence. This
  * helper function will update the seamless boot flags on each flip (if required)
  * outside of the HW commit sequence (fast or slow).
  *
- * @return: void
+ * Return: void
- * *******************************************************************************
  */
 static void update_seamless_boot_flags(struct dc *dc,
 		struct dc_state *context,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c+70−0

@@ -562,6 +562,29 @@ void hwss_build_fast_sequence(struct dc *dc, · 561 unmodified lines
562	(*num_steps)++;	562	(*num_steps)++;
563	}	563	}
564		564
		565	if (current_mpc_pipe->stream->update_flags.bits.out_csc) {
		566	block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;
		567	block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
		568	block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
		569	block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
		570	(*num_steps)++;
		571
		572	if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {
		573	block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
		574	block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
		575	block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;
		576	block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
		577	block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;
		578	(*num_steps)++;
		579	} else {
		580	block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;
		581	block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
		582	block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;
		583	block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
		584	block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;
		585	(*num_steps)++;
		586	}
		587	}
565	current_mpc_pipe = current_mpc_pipe->bottom_pipe;	588	current_mpc_pipe = current_mpc_pipe->bottom_pipe;
566	}	589	}
567	current_pipe = current_pipe->next_odm_pipe;	590	current_pipe = current_pipe->next_odm_pipe;
@@ -661,6 +684,15 @@ void hwss_execute_sequence(struct dc *dc, · 93 unmodified lines
661	params->update_visual_confirm_params.pipe_ctx,	684	params->update_visual_confirm_params.pipe_ctx,
662	params->update_visual_confirm_params.mpcc_id);	685	params->update_visual_confirm_params.mpcc_id);
663	break;	686	break;
		687	case MPC_POWER_ON_MPC_MEM_PWR:
		688	hwss_power_on_mpc_mem_pwr(params);
		689	break;
		690	case MPC_SET_OUTPUT_CSC:
		691	hwss_set_output_csc(params);
		692	break;
		693	case MPC_SET_OCSC_DEFAULT:
		694	hwss_set_ocsc_default(params);
		695	break;
664	case DMUB_SEND_DMCUB_CMD:	696	case DMUB_SEND_DMCUB_CMD:
665	hwss_send_dmcub_cmd(params);	697	hwss_send_dmcub_cmd(params);
666	break;	698	break;
@@ -718,6 +750,44 @@ void hwss_program_bias_and_scale(union block_sequence_params *params) · 51 unmodified lines
718	dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);	750	dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
719	}	751	}
720		752
		753	void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
		754	{
		755	struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;
		756	int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id;
		757	bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
		758
		759	if (mpc->funcs->power_on_mpc_mem_pwr)
		760	mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
		761	}
		762
		763	void hwss_set_output_csc(union block_sequence_params *params)
		764	{
		765	struct mpc *mpc = params->set_output_csc_params.mpc;
		766	int opp_id = params->set_output_csc_params.opp_id;
		767	const uint16_t *matrix = params->set_output_csc_params.regval;
		768	enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode;
		769
		770	if (mpc->funcs->set_output_csc != NULL)
		771	mpc->funcs->set_output_csc(mpc,
		772	opp_id,
		773	matrix,
		774	ocsc_mode);
		775	}
		776
		777	void hwss_set_ocsc_default(union block_sequence_params *params)
		778	{
		779	struct mpc *mpc = params->set_ocsc_default_params.mpc;
		780	int opp_id = params->set_ocsc_default_params.opp_id;
		781	enum dc_color_space colorspace = params->set_ocsc_default_params.color_space;
		782	enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode;
		783
		784	if (mpc->funcs->set_ocsc_default != NULL)
		785	mpc->funcs->set_ocsc_default(mpc,
		786	opp_id,
		787	colorspace,
		788	ocsc_mode);
		789	}
		790
721	void get_mclk_switch_visual_confirm_color(	791	void get_mclk_switch_visual_confirm_color(
722	struct dc *dc,	792	struct dc *dc,
723	struct dc_state *context,	793	struct dc_state *context,

drivers/gpu/drm/amd/display/dc/dc.h+6−3

 /*
- * Copyright 2012-14 Advanced Micro Devices, Inc.
+ * Copyright 2012-2023 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
 struct set_config_cmd_payload;
 struct dmub_notification;
-#define DC_VER "3.2.237"
+#define DC_VER "3.2.239"
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
 };
 enum dp_protocol_version {
-	DP_VERSION_1_4,
+	DP_VERSION_1_4 = 0,
+	DP_VERSION_2_1,
+	DP_VERSION_UNKNOWN,
 };
 enum dc_plane_type {
 	uint16_t subvp_pstate_allow_width_us;
 	uint16_t subvp_vertical_int_margin_us;
 	bool seamless_odm;
+	uint32_t max_v_total;
 	uint8_t subvp_drr_vblank_start_margin_us;
 };

drivers/gpu/drm/amd/display/dc/dc_dp_types.h+1−1

@@ -61,7 +61,7 @@ enum dc_link_rate { · 60 unmodified lines
61	*/	61	*/
62	LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane	62	LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane
63	LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane	63	LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane
64	LINK_RATE_UHBR20 = 2000, // UHBR10 - 20.0 Gbps/Lane	64	LINK_RATE_UHBR20 = 2000, // UHBR20 - 20.0 Gbps/Lane
65	};	65	};
66		66
67	enum dc_link_spread {	67	enum dc_link_spread {

drivers/gpu/drm/amd/display/dc/dc_types.h+1−0

@@ -597,6 +597,7 @@ enum dc_psr_state { · 596 unmodified lines
597	PSR_STATE4b_FULL_FRAME,	597	PSR_STATE4b_FULL_FRAME,
598	PSR_STATE4c_FULL_FRAME,	598	PSR_STATE4c_FULL_FRAME,
599	PSR_STATE4_FULL_FRAME_POWERUP,	599	PSR_STATE4_FULL_FRAME_POWERUP,
		600	PSR_STATE4_FULL_FRAME_HW_LOCK,
600	PSR_STATE5,	601	PSR_STATE5,
601	PSR_STATE5a,	602	PSR_STATE5a,
602	PSR_STATE5b,	603	PSR_STATE5b,

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c+2−0

 		state = PSR_STATE4c_FULL_FRAME;
 	else if (raw_state == 0x4E)
 		state = PSR_STATE4_FULL_FRAME_POWERUP;
+	else if (raw_state == 0x4F)
+		state = PSR_STATE4_FULL_FRAME_HW_LOCK;
 	else if (raw_state == 0x60)
 		state = PSR_STATE_HWLOCK_MGR;
 	else if (raw_state == 0x61)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c+12−8

 #define CTX \
 	oppn10->base.ctx
-/************* FORMATTER ************/
 /**
- *	set_truncation
+ * opp1_set_truncation():
  *	1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
  *	2) enable truncation
  *	3) HW remove 12bit FMT support for DCE11 power saving reason.
+ *
+ * @oppn10: output_pixel_processor struct instance for dcn10.
+ * @params: pointer to bit_depth_reduction_params.
  */
 static void opp1_set_truncation(
 		struct dcn10_opp *oppn10,
 }
 /**
- *	set_pixel_encoding
+ * opp1_set_pixel_encoding():
- *
- *	Set Pixel Encoding
  *		0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
  *		1: YCbCr 4:2:2
+ *
+ * @oppn10: output_pixel_processor struct instance for dcn10.
+ * @params: pointer to clamping_and_pixel_encoding_params.
  */
 static void opp1_set_pixel_encoding(
 	struct dcn10_opp *oppn10,
 }
 /**
- *	Set Clamping
+ * opp1_set_clamping():
  *	1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
  *		1 for 8 bpc
  *		2 for 10 bpc
  *		3 for 12 bpc
  *		7 for programable
  *	2) Enable clamp if Limited range requested
+ *
+ * @oppn10: output_pixel_processor struct instance for dcn10.
+ * @params: pointer to clamping_and_pixel_encoding_params.
  */
 static void opp1_set_clamping(
 	struct dcn10_opp *oppn10,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c+36−21

 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
 /**
-* apply_front_porch_workaround  TODO FPGA still need?
+ * apply_front_porch_workaround() - This is a workaround for a bug that has
-*
+ *                                  existed since R5xx and has not been fixed
-* This is a workaround for a bug that has existed since R5xx and has not been
+ *                                  keep Front porch at minimum 2 for Interlaced
-* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
+ *                                  mode or 1 for progressive.
-*/
+ *
+ * @timing: Timing parameters used to configure DCN blocks.
+ */
 static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
 {
 	if (timing->flags.INTERLACE == 1) {
 }
 /**
- * program_timing_generator   used by mode timing set
+ * optc1_program_timing() - used by mode timing set Program
- * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
+ *                          CRTC Timing Registers - OTG_H_*,
- * Including SYNC. Call BIOS command table to program Timings.
+ *                          OTG_V_*, Pixel repetition.
+ *                          Including SYNC. Call BIOS command table to program Timings.
+ *
+ * @optc: timing_generator instance.
+ * @dc_crtc_timing: Timing parameters used to configure DCN blocks.
+ * @vready_offset: Vready's starting position.
+ * @vstartup_start: Vstartup period.
+ * @vupdate_offset: Vupdate starting position.
+ * @vupdate_width: Vupdate duration.
+ * @signal: DC signal types.
+ * @use_vbios: to program timings from BIOS command table.
+ *
  */
 void optc1_program_timing(
 	struct timing_generator *optc,
  * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
  * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
  *
+ * @optc: timing_generator instance.
+ * @enable: Enable DRR double buffering control if true, disable otherwise.
+ *
  * Options: any time,  start of frame, dp start of frame (range timing)
  */
 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
 }
 /**
- * unblank_crtc
+ * optc1_unblank_crtc() - Call ASIC Control Object to UnBlank CRTC.
- * Call ASIC Control Object to UnBlank CRTC.
+ *
+ * @optc: timing_generator instance.
  */
 static void optc1_unblank_crtc(struct timing_generator *optc)
 {
 }
 /**
- * blank_crtc
+ * optc1_blank_crtc() - Call ASIC Control Object to Blank CRTC.
- * Call ASIC Control Object to Blank CRTC.
+ *
+ * @optc: timing_generator instance.
  */
 static void optc1_blank_crtc(struct timing_generator *optc)
 }
 /**
- * Enable CRTC
+ * optc1_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
- * Enable CRTC - call ASIC Control Object to enable Timing generator.
+ *
+ * @optc: timing_generator instance.
  */
 static bool optc1_enable_crtc(struct timing_generator *optc)
 {
 			MANUAL_FLOW_CONTROL, 0);
 }
 /**
- *****************************************************************************
+ * optc1_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
- *  Function: set_drr
  *
- *  @brief
+ * @optc: timing_generator instance.
- *     Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
+ * @params: parameters used for Dynamic Refresh Rate.
- *
- *****************************************************************************
  */
 void optc1_set_drr(
 	struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c+0−11

@@ -1741,17 +1741,6 @@ static void dcn20_program_pipe( · 1740 unmodified lines
1741		1741
1742	if (hws->funcs.setup_vupdate_interrupt)	1742	if (hws->funcs.setup_vupdate_interrupt)
1743	hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);	1743	hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1744
1745	if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
1746	unsigned int k1_div, k2_div;
1747
1748	hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
1749
1750	dc->res_pool->dccg->funcs->set_pixel_rate_div(
1751	dc->res_pool->dccg,
1752	pipe_ctx->stream_res.tg->inst,
1753	k1_div, k2_div);
1754	}
1755	}	1744	}
1756		1745
1757	if (pipe_ctx->update_flags.bits.odm)	1746	if (pipe_ctx->update_flags.bits.odm)

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c+3−0

  * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
  * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
  *
+ * @optc: timing_generator instance.
+ * @enable: Enable DRR double buffering control if true, disable otherwise.
+ *
  * Options: any time,  start of frame, dp start of frame (range timing)
  */
 static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c+1−0

@@ -2328,6 +2328,7 @@ static bool dcn30_resource_construct( · 2327 unmodified lines
2328	dc->caps.color.mpc.ocsc = 1;	2328	dc->caps.color.mpc.ocsc = 1;
2329		2329
2330	dc->caps.dp_hdmi21_pcon_support = true;	2330	dc->caps.dp_hdmi21_pcon_support = true;
		2331	dc->caps.max_v_total = (1 << 15) - 1;
2331		2332
2332	/* read VBIOS LTTPR caps */	2333	/* read VBIOS LTTPR caps */
2333	{	2334	{

drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c+1−0

@@ -1227,6 +1227,7 @@ static bool dcn302_resource_construct( · 1226 unmodified lines
1227	dc->caps.force_dp_tps4_for_cp2520 = true;	1227	dc->caps.force_dp_tps4_for_cp2520 = true;
1228	dc->caps.extended_aux_timeout_support = true;	1228	dc->caps.extended_aux_timeout_support = true;
1229	dc->caps.dmcub_support = true;	1229	dc->caps.dmcub_support = true;
		1230	dc->caps.max_v_total = (1 << 15) - 1;
1230		1231
1231	/* Color pipeline capabilities */	1232	/* Color pipeline capabilities */
1232	dc->caps.color.dpp.dcn_arch = 1;	1233	dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c+1−0

@@ -1152,6 +1152,7 @@ static bool dcn303_resource_construct( · 1151 unmodified lines
1152	dc->caps.force_dp_tps4_for_cp2520 = true;	1152	dc->caps.force_dp_tps4_for_cp2520 = true;
1153	dc->caps.extended_aux_timeout_support = true;	1153	dc->caps.extended_aux_timeout_support = true;
1154	dc->caps.dmcub_support = true;	1154	dc->caps.dmcub_support = true;
		1155	dc->caps.max_v_total = (1 << 15) - 1;
1155		1156
1156	/* Color pipeline capabilities */	1157	/* Color pipeline capabilities */
1157	dc->caps.color.dpp.dcn_arch = 1;	1158	dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c+8−0

@@ -47,6 +47,14 @@ void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) · 46 unmodified lines
47	{	47	{
48	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);	48	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
49		49
		50	if (dccg->dpp_clock_gated[dpp_inst]) {
		51	/*
		52	* Do not update the DPPCLK DTO if the clock is stopped.
		53	* It is treated the same as if the pipe itself were in PG.
		54	*/
		55	return;
		56	}
		57
50	if (dccg->ref_dppclk && req_dppclk) {	58	if (dccg->ref_dppclk && req_dppclk) {
51	int ref_dppclk = dccg->ref_dppclk;	59	int ref_dppclk = dccg->ref_dppclk;
52	int modulo, phase;	60	int modulo, phase;

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c+5−0

 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+	if (dccg->dpp_clock_gated[dpp_inst] == clock_on)
+		return;
 	if (clock_on) {
 		/* turn off the DTO and leave phase/modulo at max */
 		REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0);
 			  DPPCLK0_DTO_PHASE, 0,
 			  DPPCLK0_DTO_MODULO, 1);
 	}
+	dccg->dpp_clock_gated[dpp_inst] = !clock_on;
 }
 static const struct dccg_funcs dccg314_funcs = {

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c+2−7

 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 }
-unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
+void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
 {
 	struct dc_stream_state *stream = pipe_ctx->stream;
-	unsigned int odm_combine_factor = 0;
 	bool two_pix_per_container = false;
 	two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
-	odm_combine_factor = get_odm_config(pipe_ctx, NULL);
+	get_odm_config(pipe_ctx, NULL);
 	if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
 		*k1_div = PIXEL_RATE_DIV_BY_1;
 		} else {
 			*k1_div = PIXEL_RATE_DIV_BY_1;
 			*k2_div = PIXEL_RATE_DIV_BY_4;
-			if (odm_combine_factor == 2)
-				*k2_div = PIXEL_RATE_DIV_BY_2;
 		}
 	}
 	if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
 		ASSERT(false);
-	return odm_combine_factor;
 }
 void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h+1−1

@@ -37,7 +37,7 @@ void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool po · 36 unmodified lines
37		37
38	void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);	38	void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
39		39
40	unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx pipe_ctx, unsigned int k1_div, unsigned int *k2_div);	40	void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx pipe_ctx, unsigned int k1_div, unsigned int *k2_div);
41		41
42	void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);	42	void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
43		43

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c+25−2

@@ -874,8 +874,8 @@ static const struct dc_debug_options debug_defaults_drv = { · 873 unmodified lines
874	.force_abm_enable = false,	874	.force_abm_enable = false,
875	.timing_trace = false,	875	.timing_trace = false,
876	.clock_trace = true,	876	.clock_trace = true,
877	.disable_dpp_power_gate = true,	877	.disable_dpp_power_gate = false,
878	.disable_hubp_power_gate = true,	878	.disable_hubp_power_gate = false,
879	.disable_pplib_clock_request = false,	879	.disable_pplib_clock_request = false,
880	.pipe_split_policy = MPC_SPLIT_DYNAMIC,	880	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
881	.force_single_disp_pipe_split = false,	881	.force_single_disp_pipe_split = false,
@@ -904,6 +904,22 @@ static const struct dc_debug_options debug_defaults_drv = { · 22 unmodified lines
904	.afmt = true,	904	.afmt = true,
905	}	905	}
906	},	906	},
		907
		908	.root_clock_optimization = {
		909	.bits = {
		910	.dpp = true,
		911	.dsc = false,
		912	.hdmistream = false,
		913	.hdmichar = false,
		914	.dpstream = false,
		915	.symclk32_se = false,
		916	.symclk32_le = false,
		917	.symclk_fe = false,
		918	.physymclk = false,
		919	.dpiasymclk = false,
		920	}
		921	},
		922
907	.seamless_boot_odm_combine = true	923	.seamless_boot_odm_combine = true
908	};	924	};
909		925
@@ -1867,6 +1883,13 @@ static bool dcn314_resource_construct( · 957 unmodified lines
1867	/* Use pipe context based otg sync logic */	1883	/* Use pipe context based otg sync logic */
1868	dc->config.use_pipe_ctx_sync_logic = true;	1884	dc->config.use_pipe_ctx_sync_logic = true;
1869		1885
		1886	/* Disable pipe power gating when unsupported */
		1887	if (ctx->asic_id.hw_internal_rev == 0x01 \|\|
		1888	ctx->asic_id.hw_internal_rev == 0x80) {
		1889	dc->debug.disable_dpp_power_gate = true;
		1890	dc->debug.disable_hubp_power_gate = true;
		1891	}
		1892
1870	/* read VBIOS LTTPR caps */	1893	/* read VBIOS LTTPR caps */
1871	{	1894	{
1872	if (ctx->dc_bios->funcs->get_lttpr_caps) {	1895	if (ctx->dc_bios->funcs->get_lttpr_caps) {

drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c+1−0

@@ -1742,6 +1742,7 @@ static int dcn315_populate_dml_pipes_from_context( · 1741 unmodified lines
1742	/* Do not use asymetric crb if not enough for pstate support */	1742	/* Do not use asymetric crb if not enough for pstate support */
1743	if (remaining_det_segs < 0) {	1743	if (remaining_det_segs < 0) {
1744	pipes[pipe_cnt].pipe.src.det_size_override = 0;	1744	pipes[pipe_cnt].pipe.src.det_size_override = 0;
		1745	pipe_cnt++;
1745	continue;	1746	continue;
1746	}	1747	}
1747		1748

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c+4−7

 	}
 }
-unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
+void dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
 {
 	struct dc_stream_state *stream = pipe_ctx->stream;
-	unsigned int odm_combine_factor = 0;
 	bool two_pix_per_container = false;
 	// For phantom pipes, use the same programming as the main pipes
 		stream = pipe_ctx->stream->mall_stream_config.paired_stream;
 	}
 	two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
-	odm_combine_factor = get_odm_config(pipe_ctx, NULL);
 	if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
 		*k1_div = PIXEL_RATE_DIV_BY_1;
 		} else {
 			*k1_div = PIXEL_RATE_DIV_BY_1;
 			*k2_div = PIXEL_RATE_DIV_BY_4;
-			if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
+			if (dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
 				*k2_div = PIXEL_RATE_DIV_BY_2;
 		}
 	}
 	if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
 		ASSERT(false);
-	return odm_combine_factor;
 }
 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
 		if (pipe->top_pipe || pipe->prev_odm_pipe)
 			continue;
-		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
+		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))
+			&& pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
 			pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
 			reset_sync_context_for_pipe(dc, context, i);
 			otg_disabled[i] = true;

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h+1−1

@@ -71,7 +71,7 @@ void dcn32_update_force_pstate(struct dc dc, struct dc_state context); · 70 unmodified lines
71		71
72	void dcn32_update_odm(struct dc dc, struct dc_state context, struct pipe_ctx *pipe_ctx);	72	void dcn32_update_odm(struct dc dc, struct dc_state context, struct pipe_ctx *pipe_ctx);
73		73
74	unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx pipe_ctx, unsigned int k1_div, unsigned int *k2_div);	74	void dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx pipe_ctx, unsigned int k1_div, unsigned int *k2_div);
75		75
76	void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);	76	void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
77		77

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c+5−2

 			OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
 }
 /**
- * Enable CRTC
+ * optc32_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
- * Enable CRTC - call ASIC Control Object to enable Timing generator.
+ *
+ * @optc: timing_generator instance.
+ *
+ * Return: If CRTC is enabled, return true.
  */
 static bool optc32_enable_crtc(struct timing_generator *optc)
 {

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c+2−1

 	.fpo_vactive_margin_us = 2000, // 2000us
 	.disable_fpo_vactive = false,
 	.disable_boot_optimizations = false,
-	.disable_subvp_high_refresh = true,
+	.disable_subvp_high_refresh = false,
 	.disable_dp_plus_plus_wa = true,
 	.fpo_vactive_min_active_margin_us = 200,
 	.fpo_vactive_max_blank_us = 1000,
 	dc->caps.extended_aux_timeout_support = true;
 	dc->caps.dmcub_support = true;
 	dc->caps.seamless_odm = true;
+	dc->caps.max_v_total = (1 << 15) - 1;
 	/* Color pipeline capabilities */
 	dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h+4−0

@@ -169,6 +169,10 @@ double dcn32_determine_max_vratio_prefetch(struct dc dc, struct dc_state conte · 168 unmodified lines
169		169
170	bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height);	170	bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height);
171		171
		172	bool dcn32_subvp_drr_admissable(struct dc dc, struct dc_state context);
		173
		174	bool dcn32_subvp_vblank_admissable(struct dc dc, struct dc_state context, int vlevel);
		175
172	/* definitions for run time init of reg offsets */	176	/* definitions for run time init of reg offsets */
173		177
174	/* CLK SRC */	178	/* CLK SRC */

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c+104−43

@@ -255,8 +255,6 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe) · 254 unmodified lines
255	return psr_capable;	255	return psr_capable;
256	}	256	}
257		257
258	#define DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER 7
259
260	/**	258	/**
261	* dcn32_determine_det_override(): Determine DET allocation for each pipe	259	* dcn32_determine_det_override(): Determine DET allocation for each pipe
262	*	260	*
@@ -267,6 +265,7 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe) · 4 unmodified lines
267	* If there is a plane that's driven by more than 1 pipe (i.e. pipe split), then the	265	* If there is a plane that's driven by more than 1 pipe (i.e. pipe split), then the
268	* number of DET for that given plane will be split among the pipes driving that plane.	266	* number of DET for that given plane will be split among the pipes driving that plane.
269	*	267	*
		268	*
270	* High level algorithm:	269	* High level algorithm:
271	* 1. Split total DET among number of streams	270	* 1. Split total DET among number of streams
272	* 2. For each stream, split DET among the planes	271	* 2. For each stream, split DET among the planes
@@ -274,18 +273,6 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe) · 1 unmodified line
274	* among those pipes.	273	* among those pipes.
275	* 4. Assign the DET override to the DML pipes.	274	* 4. Assign the DET override to the DML pipes.
276	*	275	*
277	* Special cases:
278	*
279	* For two displays that have a large difference in pixel rate, we may experience
280	* underflow on the larger display when we divide the DET equally. For this, we
281	* will implement a modified algorithm to assign more DET to larger display.
282	*
283	* 1. Calculate difference in pixel rates ( multiplier ) between two displays
284	* 2. If the multiplier exceeds DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER, then
285	* implement the modified DET override algorithm.
286	* 3. Assign smaller DET size for lower pixel display and higher DET size for
287	* higher pixel display
288	*
289	* @dc: Current DC state	276	* @dc: Current DC state
290	* @context: New DC state to be programmed	277	* @context: New DC state to be programmed
291	* @pipes: Array of DML pipes	278	* @pipes: Array of DML pipes
@@ -303,31 +290,10 @@ void dcn32_determine_det_override(struct dc *dc, · 11 unmodified lines
303	struct dc_plane_state *current_plane = NULL;	290	struct dc_plane_state *current_plane = NULL;
304	uint8_t stream_count = 0;	291	uint8_t stream_count = 0;
305		292
306	int phy_pix_clk_mult, lower_mode_stream_index;
307	int phy_pix_clk[MAX_PIPES] = {0};
308	bool use_new_det_override_algorithm = false;
309
310	for (i = 0; i < context->stream_count; i++) {	293	for (i = 0; i < context->stream_count; i++) {
311	/* Don't count SubVP streams for DET allocation */	294	/* Don't count SubVP streams for DET allocation */
312	if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) {	295	if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM)
313	phy_pix_clk[i] = context->streams[i]->phy_pix_clk;
314	stream_count++;	296	stream_count++;
315	}
316	}
317
318	/* Check for special case with two displays, one with much higher pixel rate */
319	if (stream_count == 2) {
320	ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0));
321	if (phy_pix_clk[0] < phy_pix_clk[1]) {
322	lower_mode_stream_index = 0;
323	phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0];
324	} else {
325	lower_mode_stream_index = 1;
326	phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1];
327	}
328
329	if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER)
330	use_new_det_override_algorithm = true;
331	}	297	}
332		298
333	if (stream_count > 0) {	299	if (stream_count > 0) {
@@ -336,13 +302,6 @@ void dcn32_determine_det_override(struct dc *dc, · 2 unmodified lines
336	if (context->streams[i]->mall_stream_config.type == SUBVP_PHANTOM)	302	if (context->streams[i]->mall_stream_config.type == SUBVP_PHANTOM)
337	continue;	303	continue;
338		304
339	if (use_new_det_override_algorithm) {
340	if (i == lower_mode_stream_index)
341	stream_segments = 4;
342	else
343	stream_segments = 14;
344	}
345
346	if (context->stream_status[i].plane_count > 0)	305	if (context->stream_status[i].plane_count > 0)
347	plane_segments = stream_segments / context->stream_status[i].plane_count;	306	plane_segments = stream_segments / context->stream_status[i].plane_count;
348	else	307	else
@@ -660,3 +619,105 @@ bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int widt · 311 unmodified lines
660		619
661	return is_native_scaling;	620	return is_native_scaling;
662	}	621	}
		622
		623	/**
		624	* dcn32_subvp_drr_admissable() - Determine if SubVP + DRR config is admissible
		625	*
		626	* @dc: Current DC state
		627	* @context: New DC state to be programmed
		628	*
		629	* SubVP + DRR is admissible under the following conditions:
		630	* - Config must have 2 displays (i.e., 2 non-phantom master pipes)
		631	* - One display is SubVP
		632	* - Other display must have Freesync enabled
		633	* - The potential DRR display must not be PSR capable
		634	*
		635	* Return: True if admissible, false otherwise
		636	*/
		637	bool dcn32_subvp_drr_admissable(struct dc dc, struct dc_state context)
		638	{
		639	bool result = false;
		640	uint32_t i;
		641	uint8_t subvp_count = 0;
		642	uint8_t non_subvp_pipes = 0;
		643	bool drr_pipe_found = false;
		644	bool drr_psr_capable = false;
		645
		646	for (i = 0; i < dc->res_pool->pipe_count; i++) {
		647	struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
		648
		649	if (!pipe->stream)
		650	continue;
		651
		652	if (pipe->plane_state && !pipe->top_pipe) {
		653	if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
		654	subvp_count++;
		655	if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
		656	non_subvp_pipes++;
		657	drr_psr_capable = (drr_psr_capable \|\| dcn32_is_psr_capable(pipe));
		658	if (pipe->stream->ignore_msa_timing_param &&
		659	(pipe->stream->allow_freesync \|\| pipe->stream->vrr_active_variable)) {
		660	drr_pipe_found = true;
		661	}
		662	}
		663	}
		664	}
		665
		666	if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found && !drr_psr_capable)
		667	result = true;
		668
		669	return result;
		670	}
		671
		672	/**
		673	* dcn32_subvp_vblank_admissable() - Determine if SubVP + Vblank config is admissible
		674	*
		675	* @dc: Current DC state
		676	* @context: New DC state to be programmed
		677	* @vlevel: Voltage level calculated by DML
		678	*
		679	* SubVP + Vblank is admissible under the following conditions:
		680	* - Config must have 2 displays (i.e., 2 non-phantom master pipes)
		681	* - One display is SubVP
		682	* - Other display must not have Freesync capability
		683	* - DML must have output DRAM clock change support as SubVP + Vblank
		684	* - The potential vblank display must not be PSR capable
		685	*
		686	* Return: True if admissible, false otherwise
		687	*/
		688	bool dcn32_subvp_vblank_admissable(struct dc dc, struct dc_state context, int vlevel)
		689	{
		690	bool result = false;
		691	uint32_t i;
		692	uint8_t subvp_count = 0;
		693	uint8_t non_subvp_pipes = 0;
		694	bool drr_pipe_found = false;
		695	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
		696	bool vblank_psr_capable = false;
		697
		698	for (i = 0; i < dc->res_pool->pipe_count; i++) {
		699	struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
		700
		701	if (!pipe->stream)
		702	continue;
		703
		704	if (pipe->plane_state && !pipe->top_pipe) {
		705	if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
		706	subvp_count++;
		707	if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
		708	non_subvp_pipes++;
		709	vblank_psr_capable = (vblank_psr_capable \|\| dcn32_is_psr_capable(pipe));
		710	if (pipe->stream->ignore_msa_timing_param &&
		711	(pipe->stream->allow_freesync \|\| pipe->stream->vrr_active_variable)) {
		712	drr_pipe_found = true;
		713	}
		714	}
		715	}
		716	}
		717
		718	if (subvp_count == 1 && non_subvp_pipes == 1 && !drr_pipe_found && !vblank_psr_capable &&
		719	vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp)
		720	result = true;
		721
		722	return result;
		723	}

drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c+2−1

 	.fpo_vactive_margin_us = 2000, // 2000us
 	.disable_fpo_vactive = false,
 	.disable_boot_optimizations = false,
-	.disable_subvp_high_refresh = true,
+	.disable_subvp_high_refresh = false,
 	.fpo_vactive_min_active_margin_us = 200,
 	.fpo_vactive_max_blank_us = 1000,
 };
 	dc->caps.edp_dsc_support = true;
 	dc->caps.extended_aux_timeout_support = true;
 	dc->caps.dmcub_support = true;
+	dc->caps.max_v_total = (1 << 15) - 1;
 	/* Color pipeline capabilities */
 	dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c+59−0

@@ -5557,6 +5557,65 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ · 5556 unmodified lines
5557	}	5557	}
5558	}	5558	}
5559	}	5559	}
		5560	for (i = v->soc.num_states; i >= 0; i--) {
		5561	for (j = 0; j < 2; j++) {
		5562	enum dm_validation_status status = DML_VALIDATION_OK;
		5563
		5564	if (!v->ScaleRatioAndTapsSupport) {
		5565	status = DML_FAIL_SCALE_RATIO_TAP;
		5566	} else if (!v->SourceFormatPixelAndScanSupport) {
		5567	status = DML_FAIL_SOURCE_PIXEL_FORMAT;
		5568	} else if (!v->ViewportSizeSupport[i][j]) {
		5569	status = DML_FAIL_VIEWPORT_SIZE;
		5570	} else if (P2IWith420) {
		5571	status = DML_FAIL_P2I_WITH_420;
		5572	} else if (DSCOnlyIfNecessaryWithBPP) {
		5573	status = DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP;
		5574	} else if (DSC422NativeNotSupported) {
		5575	status = DML_FAIL_NOT_DSC422_NATIVE;
		5576	} else if (!v->ODMCombine4To1SupportCheckOK[i]) {
		5577	status = DML_FAIL_ODM_COMBINE4TO1;
		5578	} else if (v->NotEnoughDSCUnits[i]) {
		5579	status = DML_FAIL_NOT_ENOUGH_DSC;
		5580	} else if (!v->ROBSupport[i][j]) {
		5581	status = DML_FAIL_REORDERING_BUFFER;
		5582	} else if (!v->DISPCLK_DPPCLK_Support[i][j]) {
		5583	status = DML_FAIL_DISPCLK_DPPCLK;
		5584	} else if (!v->TotalAvailablePipesSupport[i][j]) {
		5585	status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
		5586	} else if (!EnoughWritebackUnits) {
		5587	status = DML_FAIL_ENOUGH_WRITEBACK_UNITS;
		5588	} else if (!v->WritebackLatencySupport) {
		5589	status = DML_FAIL_WRITEBACK_LATENCY;
		5590	} else if (!v->WritebackScaleRatioAndTapsSupport) {
		5591	status = DML_FAIL_WRITEBACK_SCALE_RATIO_TAP;
		5592	} else if (!v->CursorSupport) {
		5593	status = DML_FAIL_CURSOR_SUPPORT;
		5594	} else if (!v->PitchSupport) {
		5595	status = DML_FAIL_PITCH_SUPPORT;
		5596	} else if (ViewportExceedsSurface) {
		5597	status = DML_FAIL_VIEWPORT_EXCEEDS_SURFACE;
		5598	} else if (!v->PrefetchSupported[i][j]) {
		5599	status = DML_FAIL_PREFETCH_SUPPORT;
		5600	} else if (!v->DynamicMetadataSupported[i][j]) {
		5601	status = DML_FAIL_DYNAMIC_METADATA;
		5602	} else if (!v->TotalVerticalActiveBandwidthSupport[i][j]) {
		5603	status = DML_FAIL_TOTAL_V_ACTIVE_BW;
		5604	} else if (!v->VRatioInPrefetchSupported[i][j]) {
		5605	status = DML_FAIL_V_RATIO_PREFETCH;
		5606	} else if (!v->PTEBufferSizeNotExceeded[i][j]) {
		5607	status = DML_FAIL_PTE_BUFFER_SIZE;
		5608	} else if (v->NonsupportedDSCInputBPC) {
		5609	status = DML_FAIL_DSC_INPUT_BPC;
		5610	} else if ((v->HostVMEnable
		5611	&& !v->ImmediateFlipSupportedForState[i][j])) {
		5612	status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP;
		5613	} else if (FMTBufferExceeded) {
		5614	status = DML_FAIL_FMT_BUFFER_EXCEEDED;
		5615	}
		5616	mode_lib->vba.ValidationStatus[i] = status;
		5617	}
		5618	}
5560		5619
5561	{	5620	{
5562	unsigned int MaximumMPCCombine = 0;	5621	unsigned int MaximumMPCCombine = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c+110−68

 	unsigned int max_frame_time = 0;
 	bool valid_assignment_found = false;
 	unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
-	bool current_assignment_freesync = false;
 	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 				struct dc_stream_state *stream = pipe->stream;
 				unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
 						(double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
-				if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) {
+				if (frame_us > max_frame_time) {
 					*index = i;
 					max_frame_time = frame_us;
 					valid_assignment_found = true;
-					current_assignment_freesync = false;
-				/* For the 2-Freesync display case, still choose the one with the
-			     * longest frame time
-			     */
-				} else if (stream->ignore_msa_timing_param && (!valid_assignment_found ||
-						(current_assignment_freesync && frame_us > max_frame_time))) {
-					*index = i;
-					valid_assignment_found = true;
-					current_assignment_freesync = true;
 				}
 			}
 		}
 }
 /**
- * subvp_drr_schedulable - Determine if SubVP + DRR config is schedulable
+ * subvp_drr_schedulable() - Determine if SubVP + DRR config is schedulable
  * @dc: current dc state
  * @context: new dc state
- * @drr_pipe: DRR pipe_ctx for the SubVP + DRR config
  *
  * High level algorithm:
  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
  *
  * Return: True if the SubVP + DRR config is schedulable, false otherwise
  */
-static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe)
+static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
 {
 	bool schedulable = false;
 	uint32_t i;
 	struct pipe_ctx *pipe = NULL;
+	struct pipe_ctx *drr_pipe = NULL;
 	struct dc_crtc_timing *main_timing = NULL;
 	struct dc_crtc_timing *phantom_timing = NULL;
 	struct dc_crtc_timing *drr_timing = NULL;
 			break;
 	}
+	// Find the DRR pipe
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		drr_pipe = &context->res_ctx.pipe_ctx[i];
+		// We check for master pipe only
+		if (!drr_pipe->stream || !drr_pipe->plane_state || drr_pipe->top_pipe || drr_pipe->prev_odm_pipe)
+			continue;
+		if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param &&
+				(drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable))
+			break;
+	}
 	main_timing = &pipe->stream->timing;
 	phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
 	drr_timing = &drr_pipe->stream->timing;
 		if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 			subvp_pipe = pipe;
 	}
-	// Use ignore_msa_timing_param and VRR active, or Freesync flag to identify as DRR On
+	if (found) {
-	if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param &&
-			(context->res_ctx.pipe_ctx[vblank_index].stream->allow_freesync ||
-			context->res_ctx.pipe_ctx[vblank_index].stream->vrr_active_variable)) {
-		// SUBVP + DRR case -- only allowed if run through DRR validation path
-		schedulable = false;
-	} else if (found) {
 		main_timing = &subvp_pipe->stream->timing;
 		phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
 		vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
 	return schedulable;
 }
+/**
+ * subvp_subvp_admissable() - Determine if subvp + subvp config is admissible
+ *
+ * @dc: Current DC state
+ * @context: New DC state to be programmed
+ *
+ * SubVP + SubVP is admissible under the following conditions:
+ * - All SubVP pipes are < 120Hz OR
+ * - All SubVP pipes are >= 120hz
+ *
+ * Return: True if admissible, false otherwise
+ */
+static bool subvp_subvp_admissable(struct dc *dc,
+				struct dc_state *context)
+{
+	bool result = false;
+	uint32_t i;
+	uint8_t subvp_count = 0;
+	uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0;
+	uint32_t refresh_rate = 0;
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		if (!pipe->stream)
+			continue;
+		if (pipe->plane_state && !pipe->top_pipe &&
+				pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+			refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
+					pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
+					/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
+			if (refresh_rate < min_refresh)
+				min_refresh = refresh_rate;
+			if (refresh_rate > max_refresh)
+				max_refresh = refresh_rate;
+			subvp_count++;
+		}
+	}
+	if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) ||
+			(min_refresh >= 120 && max_refresh >= 120)))
+		result = true;
+	return result;
+}
 /**
  * subvp_validate_static_schedulability - Check which SubVP case is calculated
  * and handle static analysis based on the case.
 				struct dc_state *context,
 				int vlevel)
 {
-	bool schedulable = true;	// true by default for single display case
+	bool schedulable = false;
 	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 	uint32_t i, pipe_idx;
 	uint8_t subvp_count = 0;
 	uint8_t vactive_count = 0;
+	uint8_t non_subvp_pipes = 0;
 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 		if (!pipe->stream)
 			continue;
-		if (pipe->plane_state && !pipe->top_pipe &&
+		if (pipe->plane_state && !pipe->top_pipe) {
-				pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+			if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
-			subvp_count++;
+				subvp_count++;
+			if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
+				non_subvp_pipes++;
+			}
+		}
 		// Count how many planes that aren't SubVP/phantom are capable of VACTIVE
 		// switching (SubVP + VACTIVE unsupported). In situations where we force
 		// SubVP for a VACTIVE plane, we don't want to increment the vactive_count.
-		if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 &&
+		if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
 		    pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 			vactive_count++;
 		}
 	if (subvp_count == 2) {
 		// Static schedulability check for SubVP + SubVP case
-		schedulable = subvp_subvp_schedulable(dc, context);
+		schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context);
-	} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) {
+	} else if (subvp_count == 1 && non_subvp_pipes == 0) {
-		// Static schedulability check for SubVP + VBLANK case. Also handle the case where
+		// Single SubVP configs will be supported by default as long as it's suppported by DML
-		// DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK)
+		schedulable = true;
-		if (vactive_count > 0)
+	} else if (subvp_count == 1 && non_subvp_pipes == 1) {
-			schedulable = false;
+		if (dcn32_subvp_drr_admissable(dc, context))
-		else
+			schedulable = subvp_drr_schedulable(dc, context);
+		else if (dcn32_subvp_vblank_admissable(dc, context, vlevel))
 			schedulable = subvp_vblank_schedulable(dc, context);
 	} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp &&
 			vactive_count > 0) {
 	unsigned int dc_pipe_idx = 0;
 	int i = 0;
 	bool found_supported_config = false;
-	struct pipe_ctx *pipe = NULL;
-	uint32_t non_subvp_pipes = 0;
-	bool drr_pipe_found = false;
-	uint32_t drr_pipe_index = 0;
 	dc_assert_fp_enabled();
 				}
 			}
-			if (*vlevel < context->bw_ctx.dml.soc.num_states &&
+			if (*vlevel < context->bw_ctx.dml.soc.num_states
-			    vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported
+			    && subvp_validate_static_schedulability(dc, context, *vlevel))
-			    && subvp_validate_static_schedulability(dc, context, *vlevel)) {
 				found_supported_config = true;
-			} else if (*vlevel < context->bw_ctx.dml.soc.num_states) {
+			if (found_supported_config) {
-				/* Case where 1 SubVP is added, and DML reports MCLK unsupported or DRR is allowed.
+				// For SubVP + DRR cases, we can force the lowest vlevel that supports the mode
-				 * This handles the case for SubVP + DRR, where the DRR display does not support MCLK
+				if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) {
-				 * switch at it's native refresh rate / timing, or DRR is allowed for the non-subvp
-				 * display.
-				 */
-				for (i = 0; i < dc->res_pool->pipe_count; i++) {
-					pipe = &context->res_ctx.pipe_ctx[i];
-					if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
-					    pipe->stream->mall_stream_config.type == SUBVP_NONE) {
-						non_subvp_pipes++;
-						// Use ignore_msa_timing_param flag to identify as DRR
-						if (pipe->stream->ignore_msa_timing_param && pipe->stream->allow_freesync) {
-							drr_pipe_found = true;
-							drr_pipe_index = i;
-						}
-					}
-				}
-				// If there is only 1 remaining non SubVP pipe that is DRR, check static
-				// schedulability for SubVP + DRR.
-				if (non_subvp_pipes == 1 && drr_pipe_found) {
 					/* find lowest vlevel that supports the config */
 					for (i = *vlevel; i >= 0; i--) {
 						if (vba->ModeSupport[i][vba->maxMpcComb]) {
 							break;
 						}
 					}
-					found_supported_config = subvp_drr_schedulable(dc, context,
-										       &context->res_ctx.pipe_ctx[drr_pipe_index]);
 				}
 			}
 		}
 {
 	bool allow = false;
 	uint32_t refresh_rate = 0;
-	uint32_t min_refresh = subvp_high_refresh_list.min_refresh;
+	uint32_t subvp_min_refresh = subvp_high_refresh_list.min_refresh;
-	uint32_t max_refresh = subvp_high_refresh_list.max_refresh;
+	uint32_t subvp_max_refresh = subvp_high_refresh_list.max_refresh;
+	uint32_t min_refresh = subvp_max_refresh;
 	uint32_t i;
-	if (!dc->debug.disable_subvp_high_refresh && pipe->stream &&
+	/* Only allow SubVP on high refresh displays if all connected displays
+	 * are considered "high refresh" (i.e. >= 120hz). We do not want to
+	 * allow combinations such as 120hz (SubVP) + 60hz (SubVP).
+	 */
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+		if (!pipe_ctx->stream)
+			continue;
+		refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 +
+				pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)
+						/ (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total);
+		if (refresh_rate < min_refresh)
+			min_refresh = refresh_rate;
+	}
+	if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream &&
 			pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
 		refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
 						pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
 						/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
-		if (refresh_rate >= min_refresh && refresh_rate <= max_refresh) {
+		if (refresh_rate >= subvp_min_refresh && refresh_rate <= subvp_max_refresh) {
 			for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) {
 				uint32_t width = subvp_high_refresh_list.res[i].width;
 				uint32_t height = subvp_high_refresh_list.res[i].height;

drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h+8−0

@@ -190,6 +190,14 @@ enum dm_validation_status { · 189 unmodified lines
190	DML_FAIL_DSC_INPUT_BPC,	190	DML_FAIL_DSC_INPUT_BPC,
191	DML_FAIL_PREFETCH_SUPPORT,	191	DML_FAIL_PREFETCH_SUPPORT,
192	DML_FAIL_V_RATIO_PREFETCH,	192	DML_FAIL_V_RATIO_PREFETCH,
		193	DML_FAIL_P2I_WITH_420,
		194	DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP,
		195	DML_FAIL_NOT_DSC422_NATIVE,
		196	DML_FAIL_ODM_COMBINE4TO1,
		197	DML_FAIL_ENOUGH_WRITEBACK_UNITS,
		198	DML_FAIL_VIEWPORT_EXCEEDS_SURFACE,
		199	DML_FAIL_DYNAMIC_METADATA,
		200	DML_FAIL_FMT_BUFFER_EXCEEDED,
193	};	201	};
194		202
195	enum writeback_config {	203	enum writeback_config {

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h+1−0

@@ -68,6 +68,7 @@ struct dccg { · 67 unmodified lines
68	const struct dccg_funcs *funcs;	68	const struct dccg_funcs *funcs;
69	int pipe_dppclk_khz[MAX_PIPES];	69	int pipe_dppclk_khz[MAX_PIPES];
70	int ref_dppclk;	70	int ref_dppclk;
		71	bool dpp_clock_gated[MAX_PIPES];
71	//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */	72	//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
72	//int audio_dtbclk_khz;/* TODO needs to be removed */	73	//int audio_dtbclk_khz;/* TODO needs to be removed */
73	//int ref_dtbclk_khz;/* TODO needs to be removed */	74	//int ref_dtbclk_khz;/* TODO needs to be removed */

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h+32−0

@@ -114,6 +114,26 @@ struct update_visual_confirm_params { · 113 unmodified lines
114	int mpcc_id;	114	int mpcc_id;
115	};	115	};
116		116
		117	struct power_on_mpc_mem_pwr_params {
		118	struct mpc *mpc;
		119	int mpcc_id;
		120	bool power_on;
		121	};
		122
		123	struct set_output_csc_params {
		124	struct mpc *mpc;
		125	int opp_id;
		126	const uint16_t *regval;
		127	enum mpc_output_csc_mode ocsc_mode;
		128	};
		129
		130	struct set_ocsc_default_params {
		131	struct mpc *mpc;
		132	int opp_id;
		133	enum dc_color_space color_space;
		134	enum mpc_output_csc_mode ocsc_mode;
		135	};
		136
117	union block_sequence_params {	137	union block_sequence_params {
118	struct update_plane_addr_params update_plane_addr_params;	138	struct update_plane_addr_params update_plane_addr_params;
119	struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params;	139	struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params;
@@ -128,6 +148,9 @@ union block_sequence_params { · 8 unmodified lines
128	struct program_bias_and_scale_params program_bias_and_scale_params;	148	struct program_bias_and_scale_params program_bias_and_scale_params;
129	struct set_output_transfer_func_params set_output_transfer_func_params;	149	struct set_output_transfer_func_params set_output_transfer_func_params;
130	struct update_visual_confirm_params update_visual_confirm_params;	150	struct update_visual_confirm_params update_visual_confirm_params;
		151	struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params;
		152	struct set_output_csc_params set_output_csc_params;
		153	struct set_ocsc_default_params set_ocsc_default_params;
131	};	154	};
132		155
133	enum block_sequence_func {	156	enum block_sequence_func {
@@ -144,6 +167,9 @@ enum block_sequence_func { · 10 unmodified lines
144	DPP_PROGRAM_BIAS_AND_SCALE,	167	DPP_PROGRAM_BIAS_AND_SCALE,
145	DPP_SET_OUTPUT_TRANSFER_FUNC,	168	DPP_SET_OUTPUT_TRANSFER_FUNC,
146	MPC_UPDATE_VISUAL_CONFIRM,	169	MPC_UPDATE_VISUAL_CONFIRM,
		170	MPC_POWER_ON_MPC_MEM_PWR,
		171	MPC_SET_OUTPUT_CSC,
		172	MPC_SET_OCSC_DEFAULT,
147	};	173	};
148		174
149	struct block_sequence {	175	struct block_sequence {
@@ -439,4 +465,10 @@ void hwss_setup_dpp(union block_sequence_params *params); · 289 unmodified lines
439		465
440	void hwss_program_bias_and_scale(union block_sequence_params *params);	466	void hwss_program_bias_and_scale(union block_sequence_params *params);
441		467
		468	void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params);
		469
		470	void hwss_set_output_csc(union block_sequence_params *params);
		471
		472	void hwss_set_ocsc_default(union block_sequence_params *params);
		473
442	#endif /* __DC_HW_SEQUENCER_H__ */	474	#endif /* __DC_HW_SEQUENCER_H__ */

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h+1−1

@@ -156,7 +156,7 @@ struct hwseq_private_funcs { · 155 unmodified lines
156	void (program_mall_pipe_config)(struct dc dc, struct dc_state *context);	156	void (program_mall_pipe_config)(struct dc dc, struct dc_state *context);
157	void (update_force_pstate)(struct dc dc, struct dc_state *context);	157	void (update_force_pstate)(struct dc dc, struct dc_state *context);
158	void (update_mall_sel)(struct dc dc, struct dc_state *context);	158	void (update_mall_sel)(struct dc dc, struct dc_state *context);
159	unsigned int (calculate_dccg_k1_k2_values)(struct pipe_ctx pipe_ctx,	159	void (calculate_dccg_k1_k2_values)(struct pipe_ctx pipe_ctx,
160	unsigned int *k1_div,	160	unsigned int *k1_div,
161	unsigned int *k2_div);	161	unsigned int *k2_div);
162	void (set_pixels_per_cycle)(struct pipe_ctx pipe_ctx);	162	void (set_pixels_per_cycle)(struct pipe_ctx pipe_ctx);

drivers/gpu/drm/amd/display/dc/link/link_detection.c+5−0

 					(link->dpcd_caps.dongle_type !=
 							DISPLAY_DONGLE_DP_HDMI_CONVERTER))
 				converter_disable_audio = true;
+			/* limited link rate to HBR3 for DPIA until we implement USB4 V2 */
+			if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
+					link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
+				link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
 			break;
 		}

drivers/gpu/drm/amd/display/modules/freesync/freesync.c+9−2

 /*
- * Copyright 2016 Advanced Micro Devices, Inc.
+ * Copyright 2016-2023 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
 	unsigned int refresh_range = 0;
 	unsigned long long min_refresh_in_uhz = 0;
 	unsigned long long max_refresh_in_uhz = 0;
+	unsigned long long min_hardware_refresh_in_uhz = 0;
 	if (mod_freesync == NULL)
 		return;
 	nominal_field_rate_in_uhz =
 			mod_freesync_calc_nominal_field_rate(stream);
-	min_refresh_in_uhz = in_config->min_refresh_in_uhz;
+	if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
+		min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
+			(stream->timing.h_total * stream->ctx->dc->caps.max_v_total));
+	}
+	/* Limit minimum refresh rate to what can be supported by hardware */
+	min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ?
+		min_hardware_refresh_in_uhz : in_config->min_refresh_in_uhz;
 	max_refresh_in_uhz = in_config->max_refresh_in_uhz;
 	/* Full range may be larger than current video timing, so cap at nominal */

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c+14−4

@@ -431,7 +431,13 @@ static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) · 430 unmodified lines
431	{	431	{
432	struct atom_smc_dpm_info_v4_9 *smc_dpm_table;	432	struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
433	int index, ret;	433	int index, ret;
434	I2cControllerConfig_t *table_member;	434	PPTable_beige_goby_t *ppt_beige_goby;
		435	PPTable_t *ppt;
		436
		437	if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
		438	ppt_beige_goby = smu->smu_table.driver_pptable;
		439	else
		440	ppt = smu->smu_table.driver_pptable;
435		441
436	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,	442	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
437	smc_dpm_info);	443	smc_dpm_info);
@@ -440,9 +446,13 @@ static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) · 2 unmodified lines
440	(uint8_t **)&smc_dpm_table);	446	(uint8_t **)&smc_dpm_table);
441	if (ret)	447	if (ret)
442	return ret;	448	return ret;
443	GET_PPTABLE_MEMBER(I2cControllers, &table_member);	449
444	memcpy(table_member, smc_dpm_table->I2cControllers,	450	if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
445	sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));	451	smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,
		452	smc_dpm_table, I2cControllers);
		453	else
		454	smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,
		455	smc_dpm_table, I2cControllers);
446		456
447	return 0;	457	return 0;
448	}	458	}

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c+1−2

 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
 #include "smu_cmn.h"
 #include "amdgpu_ras.h"
-#include "umc_v8_10.h"
 /*
  * DO NOT use these for err/warn/info/debug messages.
 	ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
-	for (i = 0; i < UMC_V8_10_TOTAL_CHANNEL_NUM(adev); i++) {
+	for (i = 0; i < ARRAY_SIZE(ecc_table->EccInfo); i++) {
 		ecc_info_per_channel = &(eccinfo->ecc[i]);
 		ecc_info_per_channel->ce_count_lo_chip =
 				ecc_table->EccInfo[i].ce_count_lo_chip;

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c+76−4

@@ -831,6 +831,8 @@ static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu, · 830 unmodified lines
831	uint32_t max)	831	uint32_t max)
832	{	832	{
833	enum smu_message_type msg_set_min, msg_set_max;	833	enum smu_message_type msg_set_min, msg_set_max;
		834	uint32_t min_clk = min;
		835	uint32_t max_clk = max;
834	int ret = 0;	836	int ret = 0;
835		837
836	if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))	838	if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))
@@ -851,11 +853,16 @@ static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu, · 14 unmodified lines
851	return -EINVAL;	853	return -EINVAL;
852	}	854	}
853		855
854	ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);	856	if (clk_type == SMU_VCLK) {
		857	min_clk = min << SMU_13_VCLK_SHIFT;
		858	max_clk = max << SMU_13_VCLK_SHIFT;
		859	}
		860
		861	ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
855	if (ret)	862	if (ret)
856	goto out;	863	goto out;
857		864
858	ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);	865	ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
859	if (ret)	866	if (ret)
860	goto out;	867	goto out;
861		868
@@ -971,31 +978,79 @@ force_level_out: · 109 unmodified lines
971	return ret;	978	return ret;
972	}	979	}
973		980
		981	static int smu_v13_0_5_get_dpm_profile_freq(struct smu_context *smu,
		982	enum amd_dpm_forced_level level,
		983	enum smu_clk_type clk_type,
		984	uint32_t *min_clk,
		985	uint32_t *max_clk)
		986	{
		987	int ret = 0;
		988	uint32_t clk_limit = 0;
		989
		990	switch (clk_type) {
		991	case SMU_GFXCLK:
		992	case SMU_SCLK:
		993	clk_limit = SMU_13_0_5_UMD_PSTATE_GFXCLK;
		994	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
		995	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
		996	else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
		997	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
		998	break;
		999	case SMU_VCLK:
		1000	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
		1001	break;
		1002	case SMU_DCLK:
		1003	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
		1004	break;
		1005	default:
		1006	ret = -EINVAL;
		1007	break;
		1008	}
		1009	min_clk = max_clk = clk_limit;
		1010	return ret;
		1011	}
		1012
974	static int smu_v13_0_5_set_performance_level(struct smu_context *smu,	1013	static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
975	enum amd_dpm_forced_level level)	1014	enum amd_dpm_forced_level level)
976	{	1015	{
977	struct amdgpu_device *adev = smu->adev;	1016	struct amdgpu_device *adev = smu->adev;
978	uint32_t sclk_min = 0, sclk_max = 0;	1017	uint32_t sclk_min = 0, sclk_max = 0;
		1018	uint32_t vclk_min = 0, vclk_max = 0;
		1019	uint32_t dclk_min = 0, dclk_max = 0;
979	int ret = 0;	1020	int ret = 0;
980		1021
981	switch (level) {	1022	switch (level) {
982	case AMD_DPM_FORCED_LEVEL_HIGH:	1023	case AMD_DPM_FORCED_LEVEL_HIGH:
983	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);	1024	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
		1025	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
		1026	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
984	sclk_min = sclk_max;	1027	sclk_min = sclk_max;
		1028	vclk_min = vclk_max;
		1029	dclk_min = dclk_max;
985	break;	1030	break;
986	case AMD_DPM_FORCED_LEVEL_LOW:	1031	case AMD_DPM_FORCED_LEVEL_LOW:
987	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);	1032	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
		1033	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
		1034	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
988	sclk_max = sclk_min;	1035	sclk_max = sclk_min;
		1036	vclk_max = vclk_min;
		1037	dclk_max = dclk_min;
989	break;	1038	break;
990	case AMD_DPM_FORCED_LEVEL_AUTO:	1039	case AMD_DPM_FORCED_LEVEL_AUTO:
991	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);	1040	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
		1041	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
		1042	smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
992	break;	1043	break;
993	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:	1044	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
994	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:	1045	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
995	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
996	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:	1046	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
997	/* Temporarily do nothing since the optimal clocks haven't been provided yet */	1047	smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
		1048	smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
		1049	smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
998	break;	1050	break;
		1051	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
		1052	dev_err(adev->dev, "The performance level profile_min_mclk is not supported.");
		1053	return -EOPNOTSUPP;
999	case AMD_DPM_FORCED_LEVEL_MANUAL:	1054	case AMD_DPM_FORCED_LEVEL_MANUAL:
1000	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:	1055	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1001	return 0;	1056	return 0;
@@ -1016,6 +1071,23 @@ static int smu_v13_0_5_set_performance_level(struct smu_context *smu, · 14 unmodified lines
1016	smu->gfx_actual_soft_max_freq = sclk_max;	1071	smu->gfx_actual_soft_max_freq = sclk_max;
1017	}	1072	}
1018		1073
		1074	if (vclk_min && vclk_max) {
		1075	ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
		1076	SMU_VCLK,
		1077	vclk_min,
		1078	vclk_max);
		1079	if (ret)
		1080	return ret;
		1081	}
		1082
		1083	if (dclk_min && dclk_max) {
		1084	ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
		1085	SMU_DCLK,
		1086	dclk_min,
		1087	dclk_max);
		1088	if (ret)
		1089	return ret;
		1090	}
1019	return ret;	1091	return ret;
1020	}	1092	}
1021		1093

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h+1−1

@@ -24,6 +24,6 @@ · 23 unmodified lines
24	#define __SMU_V13_0_5_PPT_H__	24	#define __SMU_V13_0_5_PPT_H__
25		25
26	extern void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu);	26	extern void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu);
27	#define SMU_13_0_5_UMD_PSTATE_GFXCLK 1100	27	#define SMU_13_0_5_UMD_PSTATE_GFXCLK 700
28		28
29	#endif	29	#endif

drivers/gpu/drm/display/drm_dp_mst_topology.c+47−7

@@ -4053,17 +4053,28 @@ out: · 4052 unmodified lines
4053	}	4053	}
4054		4054
4055	/**	4055	/**
4056	* drm_dp_mst_hpd_irq() - MST hotplug IRQ notify	4056	* drm_dp_mst_hpd_irq_handle_event() - MST hotplug IRQ handle MST event
4057	* @mgr: manager to notify irq for.	4057	* @mgr: manager to notify irq for.
4058	* @esi: 4 bytes from SINK_COUNT_ESI	4058	* @esi: 4 bytes from SINK_COUNT_ESI
		4059	* @ack: 4 bytes used to ack events starting from SINK_COUNT_ESI
4059	* @handled: whether the hpd interrupt was consumed or not	4060	* @handled: whether the hpd interrupt was consumed or not
4060	*	4061	*
4061	* This should be called from the driver when it detects a short IRQ,	4062	* This should be called from the driver when it detects a HPD IRQ,
4062	* along with the value of the DEVICE_SERVICE_IRQ_VECTOR_ESI0. The	4063	* along with the value of the DEVICE_SERVICE_IRQ_VECTOR_ESI0. The
4063	* topology manager will process the sideband messages received as a result	4064	* topology manager will process the sideband messages received
4064	* of this.	4065	* as indicated in the DEVICE_SERVICE_IRQ_VECTOR_ESI0 and set the
		4066	* corresponding flags that Driver has to ack the DP receiver later.
		4067	*
		4068	* Note that driver shall also call
		4069	* drm_dp_mst_hpd_irq_send_new_request() if the 'handled' is set
		4070	* after calling this function, to try to kick off a new request in
		4071	* the queue if the previous message transaction is completed.
		4072	*
		4073	* See also:
		4074	* drm_dp_mst_hpd_irq_send_new_request()
4065	*/	4075	*/
4066	int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr mgr, u8 esi, bool *handled)	4076	int drm_dp_mst_hpd_irq_handle_event(struct drm_dp_mst_topology_mgr mgr, const u8 esi,
		4077	u8 ack, bool handled)
4067	{	4078	{
4068	int ret = 0;	4079	int ret = 0;
4069	int sc;	4080	int sc;
@@ -4078,18 +4089,47 @@ int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr mgr, u8 esi, bool *handl · 8 unmodified lines
4078	if (esi[1] & DP_DOWN_REP_MSG_RDY) {	4089	if (esi[1] & DP_DOWN_REP_MSG_RDY) {
4079	ret = drm_dp_mst_handle_down_rep(mgr);	4090	ret = drm_dp_mst_handle_down_rep(mgr);
4080	*handled = true;	4091	*handled = true;
		4092	ack[1] \|= DP_DOWN_REP_MSG_RDY;
4081	}	4093	}
4082		4094
4083	if (esi[1] & DP_UP_REQ_MSG_RDY) {	4095	if (esi[1] & DP_UP_REQ_MSG_RDY) {
4084	ret \|= drm_dp_mst_handle_up_req(mgr);	4096	ret \|= drm_dp_mst_handle_up_req(mgr);
4085	*handled = true;	4097	*handled = true;
		4098	ack[1] \|= DP_UP_REQ_MSG_RDY;
4086	}	4099	}
4087		4100
4088	drm_dp_mst_kick_tx(mgr);
4089	return ret;	4101	return ret;
4090	}	4102	}
4091	EXPORT_SYMBOL(drm_dp_mst_hpd_irq);	4103	EXPORT_SYMBOL(drm_dp_mst_hpd_irq_handle_event);
4092		4104
		4105	/**
		4106	* drm_dp_mst_hpd_irq_send_new_request() - MST hotplug IRQ kick off new request
		4107	* @mgr: manager to notify irq for.
		4108	*
		4109	* This should be called from the driver when mst irq event is handled
		4110	* and acked. Note that new down request should only be sent when
		4111	* previous message transaction is completed. Source is not supposed to generate
		4112	* interleaved message transactions.
		4113	*/
		4114	void drm_dp_mst_hpd_irq_send_new_request(struct drm_dp_mst_topology_mgr *mgr)
		4115	{
		4116	struct drm_dp_sideband_msg_tx *txmsg;
		4117	bool kick = true;
		4118
		4119	mutex_lock(&mgr->qlock);
		4120	txmsg = list_first_entry_or_null(&mgr->tx_msg_downq,
		4121	struct drm_dp_sideband_msg_tx, next);
		4122	/* If last transaction is not completed yet*/
		4123	if (!txmsg \|\|
		4124	txmsg->state == DRM_DP_SIDEBAND_TX_START_SEND \|\|
		4125	txmsg->state == DRM_DP_SIDEBAND_TX_SENT)
		4126	kick = false;
		4127	mutex_unlock(&mgr->qlock);
		4128
		4129	if (kick)
		4130	drm_dp_mst_kick_tx(mgr);
		4131	}
		4132	EXPORT_SYMBOL(drm_dp_mst_hpd_irq_send_new_request);
4093	/**	4133	/**
4094	* drm_dp_mst_detect_port() - get connection status for an MST port	4134	* drm_dp_mst_detect_port() - get connection status for an MST port
4095	* @connector: DRM connector for this port	4135	* @connector: DRM connector for this port

drivers/gpu/drm/i915/display/intel_dp.c+4−3

 {
 	bool handled = false;
-	drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
+	drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
-	if (handled)
-		ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
 	if (esi[1] & DP_CP_IRQ) {
 		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
 		if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
 			drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
+		if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
+			drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
 	}
 	return link_ok;

drivers/gpu/drm/nouveau/dispnv50/disp.c+8−4

@@ -1359,22 +1359,26 @@ nv50_mstm_service(struct nouveau_drm *drm, · 1358 unmodified lines
1359	u8 esi[8] = {};	1359	u8 esi[8] = {};
1360		1360
1361	while (handled) {	1361	while (handled) {
		1362	u8 ack[8] = {};
		1363
1362	rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);	1364	rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1363	if (rc != 8) {	1365	if (rc != 8) {
1364	ret = false;	1366	ret = false;
1365	break;	1367	break;
1366	}	1368	}
1367		1369
1368	drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);	1370	drm_dp_mst_hpd_irq_handle_event(&mstm->mgr, esi, ack, &handled);
1369	if (!handled)	1371	if (!handled)
1370	break;	1372	break;
1371		1373
1372	rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1],	1374	rc = drm_dp_dpcd_writeb(aux, DP_SINK_COUNT_ESI + 1, ack[1]);
1373	3);	1375
1374	if (rc != 3) {	1376	if (rc != 1) {
1375	ret = false;	1377	ret = false;
1376	break;	1378	break;
1377	}	1379	}
		1380
		1381	drm_dp_mst_hpd_irq_send_new_request(&mstm->mgr);
1378	}	1382	}
1379		1383
1380	if (!ret)	1384	if (!ret)

drivers/gpu/drm/radeon/radeon_acpi.h+9−0

@@ -453,4 +453,13 @@ struct acpi_bus_event; · 452 unmodified lines
453	* BYTE - number of active lanes	453	* BYTE - number of active lanes
454	*/	454	*/
455		455
		456	#if defined(CONFIG_VGA_SWITCHEROO)
		457	void radeon_register_atpx_handler(void);
		458	void radeon_unregister_atpx_handler(void);
		459	bool radeon_has_atpx_dgpu_power_cntl(void);
		460	bool radeon_is_atpx_hybrid(void);
		461	bool radeon_has_atpx(void);
		462	bool radeon_atpx_dgpu_req_power_for_displays(void);
		463	#endif
		464
456	#endif	465	#endif

drivers/gpu/drm/radeon/radeon_atpx_handler.c+1−1

@@ -147,7 +147,7 @@ static void radeon_atpx_parse_functions(struct radeon_atpx_functions *f, u32 mas · 146 unmodified lines
147	}	147	}
148		148
149	/**	149	/**
150	* radeon_atpx_validate_functions - validate ATPX functions	150	* radeon_atpx_validate() - validate ATPX functions
151	*	151	*
152	* @atpx: radeon atpx struct	152	* @atpx: radeon atpx struct
153	*	153	*

drivers/gpu/drm/radeon/radeon_fbdev.c+1−0

@@ -304,6 +304,7 @@ static void radeon_fbdev_client_unregister(struct drm_client_dev *client) · 303 unmodified lines
304		304
305	if (fb_helper->info) {	305	if (fb_helper->info) {
306	vga_switcheroo_client_fb_set(rdev->pdev, NULL);	306	vga_switcheroo_client_fb_set(rdev->pdev, NULL);
		307	drm_helper_force_disable_all(dev);
307	drm_fb_helper_unregister_info(fb_helper);	308	drm_fb_helper_unregister_info(fb_helper);
308	} else {	309	} else {
309	drm_client_release(&fb_helper->client);	310	drm_client_release(&fb_helper->client);

drivers/gpu/drm/scheduler/sched_entity.c+1−1

@@ -384,7 +384,7 @@ static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity) · 383 unmodified lines
384	}	384	}
385		385
386	s_fence = to_drm_sched_fence(fence);	386	s_fence = to_drm_sched_fence(fence);
387	if (s_fence && s_fence->sched == sched &&	387	if (!fence->error && s_fence && s_fence->sched == sched &&
388	!test_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &fence->flags)) {	388	!test_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &fence->flags)) {
389		389
390	/*	390	/*

include/drm/display/drm_dp_mst_helper.h+5−2

@@ -810,8 +810,11 @@ void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); · 809 unmodified lines
810	bool drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);	810	bool drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
811	int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state);	811	int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state);
812		812
813	int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr mgr, u8 esi, bool *handled);	813	int drm_dp_mst_hpd_irq_handle_event(struct drm_dp_mst_topology_mgr *mgr,
814		814	const u8 *esi,
		815	u8 *ack,
		816	bool *handled);
		817	void drm_dp_mst_hpd_irq_send_new_request(struct drm_dp_mst_topology_mgr *mgr);
815		818
816	int	819	int
817	drm_dp_mst_detect_port(struct drm_connector *connector,	820	drm_dp_mst_detect_port(struct drm_connector *connector,

include/uapi/linux/kfd_ioctl.h+11−2

  * - 1.11 - Add unified memory for ctx save/restore area
  * - 1.12 - Add DMA buf export ioctl
  * - 1.13 - Add debugger API
+ * - 1.14 - Update kfd_event_data
  */
 #define KFD_IOCTL_MAJOR_VERSION 1
-#define KFD_IOCTL_MINOR_VERSION 13
+#define KFD_IOCTL_MINOR_VERSION 14
 struct kfd_ioctl_get_version_args {
 	__u32 major_version;	/* from KFD */
 	__u32 gpu_id;
 };
+/* hsa signal event data */
+struct kfd_hsa_signal_event_data {
+	__u64 last_event_age;	/* to and from KFD */
+};
 /* Event data */
 struct kfd_event_data {
 	union {
+		/* From KFD */
 		struct kfd_hsa_memory_exception_data memory_exception_data;
 		struct kfd_hsa_hw_exception_data hw_exception_data;
-	};				/* From KFD */
+		/* To and From KFD */
+		struct kfd_hsa_signal_event_data signal_event_data;
+	};
 	__u64 kfd_event_data_ext;	/* pointer to an extension structure
 					   for future exception types */
 	__u32 event_id;		/* to KFD */

Merge tag 'amd-drm-next-6.5-2023-06-16' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

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