lael-labs/linux

arch/mips/Kconfig+6−0

 	select SYS_HAS_EARLY_PRINTK
 	select HAVE_PCI
 	select IRQ_MIPS_CPU
+	select IRQ_DOMAIN_HIERARCHY
 	select NR_CPUS_DEFAULT_64
+	select PCI_DRIVERS_GENERIC
+	select PCI_XTALK_BRIDGE
 	select SYS_HAS_CPU_R10000
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
 config PCI_GT64XXX_PCI0
 	bool
+config PCI_XTALK_BRIDGE
+	bool
 config NO_EXCEPT_FILL
 	bool

arch/mips/alchemy/common/platform.c+14−8

 }
-/* The dmamask must be set for OHCI/EHCI to work */
+static u64 alchemy_all_dmamask = DMA_BIT_MASK(32);
-static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32);
-static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32);
 /* Power on callback for the ehci platform driver */
 static int alchemy_ehci_power_on(struct platform_device *pdev)
 	res[1].flags = IORESOURCE_IRQ;
 	pdev->name = "ohci-platform";
 	pdev->id = 0;
-	pdev->dev.dma_mask = &alchemy_ohci_dmamask;
+	pdev->dev.dma_mask = &alchemy_all_dmamask;
 	pdev->dev.platform_data = &alchemy_ohci_pdata;
 	if (platform_device_register(pdev))
 		res[1].flags = IORESOURCE_IRQ;
 		pdev->name = "ehci-platform";
 		pdev->id = 0;
-		pdev->dev.dma_mask = &alchemy_ehci_dmamask;
+		pdev->dev.dma_mask = &alchemy_all_dmamask;
 		pdev->dev.platform_data = &alchemy_ehci_pdata;
 		if (platform_device_register(pdev))
 		res[1].flags = IORESOURCE_IRQ;
 		pdev->name = "ohci-platform";
 		pdev->id = 1;
-		pdev->dev.dma_mask = &alchemy_ohci_dmamask;
+		pdev->dev.dma_mask = &alchemy_all_dmamask;
 		pdev->dev.platform_data = &alchemy_ohci_pdata;
 		if (platform_device_register(pdev))
 	.name		= "au1000-eth",
 	.id		= 0,
 	.num_resources	= MAC_RES_COUNT,
-	.dev.platform_data = &au1xxx_eth0_platform_data,
+	.dev = {
+		.dma_mask               = &alchemy_all_dmamask,
+		.coherent_dma_mask      = DMA_BIT_MASK(32),
+		.platform_data          = &au1xxx_eth0_platform_data,
+	},
 };
 static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
 	.name		= "au1000-eth",
 	.id		= 1,
 	.num_resources	= MAC_RES_COUNT,
-	.dev.platform_data = &au1xxx_eth1_platform_data,
+	.dev = {
+		.dma_mask               = &alchemy_all_dmamask,
+		.coherent_dma_mask      = DMA_BIT_MASK(32),
+		.platform_data          = &au1xxx_eth1_platform_data,
+	},
 };
 void __init au1xxx_override_eth_cfg(unsigned int port,

arch/mips/generic/init.c+2−2

@@ -43,14 +43,14 @@ void __init *plat_get_fdt(void) · 42 unmodified lines
43	/* Already set up */	43	/* Already set up */
44	return (void *)fdt;	44	return (void *)fdt;
45		45
46	if ((fw_arg0 == -2) && !fdt_check_header((void *)fw_arg1)) {	46	if ((fw_arg0 == -2) && !fdt_check_header((void *)fw_passed_dtb)) {
47	/*	47	/*
48	* We booted using the UHI boot protocol, so we have been	48	* We booted using the UHI boot protocol, so we have been
49	* provided with the appropriate device tree for the board.	49	* provided with the appropriate device tree for the board.
50	* Make use of it & search for any machine struct based upon	50	* Make use of it & search for any machine struct based upon
51	* the root compatible string.	51	* the root compatible string.
52	*/	52	*/
53	fdt = (void *)fw_arg1;	53	fdt = (void *)fw_passed_dtb;
54		54
55	for_each_mips_machine(check_mach) {	55	for_each_mips_machine(check_mach) {
56	match = mips_machine_is_compatible(check_mach, fdt);	56	match = mips_machine_is_compatible(check_mach, fdt);

arch/mips/include/asm/mach-ip27/topology.h+1−10

 #include <asm/mmzone.h>
 struct cpuinfo_ip27 {
-//	cpuid_t		p_cpuid;	/* PROM assigned cpuid */
 	cnodeid_t	p_nodeid;	/* my node ID in compact-id-space */
 	nasid_t		p_nasid;	/* my node ID in numa-as-id-space */
 	unsigned char	p_slice;	/* Physical position on node board */
-#if 0
-	unsigned long		loops_per_sec;
-	unsigned long		ipi_count;
-	unsigned long		irq_attempt[NR_IRQS];
-	unsigned long		smp_local_irq_count;
-	unsigned long		prof_multiplier;
-	unsigned long		prof_counter;
-#endif
 };
 extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
 struct pci_bus;
 extern int pcibus_to_node(struct pci_bus *);
-#define cpumask_of_pcibus(bus)	(cpu_online_mask)
+#define cpumask_of_pcibus(bus)	(cpumask_of_node(pcibus_to_node(bus)))
 extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];

arch/mips/include/asm/pci/bridge.h+4−10

 #define PCI64_ATTR_RMF_SHFT	48
 struct bridge_controller {
-	struct pci_controller	pc;
-	struct resource		mem;
-	struct resource		io;
 	struct resource		busn;
 	struct bridge_regs	*base;
-	nasid_t			nasid;
+	unsigned long		baddr;
-	unsigned int		widget_id;
+	unsigned long		intr_addr;
-	u64			baddr;
+	struct irq_domain	*domain;
 	unsigned int		pci_int[8];
+	nasid_t			nasid;
 };
 #define BRIDGE_CONTROLLER(bus) \
 #define bridge_clr(bc, reg, val)	\
 	__raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)
-extern int request_bridge_irq(struct bridge_controller *bc, int pin);
-extern struct pci_ops bridge_pci_ops;
 #endif /* _ASM_PCI_BRIDGE_H */

arch/mips/include/asm/sn/irq_alloc.h+11−0

@@ -0,0 +1,11 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	#ifndef __ASM_SN_IRQ_ALLOC_H
	3	#define __ASM_SN_IRQ_ALLOC_H
	4
	5	struct irq_alloc_info {
	6	void *ctrl;
	7	nasid_t nasid;
	8	int pin;
	9	};
	10
	11	#endif /* __ASM_SN_IRQ_ALLOC_H */

arch/mips/include/asm/xtalk/xtalk.h+0−9

@@ -47,15 +47,6 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t; · 46 unmodified lines
47	#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))	47	#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
48	#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) \| ((o)&XIO_ADDR_BITS))	48	#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) \| ((o)&XIO_ADDR_BITS))
49		49
50	#ifdef CONFIG_PCI
51	extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
52	#else
53	static inline int bridge_probe(nasid_t nasid, int widget, int masterwid)
54	{
55	return 0;
56	}
57	#endif
58
59	#endif /* !__ASSEMBLY__ */	50	#endif /* !__ASSEMBLY__ */
60		51
61	#endif /* _ASM_XTALK_XTALK_H */	52	#endif /* _ASM_XTALK_XTALK_H */

arch/mips/kernel/cpu-probe.c+8−0

@@ -1973,6 +1973,14 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) · 1972 unmodified lines
1973	panic("Unknown Ingenic Processor ID!");	1973	panic("Unknown Ingenic Processor ID!");
1974	break;	1974	break;
1975	}	1975	}
		1976
		1977	/*
		1978	* The config0 register in the Xburst CPUs with a processor ID of
		1979	* PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
		1980	* but they don't actually support this ISA.
		1981	*/
		1982	if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0)
		1983	c->isa_level &= ~MIPS_CPU_ISA_M32R2;
1976	}	1984	}
1977		1985
1978	static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)	1986	static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)

arch/mips/kernel/perf_event_mipsxx.c+3−18

 	#define CNTR_EVEN	0x55555555
 	#define CNTR_ODD	0xaaaaaaaa
 	#define CNTR_ALL	0xffffffff
-#ifdef CONFIG_MIPS_MT_SMP
 	enum {
 		T  = 0,
 		V  = 1,
 		P  = 2,
 	} range;
-#else
-	#define T
-	#define V
-	#define P
-#endif
 };
 static struct mips_perf_event raw_event;
 {
 	struct perf_event *event = container_of(evt, struct perf_event, hw);
 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
-#ifdef CONFIG_MIPS_MT_SMP
 	unsigned int range = evt->event_base >> 24;
-#endif /* CONFIG_MIPS_MT_SMP */
 	WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 		/* Make sure interrupt enabled. */
 		MIPS_PERFCTRL_IE;
-#ifdef CONFIG_CPU_BMIPS5000
+	if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) {
-	{
 		/* enable the counter for the calling thread */
 		cpuc->saved_ctrl[idx] |=
 			(1 << (12 + vpe_id())) | BRCM_PERFCTRL_TC;
-	}
+	} else if (IS_ENABLED(CONFIG_MIPS_MT_SMP) && range > V) {
-#else
-#ifdef CONFIG_MIPS_MT_SMP
-	if (range > V) {
 		/* The counter is processor wide. Set it up to count all TCs. */
 		pr_debug("Enabling perf counter for all TCs\n");
 		cpuc->saved_ctrl[idx] |= M_TC_EN_ALL;
-	} else
+	} else {
-#endif /* CONFIG_MIPS_MT_SMP */
-	{
 		unsigned int cpu, ctrl;
 		/*
 		cpuc->saved_ctrl[idx] |= ctrl;
 		pr_debug("Enabling perf counter for CPU%d\n", cpu);
 	}
-#endif /* CONFIG_CPU_BMIPS5000 */
 	/*
 	 * We do not actually let the counter run. Leave it until start().
 	 */

arch/mips/pci/Makefile+2−1

 obj-$(CONFIG_SOC_AR71XX)	+= pci-ar71xx.o
 obj-$(CONFIG_PCI_AR724X)	+= pci-ar724x.o
 obj-$(CONFIG_MIPS_PCI_VIRTIO)	+= pci-virtio-guest.o
+obj-$(CONFIG_PCI_XTALK_BRIDGE)	+= pci-xtalk-bridge.o
 #
 # These are still pretty much in the old state, watch, go blind.
 #
 obj-$(CONFIG_PMC_MSP7120_GW)	+= fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)	+= fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_FPGA)	+= fixup-pmcmsp.o ops-pmcmsp.o
-obj-$(CONFIG_SGI_IP27)		+= ops-bridge.o pci-ip27.o
+obj-$(CONFIG_SGI_IP27)		+= pci-ip27.o
 obj-$(CONFIG_SGI_IP32)		+= fixup-ip32.o ops-mace.o pci-ip32.o
 obj-$(CONFIG_SIBYTE_SB1250)	+= fixup-sb1250.o pci-sb1250.o
 obj-$(CONFIG_SIBYTE_BCM112X)	+= fixup-sb1250.o pci-sb1250.o

arch/mips/pci/ops-bridge.c+0−302

@@ -1,302 +0,0 @@
1	/*
2	* This file is subject to the terms and conditions of the GNU General Public
3	* License. See the file "COPYING" in the main directory of this archive
4	* for more details.
5	*
6	* Copyright (C) 1999, 2000, 04, 06 Ralf Baechle (ralf@linux-mips.org)
7	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8	*/
9	#include <linux/pci.h>
10	#include <asm/paccess.h>
11	#include <asm/pci/bridge.h>
12	#include <asm/sn/arch.h>
13	#include <asm/sn/intr.h>
14	#include <asm/sn/sn0/hub.h>
15
16	/*
17	* Most of the IOC3 PCI config register aren't present
18	* we emulate what is needed for a normal PCI enumeration
19	*/
20	static u32 emulate_ioc3_cfg(int where, int size)
21	{
22	if (size == 1 && where == 0x3d)
23	return 0x01;
24	else if (size == 2 && where == 0x3c)
25	return 0x0100;
26	else if (size == 4 && where == 0x3c)
27	return 0x00000100;
28
29	return 0;
30	}
31
32	/*
33	* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
34	* not really documented, so right now I can't write code which uses it.
35	* Therefore we use type 0 accesses for now even though they won't work
36	* correctly for PCI-to-PCI bridges.
37	*
38	* The function is complicated by the ultimate brokenness of the IOC3 chip
39	* which is used in SGI systems. The IOC3 can only handle 32-bit PCI
40	* accesses and does only decode parts of it's address space.
41	*/
42
43	static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
44	int where, int size, u32 * value)
45	{
46	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
47	struct bridge_regs *bridge = bc->base;
48	int slot = PCI_SLOT(devfn);
49	int fn = PCI_FUNC(devfn);
50	volatile void *addr;
51	u32 cf, shift, mask;
52	int res;
53
54	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
55	if (get_dbe(cf, (u32 *) addr))
56	return PCIBIOS_DEVICE_NOT_FOUND;
57
58	/*
59	* IOC3 is broken beyond belief ... Don't even give the
60	* generic PCI code a chance to look at it for real ...
61	*/
62	if (cf == (PCI_VENDOR_ID_SGI \| (PCI_DEVICE_ID_SGI_IOC3 << 16)))
63	goto is_ioc3;
64
65	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
66
67	if (size == 1)
68	res = get_dbe(value, (u8 ) addr);
69	else if (size == 2)
70	res = get_dbe(value, (u16 ) addr);
71	else
72	res = get_dbe(value, (u32 ) addr);
73
74	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
75
76	is_ioc3:
77
78	/*
79	* IOC3 special handling
80	*/
81	if ((where >= 0x14 && where < 0x40) \|\| (where >= 0x48)) {
82	*value = emulate_ioc3_cfg(where, size);
83	return PCIBIOS_SUCCESSFUL;
84	}
85
86	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
87
88	if (get_dbe(cf, (u32 *) addr))
89	return PCIBIOS_DEVICE_NOT_FOUND;
90
91	shift = ((where & 3) << 3);
92	mask = (0xffffffffU >> ((4 - size) << 3));
93	*value = (cf >> shift) & mask;
94
95	return PCIBIOS_SUCCESSFUL;
96	}
97
98	static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
99	int where, int size, u32 * value)
100	{
101	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
102	struct bridge_regs *bridge = bc->base;
103	int busno = bus->number;
104	int slot = PCI_SLOT(devfn);
105	int fn = PCI_FUNC(devfn);
106	volatile void *addr;
107	u32 cf, shift, mask;
108	int res;
109
110	bridge_write(bc, b_pci_cfg, (busno << 16) \| (slot << 11));
111	addr = &bridge->b_type1_cfg.c[(fn << 8) \| PCI_VENDOR_ID];
112	if (get_dbe(cf, (u32 *) addr))
113	return PCIBIOS_DEVICE_NOT_FOUND;
114
115	/*
116	* IOC3 is broken beyond belief ... Don't even give the
117	* generic PCI code a chance to look at it for real ...
118	*/
119	if (cf == (PCI_VENDOR_ID_SGI \| (PCI_DEVICE_ID_SGI_IOC3 << 16)))
120	goto is_ioc3;
121
122	bridge_write(bc, b_pci_cfg, (busno << 16) \| (slot << 11));
123	addr = &bridge->b_type1_cfg.c[(fn << 8) \| (where ^ (4 - size))];
124
125	if (size == 1)
126	res = get_dbe(value, (u8 ) addr);
127	else if (size == 2)
128	res = get_dbe(value, (u16 ) addr);
129	else
130	res = get_dbe(value, (u32 ) addr);
131
132	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
133
134	is_ioc3:
135
136	/*
137	* IOC3 special handling
138	*/
139	if ((where >= 0x14 && where < 0x40) \|\| (where >= 0x48)) {
140	*value = emulate_ioc3_cfg(where, size);
141	return PCIBIOS_SUCCESSFUL;
142	}
143
144	bridge_write(bc, b_pci_cfg, (busno << 16) \| (slot << 11));
145	addr = &bridge->b_type1_cfg.c[(fn << 8) \| where];
146
147	if (get_dbe(cf, (u32 *) addr))
148	return PCIBIOS_DEVICE_NOT_FOUND;
149
150	shift = ((where & 3) << 3);
151	mask = (0xffffffffU >> ((4 - size) << 3));
152	*value = (cf >> shift) & mask;
153
154	return PCIBIOS_SUCCESSFUL;
155	}
156
157	static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
158	int where, int size, u32 * value)
159	{
160	if (!pci_is_root_bus(bus))
161	return pci_conf1_read_config(bus, devfn, where, size, value);
162
163	return pci_conf0_read_config(bus, devfn, where, size, value);
164	}
165
166	static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
167	int where, int size, u32 value)
168	{
169	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
170	struct bridge_regs *bridge = bc->base;
171	int slot = PCI_SLOT(devfn);
172	int fn = PCI_FUNC(devfn);
173	volatile void *addr;
174	u32 cf, shift, mask, smask;
175	int res;
176
177	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
178	if (get_dbe(cf, (u32 *) addr))
179	return PCIBIOS_DEVICE_NOT_FOUND;
180
181	/*
182	* IOC3 is broken beyond belief ... Don't even give the
183	* generic PCI code a chance to look at it for real ...
184	*/
185	if (cf == (PCI_VENDOR_ID_SGI \| (PCI_DEVICE_ID_SGI_IOC3 << 16)))
186	goto is_ioc3;
187
188	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
189
190	if (size == 1) {
191	res = put_dbe(value, (u8 *) addr);
192	} else if (size == 2) {
193	res = put_dbe(value, (u16 *) addr);
194	} else {
195	res = put_dbe(value, (u32 *) addr);
196	}
197
198	if (res)
199	return PCIBIOS_DEVICE_NOT_FOUND;
200
201	return PCIBIOS_SUCCESSFUL;
202
203	is_ioc3:
204
205	/*
206	* IOC3 special handling
207	*/
208	if ((where >= 0x14 && where < 0x40) \|\| (where >= 0x48))
209	return PCIBIOS_SUCCESSFUL;
210
211	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
212
213	if (get_dbe(cf, (u32 *) addr))
214	return PCIBIOS_DEVICE_NOT_FOUND;
215
216	shift = ((where & 3) << 3);
217	mask = (0xffffffffU >> ((4 - size) << 3));
218	smask = mask << shift;
219
220	cf = (cf & ~smask) \| ((value & mask) << shift);
221	if (put_dbe(cf, (u32 *) addr))
222	return PCIBIOS_DEVICE_NOT_FOUND;
223
224	return PCIBIOS_SUCCESSFUL;
225	}
226
227	static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
228	int where, int size, u32 value)
229	{
230	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
231	struct bridge_regs *bridge = bc->base;
232	int slot = PCI_SLOT(devfn);
233	int fn = PCI_FUNC(devfn);
234	int busno = bus->number;
235	volatile void *addr;
236	u32 cf, shift, mask, smask;
237	int res;
238
239	bridge_write(bc, b_pci_cfg, (busno << 16) \| (slot << 11));
240	addr = &bridge->b_type1_cfg.c[(fn << 8) \| PCI_VENDOR_ID];
241	if (get_dbe(cf, (u32 *) addr))
242	return PCIBIOS_DEVICE_NOT_FOUND;
243
244	/*
245	* IOC3 is broken beyond belief ... Don't even give the
246	* generic PCI code a chance to look at it for real ...
247	*/
248	if (cf == (PCI_VENDOR_ID_SGI \| (PCI_DEVICE_ID_SGI_IOC3 << 16)))
249	goto is_ioc3;
250
251	addr = &bridge->b_type1_cfg.c[(fn << 8) \| (where ^ (4 - size))];
252
253	if (size == 1) {
254	res = put_dbe(value, (u8 *) addr);
255	} else if (size == 2) {
256	res = put_dbe(value, (u16 *) addr);
257	} else {
258	res = put_dbe(value, (u32 *) addr);
259	}
260
261	if (res)
262	return PCIBIOS_DEVICE_NOT_FOUND;
263
264	return PCIBIOS_SUCCESSFUL;
265
266	is_ioc3:
267
268	/*
269	* IOC3 special handling
270	*/
271	if ((where >= 0x14 && where < 0x40) \|\| (where >= 0x48))
272	return PCIBIOS_SUCCESSFUL;
273
274	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
275
276	if (get_dbe(cf, (u32 *) addr))
277	return PCIBIOS_DEVICE_NOT_FOUND;
278
279	shift = ((where & 3) << 3);
280	mask = (0xffffffffU >> ((4 - size) << 3));
281	smask = mask << shift;
282
283	cf = (cf & ~smask) \| ((value & mask) << shift);
284	if (put_dbe(cf, (u32 *) addr))
285	return PCIBIOS_DEVICE_NOT_FOUND;
286
287	return PCIBIOS_SUCCESSFUL;
288	}
289
290	static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
291	int where, int size, u32 value)
292	{
293	if (!pci_is_root_bus(bus))
294	return pci_conf1_write_config(bus, devfn, where, size, value);
295
296	return pci_conf0_write_config(bus, devfn, where, size, value);
297	}
298
299	struct pci_ops bridge_pci_ops = {
300	.read = pci_read_config,
301	.write = pci_write_config,
302	};

arch/mips/pci/pci-ip27.c+0−181

@@ -7,162 +7,7 @@ · 6 unmodified lines
7	* Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)	7	* Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
8	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.	8	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9	*/	9	*/
10	#include <linux/kernel.h>
11	#include <linux/export.h>
12	#include <linux/pci.h>
13	#include <linux/smp.h>
14	#include <linux/dma-direct.h>
15	#include <asm/sn/arch.h>
16	#include <asm/pci/bridge.h>	10	#include <asm/pci/bridge.h>
17	#include <asm/paccess.h>
18	#include <asm/sn/intr.h>
19	#include <asm/sn/sn0/hub.h>
20
21	/*
22	* Max #PCI busses we can handle; ie, max #PCI bridges.
23	*/
24	#define MAX_PCI_BUSSES 40
25
26	/*
27	* XXX: No kmalloc available when we do our crosstalk scan,
28	* we should try to move it later in the boot process.
29	*/
30	static struct bridge_controller bridges[MAX_PCI_BUSSES];
31
32	extern struct pci_ops bridge_pci_ops;
33
34	int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
35	{
36	unsigned long offset = NODE_OFFSET(nasid);
37	struct bridge_controller *bc;
38	static int num_bridges = 0;
39	int slot;
40
41	pci_set_flags(PCI_PROBE_ONLY);
42
43	printk("a bridge\n");
44
45	/* XXX: kludge alert.. */
46	if (!num_bridges)
47	ioport_resource.end = ~0UL;
48
49	bc = &bridges[num_bridges];
50
51	bc->pc.pci_ops = &bridge_pci_ops;
52	bc->pc.mem_resource = &bc->mem;
53	bc->pc.io_resource = &bc->io;
54
55	bc->pc.index = num_bridges;
56
57	bc->mem.name = "Bridge PCI MEM";
58	bc->pc.mem_offset = offset;
59	bc->mem.start = 0;
60	bc->mem.end = ~0UL;
61	bc->mem.flags = IORESOURCE_MEM;
62
63	bc->io.name = "Bridge IO MEM";
64	bc->pc.io_offset = offset;
65	bc->io.start = 0UL;
66	bc->io.end = ~0UL;
67	bc->io.flags = IORESOURCE_IO;
68
69	bc->widget_id = widget_id;
70	bc->nasid = nasid;
71
72	bc->baddr = (u64)masterwid << 60 \| PCI64_ATTR_BAR;
73
74	/*
75	* point to this bridge
76	*/
77	bc->base = (struct bridge_regs *)RAW_NODE_SWIN_BASE(nasid, widget_id);
78
79	/*
80	* Clear all pending interrupts.
81	*/
82	bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
83
84	/*
85	* Until otherwise set up, assume all interrupts are from slot 0
86	*/
87	bridge_write(bc, b_int_device, 0x0);
88
89	/*
90	* swap pio's to pci mem and io space (big windows)
91	*/
92	bridge_set(bc, b_wid_control, BRIDGE_CTRL_IO_SWAP \|
93	BRIDGE_CTRL_MEM_SWAP);
94	#ifdef CONFIG_PAGE_SIZE_4KB
95	bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
96	#else /* 16kB or larger */
97	bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
98	#endif
99
100	/*
101	* Hmm... IRIX sets additional bits in the address which
102	* are documented as reserved in the bridge docs.
103	*/
104	bridge_write(bc, b_wid_int_upper, 0x8000 \| (masterwid << 16));
105	bridge_write(bc, b_wid_int_lower, 0x01800090); /* PI_INT_PEND_MOD off*/
106	bridge_write(bc, b_dir_map, (masterwid << 20)); /* DMA */
107	bridge_write(bc, b_int_enable, 0);
108
109	for (slot = 0; slot < 8; slot ++) {
110	bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
111	bc->pci_int[slot] = -1;
112	}
113	bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */
114
115	register_pci_controller(&bc->pc);
116
117	num_bridges++;
118
119	return 0;
120	}
121
122	/*
123	* All observed requests have pin == 1. We could have a global here, that
124	* gets incremented and returned every time - unfortunately, pci_map_irq
125	* may be called on the same device over and over, and need to return the
126	* same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
127	*
128	* A given PCI device, in general, should be able to intr any of the cpus
129	* on any one of the hubs connected to its xbow.
130	*/
131	int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
132	{
133	return 0;
134	}
135
136	static inline struct pci_dev bridge_root_dev(struct pci_dev dev)
137	{
138	while (dev->bus->parent) {
139	/* Move up the chain of bridges. */
140	dev = dev->bus->self;
141	}
142
143	return dev;
144	}
145
146	/* Do platform specific device initialization at pci_enable_device() time */
147	int pcibios_plat_dev_init(struct pci_dev *dev)
148	{
149	struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
150	struct pci_dev *rdev = bridge_root_dev(dev);
151	int slot = PCI_SLOT(rdev->devfn);
152	int irq;
153
154	irq = bc->pci_int[slot];
155	if (irq == -1) {
156	irq = request_bridge_irq(bc, slot);
157	if (irq < 0)
158	return irq;
159
160	bc->pci_int[slot] = irq;
161	}
162	dev->irq = irq;
163
164	return 0;
165	}
166		11
167	dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)	12	dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
168	{	13	{
@@ -177,29 +22,6 @@ phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr) · 8 unmodified lines
177	return dma_addr & ~(0xffUL << 56);	22	return dma_addr & ~(0xffUL << 56);
178	}	23	}
179		24
180	/*
181	* Device might live on a subordinate PCI bus. XXX Walk up the chain of buses
182	* to find the slot number in sense of the bridge device register.
183	* XXX This also means multiple devices might rely on conflicting bridge
184	* settings.
185	*/
186
187	static inline void pci_disable_swapping(struct pci_dev *dev)
188	{
189	struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
190	struct bridge_regs *bridge = bc->base;
191	int slot = PCI_SLOT(dev->devfn);
192
193	/* Turn off byte swapping */
194	bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR;
195	bridge->b_widget.w_tflush; /* Flush */
196	}
197
198	static void pci_fixup_ioc3(struct pci_dev *d)
199	{
200	pci_disable_swapping(d);
201	}
202
203	#ifdef CONFIG_NUMA	25	#ifdef CONFIG_NUMA
204	int pcibus_to_node(struct pci_bus *bus)	26	int pcibus_to_node(struct pci_bus *bus)
205	{	27	{
@@ -209,6 +31,3 @@ int pcibus_to_node(struct pci_bus *bus) · 3 unmodified lines
209	}	31	}
210	EXPORT_SYMBOL(pcibus_to_node);	32	EXPORT_SYMBOL(pcibus_to_node);
211	#endif /* CONFIG_NUMA */	33	#endif /* CONFIG_NUMA */
212
213	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
214	pci_fixup_ioc3);

arch/mips/pci/pci-xtalk-bridge.c+610−0

@@ -0,0 +1,610 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
	4	* Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
	5	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
	6	*/
	7	#include <linux/kernel.h>
	8	#include <linux/export.h>
	9	#include <linux/pci.h>
	10	#include <linux/smp.h>
	11	#include <linux/dma-direct.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/platform_data/xtalk-bridge.h>
	14
	15	#include <asm/pci/bridge.h>
	16	#include <asm/paccess.h>
	17	#include <asm/sn/irq_alloc.h>
	18
	19	/*
	20	* Most of the IOC3 PCI config register aren't present
	21	* we emulate what is needed for a normal PCI enumeration
	22	*/
	23	static u32 emulate_ioc3_cfg(int where, int size)
	24	{
	25	if (size == 1 && where == 0x3d)
	26	return 0x01;
	27	else if (size == 2 && where == 0x3c)
	28	return 0x0100;
	29	else if (size == 4 && where == 0x3c)
	30	return 0x00000100;
	31
	32	return 0;
	33	}
	34
	35	static void bridge_disable_swapping(struct pci_dev *dev)
	36	{
	37	struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
	38	int slot = PCI_SLOT(dev->devfn);
	39
	40	/* Turn off byte swapping */
	41	bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
	42	bridge_read(bc, b_widget.w_tflush); /* Flush */
	43	}
	44
	45	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
	46	bridge_disable_swapping);
	47
	48
	49	/*
	50	* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
	51	* not really documented, so right now I can't write code which uses it.
	52	* Therefore we use type 0 accesses for now even though they won't work
	53	* correctly for PCI-to-PCI bridges.
	54	*
	55	* The function is complicated by the ultimate brokenness of the IOC3 chip
	56	* which is used in SGI systems. The IOC3 can only handle 32-bit PCI
	57	* accesses and does only decode parts of it's address space.
	58	*/
	59	static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
	60	int where, int size, u32 *value)
	61	{
	62	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
	63	struct bridge_regs *bridge = bc->base;
	64	int slot = PCI_SLOT(devfn);
	65	int fn = PCI_FUNC(devfn);
	66	void *addr;
	67	u32 cf, shift, mask;
	68	int res;
	69
	70	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
	71	if (get_dbe(cf, (u32 *)addr))
	72	return PCIBIOS_DEVICE_NOT_FOUND;
	73
	74	/*
	75	* IOC3 is broken beyond belief ... Don't even give the
	76	* generic PCI code a chance to look at it for real ...
	77	*/
	78	if (cf == (PCI_VENDOR_ID_SGI \| (PCI_DEVICE_ID_SGI_IOC3 << 16)))
	79	goto is_ioc3;
	80
	81	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
	82
	83	if (size == 1)
	84	res = get_dbe(value, (u8 )addr);
	85	else if (size == 2)
	86	res = get_dbe(value, (u16 )addr);
	87	else
	88	res = get_dbe(value, (u32 )addr);
	89
	90	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
	91
	92	is_ioc3:
	93
	94	/*
	95	* IOC3 special handling
	96	*/
	97	if ((where >= 0x14 && where < 0x40) \|\| (where >= 0x48)) {
	98	*value = emulate_ioc3_cfg(where, size);
	99	return PCIBIOS_SUCCESSFUL;
	100	}
	101
	102	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
	103	if (get_dbe(cf, (u32 *)addr))
	104	return PCIBIOS_DEVICE_NOT_FOUND;
	105
	106	shift = ((where & 3) << 3);
	107	mask = (0xffffffffU >> ((4 - size) << 3));
	108	*value = (cf >> shift) & mask;
	109
	110	return PCIBIOS_SUCCESSFUL;
	111	}
	112
	113	static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
	114	int where, int size, u32 *value)
	115	{
	116	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
	117	struct bridge_regs *bridge = bc->base;
	118	int busno = bus->number;
	119	int slot = PCI_SLOT(devfn);
	120	int fn = PCI_FUNC(devfn);
	121	void *addr;
	122	u32 cf, shift, mask;
	123	int res;
	124
	125	bridge_write(bc, b_pci_cfg, (busno << 16) \| (slot << 11));
	126	addr = &bridge->b_type1_cfg.c[(fn << 8) \| PCI_VENDOR_ID];
	127	if (get_dbe(cf, (u32 *)addr))
	128	return PCIBIOS_DEVICE_NOT_FOUND;
	129
	130	/*
	131	* IOC3 is broken beyond belief ... Don't even give the
	132	* generic PCI code a chance to look at it for real ...
	133	*/
	134	if (cf == (PCI_VENDOR_ID_SGI \| (PCI_DEVICE_ID_SGI_IOC3 << 16)))
	135	goto is_ioc3;
	136
	137	addr = &bridge->b_type1_cfg.c[(fn << 8) \| (where ^ (4 - size))];
	138
	139	if (size == 1)
	140	res = get_dbe(value, (u8 )addr);
	141	else if (size == 2)
	142	res = get_dbe(value, (u16 )addr);
	143	else
	144	res = get_dbe(value, (u32 )addr);
	145
	146	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
	147
	148	is_ioc3:
	149
	150	/*
	151	* IOC3 special handling
	152	*/
	153	if ((where >= 0x14 && where < 0x40) \|\| (where >= 0x48)) {
	154	*value = emulate_ioc3_cfg(where, size);
	155	return PCIBIOS_SUCCESSFUL;
	156	}
	157
	158	addr = &bridge->b_type1_cfg.c[(fn << 8) \| where];
	159	if (get_dbe(cf, (u32 *)addr))
	160	return PCIBIOS_DEVICE_NOT_FOUND;
	161
	162	shift = ((where & 3) << 3);
	163	mask = (0xffffffffU >> ((4 - size) << 3));
	164	*value = (cf >> shift) & mask;
	165
	166	return PCIBIOS_SUCCESSFUL;
	167	}
	168
	169	static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
	170	int where, int size, u32 *value)
	171	{
	172	if (!pci_is_root_bus(bus))
	173	return pci_conf1_read_config(bus, devfn, where, size, value);
	174
	175	return pci_conf0_read_config(bus, devfn, where, size, value);
	176	}
	177
	178	static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
	179	int where, int size, u32 value)
	180	{
	181	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
	182	struct bridge_regs *bridge = bc->base;
	183	int slot = PCI_SLOT(devfn);
	184	int fn = PCI_FUNC(devfn);
	185	void *addr;
	186	u32 cf, shift, mask, smask;
	187	int res;
	188
	189	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
	190	if (get_dbe(cf, (u32 *)addr))
	191	return PCIBIOS_DEVICE_NOT_FOUND;
	192
	193	/*
	194	* IOC3 is broken beyond belief ... Don't even give the
	195	* generic PCI code a chance to look at it for real ...
	196	*/
	197	if (cf == (PCI_VENDOR_ID_SGI \| (PCI_DEVICE_ID_SGI_IOC3 << 16)))
	198	goto is_ioc3;
	199
	200	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
	201
	202	if (size == 1)
	203	res = put_dbe(value, (u8 *)addr);
	204	else if (size == 2)
	205	res = put_dbe(value, (u16 *)addr);
	206	else
	207	res = put_dbe(value, (u32 *)addr);
	208
	209	if (res)
	210	return PCIBIOS_DEVICE_NOT_FOUND;
	211
	212	return PCIBIOS_SUCCESSFUL;
	213
	214	is_ioc3:
	215
	216	/*
	217	* IOC3 special handling
	218	*/
	219	if ((where >= 0x14 && where < 0x40) \|\| (where >= 0x48))
	220	return PCIBIOS_SUCCESSFUL;
	221
	222	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
	223
	224	if (get_dbe(cf, (u32 *)addr))
	225	return PCIBIOS_DEVICE_NOT_FOUND;
	226
	227	shift = ((where & 3) << 3);
	228	mask = (0xffffffffU >> ((4 - size) << 3));
	229	smask = mask << shift;
	230
	231	cf = (cf & ~smask) \| ((value & mask) << shift);
	232	if (put_dbe(cf, (u32 *)addr))
	233	return PCIBIOS_DEVICE_NOT_FOUND;
	234
	235	return PCIBIOS_SUCCESSFUL;
	236	}
	237
	238	static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
	239	int where, int size, u32 value)
	240	{
	241	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
	242	struct bridge_regs *bridge = bc->base;
	243	int slot = PCI_SLOT(devfn);
	244	int fn = PCI_FUNC(devfn);
	245	int busno = bus->number;
	246	void *addr;
	247	u32 cf, shift, mask, smask;
	248	int res;
	249
	250	bridge_write(bc, b_pci_cfg, (busno << 16) \| (slot << 11));
	251	addr = &bridge->b_type1_cfg.c[(fn << 8) \| PCI_VENDOR_ID];
	252	if (get_dbe(cf, (u32 *)addr))
	253	return PCIBIOS_DEVICE_NOT_FOUND;
	254
	255	/*
	256	* IOC3 is broken beyond belief ... Don't even give the
	257	* generic PCI code a chance to look at it for real ...
	258	*/
	259	if (cf == (PCI_VENDOR_ID_SGI \| (PCI_DEVICE_ID_SGI_IOC3 << 16)))
	260	goto is_ioc3;
	261
	262	addr = &bridge->b_type1_cfg.c[(fn << 8) \| (where ^ (4 - size))];
	263
	264	if (size == 1)
	265	res = put_dbe(value, (u8 *)addr);
	266	else if (size == 2)
	267	res = put_dbe(value, (u16 *)addr);
	268	else
	269	res = put_dbe(value, (u32 *)addr);
	270
	271	if (res)
	272	return PCIBIOS_DEVICE_NOT_FOUND;
	273
	274	return PCIBIOS_SUCCESSFUL;
	275
	276	is_ioc3:
	277
	278	/*
	279	* IOC3 special handling
	280	*/
	281	if ((where >= 0x14 && where < 0x40) \|\| (where >= 0x48))
	282	return PCIBIOS_SUCCESSFUL;
	283
	284	addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
	285	if (get_dbe(cf, (u32 *)addr))
	286	return PCIBIOS_DEVICE_NOT_FOUND;
	287
	288	shift = ((where & 3) << 3);
	289	mask = (0xffffffffU >> ((4 - size) << 3));
	290	smask = mask << shift;
	291
	292	cf = (cf & ~smask) \| ((value & mask) << shift);
	293	if (put_dbe(cf, (u32 *)addr))
	294	return PCIBIOS_DEVICE_NOT_FOUND;
	295
	296	return PCIBIOS_SUCCESSFUL;
	297	}
	298
	299	static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
	300	int where, int size, u32 value)
	301	{
	302	if (!pci_is_root_bus(bus))
	303	return pci_conf1_write_config(bus, devfn, where, size, value);
	304
	305	return pci_conf0_write_config(bus, devfn, where, size, value);
	306	}
	307
	308	static struct pci_ops bridge_pci_ops = {
	309	.read = pci_read_config,
	310	.write = pci_write_config,
	311	};
	312
	313	struct bridge_irq_chip_data {
	314	struct bridge_controller *bc;
	315	nasid_t nasid;
	316	};
	317
	318	static int bridge_set_affinity(struct irq_data d, const struct cpumask mask,
	319	bool force)
	320	{
	321	#ifdef CONFIG_NUMA
	322	struct bridge_irq_chip_data *data = d->chip_data;
	323	int bit = d->parent_data->hwirq;
	324	int pin = d->hwirq;
	325	nasid_t nasid;
	326	int ret, cpu;
	327
	328	ret = irq_chip_set_affinity_parent(d, mask, force);
	329	if (ret >= 0) {
	330	cpu = cpumask_first_and(mask, cpu_online_mask);
	331	nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	332	bridge_write(data->bc, b_int_addr[pin].addr,
	333	(((data->bc->intr_addr >> 30) & 0x30000) \|
	334	bit \| (nasid << 8)));
	335	bridge_read(data->bc, b_wid_tflush);
	336	}
	337	return ret;
	338	#else
	339	return irq_chip_set_affinity_parent(d, mask, force);
	340	#endif
	341	}
	342
	343	struct irq_chip bridge_irq_chip = {
	344	.name = "BRIDGE",
	345	.irq_mask = irq_chip_mask_parent,
	346	.irq_unmask = irq_chip_unmask_parent,
	347	.irq_set_affinity = bridge_set_affinity
	348	};
	349
	350	static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq,
	351	unsigned int nr_irqs, void *arg)
	352	{
	353	struct bridge_irq_chip_data *data;
	354	struct irq_alloc_info *info = arg;
	355	int ret;
	356
	357	if (nr_irqs > 1 \|\| !info)
	358	return -EINVAL;
	359
	360	data = kzalloc(sizeof(*data), GFP_KERNEL);
	361	if (!data)
	362	return -ENOMEM;
	363
	364	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
	365	if (ret >= 0) {
	366	data->bc = info->ctrl;
	367	data->nasid = info->nasid;
	368	irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip,
	369	data, handle_level_irq, NULL, NULL);
	370	} else {
	371	kfree(data);
	372	}
	373
	374	return ret;
	375	}
	376
	377	static void bridge_domain_free(struct irq_domain *domain, unsigned int virq,
	378	unsigned int nr_irqs)
	379	{
	380	struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
	381
	382	if (nr_irqs)
	383	return;
	384
	385	kfree(irqd->chip_data);
	386	irq_domain_free_irqs_top(domain, virq, nr_irqs);
	387	}
	388
	389	static int bridge_domain_activate(struct irq_domain *domain,
	390	struct irq_data *irqd, bool reserve)
	391	{
	392	struct bridge_irq_chip_data *data = irqd->chip_data;
	393	struct bridge_controller *bc = data->bc;
	394	int bit = irqd->parent_data->hwirq;
	395	int pin = irqd->hwirq;
	396	u32 device;
	397
	398	bridge_write(bc, b_int_addr[pin].addr,
	399	(((bc->intr_addr >> 30) & 0x30000) \|
	400	bit \| (data->nasid << 8)));
	401	bridge_set(bc, b_int_enable, (1 << pin));
	402	bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
	403
	404	/*
	405	* Enable sending of an interrupt clear packt to the hub on a high to
	406	* low transition of the interrupt pin.
	407	*
	408	* IRIX sets additional bits in the address which are documented as
	409	* reserved in the bridge docs.
	410	*/
	411	bridge_set(bc, b_int_mode, (1UL << pin));
	412
	413	/*
	414	* We assume the bridge to have a 1:1 mapping between devices
	415	* (slots) and intr pins.
	416	*/
	417	device = bridge_read(bc, b_int_device);
	418	device &= ~(7 << (pin*3));
	419	device \|= (pin << (pin*3));
	420	bridge_write(bc, b_int_device, device);
	421
	422	bridge_read(bc, b_wid_tflush);
	423	return 0;
	424	}
	425
	426	static void bridge_domain_deactivate(struct irq_domain *domain,
	427	struct irq_data *irqd)
	428	{
	429	struct bridge_irq_chip_data *data = irqd->chip_data;
	430
	431	bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq));
	432	bridge_read(data->bc, b_wid_tflush);
	433	}
	434
	435	static const struct irq_domain_ops bridge_domain_ops = {
	436	.alloc = bridge_domain_alloc,
	437	.free = bridge_domain_free,
	438	.activate = bridge_domain_activate,
	439	.deactivate = bridge_domain_deactivate
	440	};
	441
	442	/*
	443	* All observed requests have pin == 1. We could have a global here, that
	444	* gets incremented and returned every time - unfortunately, pci_map_irq
	445	* may be called on the same device over and over, and need to return the
	446	* same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
	447	*
	448	* A given PCI device, in general, should be able to intr any of the cpus
	449	* on any one of the hubs connected to its xbow.
	450	*/
	451	static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
	452	{
	453	struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
	454	struct irq_alloc_info info;
	455	int irq;
	456
	457	irq = bc->pci_int[slot];
	458	if (irq == -1) {
	459	info.ctrl = bc;
	460	info.nasid = bc->nasid;
	461	info.pin = slot;
	462
	463	irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info);
	464	if (irq < 0)
	465	return irq;
	466
	467	bc->pci_int[slot] = irq;
	468	}
	469	return irq;
	470	}
	471
	472	static int bridge_probe(struct platform_device *pdev)
	473	{
	474	struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev);
	475	struct device *dev = &pdev->dev;
	476	struct bridge_controller *bc;
	477	struct pci_host_bridge *host;
	478	struct irq_domain domain, parent;
	479	struct fwnode_handle *fn;
	480	int slot;
	481	int err;
	482
	483	parent = irq_get_default_host();
	484	if (!parent)
	485	return -ENODEV;
	486	fn = irq_domain_alloc_named_fwnode("BRIDGE");
	487	if (!fn)
	488	return -ENOMEM;
	489	domain = irq_domain_create_hierarchy(parent, 0, 8, fn,
	490	&bridge_domain_ops, NULL);
	491	irq_domain_free_fwnode(fn);
	492	if (!domain)
	493	return -ENOMEM;
	494
	495	pci_set_flags(PCI_PROBE_ONLY);
	496
	497	host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
	498	if (!host) {
	499	err = -ENOMEM;
	500	goto err_remove_domain;
	501	}
	502
	503	bc = pci_host_bridge_priv(host);
	504
	505	bc->busn.name = "Bridge PCI busn";
	506	bc->busn.start = 0;
	507	bc->busn.end = 0xff;
	508	bc->busn.flags = IORESOURCE_BUS;
	509
	510	bc->domain = domain;
	511
	512	pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset);
	513	pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset);
	514	pci_add_resource(&host->windows, &bc->busn);
	515
	516	err = devm_request_pci_bus_resources(dev, &host->windows);
	517	if (err < 0)
	518	goto err_free_resource;
	519
	520	bc->nasid = bd->nasid;
	521
	522	bc->baddr = (u64)bd->masterwid << 60 \| PCI64_ATTR_BAR;
	523	bc->base = (struct bridge_regs *)bd->bridge_addr;
	524	bc->intr_addr = bd->intr_addr;
	525
	526	/*
	527	* Clear all pending interrupts.
	528	*/
	529	bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
	530
	531	/*
	532	* Until otherwise set up, assume all interrupts are from slot 0
	533	*/
	534	bridge_write(bc, b_int_device, 0x0);
	535
	536	/*
	537	* disable swapping for big windows
	538	*/
	539	bridge_clr(bc, b_wid_control,
	540	BRIDGE_CTRL_IO_SWAP \| BRIDGE_CTRL_MEM_SWAP);
	541	#ifdef CONFIG_PAGE_SIZE_4KB
	542	bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
	543	#else /* 16kB or larger */
	544	bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
	545	#endif
	546
	547	/*
	548	* Hmm... IRIX sets additional bits in the address which
	549	* are documented as reserved in the bridge docs.
	550	*/
	551	bridge_write(bc, b_wid_int_upper,
	552	((bc->intr_addr >> 32) & 0xffff) \| (bd->masterwid << 16));
	553	bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
	554	bridge_write(bc, b_dir_map, (bd->masterwid << 20)); /* DMA */
	555	bridge_write(bc, b_int_enable, 0);
	556
	557	for (slot = 0; slot < 8; slot++) {
	558	bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
	559	bc->pci_int[slot] = -1;
	560	}
	561	bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */
	562
	563	host->dev.parent = dev;
	564	host->sysdata = bc;
	565	host->busnr = 0;
	566	host->ops = &bridge_pci_ops;
	567	host->map_irq = bridge_map_irq;
	568	host->swizzle_irq = pci_common_swizzle;
	569
	570	err = pci_scan_root_bus_bridge(host);
	571	if (err < 0)
	572	goto err_free_resource;
	573
	574	pci_bus_claim_resources(host->bus);
	575	pci_bus_add_devices(host->bus);
	576
	577	platform_set_drvdata(pdev, host->bus);
	578
	579	return 0;
	580
	581	err_free_resource:
	582	pci_free_resource_list(&host->windows);
	583	err_remove_domain:
	584	irq_domain_remove(domain);
	585	return err;
	586	}
	587
	588	static int bridge_remove(struct platform_device *pdev)
	589	{
	590	struct pci_bus *bus = platform_get_drvdata(pdev);
	591	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
	592
	593	irq_domain_remove(bc->domain);
	594	pci_lock_rescan_remove();
	595	pci_stop_root_bus(bus);
	596	pci_remove_root_bus(bus);
	597	pci_unlock_rescan_remove();
	598
	599	return 0;
	600	}
	601
	602	static struct platform_driver bridge_driver = {
	603	.probe = bridge_probe,
	604	.remove = bridge_remove,
	605	.driver = {
	606	.name = "xtalk-bridge",
	607	}
	608	};
	609
	610	builtin_platform_driver(bridge_driver);

arch/mips/sgi-ip22/ip22-platform.c+13−0

 #include <linux/if_ether.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
 #include <asm/paccess.h>
 #include <asm/sgi/ip22.h>
 	.irq	= SGI_WD93_0_IRQ,
 };
+static u64 sgiwd93_0_dma_mask = DMA_BIT_MASK(32);
 static struct platform_device sgiwd93_0_device = {
 	.name		= "sgiwd93",
 	.id		= 0,
 	.resource	= sgiwd93_0_resources,
 	.dev = {
 		.platform_data = &sgiwd93_0_pd,
+		.dma_mask = &sgiwd93_0_dma_mask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
 	},
 };
 	.irq	= SGI_WD93_1_IRQ,
 };
+static u64 sgiwd93_1_dma_mask = DMA_BIT_MASK(32);
 static struct platform_device sgiwd93_1_device = {
 	.name		= "sgiwd93",
 	.id		= 1,
 	.resource	= sgiwd93_1_resources,
 	.dev = {
 		.platform_data = &sgiwd93_1_pd,
+		.dma_mask = &sgiwd93_1_dma_mask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
 	},
 };
 static struct sgiseeq_platform_data eth0_pd;
+static u64 sgiseeq_dma_mask = DMA_BIT_MASK(32);
 static struct platform_device eth0_device = {
 	.name		= "sgiseeq",
 	.id		= 0,
 	.resource	= sgiseeq_0_resources,
 	.dev = {
 		.platform_data = &eth0_pd,
+		.dma_mask = &sgiseeq_dma_mask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
 	},
 };

arch/mips/sgi-ip27/ip27-init.c+2−0

@@ -184,5 +184,7 @@ void __init plat_mem_setup(void) · 183 unmodified lines
184		184
185	ioc3_eth_init();	185	ioc3_eth_init();
186		186
		187	ioport_resource.start = 0;
		188	ioport_resource.end = ~0UL;
187	set_io_port_base(IO_BASE);	189	set_io_port_base(IO_BASE);
188	}	190	}

arch/mips/sgi-ip27/ip27-irq.c+84−106

@@ -12,22 +12,20 @@ · 11 unmodified lines
12	#include <linux/ioport.h>	12	#include <linux/ioport.h>
13	#include <linux/kernel.h>	13	#include <linux/kernel.h>
14	#include <linux/bitops.h>	14	#include <linux/bitops.h>
		15	#include <linux/sched.h>
15		16
16	#include <asm/io.h>	17	#include <asm/io.h>
17	#include <asm/irq_cpu.h>	18	#include <asm/irq_cpu.h>
18	#include <asm/pci/bridge.h>
19	#include <asm/sn/addrs.h>	19	#include <asm/sn/addrs.h>
20	#include <asm/sn/agent.h>	20	#include <asm/sn/agent.h>
21	#include <asm/sn/arch.h>	21	#include <asm/sn/arch.h>
22	#include <asm/sn/hub.h>	22	#include <asm/sn/hub.h>
23	#include <asm/sn/intr.h>	23	#include <asm/sn/intr.h>
		24	#include <asm/sn/irq_alloc.h>
24		25
25	struct hub_irq_data {	26	struct hub_irq_data {
26	struct bridge_controller *bc;
27	u64 *irq_mask[2];	27	u64 *irq_mask[2];
28	cpuid_t cpu;	28	cpuid_t cpu;
29	int bit;
30	int pin;
31	};	29	};
32		30
33	static DECLARE_BITMAP(hub_irq_map, IP27_HUB_IRQ_COUNT);	31	static DECLARE_BITMAP(hub_irq_map, IP27_HUB_IRQ_COUNT);
@@ -54,7 +52,7 @@ static void enable_hub_irq(struct irq_data *d) · 20 unmodified lines
54	struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);	52	struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
55	unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);	53	unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
56		54
57	set_bit(hd->bit, mask);	55	set_bit(d->hwirq, mask);
58	__raw_writeq(mask[0], hd->irq_mask[0]);	56	__raw_writeq(mask[0], hd->irq_mask[0]);
59	__raw_writeq(mask[1], hd->irq_mask[1]);	57	__raw_writeq(mask[1], hd->irq_mask[1]);
60	}	58	}
@@ -64,71 +62,11 @@ static void disable_hub_irq(struct irq_data *d) · 3 unmodified lines
64	struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);	62	struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
65	unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);	63	unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
66		64
67	clear_bit(hd->bit, mask);	65	clear_bit(d->hwirq, mask);
68	__raw_writeq(mask[0], hd->irq_mask[0]);	66	__raw_writeq(mask[0], hd->irq_mask[0]);
69	__raw_writeq(mask[1], hd->irq_mask[1]);	67	__raw_writeq(mask[1], hd->irq_mask[1]);
70	}	68	}
71		69
72	static unsigned int startup_bridge_irq(struct irq_data *d)
73	{
74	struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
75	struct bridge_controller *bc;
76	nasid_t nasid;
77	u32 device;
78	int pin;
79
80	if (!hd)
81	return -EINVAL;
82
83	pin = hd->pin;
84	bc = hd->bc;
85
86	nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(hd->cpu));
87	bridge_write(bc, b_int_addr[pin].addr,
88	(0x20000 \| hd->bit \| (nasid << 8)));
89	bridge_set(bc, b_int_enable, (1 << pin));
90	bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
91
92	/*
93	* Enable sending of an interrupt clear packt to the hub on a high to
94	* low transition of the interrupt pin.
95	*
96	* IRIX sets additional bits in the address which are documented as
97	* reserved in the bridge docs.
98	*/
99	bridge_set(bc, b_int_mode, (1UL << pin));
100
101	/*
102	* We assume the bridge to have a 1:1 mapping between devices
103	* (slots) and intr pins.
104	*/
105	device = bridge_read(bc, b_int_device);
106	device &= ~(7 << (pin*3));
107	device \|= (pin << (pin*3));
108	bridge_write(bc, b_int_device, device);
109
110	bridge_read(bc, b_wid_tflush);
111
112	enable_hub_irq(d);
113
114	return 0; /* Never anything pending. */
115	}
116
117	static void shutdown_bridge_irq(struct irq_data *d)
118	{
119	struct hub_irq_data *hd = irq_data_get_irq_chip_data(d);
120	struct bridge_controller *bc;
121
122	if (!hd)
123	return;
124
125	disable_hub_irq(d);
126
127	bc = hd->bc;
128	bridge_clr(bc, b_int_enable, (1 << hd->pin));
129	bridge_read(bc, b_wid_tflush);
130	}
131
132	static void setup_hub_mask(struct hub_irq_data hd, const struct cpumask mask)	70	static void setup_hub_mask(struct hub_irq_data hd, const struct cpumask mask)
133	{	71	{
134	nasid_t nasid;	72	nasid_t nasid;
@@ -144,9 +82,6 @@ static void setup_hub_mask(struct hub_irq_data hd, const struct cpumask mask) · 9 unmodified lines
144	hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B);	82	hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B);
145	hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B);	83	hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B);
146	}	84	}
147
148	/* Make sure it's not already pending when we connect it. */
149	REMOTE_HUB_CLR_INTR(nasid, hd->bit);
150	}	85	}
151		86
152	static int set_affinity_hub_irq(struct irq_data d, const struct cpumask mask,	87	static int set_affinity_hub_irq(struct irq_data d, const struct cpumask mask,
@@ -163,7 +98,7 @@ static int set_affinity_hub_irq(struct irq_data d, const struct cpumask mask, · 10 unmodified lines
163	setup_hub_mask(hd, mask);	98	setup_hub_mask(hd, mask);
164		99
165	if (irqd_is_started(d))	100	if (irqd_is_started(d))
166	startup_bridge_irq(d);	101	enable_hub_irq(d);
167		102
168	irq_data_update_effective_affinity(d, cpumask_of(hd->cpu));	103	irq_data_update_effective_affinity(d, cpumask_of(hd->cpu));
169		104
@@ -172,20 +107,22 @@ static int set_affinity_hub_irq(struct irq_data d, const struct cpumask mask, · 2 unmodified lines
172		107
173	static struct irq_chip hub_irq_type = {	108	static struct irq_chip hub_irq_type = {
174	.name = "HUB",	109	.name = "HUB",
175	.irq_startup = startup_bridge_irq,
176	.irq_shutdown = shutdown_bridge_irq,
177	.irq_mask = disable_hub_irq,	110	.irq_mask = disable_hub_irq,
178	.irq_unmask = enable_hub_irq,	111	.irq_unmask = enable_hub_irq,
179	.irq_set_affinity = set_affinity_hub_irq,	112	.irq_set_affinity = set_affinity_hub_irq,
180	};	113	};
181		114
182	int request_bridge_irq(struct bridge_controller *bc, int pin)	115	static int hub_domain_alloc(struct irq_domain *domain, unsigned int virq,
		116	unsigned int nr_irqs, void *arg)
183	{	117	{
		118	struct irq_alloc_info *info = arg;
184	struct hub_irq_data *hd;	119	struct hub_irq_data *hd;
185	struct hub_data *hub;	120	struct hub_data *hub;
186	struct irq_desc *desc;	121	struct irq_desc *desc;
187	int swlevel;	122	int swlevel;
188	int irq;	123
		124	if (nr_irqs > 1 \|\| !info)
		125	return -EINVAL;
189		126
190	hd = kzalloc(sizeof(*hd), GFP_KERNEL);	127	hd = kzalloc(sizeof(*hd), GFP_KERNEL);
191	if (!hd)	128	if (!hd)
@@ -196,46 +133,41 @@ int request_bridge_irq(struct bridge_controller *bc, int pin) · 4 unmodified lines
196	kfree(hd);	133	kfree(hd);
197	return -EAGAIN;	134	return -EAGAIN;
198	}	135	}
199	irq = swlevel + IP27_HUB_IRQ_BASE;	136	irq_domain_set_info(domain, virq, swlevel, &hub_irq_type, hd,
200		137	handle_level_irq, NULL, NULL);
201	hd->bc = bc;
202	hd->bit = swlevel;
203	hd->pin = pin;
204	irq_set_chip_data(irq, hd);
205		138
206	/* use CPU connected to nearest hub */	139	/* use CPU connected to nearest hub */
207	hub = hub_data(NASID_TO_COMPACT_NODEID(bc->nasid));	140	hub = hub_data(NASID_TO_COMPACT_NODEID(info->nasid));
208	setup_hub_mask(hd, &hub->h_cpus);	141	setup_hub_mask(hd, &hub->h_cpus);
209		142
210	desc = irq_to_desc(irq);	143	/* Make sure it's not already pending when we connect it. */
211	desc->irq_common_data.node = bc->nasid;	144	REMOTE_HUB_CLR_INTR(info->nasid, swlevel);
		145
		146	desc = irq_to_desc(virq);
		147	desc->irq_common_data.node = info->nasid;
212	cpumask_copy(desc->irq_common_data.affinity, &hub->h_cpus);	148	cpumask_copy(desc->irq_common_data.affinity, &hub->h_cpus);
213		149
214	return irq;	150	return 0;
215	}	151	}
216		152
217	void ip27_hub_irq_init(void)	153	static void hub_domain_free(struct irq_domain *domain,
		154	unsigned int virq, unsigned int nr_irqs)
218	{	155	{
219	int i;	156	struct irq_data *irqd;
220		157
221	for (i = IP27_HUB_IRQ_BASE;	158	if (nr_irqs > 1)
222	i < (IP27_HUB_IRQ_BASE + IP27_HUB_IRQ_COUNT); i++)	159	return;
223	irq_set_chip_and_handler(i, &hub_irq_type, handle_level_irq);
224
225	/*
226	* Some interrupts are reserved by hardware or by software convention.
227	* Mark these as reserved right away so they won't be used accidentally
228	* later.
229	*/
230	for (i = 0; i <= BASE_PCI_IRQ; i++)
231	set_bit(i, hub_irq_map);
232
233	set_bit(IP_PEND0_6_63, hub_irq_map);
234		160
235	for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++)	161	irqd = irq_domain_get_irq_data(domain, virq);
236	set_bit(i, hub_irq_map);	162	if (irqd && irqd->chip_data)
		163	kfree(irqd->chip_data);
237	}	164	}
238		165
		166	static const struct irq_domain_ops hub_domain_ops = {
		167	.alloc = hub_domain_alloc,
		168	.free = hub_domain_free,
		169	};
		170
239	/*	171	/*
240	* This code is unnecessarily complex, because we do	172	* This code is unnecessarily complex, because we do
241	* intr enabling. Basically, once we grab the set of intrs we need	173	* intr enabling. Basically, once we grab the set of intrs we need
@@ -252,7 +184,9 @@ static void ip27_do_irq_mask0(struct irq_desc *desc) · 10 unmodified lines
252	{	184	{
253	cpuid_t cpu = smp_processor_id();	185	cpuid_t cpu = smp_processor_id();
254	unsigned long *mask = per_cpu(irq_enable_mask, cpu);	186	unsigned long *mask = per_cpu(irq_enable_mask, cpu);
		187	struct irq_domain *domain;
255	u64 pend0;	188	u64 pend0;
		189	int irq;
256		190
257	/* copied from Irix intpend0() */	191	/* copied from Irix intpend0() */
258	pend0 = LOCAL_HUB_L(PI_INT_PEND0);	192	pend0 = LOCAL_HUB_L(PI_INT_PEND0);
@@ -276,7 +210,14 @@ static void ip27_do_irq_mask0(struct irq_desc *desc) · 17 unmodified lines
276	generic_smp_call_function_interrupt();	210	generic_smp_call_function_interrupt();
277	} else	211	} else
278	#endif	212	#endif
279	generic_handle_irq(__ffs(pend0) + IP27_HUB_IRQ_BASE);	213	{
		214	domain = irq_desc_get_handler_data(desc);
		215	irq = irq_linear_revmap(domain, __ffs(pend0));
		216	if (irq)
		217	generic_handle_irq(irq);
		218	else
		219	spurious_interrupt();
		220	}
280		221
281	LOCAL_HUB_L(PI_INT_PEND0);	222	LOCAL_HUB_L(PI_INT_PEND0);
282	}	223	}
@@ -285,7 +226,9 @@ static void ip27_do_irq_mask1(struct irq_desc *desc) · 2 unmodified lines
285	{	226	{
286	cpuid_t cpu = smp_processor_id();	227	cpuid_t cpu = smp_processor_id();
287	unsigned long *mask = per_cpu(irq_enable_mask, cpu);	228	unsigned long *mask = per_cpu(irq_enable_mask, cpu);
		229	struct irq_domain *domain;
288	u64 pend1;	230	u64 pend1;
		231	int irq;
289		232
290	/* copied from Irix intpend0() */	233	/* copied from Irix intpend0() */
291	pend1 = LOCAL_HUB_L(PI_INT_PEND1);	234	pend1 = LOCAL_HUB_L(PI_INT_PEND1);
@@ -294,7 +237,12 @@ static void ip27_do_irq_mask1(struct irq_desc *desc) · 2 unmodified lines
294	if (!pend1)	237	if (!pend1)
295	return;	238	return;
296		239
297	generic_handle_irq(__ffs(pend1) + IP27_HUB_IRQ_BASE + 64);	240	domain = irq_desc_get_handler_data(desc);
		241	irq = irq_linear_revmap(domain, __ffs(pend1) + 64);
		242	if (irq)
		243	generic_handle_irq(irq);
		244	else
		245	spurious_interrupt();
298		246
299	LOCAL_HUB_L(PI_INT_PEND1);	247	LOCAL_HUB_L(PI_INT_PEND1);
300	}	248	}
@@ -325,11 +273,41 @@ void install_ipi(void) · 24 unmodified lines
325		273
326	void __init arch_init_irq(void)	274	void __init arch_init_irq(void)
327	{	275	{
		276	struct irq_domain *domain;
		277	struct fwnode_handle *fn;
		278	int i;
		279
328	mips_cpu_irq_init();	280	mips_cpu_irq_init();
329	ip27_hub_irq_init();	281
		282	/*
		283	* Some interrupts are reserved by hardware or by software convention.
		284	* Mark these as reserved right away so they won't be used accidentally
		285	* later.
		286	*/
		287	for (i = 0; i <= BASE_PCI_IRQ; i++)
		288	set_bit(i, hub_irq_map);
		289
		290	set_bit(IP_PEND0_6_63, hub_irq_map);
		291
		292	for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++)
		293	set_bit(i, hub_irq_map);
		294
		295	fn = irq_domain_alloc_named_fwnode("HUB");
		296	WARN_ON(fn == NULL);
		297	if (!fn)
		298	return;
		299	domain = irq_domain_create_linear(fn, IP27_HUB_IRQ_COUNT,
		300	&hub_domain_ops, NULL);
		301	WARN_ON(domain == NULL);
		302	if (!domain)
		303	return;
		304
		305	irq_set_default_host(domain);
330		306
331	irq_set_percpu_devid(IP27_HUB_PEND0_IRQ);	307	irq_set_percpu_devid(IP27_HUB_PEND0_IRQ);
332	irq_set_chained_handler(IP27_HUB_PEND0_IRQ, ip27_do_irq_mask0);	308	irq_set_chained_handler_and_data(IP27_HUB_PEND0_IRQ, ip27_do_irq_mask0,
		309	domain);
333	irq_set_percpu_devid(IP27_HUB_PEND1_IRQ);	310	irq_set_percpu_devid(IP27_HUB_PEND1_IRQ);
334	irq_set_chained_handler(IP27_HUB_PEND1_IRQ, ip27_do_irq_mask1);	311	irq_set_chained_handler_and_data(IP27_HUB_PEND1_IRQ, ip27_do_irq_mask1,
		312	domain);
335	}	313	}

arch/mips/sgi-ip27/ip27-xtalk.c+49−12

 #include <linux/kernel.h>
 #include <linux/smp.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/xtalk-bridge.h>
+#include <asm/sn/addrs.h>
 #include <asm/sn/types.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/hub.h>
 #define XXBOW_WIDGET_PART_NUM	0xd000	/* Xbow in Xbridge */
 #define BASE_XBOW_PORT		8     /* Lowest external port */
-extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
+static void bridge_platform_create(nasid_t nasid, int widget, int masterwid)
+{
+	struct xtalk_bridge_platform_data *bd;
+	struct platform_device *pdev;
+	unsigned long offset;
+	bd = kzalloc(sizeof(*bd), GFP_KERNEL);
+	if (!bd)
+		goto no_mem;
+	pdev = platform_device_alloc("xtalk-bridge", PLATFORM_DEVID_AUTO);
+	if (!pdev) {
+		kfree(bd);
+		goto no_mem;
+	}
+	offset = NODE_OFFSET(nasid);
+	bd->bridge_addr = RAW_NODE_SWIN_BASE(nasid, widget);
+	bd->intr_addr	= BIT_ULL(47) + 0x01800000 + PI_INT_PEND_MOD;
+	bd->nasid	= nasid;
+	bd->masterwid	= masterwid;
+	bd->mem.name	= "Bridge PCI MEM";
+	bd->mem.start	= offset + (widget << SWIN_SIZE_BITS);
+	bd->mem.end	= bd->mem.start + SWIN_SIZE - 1;
+	bd->mem.flags	= IORESOURCE_MEM;
+	bd->mem_offset	= offset;
+	bd->io.name	= "Bridge PCI IO";
+	bd->io.start	= offset + (widget << SWIN_SIZE_BITS);
+	bd->io.end	= bd->io.start + SWIN_SIZE - 1;
+	bd->io.flags	= IORESOURCE_IO;
+	bd->io_offset	= offset;
+	platform_device_add_data(pdev, bd, sizeof(*bd));
+	platform_device_add(pdev);
+	pr_info("xtalk:n%d/%x bridge widget\n", nasid, widget);
+	return;
+no_mem:
+	pr_warn("xtalk:n%d/%x bridge create out of memory\n", nasid, widget);
+}
 static int probe_one_port(nasid_t nasid, int widget, int masterwid)
 {
 		(RAW_NODE_SWIN_BASE(nasid, widget) + WIDGET_ID);
 	partnum = XWIDGET_PART_NUM(widget_id);
-	printk(KERN_INFO "Cpu %d, Nasid 0x%x, widget 0x%x (partnum 0x%x) is ",
-			smp_processor_id(), nasid, widget, partnum);
 	switch (partnum) {
 	case BRIDGE_WIDGET_PART_NUM:
 	case XBRIDGE_WIDGET_PART_NUM:
-		bridge_probe(nasid, widget, masterwid);
+		bridge_platform_create(nasid, widget, masterwid);
 		break;
 	default:
 		break;
 	klxbow_t *xbow_p;
 	unsigned masterwid, i;
-	printk("is xbow\n");
 	/*
 	 * found xbow, so may have multiple bridges
 	 * need to probe xbow
 		       (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID);
 	partnum = XWIDGET_PART_NUM(widget_id);
-	printk(KERN_INFO "Cpu %d, Nasid 0x%x: partnum 0x%x is ",
-			smp_processor_id(), nasid, partnum);
 	switch (partnum) {
 	case BRIDGE_WIDGET_PART_NUM:
-		bridge_probe(nasid, 0x8, 0xa);
+		bridge_platform_create(nasid, 0x8, 0xa);
 		break;
 	case XBOW_WIDGET_PART_NUM:
 	case XXBOW_WIDGET_PART_NUM:
+		pr_info("xtalk:n%d/0 xbow widget\n", nasid);
 		xbow_probe(nasid);
 		break;
 	default:
-		printk(" unknown widget??\n");
+		pr_info("xtalk:n%d/0 unknown widget (0x%x)\n", nasid, partnum);
 		break;
 	}
 }

include/linux/platform_data/xtalk-bridge.h+22−0

@@ -0,0 +1,22 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* SGI PCI Xtalk Bridge
	4	*/
	5
	6	#ifndef PLATFORM_DATA_XTALK_BRIDGE_H
	7	#define PLATFORM_DATA_XTALK_BRIDGE_H
	8
	9	#include <asm/sn/types.h>
	10
	11	struct xtalk_bridge_platform_data {
	12	struct resource mem;
	13	struct resource io;
	14	unsigned long bridge_addr;
	15	unsigned long intr_addr;
	16	unsigned long mem_offset;
	17	unsigned long io_offset;
	18	nasid_t nasid;
	19	int masterwid;
	20	};
	21
	22	#endif /* PLATFORM_DATA_XTALK_BRIDGE_H */