Merge tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6

Pull SPI changes from Grant Likely: "Bug fixes and new features for SPI device drivers. Also move device tree support code out of drivers/of and into drivers/spi/spi.c where it makes more sense." * tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6: spi: By default setup spi_masters with 1 chipselect and dynamics bus number SPI: PRIMA2: use the newest APIs of PINCTRL to fix compiling errors spi/spi-fsl-spi: reference correct pdata in fsl_spi_cs_control spi: refactor spi-coldfire-qspi to use SPI queue framework. spi/omap2-mcspi: convert to the pump message infrastructure spi/rspi: add dmaengine support spi/topcliff: use correct __devexit_p annotation spi: Dont call prepare/unprepare transfer if not populated spi/ep93xx: clean probe/remove routines spi/devicetree: Move devicetree support code into spi directory spi: use module_pci_driver spi/omap2-mcspi: Trivial optimisation spi: omap2-mcspi: add support for pm_runtime autosuspend spi/omap: Remove bus_num usage for instance index OMAP : SPI : use devm_* functions spi: omap2-mcspi: convert to module_platform_driver spi: omap2-mcspi: make it behave as a module

Linus Torvalds committed 14 years ago

Commit be122ab2 parents b343c8b 1e8a52e21 files · +736 −573Browse files

Unified · Split

21 files

drivers/of/Kconfig +0 −6
drivers/of/Makefile +0 −1
drivers/of/of_spi.c +0 −99
drivers/spi/spi-ath79.c +0 −3
drivers/spi/spi-coldfire-qspi.c +114 −141
drivers/spi/spi-dw-pci.c +1 −12
drivers/spi/spi-ep93xx.c +10 −27
drivers/spi/spi-fsl-espi.c +0 −1
drivers/spi/spi-fsl-lib.c +1 −1
drivers/spi/spi-fsl-spi.c +1 −1
drivers/spi/spi-lm70llp.c +0 −3
drivers/spi/spi-mpc52xx.c +0 −3
drivers/spi/spi-omap2-mcspi.c +159 −214
drivers/spi/spi-ppc4xx.c +0 −4
drivers/spi/spi-pxa2xx-pci.c +1 −11
drivers/spi/spi-rspi.c +314 −6
drivers/spi/spi-sirf.c +8 −12
drivers/spi/spi-topcliff-pch.c +1 −2
drivers/spi/spi.c +95 −3
include/linux/of_spi.h +0 −23
include/linux/spi/rspi.h +31 −0

drivers/of/Kconfig+0−6

@@ -67,12 +67,6 @@ config OF_NET · 66 unmodified lines
67	67	depends on NETDEVICES
68	68	def_bool y
69	69
70		−config OF_SPI
71		− def_tristate SPI
72		− depends on SPI && !SPARC
73		− help
74		− OpenFirmware SPI accessors
75		−
76	70	config OF_MDIO
77	71	def_tristate PHYLIB
78	72	depends on PHYLIB

drivers/of/Makefile+0−1

@@ -7,7 +7,6 @@ obj-$(CONFIG_OF_DEVICE) += device.o platform.o · 6 unmodified lines
7	7	obj-$(CONFIG_OF_GPIO) += gpio.o
8	8	obj-$(CONFIG_OF_I2C) += of_i2c.o
9	9	obj-$(CONFIG_OF_NET) += of_net.o
10		−obj-$(CONFIG_OF_SPI) += of_spi.o
11	10	obj-$(CONFIG_OF_SELFTEST) += selftest.o
12	11	obj-$(CONFIG_OF_MDIO) += of_mdio.o
13	12	obj-$(CONFIG_OF_PCI) += of_pci.o

drivers/of/of_spi.c+0−99

@@ -1,99 +0,0 @@
1		−/*
2		− * SPI OF support routines
3		− * Copyright (C) 2008 Secret Lab Technologies Ltd.
4		− *
5		− * Support routines for deriving SPI device attachments from the device
6		− * tree.
7		− */
8		−
9		−#include <linux/module.h>
10		−#include <linux/of.h>
11		−#include <linux/device.h>
12		−#include <linux/spi/spi.h>
13		−#include <linux/of_irq.h>
14		−#include <linux/of_spi.h>
15		−
16		−/**
17		− * of_register_spi_devices - Register child devices onto the SPI bus
18		− * @master: Pointer to spi_master device
19		− *
20		− * Registers an spi_device for each child node of master node which has a 'reg'
21		− * property.
22		− */
23		−void of_register_spi_devices(struct spi_master *master)
24		−{
25		− struct spi_device *spi;
26		− struct device_node *nc;
27		− const __be32 *prop;
28		− int rc;
29		− int len;
30		−
31		− if (!master->dev.of_node)
32		− return;
33		−
34		− for_each_child_of_node(master->dev.of_node, nc) {
35		− /* Alloc an spi_device */
36		− spi = spi_alloc_device(master);
37		− if (!spi) {
38		− dev_err(&master->dev, "spi_device alloc error for %s\n",
39		− nc->full_name);
40		− spi_dev_put(spi);
41		− continue;
42		− }
43		−
44		− /* Select device driver */
45		− if (of_modalias_node(nc, spi->modalias,
46		− sizeof(spi->modalias)) < 0) {
47		− dev_err(&master->dev, "cannot find modalias for %s\n",
48		− nc->full_name);
49		− spi_dev_put(spi);
50		− continue;
51		− }
52		−
53		− /* Device address */
54		− prop = of_get_property(nc, "reg", &len);
55		− if (!prop \|\| len < sizeof(*prop)) {
56		− dev_err(&master->dev, "%s has no 'reg' property\n",
57		− nc->full_name);
58		− spi_dev_put(spi);
59		− continue;
60		− }
61		− spi->chip_select = be32_to_cpup(prop);
62		−
63		− /* Mode (clock phase/polarity/etc.) */
64		− if (of_find_property(nc, "spi-cpha", NULL))
65		− spi->mode \|= SPI_CPHA;
66		− if (of_find_property(nc, "spi-cpol", NULL))
67		− spi->mode \|= SPI_CPOL;
68		− if (of_find_property(nc, "spi-cs-high", NULL))
69		− spi->mode \|= SPI_CS_HIGH;
70		−
71		− /* Device speed */
72		− prop = of_get_property(nc, "spi-max-frequency", &len);
73		− if (!prop \|\| len < sizeof(*prop)) {
74		− dev_err(&master->dev, "%s has no 'spi-max-frequency' property\n",
75		− nc->full_name);
76		− spi_dev_put(spi);
77		− continue;
78		− }
79		− spi->max_speed_hz = be32_to_cpup(prop);
80		−
81		− /* IRQ */
82		− spi->irq = irq_of_parse_and_map(nc, 0);
83		−
84		− /* Store a pointer to the node in the device structure */
85		− of_node_get(nc);
86		− spi->dev.of_node = nc;
87		−
88		− /* Register the new device */
89		− request_module(spi->modalias);
90		− rc = spi_add_device(spi);
91		− if (rc) {
92		− dev_err(&master->dev, "spi_device register error %s\n",
93		− nc->full_name);
94		− spi_dev_put(spi);
95		− }
96		−
97		− }
98		−}
99		−EXPORT_SYMBOL(of_register_spi_devices);

drivers/spi/spi-ath79.c+0−3

@@ -216,9 +216,6 @@ static __devinit int ath79_spi_probe(struct platform_device *pdev) · 215 unmodified lines
216	216	if (pdata) {
217	217	master->bus_num = pdata->bus_num;
218	218	master->num_chipselect = pdata->num_chipselect;
219		− } else {
220		− master->bus_num = -1;
221		− master->num_chipselect = 1;
222	219	}
223	220
224	221	sp->bitbang.master = spi_master_get(master);

drivers/spi/spi-coldfire-qspi.c+114−141

@@ -25,12 +25,12 @@ · 24 unmodified lines
25	25	#include <linux/errno.h>
26	26	#include <linux/platform_device.h>
27	27	#include <linux/sched.h>
28		−#include <linux/workqueue.h>
29	28	#include <linux/delay.h>
30	29	#include <linux/io.h>
31	30	#include <linux/clk.h>
32	31	#include <linux/err.h>
33	32	#include <linux/spi/spi.h>
	33	+#include <linux/pm_runtime.h>
34	34
35	35	#include <asm/coldfire.h>
36	36	#include <asm/mcfsim.h>
@@ -78,10 +78,7 @@ struct mcfqspi { · 41 unmodified lines
78	78
79	79	wait_queue_head_t waitq;
80	80
81		− struct work_struct work;
82		− struct workqueue_struct *workq;
83		− spinlock_t lock;
84		− struct list_head msgq;
	81	+ struct device *dev;
85	82	};
86	83
87	84	static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
@@ -303,120 +300,80 @@ static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count, · 215 unmodified lines
303	300	}
304	301	}
305	302
306		−static void mcfqspi_work(struct work_struct *work)
	303	+static int mcfqspi_transfer_one_message(struct spi_master *master,
	304	+ struct spi_message *msg)
307	305	{
308		− struct mcfqspi *mcfqspi = container_of(work, struct mcfqspi, work);
309		− unsigned long flags;
310		−
311		− spin_lock_irqsave(&mcfqspi->lock, flags);
312		− while (!list_empty(&mcfqspi->msgq)) {
313		− struct spi_message *msg;
314		− struct spi_device *spi;
315		− struct spi_transfer *xfer;
316		− int status = 0;
317		−
318		− msg = container_of(mcfqspi->msgq.next, struct spi_message,
319		− queue);
320		−
321		− list_del_init(&msg->queue);
322		− spin_unlock_irqrestore(&mcfqspi->lock, flags);
323		−
324		− spi = msg->spi;
325		−
326		− list_for_each_entry(xfer, &msg->transfers, transfer_list) {
327		− bool cs_high = spi->mode & SPI_CS_HIGH;
328		− u16 qmr = MCFQSPI_QMR_MSTR;
329		−
330		− if (xfer->bits_per_word)
331		− qmr \|= xfer->bits_per_word << 10;
332		− else
333		− qmr \|= spi->bits_per_word << 10;
334		− if (spi->mode & SPI_CPHA)
335		− qmr \|= MCFQSPI_QMR_CPHA;
336		− if (spi->mode & SPI_CPOL)
337		− qmr \|= MCFQSPI_QMR_CPOL;
338		− if (xfer->speed_hz)
339		− qmr \|= mcfqspi_qmr_baud(xfer->speed_hz);
340		− else
341		− qmr \|= mcfqspi_qmr_baud(spi->max_speed_hz);
342		− mcfqspi_wr_qmr(mcfqspi, qmr);
343		−
344		− mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
345		−
346		− mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
347		− if ((xfer->bits_per_word ? xfer->bits_per_word :
348		− spi->bits_per_word) == 8)
349		− mcfqspi_transfer_msg8(mcfqspi, xfer->len,
350		− xfer->tx_buf,
351		− xfer->rx_buf);
352		− else
353		− mcfqspi_transfer_msg16(mcfqspi, xfer->len / 2,
354		− xfer->tx_buf,
355		− xfer->rx_buf);
356		− mcfqspi_wr_qir(mcfqspi, 0);
357		−
358		− if (xfer->delay_usecs)
359		− udelay(xfer->delay_usecs);
360		− if (xfer->cs_change) {
361		− if (!list_is_last(&xfer->transfer_list,
362		− &msg->transfers))
363		− mcfqspi_cs_deselect(mcfqspi,
364		− spi->chip_select,
365		− cs_high);
366		− } else {
367		− if (list_is_last(&xfer->transfer_list,
368		− &msg->transfers))
369		− mcfqspi_cs_deselect(mcfqspi,
370		− spi->chip_select,
371		− cs_high);
372		− }
373		− msg->actual_length += xfer->len;
	306	+ struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	307	+ struct spi_device *spi = msg->spi;
	308	+ struct spi_transfer *t;
	309	+ int status = 0;
	310	+
	311	+ list_for_each_entry(t, &msg->transfers, transfer_list) {
	312	+ bool cs_high = spi->mode & SPI_CS_HIGH;
	313	+ u16 qmr = MCFQSPI_QMR_MSTR;
	314	+
	315	+ if (t->bits_per_word)
	316	+ qmr \|= t->bits_per_word << 10;
	317	+ else
	318	+ qmr \|= spi->bits_per_word << 10;
	319	+ if (spi->mode & SPI_CPHA)
	320	+ qmr \|= MCFQSPI_QMR_CPHA;
	321	+ if (spi->mode & SPI_CPOL)
	322	+ qmr \|= MCFQSPI_QMR_CPOL;
	323	+ if (t->speed_hz)
	324	+ qmr \|= mcfqspi_qmr_baud(t->speed_hz);
	325	+ else
	326	+ qmr \|= mcfqspi_qmr_baud(spi->max_speed_hz);
	327	+ mcfqspi_wr_qmr(mcfqspi, qmr);
	328	+
	329	+ mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
	330	+
	331	+ mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
	332	+ if ((t->bits_per_word ? t->bits_per_word :
	333	+ spi->bits_per_word) == 8)
	334	+ mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf,
	335	+ t->rx_buf);
	336	+ else
	337	+ mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
	338	+ t->rx_buf);
	339	+ mcfqspi_wr_qir(mcfqspi, 0);
	340	+
	341	+ if (t->delay_usecs)
	342	+ udelay(t->delay_usecs);
	343	+ if (t->cs_change) {
	344	+ if (!list_is_last(&t->transfer_list, &msg->transfers))
	345	+ mcfqspi_cs_deselect(mcfqspi, spi->chip_select,
	346	+ cs_high);
	347	+ } else {
	348	+ if (list_is_last(&t->transfer_list, &msg->transfers))
	349	+ mcfqspi_cs_deselect(mcfqspi, spi->chip_select,
	350	+ cs_high);
374	351	}
375		− msg->status = status;
376		− msg->complete(msg->context);
377		−
378		− spin_lock_irqsave(&mcfqspi->lock, flags);
	352	+ msg->actual_length += t->len;
379	353	}
380		− spin_unlock_irqrestore(&mcfqspi->lock, flags);
	354	+ msg->status = status;
	355	+ spi_finalize_current_message(master);
	356	+
	357	+ return status;
	358	+
381	359	}
382	360
383		−static int mcfqspi_transfer(struct spi_device spi, struct spi_message msg)
	361	+static int mcfqspi_prepare_transfer_hw(struct spi_master *master)
384	362	{
385		− struct mcfqspi *mcfqspi;
386		− struct spi_transfer *xfer;
387		− unsigned long flags;
388		−
389		− mcfqspi = spi_master_get_devdata(spi->master);
390		−
391		− list_for_each_entry(xfer, &msg->transfers, transfer_list) {
392		− if (xfer->bits_per_word && ((xfer->bits_per_word < 8)
393		− \|\| (xfer->bits_per_word > 16))) {
394		− dev_dbg(&spi->dev,
395		− "%d bits per word is not supported\n",
396		− xfer->bits_per_word);
397		− goto fail;
398		− }
399		− if (xfer->speed_hz) {
400		− u32 real_speed = MCFQSPI_BUSCLK /
401		− mcfqspi_qmr_baud(xfer->speed_hz);
402		− if (real_speed != xfer->speed_hz)
403		− dev_dbg(&spi->dev,
404		− "using speed %d instead of %d\n",
405		− real_speed, xfer->speed_hz);
406		− }
407		− }
408		− msg->status = -EINPROGRESS;
409		− msg->actual_length = 0;
	363	+ struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
410	364
411		− spin_lock_irqsave(&mcfqspi->lock, flags);
412		− list_add_tail(&msg->queue, &mcfqspi->msgq);
413		− queue_work(mcfqspi->workq, &mcfqspi->work);
414		− spin_unlock_irqrestore(&mcfqspi->lock, flags);
	365	+ pm_runtime_get_sync(mcfqspi->dev);
	366	+
	367	+ return 0;
	368	+}
	369	+
	370	+static int mcfqspi_unprepare_transfer_hw(struct spi_master *master)
	371	+{
	372	+ struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	373	+
	374	+ pm_runtime_put_sync(mcfqspi->dev);
415	375
416	376	return 0;
417		−fail:
418		− msg->status = -EINVAL;
419		− return -EINVAL;
420	377	}
421	378
422	379	static int mcfqspi_setup(struct spi_device *spi)
@@ -502,21 +459,10 @@ static int __devinit mcfqspi_probe(struct platform_device *pdev) · 79 unmodified lines
502	459	}
503	460	clk_enable(mcfqspi->clk);
504	461
505		− mcfqspi->workq = create_singlethread_workqueue(dev_name(master->dev.parent));
506		− if (!mcfqspi->workq) {
507		− dev_dbg(&pdev->dev, "create_workqueue failed\n");
508		− status = -ENOMEM;
509		− goto fail4;
510		− }
511		− INIT_WORK(&mcfqspi->work, mcfqspi_work);
512		− spin_lock_init(&mcfqspi->lock);
513		− INIT_LIST_HEAD(&mcfqspi->msgq);
514		− init_waitqueue_head(&mcfqspi->waitq);
515		−
516	462	pdata = pdev->dev.platform_data;
517	463	if (!pdata) {
518	464	dev_dbg(&pdev->dev, "platform data is missing\n");
519		− goto fail5;
	465	+ goto fail4;
520	466	}
521	467	master->bus_num = pdata->bus_num;
522	468	master->num_chipselect = pdata->num_chipselect;
@@ -525,28 +471,33 @@ static int __devinit mcfqspi_probe(struct platform_device *pdev) · 2 unmodified lines
525	471	status = mcfqspi_cs_setup(mcfqspi);
526	472	if (status) {
527	473	dev_dbg(&pdev->dev, "error initializing cs_control\n");
528		− goto fail5;
	474	+ goto fail4;
529	475	}
530	476
	477	+ init_waitqueue_head(&mcfqspi->waitq);
	478	+ mcfqspi->dev = &pdev->dev;
	479	+
531	480	master->mode_bits = SPI_CS_HIGH \| SPI_CPOL \| SPI_CPHA;
532	481	master->setup = mcfqspi_setup;
533		− master->transfer = mcfqspi_transfer;
	482	+ master->transfer_one_message = mcfqspi_transfer_one_message;
	483	+ master->prepare_transfer_hardware = mcfqspi_prepare_transfer_hw;
	484	+ master->unprepare_transfer_hardware = mcfqspi_unprepare_transfer_hw;
534	485
535	486	platform_set_drvdata(pdev, master);
536	487
537	488	status = spi_register_master(master);
538	489	if (status) {
539	490	dev_dbg(&pdev->dev, "spi_register_master failed\n");
540		− goto fail6;
	491	+ goto fail5;
541	492	}
	493	+ pm_runtime_enable(mcfqspi->dev);
	494	+
542	495	dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
543	496
544	497	return 0;
545	498
546		−fail6:
547		− mcfqspi_cs_teardown(mcfqspi);
548	499	fail5:
549		− destroy_workqueue(mcfqspi->workq);
	500	+ mcfqspi_cs_teardown(mcfqspi);
550	501	fail4:
551	502	clk_disable(mcfqspi->clk);
552	503	clk_put(mcfqspi->clk);
@@ -570,12 +521,12 @@ static int __devexit mcfqspi_remove(struct platform_device *pdev) · 17 unmodified lines
570	521	struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
571	522	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
572	523
	524	+ pm_runtime_disable(mcfqspi->dev);
573	525	/* disable the hardware (set the baud rate to 0) */
574	526	mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
575	527
576	528	platform_set_drvdata(pdev, NULL);
577	529	mcfqspi_cs_teardown(mcfqspi);
578		− destroy_workqueue(mcfqspi->workq);
579	530	clk_disable(mcfqspi->clk);
580	531	clk_put(mcfqspi->clk);
581	532	free_irq(mcfqspi->irq, mcfqspi);
@@ -587,11 +538,13 @@ static int __devexit mcfqspi_remove(struct platform_device *pdev) · 5 unmodified lines
587	538	return 0;
588	539	}
589	540
590		−#ifdef CONFIG_PM
591		−
	541	+#ifdef CONFIG_PM_SLEEP
592	542	static int mcfqspi_suspend(struct device *dev)
593	543	{
594		− struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev));
	544	+ struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
	545	+ struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	546	+
	547	+ spi_master_suspend(master);
595	548
596	549	clk_disable(mcfqspi->clk);
597	550
@@ -600,27 +553,47 @@ static int mcfqspi_suspend(struct device *dev) · 2 unmodified lines
600	553
601	554	static int mcfqspi_resume(struct device *dev)
602	555	{
603		− struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev));
	556	+ struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
	557	+ struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
	558	+
	559	+ spi_master_resume(master);
604	560
605	561	clk_enable(mcfqspi->clk);
606	562
607	563	return 0;
608	564	}
	565	+#endif
609	566
610		−static struct dev_pm_ops mcfqspi_dev_pm_ops = {
611		− .suspend = mcfqspi_suspend,
612		− .resume = mcfqspi_resume,
613		−};
	567	+#ifdef CONFIG_PM_RUNTIME
	568	+static int mcfqspi_runtime_suspend(struct device *dev)
	569	+{
	570	+ struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev));
614	571
615		−#define MCFQSPI_DEV_PM_OPS (&mcfqspi_dev_pm_ops)
616		−#else
617		−#define MCFQSPI_DEV_PM_OPS NULL
	572	+ clk_disable(mcfqspi->clk);
	573	+
	574	+ return 0;
	575	+}
	576	+
	577	+static int mcfqspi_runtime_resume(struct device *dev)
	578	+{
	579	+ struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev));
	580	+
	581	+ clk_enable(mcfqspi->clk);
	582	+
	583	+ return 0;
	584	+}
618	585	#endif
619	586
	587	+static const struct dev_pm_ops mcfqspi_pm = {
	588	+ SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
	589	+ SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
	590	+ NULL)
	591	+};
	592	+
620	593	static struct platform_driver mcfqspi_driver = {
621	594	.driver.name = DRIVER_NAME,
622	595	.driver.owner = THIS_MODULE,
623		− .driver.pm = MCFQSPI_DEV_PM_OPS,
	596	+ .driver.pm = &mcfqspi_pm,
624	597	.probe = mcfqspi_probe,
625	598	.remove = __devexit_p(mcfqspi_remove),
626	599	};

drivers/spi/spi-dw-pci.c+1−12

@@ -164,18 +164,7 @@ static struct pci_driver dw_spi_driver = { · 163 unmodified lines
164	164	.resume = spi_resume,
165	165	};
166	166
167		−static int __init mrst_spi_init(void)
168		−{
169		− return pci_register_driver(&dw_spi_driver);
170		−}
171		−
172		−static void __exit mrst_spi_exit(void)
173		−{
174		− pci_unregister_driver(&dw_spi_driver);
175		−}
176		−
177		−module_init(mrst_spi_init);
178		−module_exit(mrst_spi_exit);
	167	+module_pci_driver(dw_spi_driver);
179	168
180	169	MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
181	170	MODULE_DESCRIPTION("PCI interface driver for DW SPI Core");

drivers/spi/spi-ep93xx.c+10−27

@@ -76,7 +76,6 @@ · 75 unmodified lines
76	76	* @clk: clock for the controller
77	77	* @regs_base: pointer to ioremap()'d registers
78	78	* @sspdr_phys: physical address of the SSPDR register
79		− * @irq: IRQ number used by the driver
80	79	* @min_rate: minimum clock rate (in Hz) supported by the controller
81	80	* @max_rate: maximum clock rate (in Hz) supported by the controller
82	81	* @running: is the queue running
@@ -114,7 +113,6 @@ struct ep93xx_spi { · 31 unmodified lines
114	113	struct clk *clk;
115	114	void __iomem *regs_base;
116	115	unsigned long sspdr_phys;
117		− int irq;
118	116	unsigned long min_rate;
119	117	unsigned long max_rate;
120	118	bool running;
@@ -1031,6 +1029,7 @@ static int __devinit ep93xx_spi_probe(struct platform_device *pdev) · 910 unmodified lines
1031	1029	struct ep93xx_spi_info *info;
1032	1030	struct ep93xx_spi *espi;
1033	1031	struct resource *res;
	1032	+ int irq;
1034	1033	int error;
1035	1034
1036	1035	info = pdev->dev.platform_data;
@@ -1070,8 +1069,8 @@ static int __devinit ep93xx_spi_probe(struct platform_device *pdev) · 33 unmodified lines
1070	1069	espi->min_rate = clk_get_rate(espi->clk) / (254 * 256);
1071	1070	espi->pdev = pdev;
1072	1071
1073		− espi->irq = platform_get_irq(pdev, 0);
1074		− if (espi->irq < 0) {
	1072	+ irq = platform_get_irq(pdev, 0);
	1073	+ if (irq < 0) {
1075	1074	error = -EBUSY;
1076	1075	dev_err(&pdev->dev, "failed to get irq resources\n");
1077	1076	goto fail_put_clock;
@@ -1084,26 +1083,20 @@ static int __devinit ep93xx_spi_probe(struct platform_device *pdev) · 6 unmodified lines
1084	1083	goto fail_put_clock;
1085	1084	}
1086	1085
1087		− res = request_mem_region(res->start, resource_size(res), pdev->name);
1088		− if (!res) {
1089		− dev_err(&pdev->dev, "unable to request iomem resources\n");
1090		− error = -EBUSY;
1091		− goto fail_put_clock;
1092		− }
1093		−
1094	1086	espi->sspdr_phys = res->start + SSPDR;
1095		− espi->regs_base = ioremap(res->start, resource_size(res));
	1087	+
	1088	+ espi->regs_base = devm_request_and_ioremap(&pdev->dev, res);
1096	1089	if (!espi->regs_base) {
1097	1090	dev_err(&pdev->dev, "failed to map resources\n");
1098	1091	error = -ENODEV;
1099		− goto fail_free_mem;
	1092	+ goto fail_put_clock;
1100	1093	}
1101	1094
1102		− error = request_irq(espi->irq, ep93xx_spi_interrupt, 0,
1103		− "ep93xx-spi", espi);
	1095	+ error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
	1096	+ 0, "ep93xx-spi", espi);
1104	1097	if (error) {
1105	1098	dev_err(&pdev->dev, "failed to request irq\n");
1106		− goto fail_unmap_regs;
	1099	+ goto fail_put_clock;
1107	1100	}
1108	1101
1109	1102	if (info->use_dma && ep93xx_spi_setup_dma(espi))
@@ -1128,7 +1121,7 @@ static int __devinit ep93xx_spi_probe(struct platform_device *pdev) · 18 unmodified lines
1128	1121	}
1129	1122
1130	1123	dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
1131		− (unsigned long)res->start, espi->irq);
	1124	+ (unsigned long)res->start, irq);
1132	1125
1133	1126	return 0;
1134	1127
@@ -1136,11 +1129,6 @@ fail_free_queue: · 1 unmodified line
1136	1129	destroy_workqueue(espi->wq);
1137	1130	fail_free_dma:
1138	1131	ep93xx_spi_release_dma(espi);
1139		− free_irq(espi->irq, espi);
1140		−fail_unmap_regs:
1141		− iounmap(espi->regs_base);
1142		−fail_free_mem:
1143		− release_mem_region(res->start, resource_size(res));
1144	1132	fail_put_clock:
1145	1133	clk_put(espi->clk);
1146	1134	fail_release_master:
@@ -1154,7 +1142,6 @@ static int __devexit ep93xx_spi_remove(struct platform_device *pdev) · 7 unmodified lines
1154	1142	{
1155	1143	struct spi_master *master = platform_get_drvdata(pdev);
1156	1144	struct ep93xx_spi *espi = spi_master_get_devdata(master);
1157		− struct resource *res;
1158	1145
1159	1146	spin_lock_irq(&espi->lock);
1160	1147	espi->running = false;
@@ -1180,10 +1167,6 @@ static int __devexit ep93xx_spi_remove(struct platform_device *pdev) · 19 unmodified lines
1180	1167	spin_unlock_irq(&espi->lock);
1181	1168
1182	1169	ep93xx_spi_release_dma(espi);
1183		− free_irq(espi->irq, espi);
1184		− iounmap(espi->regs_base);
1185		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1186		− release_mem_region(res->start, resource_size(res));
1187	1170	clk_put(espi->clk);
1188	1171	platform_set_drvdata(pdev, NULL);
1189	1172

drivers/spi/spi-fsl-espi.c+0−1

@@ -17,7 +17,6 @@ · 16 unmodified lines
17	17	#include <linux/mm.h>
18	18	#include <linux/of.h>
19	19	#include <linux/of_platform.h>
20		−#include <linux/of_spi.h>
21	20	#include <linux/interrupt.h>
22	21	#include <linux/err.h>
23	22	#include <sysdev/fsl_soc.h>

drivers/spi/spi-fsl-lib.c+1−1

@@ -22,7 +22,7 @@ · 21 unmodified lines
22	22	#include <linux/dma-mapping.h>
23	23	#include <linux/mm.h>
24	24	#include <linux/of_platform.h>
25		−#include <linux/of_spi.h>
	25	+#include <linux/spi/spi.h>
26	26	#include <sysdev/fsl_soc.h>
27	27
28	28	#include "spi-fsl-lib.h"

drivers/spi/spi-fsl-spi.c+1−1

@@ -933,7 +933,7 @@ err: · 932 unmodified lines
933	933
934	934	static void fsl_spi_cs_control(struct spi_device *spi, bool on)
935	935	{
936		− struct device *dev = spi->dev.parent;
	936	+ struct device *dev = spi->dev.parent->parent;
937	937	struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
938	938	u16 cs = spi->chip_select;
939	939	int gpio = pinfo->gpios[cs];

drivers/spi/spi-lm70llp.c+0−3

@@ -219,9 +219,6 @@ static void spi_lm70llp_attach(struct parport *p) · 218 unmodified lines
219	219	}
220	220	pp = spi_master_get_devdata(master);
221	221
222		− master->bus_num = -1; /* dynamic alloc of a bus number */
223		− master->num_chipselect = 1;
224		−
225	222	/*
226	223	* SPI and bitbang hookup.
227	224	*/

drivers/spi/spi-mpc52xx.c+0−3

@@ -433,7 +433,6 @@ static int __devinit mpc52xx_spi_probe(struct platform_device *op) · 432 unmodified lines
433	433	goto err_alloc;
434	434	}
435	435
436		− master->bus_num = -1;
437	436	master->setup = mpc52xx_spi_setup;
438	437	master->transfer = mpc52xx_spi_transfer;
439	438	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_LSB_FIRST;
@@ -479,8 +478,6 @@ static int __devinit mpc52xx_spi_probe(struct platform_device *op) · 39 unmodified lines
479	478	gpio_direction_output(gpio_cs, 1);
480	479	ms->gpio_cs[i] = gpio_cs;
481	480	}
482		− } else {
483		− master->num_chipselect = 1;
484	481	}
485	482
486	483	spin_lock_init(&ms->lock);

drivers/spi/spi-omap2-mcspi.c+159−214

@@ -44,9 +44,7 @@ · 43 unmodified lines
44	44	#include <plat/mcspi.h>
45	45
46	46	#define OMAP2_MCSPI_MAX_FREQ 48000000
47		−
48		−/* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
49		−#define OMAP2_MCSPI_MAX_CTRL 4
	47	+#define SPI_AUTOSUSPEND_TIMEOUT 2000
50	48
51	49	#define OMAP2_MCSPI_REVISION 0x00
52	50	#define OMAP2_MCSPI_SYSSTATUS 0x14
@@ -111,19 +109,25 @@ struct omap2_mcspi_dma { · 58 unmodified lines
111	109	#define DMA_MIN_BYTES 160
112	110
113	111
	112	+/*
	113	+ * Used for context save and restore, structure members to be updated whenever
	114	+ * corresponding registers are modified.
	115	+ */
	116	+struct omap2_mcspi_regs {
	117	+ u32 modulctrl;
	118	+ u32 wakeupenable;
	119	+ struct list_head cs;
	120	+};
	121	+
114	122	struct omap2_mcspi {
115		− struct work_struct work;
116		− /* lock protects queue and registers */
117		− spinlock_t lock;
118		− struct list_head msg_queue;
119	123	struct spi_master *master;
120	124	/* Virtual base address of the controller */
121	125	void __iomem *base;
122	126	unsigned long phys;
123	127	/* SPI1 has 4 channels, while SPI2 has 2 */
124	128	struct omap2_mcspi_dma *dma_channels;
125		− struct device *dev;
126		− struct workqueue_struct *wq;
	129	+ struct device *dev;
	130	+ struct omap2_mcspi_regs ctx;
127	131	};
128	132
129	133	struct omap2_mcspi_cs {
@@ -135,17 +139,6 @@ struct omap2_mcspi_cs { · 5 unmodified lines
135	139	u32 chconf0;
136	140	};
137	141
138		−/* used for context save and restore, structure members to be updated whenever
139		− * corresponding registers are modified.
140		− */
141		−struct omap2_mcspi_regs {
142		− u32 modulctrl;
143		− u32 wakeupenable;
144		− struct list_head cs;
145		−};
146		−
147		−static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
148		−
149	142	#define MOD_REG_BIT(val, mask, set) do { \
150	143	if (set) \
151	144	val \|= mask; \
@@ -236,9 +229,12 @@ static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) · 84 unmodified lines
236	229
237	230	static void omap2_mcspi_set_master_mode(struct spi_master *master)
238	231	{
	232	+ struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
	233	+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
239	234	u32 l;
240	235
241		− /* setup when switching from (reset default) slave mode
	236	+ /*
	237	+ * Setup when switching from (reset default) slave mode
242	238	* to single-channel master mode
243	239	*/
244	240	l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
@@ -247,29 +243,26 @@ static void omap2_mcspi_set_master_mode(struct spi_master *master) · 2 unmodified lines
247	243	MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
248	244	mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
249	245
250		− omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
	246	+ ctx->modulctrl = l;
251	247	}
252	248
253	249	static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
254	250	{
255		− struct spi_master *spi_cntrl;
256		− struct omap2_mcspi_cs *cs;
257		− spi_cntrl = mcspi->master;
	251	+ struct spi_master *spi_cntrl = mcspi->master;
	252	+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
	253	+ struct omap2_mcspi_cs *cs;
258	254
259	255	/* McSPI: context restore */
260		− mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
261		− omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
262		−
263		− mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
264		− omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
	256	+ mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
	257	+ mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
265	258
266		− list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
267		− node)
	259	+ list_for_each_entry(cs, &ctx->cs, node)
268	260	__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
269	261	}
270	262	static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
271	263	{
272		− pm_runtime_put_sync(mcspi->dev);
	264	+ pm_runtime_mark_last_busy(mcspi->dev);
	265	+ pm_runtime_put_autosuspend(mcspi->dev);
273	266	}
274	267
275	268	static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
@@ -277,6 +270,23 @@ static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) · 1 unmodified line
277	270	return pm_runtime_get_sync(mcspi->dev);
278	271	}
279	272
	273	+static int omap2_prepare_transfer(struct spi_master *master)
	274	+{
	275	+ struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
	276	+
	277	+ pm_runtime_get_sync(mcspi->dev);
	278	+ return 0;
	279	+}
	280	+
	281	+static int omap2_unprepare_transfer(struct spi_master *master)
	282	+{
	283	+ struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
	284	+
	285	+ pm_runtime_mark_last_busy(mcspi->dev);
	286	+ pm_runtime_put_autosuspend(mcspi->dev);
	287	+ return 0;
	288	+}
	289	+
280	290	static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
281	291	{
282	292	unsigned long timeout;
@@ -777,7 +787,8 @@ static int omap2_mcspi_request_dma(struct spi_device *spi) · 494 unmodified lines
777	787	static int omap2_mcspi_setup(struct spi_device *spi)
778	788	{
779	789	int ret;
780		− struct omap2_mcspi *mcspi;
	790	+ struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
	791	+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
781	792	struct omap2_mcspi_dma *mcspi_dma;
782	793	struct omap2_mcspi_cs *cs = spi->controller_state;
783	794
@@ -787,11 +798,10 @@ static int omap2_mcspi_setup(struct spi_device *spi) · 3 unmodified lines
787	798	return -EINVAL;
788	799	}
789	800
790		− mcspi = spi_master_get_devdata(spi->master);
791	801	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
792	802
793	803	if (!cs) {
794		− cs = kzalloc(sizeof *cs, GFP_KERNEL);
	804	+ cs = devm_kzalloc(&spi->dev , sizeof *cs, GFP_KERNEL);
795	805	if (!cs)
796	806	return -ENOMEM;
797	807	cs->base = mcspi->base + spi->chip_select * 0x14;
@@ -799,8 +809,7 @@ static int omap2_mcspi_setup(struct spi_device *spi) · 1 unmodified line
799	809	cs->chconf0 = 0;
800	810	spi->controller_state = cs;
801	811	/* Link this to context save list */
802		− list_add_tail(&cs->node,
803		− &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
	812	+ list_add_tail(&cs->node, &ctx->cs);
804	813	}
805	814
806	815	if (mcspi_dma->dma_rx_channel == -1
@@ -833,7 +842,6 @@ static void omap2_mcspi_cleanup(struct spi_device *spi) · 26 unmodified lines
833	842	cs = spi->controller_state;
834	843	list_del(&cs->node);
835	844
836		− kfree(spi->controller_state);
837	845	}
838	846
839	847	if (spi->chip_select < spi->master->num_chipselect) {
@@ -850,144 +858,122 @@ static void omap2_mcspi_cleanup(struct spi_device *spi) · 10 unmodified lines
850	858	}
851	859	}
852	860
853		−static void omap2_mcspi_work(struct work_struct *work)
	861	+static void omap2_mcspi_work(struct omap2_mcspi mcspi, struct spi_message m)
854	862	{
855		− struct omap2_mcspi *mcspi;
856		−
857		− mcspi = container_of(work, struct omap2_mcspi, work);
858		−
859		− if (omap2_mcspi_enable_clocks(mcspi) < 0)
860		− return;
861		−
862		− spin_lock_irq(&mcspi->lock);
863	863
864	864	/* We only enable one channel at a time -- the one whose message is
865		− * at the head of the queue -- although this controller would gladly
	865	+ * -- although this controller would gladly
866	866	* arbitrate among multiple channels. This corresponds to "single
867	867	* channel" master mode. As a side effect, we need to manage the
868	868	* chipselect with the FORCE bit ... CS != channel enable.
869	869	*/
870		− while (!list_empty(&mcspi->msg_queue)) {
871		− struct spi_message *m;
872		− struct spi_device *spi;
873		− struct spi_transfer *t = NULL;
874		− int cs_active = 0;
875		− struct omap2_mcspi_cs *cs;
876		− struct omap2_mcspi_device_config *cd;
877		− int par_override = 0;
878		− int status = 0;
879		− u32 chconf;
880		−
881		− m = container_of(mcspi->msg_queue.next, struct spi_message,
882		− queue);
883		−
884		− list_del_init(&m->queue);
885		− spin_unlock_irq(&mcspi->lock);
886		−
887		− spi = m->spi;
888		− cs = spi->controller_state;
889		− cd = spi->controller_data;
890	870
891		− omap2_mcspi_set_enable(spi, 1);
892		− list_for_each_entry(t, &m->transfers, transfer_list) {
893		− if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
894		− status = -EINVAL;
895		− break;
896		− }
897		− if (par_override \|\| t->speed_hz \|\| t->bits_per_word) {
898		− par_override = 1;
899		− status = omap2_mcspi_setup_transfer(spi, t);
900		− if (status < 0)
901		− break;
902		− if (!t->speed_hz && !t->bits_per_word)
903		− par_override = 0;
904		− }
	871	+ struct spi_device *spi;
	872	+ struct spi_transfer *t = NULL;
	873	+ int cs_active = 0;
	874	+ struct omap2_mcspi_cs *cs;
	875	+ struct omap2_mcspi_device_config *cd;
	876	+ int par_override = 0;
	877	+ int status = 0;
	878	+ u32 chconf;
905	879
906		− if (!cs_active) {
907		− omap2_mcspi_force_cs(spi, 1);
908		− cs_active = 1;
909		− }
	880	+ spi = m->spi;
	881	+ cs = spi->controller_state;
	882	+ cd = spi->controller_data;
910	883
911		− chconf = mcspi_cached_chconf0(spi);
912		− chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
913		− chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
	884	+ omap2_mcspi_set_enable(spi, 1);
	885	+ list_for_each_entry(t, &m->transfers, transfer_list) {
	886	+ if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
	887	+ status = -EINVAL;
	888	+ break;
	889	+ }
	890	+ if (par_override \|\| t->speed_hz \|\| t->bits_per_word) {
	891	+ par_override = 1;
	892	+ status = omap2_mcspi_setup_transfer(spi, t);
	893	+ if (status < 0)
	894	+ break;
	895	+ if (!t->speed_hz && !t->bits_per_word)
	896	+ par_override = 0;
	897	+ }
914	898
915		− if (t->tx_buf == NULL)
916		− chconf \|= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
917		− else if (t->rx_buf == NULL)
918		− chconf \|= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
919		−
920		− if (cd && cd->turbo_mode && t->tx_buf == NULL) {
921		− /* Turbo mode is for more than one word */
922		− if (t->len > ((cs->word_len + 7) >> 3))
923		− chconf \|= OMAP2_MCSPI_CHCONF_TURBO;
924		− }
	899	+ if (!cs_active) {
	900	+ omap2_mcspi_force_cs(spi, 1);
	901	+ cs_active = 1;
	902	+ }
925	903
926		− mcspi_write_chconf0(spi, chconf);
	904	+ chconf = mcspi_cached_chconf0(spi);
	905	+ chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
	906	+ chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
927	907
928		− if (t->len) {
929		− unsigned count;
	908	+ if (t->tx_buf == NULL)
	909	+ chconf \|= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
	910	+ else if (t->rx_buf == NULL)
	911	+ chconf \|= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
930	912
931		− /* RX_ONLY mode needs dummy data in TX reg */
932		− if (t->tx_buf == NULL)
933		− __raw_writel(0, cs->base
934		− + OMAP2_MCSPI_TX0);
	913	+ if (cd && cd->turbo_mode && t->tx_buf == NULL) {
	914	+ /* Turbo mode is for more than one word */
	915	+ if (t->len > ((cs->word_len + 7) >> 3))
	916	+ chconf \|= OMAP2_MCSPI_CHCONF_TURBO;
	917	+ }
935	918
936		− if (m->is_dma_mapped \|\| t->len >= DMA_MIN_BYTES)
937		− count = omap2_mcspi_txrx_dma(spi, t);
938		− else
939		− count = omap2_mcspi_txrx_pio(spi, t);
940		− m->actual_length += count;
	919	+ mcspi_write_chconf0(spi, chconf);
941	920
942		− if (count != t->len) {
943		− status = -EIO;
944		− break;
945		− }
946		− }
	921	+ if (t->len) {
	922	+ unsigned count;
947	923
948		− if (t->delay_usecs)
949		− udelay(t->delay_usecs);
	924	+ /* RX_ONLY mode needs dummy data in TX reg */
	925	+ if (t->tx_buf == NULL)
	926	+ __raw_writel(0, cs->base
	927	+ + OMAP2_MCSPI_TX0);
	928	+
	929	+ if (m->is_dma_mapped \|\| t->len >= DMA_MIN_BYTES)
	930	+ count = omap2_mcspi_txrx_dma(spi, t);
	931	+ else
	932	+ count = omap2_mcspi_txrx_pio(spi, t);
	933	+ m->actual_length += count;
950	934
951		− /* ignore the "leave it on after last xfer" hint */
952		− if (t->cs_change) {
953		− omap2_mcspi_force_cs(spi, 0);
954		− cs_active = 0;
	935	+ if (count != t->len) {
	936	+ status = -EIO;
	937	+ break;
955	938	}
956	939	}
957	940
958		− /* Restore defaults if they were overriden */
959		− if (par_override) {
960		− par_override = 0;
961		− status = omap2_mcspi_setup_transfer(spi, NULL);
962		− }
	941	+ if (t->delay_usecs)
	942	+ udelay(t->delay_usecs);
963	943
964		− if (cs_active)
	944	+ /* ignore the "leave it on after last xfer" hint */
	945	+ if (t->cs_change) {
965	946	omap2_mcspi_force_cs(spi, 0);
	947	+ cs_active = 0;
	948	+ }
	949	+ }
	950	+ /* Restore defaults if they were overriden */
	951	+ if (par_override) {
	952	+ par_override = 0;
	953	+ status = omap2_mcspi_setup_transfer(spi, NULL);
	954	+ }
966	955
967		− omap2_mcspi_set_enable(spi, 0);
968		−
969		− m->status = status;
970		− m->complete(m->context);
	956	+ if (cs_active)
	957	+ omap2_mcspi_force_cs(spi, 0);
971	958
972		− spin_lock_irq(&mcspi->lock);
973		− }
	959	+ omap2_mcspi_set_enable(spi, 0);
974	960
975		− spin_unlock_irq(&mcspi->lock);
	961	+ m->status = status;
976	962
977		− omap2_mcspi_disable_clocks(mcspi);
978	963	}
979	964
980		−static int omap2_mcspi_transfer(struct spi_device spi, struct spi_message m)
	965	+static int omap2_mcspi_transfer_one_message(struct spi_master *master,
	966	+ struct spi_message *m)
981	967	{
982	968	struct omap2_mcspi *mcspi;
983		− unsigned long flags;
984	969	struct spi_transfer *t;
985	970
	971	+ mcspi = spi_master_get_devdata(master);
986	972	m->actual_length = 0;
987	973	m->status = 0;
988	974
989	975	/* reject invalid messages and transfers */
990		− if (list_empty(&m->transfers) \|\| !m->complete)
	976	+ if (list_empty(&m->transfers))
991	977	return -EINVAL;
992	978	list_for_each_entry(t, &m->transfers, transfer_list) {
993	979	const void *tx_buf = t->tx_buf;
@@ -999,7 +985,7 @@ static int omap2_mcspi_transfer(struct spi_device spi, struct spi_message m) · 5 unmodified lines
999	985	\|\| (t->bits_per_word &&
1000	986	( t->bits_per_word < 4
1001	987	\|\| t->bits_per_word > 32))) {
1002		− dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
	988	+ dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1003	989	t->speed_hz,
1004	990	len,
1005	991	tx_buf ? "tx" : "",
@@ -1008,7 +994,7 @@ static int omap2_mcspi_transfer(struct spi_device spi, struct spi_message m) · 2 unmodified lines
1008	994	return -EINVAL;
1009	995	}
1010	996	if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1011		− dev_dbg(&spi->dev, "speed_hz %d below minimum %d Hz\n",
	997	+ dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1012	998	t->speed_hz,
1013	999	OMAP2_MCSPI_MAX_FREQ >> 15);
1014	1000	return -EINVAL;
@@ -1018,51 +1004,46 @@ static int omap2_mcspi_transfer(struct spi_device spi, struct spi_message m) · 3 unmodified lines
1018	1004	continue;
1019	1005
1020	1006	if (tx_buf != NULL) {
1021		− t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
	1007	+ t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1022	1008	len, DMA_TO_DEVICE);
1023		− if (dma_mapping_error(&spi->dev, t->tx_dma)) {
1024		− dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
	1009	+ if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
	1010	+ dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1025	1011	'T', len);
1026	1012	return -EINVAL;
1027	1013	}
1028	1014	}
1029	1015	if (rx_buf != NULL) {
1030		− t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
	1016	+ t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1031	1017	DMA_FROM_DEVICE);
1032		− if (dma_mapping_error(&spi->dev, t->rx_dma)) {
1033		− dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
	1018	+ if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
	1019	+ dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1034	1020	'R', len);
1035	1021	if (tx_buf != NULL)
1036		− dma_unmap_single(&spi->dev, t->tx_dma,
	1022	+ dma_unmap_single(mcspi->dev, t->tx_dma,
1037	1023	len, DMA_TO_DEVICE);
1038	1024	return -EINVAL;
1039	1025	}
1040	1026	}
1041	1027	}
1042	1028
1043		− mcspi = spi_master_get_devdata(spi->master);
1044		−
1045		− spin_lock_irqsave(&mcspi->lock, flags);
1046		− list_add_tail(&m->queue, &mcspi->msg_queue);
1047		− queue_work(mcspi->wq, &mcspi->work);
1048		− spin_unlock_irqrestore(&mcspi->lock, flags);
1049		−
	1029	+ omap2_mcspi_work(mcspi, m);
	1030	+ spi_finalize_current_message(master);
1050	1031	return 0;
1051	1032	}
1052	1033
1053	1034	static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1054	1035	{
1055	1036	struct spi_master *master = mcspi->master;
1056		− u32 tmp;
1057		− int ret = 0;
	1037	+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
	1038	+ int ret = 0;
1058	1039
1059	1040	ret = omap2_mcspi_enable_clocks(mcspi);
1060	1041	if (ret < 0)
1061	1042	return ret;
1062	1043
1063		− tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1064		− mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
1065		− omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
	1044	+ mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
	1045	+ OMAP2_MCSPI_WAKEUPENABLE_WKEN);
	1046	+ ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1066	1047
1067	1048	omap2_mcspi_set_master_mode(master);
1068	1049	omap2_mcspi_disable_clocks(mcspi);
@@ -1102,14 +1083,13 @@ static const struct of_device_id omap_mcspi_of_match[] = { · 33 unmodified lines
1102	1083	};
1103	1084	MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1104	1085
1105		−static int __init omap2_mcspi_probe(struct platform_device *pdev)
	1086	+static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
1106	1087	{
1107	1088	struct spi_master *master;
1108	1089	struct omap2_mcspi_platform_config *pdata;
1109	1090	struct omap2_mcspi *mcspi;
1110	1091	struct resource *r;
1111	1092	int status = 0, i;
1112		− char wq_name[20];
1113	1093	u32 regs_offset = 0;
1114	1094	static int bus_num = 1;
1115	1095	struct device_node *node = pdev->dev.of_node;
@@ -1125,7 +1105,9 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) · 9 unmodified lines
1125	1105	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
1126	1106
1127	1107	master->setup = omap2_mcspi_setup;
1128		− master->transfer = omap2_mcspi_transfer;
	1108	+ master->prepare_transfer_hardware = omap2_prepare_transfer;
	1109	+ master->unprepare_transfer_hardware = omap2_unprepare_transfer;
	1110	+ master->transfer_one_message = omap2_mcspi_transfer_one_message;
1129	1111	master->cleanup = omap2_mcspi_cleanup;
1130	1112	master->dev.of_node = node;
1131	1113
@@ -1150,13 +1132,6 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) · 18 unmodified lines
1150	1132	mcspi = spi_master_get_devdata(master);
1151	1133	mcspi->master = master;
1152	1134
1153		− sprintf(wq_name, "omap2_mcspi/%d", master->bus_num);
1154		− mcspi->wq = alloc_workqueue(wq_name, WQ_MEM_RECLAIM, 1);
1155		− if (mcspi->wq == NULL) {
1156		− status = -ENOMEM;
1157		− goto free_master;
1158		− }
1159		−
1160	1135	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1161	1136	if (r == NULL) {
1162	1137	status = -ENODEV;
@@ -1166,32 +1141,24 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) · 3 unmodified lines
1166	1141	r->start += regs_offset;
1167	1142	r->end += regs_offset;
1168	1143	mcspi->phys = r->start;
1169		− if (!request_mem_region(r->start, resource_size(r),
1170		− dev_name(&pdev->dev))) {
1171		− status = -EBUSY;
1172		− goto free_master;
1173		− }
1174	1144
1175		− mcspi->base = ioremap(r->start, resource_size(r));
	1145	+ mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
1176	1146	if (!mcspi->base) {
1177	1147	dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1178	1148	status = -ENOMEM;
1179		− goto release_region;
	1149	+ goto free_master;
1180	1150	}
1181	1151
1182	1152	mcspi->dev = &pdev->dev;
1183		− INIT_WORK(&mcspi->work, omap2_mcspi_work);
1184	1153
1185		− spin_lock_init(&mcspi->lock);
1186		− INIT_LIST_HEAD(&mcspi->msg_queue);
1187		− INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
	1154	+ INIT_LIST_HEAD(&mcspi->ctx.cs);
1188	1155
1189	1156	mcspi->dma_channels = kcalloc(master->num_chipselect,
1190	1157	sizeof(struct omap2_mcspi_dma),
1191	1158	GFP_KERNEL);
1192	1159
1193	1160	if (mcspi->dma_channels == NULL)
1194		− goto unmap_io;
	1161	+ goto free_master;
1195	1162
1196	1163	for (i = 0; i < master->num_chipselect; i++) {
1197	1164	char dma_ch_name[14];
@@ -1224,6 +1191,8 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) · 26 unmodified lines
1224	1191	if (status < 0)
1225	1192	goto dma_chnl_free;
1226	1193
	1194	+ pm_runtime_use_autosuspend(&pdev->dev);
	1195	+ pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1227	1196	pm_runtime_enable(&pdev->dev);
1228	1197
1229	1198	if (status \|\| omap2_mcspi_master_setup(mcspi) < 0)
@@ -1241,23 +1210,17 @@ disable_pm: · 11 unmodified lines
1241	1210	pm_runtime_disable(&pdev->dev);
1242	1211	dma_chnl_free:
1243	1212	kfree(mcspi->dma_channels);
1244		−unmap_io:
1245		− iounmap(mcspi->base);
1246		−release_region:
1247		− release_mem_region(r->start, resource_size(r));
1248	1213	free_master:
1249	1214	kfree(master);
1250	1215	platform_set_drvdata(pdev, NULL);
1251	1216	return status;
1252	1217	}
1253	1218
1254		−static int __exit omap2_mcspi_remove(struct platform_device *pdev)
	1219	+static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
1255	1220	{
1256	1221	struct spi_master *master;
1257	1222	struct omap2_mcspi *mcspi;
1258	1223	struct omap2_mcspi_dma *dma_channels;
1259		− struct resource *r;
1260		− void __iomem *base;
1261	1224
1262	1225	master = dev_get_drvdata(&pdev->dev);
1263	1226	mcspi = spi_master_get_devdata(master);
@@ -1265,14 +1228,9 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev) · 1 unmodified line
1265	1228
1266	1229	omap2_mcspi_disable_clocks(mcspi);
1267	1230	pm_runtime_disable(&pdev->dev);
1268		− r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1269		− release_mem_region(r->start, resource_size(r));
1270	1231
1271		− base = mcspi->base;
1272	1232	spi_unregister_master(master);
1273		− iounmap(base);
1274	1233	kfree(dma_channels);
1275		− destroy_workqueue(mcspi->wq);
1276	1234	platform_set_drvdata(pdev, NULL);
1277	1235
1278	1236	return 0;
@@ -1291,13 +1249,12 @@ static int omap2_mcspi_resume(struct device *dev) · 12 unmodified lines
1291	1249	{
1292	1250	struct spi_master *master = dev_get_drvdata(dev);
1293	1251	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1294		− struct omap2_mcspi_cs *cs;
	1252	+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
	1253	+ struct omap2_mcspi_cs *cs;
1295	1254
1296	1255	omap2_mcspi_enable_clocks(mcspi);
1297		− list_for_each_entry(cs, &omap2_mcspi_ctx[master->bus_num - 1].cs,
1298		− node) {
	1256	+ list_for_each_entry(cs, &ctx->cs, node) {
1299	1257	if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1300		−
1301	1258	/*
1302	1259	* We need to toggle CS state for OMAP take this
1303	1260	* change in account.
@@ -1327,21 +1284,9 @@ static struct platform_driver omap2_mcspi_driver = { · 23 unmodified lines
1327	1284	.pm = &omap2_mcspi_pm_ops,
1328	1285	.of_match_table = omap_mcspi_of_match,
1329	1286	},
1330		− .remove = __exit_p(omap2_mcspi_remove),
	1287	+ .probe = omap2_mcspi_probe,
	1288	+ .remove = __devexit_p(omap2_mcspi_remove),
1331	1289	};
1332	1290
1333		−
1334		−static int __init omap2_mcspi_init(void)
1335		−{
1336		− return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1337		−}
1338		−subsys_initcall(omap2_mcspi_init);
1339		−
1340		−static void __exit omap2_mcspi_exit(void)
1341		−{
1342		− platform_driver_unregister(&omap2_mcspi_driver);
1343		−
1344		−}
1345		−module_exit(omap2_mcspi_exit);
1346		−
	1291	+module_platform_driver(omap2_mcspi_driver);
1347	1292	MODULE_LICENSE("GPL");

drivers/spi/spi-ppc4xx.c+0−4

@@ -30,7 +30,6 @@ · 29 unmodified lines
30	30	#include <linux/errno.h>
31	31	#include <linux/wait.h>
32	32	#include <linux/of_platform.h>
33		−#include <linux/of_spi.h>
34	33	#include <linux/of_gpio.h>
35	34	#include <linux/interrupt.h>
36	35	#include <linux/delay.h>
@@ -467,9 +466,6 @@ static int __init spi_ppc4xx_of_probe(struct platform_device *op) · 430 unmodified lines
467	466	bbp->master->setup = spi_ppc4xx_setup;
468	467	bbp->master->cleanup = spi_ppc4xx_cleanup;
469	468
470		− /* Allocate bus num dynamically. */
471		− bbp->master->bus_num = -1;
472		−
473	469	/* the spi->mode bits understood by this driver: */
474	470	bbp->master->mode_bits =
475	471	SPI_CPHA \| SPI_CPOL \| SPI_CS_HIGH \| SPI_LSB_FIRST;

drivers/spi/spi-pxa2xx-pci.c+1−11

@@ -164,17 +164,7 @@ static struct pci_driver ce4100_spi_driver = { · 163 unmodified lines
164	164	.remove = __devexit_p(ce4100_spi_remove),
165	165	};
166	166
167		−static int __init ce4100_spi_init(void)
168		−{
169		− return pci_register_driver(&ce4100_spi_driver);
170		−}
171		−module_init(ce4100_spi_init);
172		−
173		−static void __exit ce4100_spi_exit(void)
174		−{
175		− pci_unregister_driver(&ce4100_spi_driver);
176		−}
177		−module_exit(ce4100_spi_exit);
	167	+module_pci_driver(ce4100_spi_driver);
178	168
179	169	MODULE_DESCRIPTION("CE4100 PCI-SPI glue code for PXA's driver");
180	170	MODULE_LICENSE("GPL v2");

drivers/spi/spi-rspi.c+314−6

@@ -31,7 +31,11 @@ · 30 unmodified lines
31	31	#include <linux/platform_device.h>
32	32	#include <linux/io.h>
33	33	#include <linux/clk.h>
	34	+#include <linux/dmaengine.h>
	35	+#include <linux/dma-mapping.h>
	36	+#include <linux/sh_dma.h>
34	37	#include <linux/spi/spi.h>
	38	+#include <linux/spi/rspi.h>
35	39
36	40	#define RSPI_SPCR 0x00
37	41	#define RSPI_SSLP 0x01
@@ -141,6 +145,16 @@ struct rspi_data { · 103 unmodified lines
141	145	spinlock_t lock;
142	146	struct clk *clk;
143	147	unsigned char spsr;
	148	+
	149	+ /* for dmaengine */
	150	+ struct sh_dmae_slave dma_tx;
	151	+ struct sh_dmae_slave dma_rx;
	152	+ struct dma_chan *chan_tx;
	153	+ struct dma_chan *chan_rx;
	154	+ int irq;
	155	+
	156	+ unsigned dma_width_16bit:1;
	157	+ unsigned dma_callbacked:1;
144	158	};
145	159
146	160	static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset)
@@ -265,11 +279,125 @@ static int rspi_send_pio(struct rspi_data rspi, struct spi_message mesg, · 118 unmodified lines
265	279	return 0;
266	280	}
267	281
268		−static int rspi_receive_pio(struct rspi_data rspi, struct spi_message mesg,
269		− struct spi_transfer *t)
	282	+static void rspi_dma_complete(void *arg)
	283	+{
	284	+ struct rspi_data *rspi = arg;
	285	+
	286	+ rspi->dma_callbacked = 1;
	287	+ wake_up_interruptible(&rspi->wait);
	288	+}
	289	+
	290	+static int rspi_dma_map_sg(struct scatterlist sg, void buf, unsigned len,
	291	+ struct dma_chan *chan,
	292	+ enum dma_transfer_direction dir)
	293	+{
	294	+ sg_init_table(sg, 1);
	295	+ sg_set_buf(sg, buf, len);
	296	+ sg_dma_len(sg) = len;
	297	+ return dma_map_sg(chan->device->dev, sg, 1, dir);
	298	+}
	299	+
	300	+static void rspi_dma_unmap_sg(struct scatterlist sg, struct dma_chan chan,
	301	+ enum dma_transfer_direction dir)
	302	+{
	303	+ dma_unmap_sg(chan->device->dev, sg, 1, dir);
	304	+}
	305	+
	306	+static void rspi_memory_to_8bit(void buf, const void data, unsigned len)
	307	+{
	308	+ u16 *dst = buf;
	309	+ const u8 *src = data;
	310	+
	311	+ while (len) {
	312	+ dst++ = (u16)(src++);
	313	+ len--;
	314	+ }
	315	+}
	316	+
	317	+static void rspi_memory_from_8bit(void buf, const void data, unsigned len)
	318	+{
	319	+ u8 *dst = buf;
	320	+ const u16 *src = data;
	321	+
	322	+ while (len) {
	323	+ dst++ = (u8)src++;
	324	+ len--;
	325	+ }
	326	+}
	327	+
	328	+static int rspi_send_dma(struct rspi_data rspi, struct spi_transfer t)
	329	+{
	330	+ struct scatterlist sg;
	331	+ void *buf = NULL;
	332	+ struct dma_async_tx_descriptor *desc;
	333	+ unsigned len;
	334	+ int ret = 0;
	335	+
	336	+ if (rspi->dma_width_16bit) {
	337	+ /*
	338	+ * If DMAC bus width is 16-bit, the driver allocates a dummy
	339	+ * buffer. And, the driver converts original data into the
	340	+ * DMAC data as the following format:
	341	+ * original data: 1st byte, 2nd byte ...
	342	+ * DMAC data: 1st byte, dummy, 2nd byte, dummy ...
	343	+ */
	344	+ len = t->len * 2;
	345	+ buf = kmalloc(len, GFP_KERNEL);
	346	+ if (!buf)
	347	+ return -ENOMEM;
	348	+ rspi_memory_to_8bit(buf, t->tx_buf, t->len);
	349	+ } else {
	350	+ len = t->len;
	351	+ buf = (void *)t->tx_buf;
	352	+ }
	353	+
	354	+ if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) {
	355	+ ret = -EFAULT;
	356	+ goto end_nomap;
	357	+ }
	358	+ desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE,
	359	+ DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	360	+ if (!desc) {
	361	+ ret = -EIO;
	362	+ goto end;
	363	+ }
	364	+
	365	+ /*
	366	+ * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
	367	+ * called. So, this driver disables the IRQ while DMA transfer.
	368	+ */
	369	+ disable_irq(rspi->irq);
	370	+
	371	+ rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) \| SPCR_TXMD, RSPI_SPCR);
	372	+ rspi_enable_irq(rspi, SPCR_SPTIE);
	373	+ rspi->dma_callbacked = 0;
	374	+
	375	+ desc->callback = rspi_dma_complete;
	376	+ desc->callback_param = rspi;
	377	+ dmaengine_submit(desc);
	378	+ dma_async_issue_pending(rspi->chan_tx);
	379	+
	380	+ ret = wait_event_interruptible_timeout(rspi->wait,
	381	+ rspi->dma_callbacked, HZ);
	382	+ if (ret > 0 && rspi->dma_callbacked)
	383	+ ret = 0;
	384	+ else if (!ret)
	385	+ ret = -ETIMEDOUT;
	386	+ rspi_disable_irq(rspi, SPCR_SPTIE);
	387	+
	388	+ enable_irq(rspi->irq);
	389	+
	390	+end:
	391	+ rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE);
	392	+end_nomap:
	393	+ if (rspi->dma_width_16bit)
	394	+ kfree(buf);
	395	+
	396	+ return ret;
	397	+}
	398	+
	399	+static void rspi_receive_init(struct rspi_data *rspi)
270	400	{
271		− int remain = t->len;
272		− u8 *data;
273	401	unsigned char spsr;
274	402
275	403	spsr = rspi_read8(rspi, RSPI_SPSR);
@@ -278,6 +406,15 @@ static int rspi_receive_pio(struct rspi_data rspi, struct spi_message mesg, · 2 unmodified lines
278	406	if (spsr & SPSR_OVRF)
279	407	rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
280	408	RSPI_SPCR);
	409	+}
	410	+
	411	+static int rspi_receive_pio(struct rspi_data rspi, struct spi_message mesg,
	412	+ struct spi_transfer *t)
	413	+{
	414	+ int remain = t->len;
	415	+ u8 *data;
	416	+
	417	+ rspi_receive_init(rspi);
281	418
282	419	data = (u8 *)t->rx_buf;
283	420	while (remain > 0) {
@@ -307,6 +444,120 @@ static int rspi_receive_pio(struct rspi_data rspi, struct spi_message mesg, · 23 unmodified lines
307	444	return 0;
308	445	}
309	446
	447	+static int rspi_receive_dma(struct rspi_data rspi, struct spi_transfer t)
	448	+{
	449	+ struct scatterlist sg, sg_dummy;
	450	+ void dummy = NULL, rx_buf = NULL;
	451	+ struct dma_async_tx_descriptor desc, desc_dummy;
	452	+ unsigned len;
	453	+ int ret = 0;
	454	+
	455	+ if (rspi->dma_width_16bit) {
	456	+ /*
	457	+ * If DMAC bus width is 16-bit, the driver allocates a dummy
	458	+ * buffer. And, finally the driver converts the DMAC data into
	459	+ * actual data as the following format:
	460	+ * DMAC data: 1st byte, dummy, 2nd byte, dummy ...
	461	+ * actual data: 1st byte, 2nd byte ...
	462	+ */
	463	+ len = t->len * 2;
	464	+ rx_buf = kmalloc(len, GFP_KERNEL);
	465	+ if (!rx_buf)
	466	+ return -ENOMEM;
	467	+ } else {
	468	+ len = t->len;
	469	+ rx_buf = t->rx_buf;
	470	+ }
	471	+
	472	+ /* prepare dummy transfer to generate SPI clocks */
	473	+ dummy = kzalloc(len, GFP_KERNEL);
	474	+ if (!dummy) {
	475	+ ret = -ENOMEM;
	476	+ goto end_nomap;
	477	+ }
	478	+ if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx,
	479	+ DMA_TO_DEVICE)) {
	480	+ ret = -EFAULT;
	481	+ goto end_nomap;
	482	+ }
	483	+ desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1,
	484	+ DMA_TO_DEVICE, DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	485	+ if (!desc_dummy) {
	486	+ ret = -EIO;
	487	+ goto end_dummy_mapped;
	488	+ }
	489	+
	490	+ /* prepare receive transfer */
	491	+ if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx,
	492	+ DMA_FROM_DEVICE)) {
	493	+ ret = -EFAULT;
	494	+ goto end_dummy_mapped;
	495	+
	496	+ }
	497	+ desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE,
	498	+ DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	499	+ if (!desc) {
	500	+ ret = -EIO;
	501	+ goto end;
	502	+ }
	503	+
	504	+ rspi_receive_init(rspi);
	505	+
	506	+ /*
	507	+ * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
	508	+ * called. So, this driver disables the IRQ while DMA transfer.
	509	+ */
	510	+ disable_irq(rspi->irq);
	511	+
	512	+ rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR);
	513	+ rspi_enable_irq(rspi, SPCR_SPTIE \| SPCR_SPRIE);
	514	+ rspi->dma_callbacked = 0;
	515	+
	516	+ desc->callback = rspi_dma_complete;
	517	+ desc->callback_param = rspi;
	518	+ dmaengine_submit(desc);
	519	+ dma_async_issue_pending(rspi->chan_rx);
	520	+
	521	+ desc_dummy->callback = NULL; /* No callback */
	522	+ dmaengine_submit(desc_dummy);
	523	+ dma_async_issue_pending(rspi->chan_tx);
	524	+
	525	+ ret = wait_event_interruptible_timeout(rspi->wait,
	526	+ rspi->dma_callbacked, HZ);
	527	+ if (ret > 0 && rspi->dma_callbacked)
	528	+ ret = 0;
	529	+ else if (!ret)
	530	+ ret = -ETIMEDOUT;
	531	+ rspi_disable_irq(rspi, SPCR_SPTIE \| SPCR_SPRIE);
	532	+
	533	+ enable_irq(rspi->irq);
	534	+
	535	+end:
	536	+ rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE);
	537	+end_dummy_mapped:
	538	+ rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE);
	539	+end_nomap:
	540	+ if (rspi->dma_width_16bit) {
	541	+ if (!ret)
	542	+ rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len);
	543	+ kfree(rx_buf);
	544	+ }
	545	+ kfree(dummy);
	546	+
	547	+ return ret;
	548	+}
	549	+
	550	+static int rspi_is_dma(struct rspi_data rspi, struct spi_transfer t)
	551	+{
	552	+ if (t->tx_buf && rspi->chan_tx)
	553	+ return 1;
	554	+ /* If the module receives data by DMAC, it also needs TX DMAC */
	555	+ if (t->rx_buf && rspi->chan_tx && rspi->chan_rx)
	556	+ return 1;
	557	+
	558	+ return 0;
	559	+}
	560	+
310	561	static void rspi_work(struct work_struct *work)
311	562	{
312	563	struct rspi_data *rspi = container_of(work, struct rspi_data, ws);
@@ -325,12 +576,18 @@ static void rspi_work(struct work_struct *work) · 12 unmodified lines
325	576
326	577	list_for_each_entry(t, &mesg->transfers, transfer_list) {
327	578	if (t->tx_buf) {
328		− ret = rspi_send_pio(rspi, mesg, t);
	579	+ if (rspi_is_dma(rspi, t))
	580	+ ret = rspi_send_dma(rspi, t);
	581	+ else
	582	+ ret = rspi_send_pio(rspi, mesg, t);
329	583	if (ret < 0)
330	584	goto error;
331	585	}
332	586	if (t->rx_buf) {
333		− ret = rspi_receive_pio(rspi, mesg, t);
	587	+ if (rspi_is_dma(rspi, t))
	588	+ ret = rspi_receive_dma(rspi, t);
	589	+ else
	590	+ ret = rspi_receive_pio(rspi, mesg, t);
334	591	if (ret < 0)
335	592	goto error;
336	593	}
@@ -406,11 +663,58 @@ static irqreturn_t rspi_irq(int irq, void *_sr) · 69 unmodified lines
406	663	return ret;
407	664	}
408	665
	666	+static bool rspi_filter(struct dma_chan chan, void filter_param)
	667	+{
	668	+ chan->private = filter_param;
	669	+ return true;
	670	+}
	671	+
	672	+static void __devinit rspi_request_dma(struct rspi_data *rspi,
	673	+ struct platform_device *pdev)
	674	+{
	675	+ struct rspi_plat_data *rspi_pd = pdev->dev.platform_data;
	676	+ dma_cap_mask_t mask;
	677	+
	678	+ if (!rspi_pd)
	679	+ return;
	680	+
	681	+ rspi->dma_width_16bit = rspi_pd->dma_width_16bit;
	682	+
	683	+ /* If the module receives data by DMAC, it also needs TX DMAC */
	684	+ if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) {
	685	+ dma_cap_zero(mask);
	686	+ dma_cap_set(DMA_SLAVE, mask);
	687	+ rspi->dma_rx.slave_id = rspi_pd->dma_rx_id;
	688	+ rspi->chan_rx = dma_request_channel(mask, rspi_filter,
	689	+ &rspi->dma_rx);
	690	+ if (rspi->chan_rx)
	691	+ dev_info(&pdev->dev, "Use DMA when rx.\n");
	692	+ }
	693	+ if (rspi_pd->dma_tx_id) {
	694	+ dma_cap_zero(mask);
	695	+ dma_cap_set(DMA_SLAVE, mask);
	696	+ rspi->dma_tx.slave_id = rspi_pd->dma_tx_id;
	697	+ rspi->chan_tx = dma_request_channel(mask, rspi_filter,
	698	+ &rspi->dma_tx);
	699	+ if (rspi->chan_tx)
	700	+ dev_info(&pdev->dev, "Use DMA when tx\n");
	701	+ }
	702	+}
	703	+
	704	+static void __devexit rspi_release_dma(struct rspi_data *rspi)
	705	+{
	706	+ if (rspi->chan_tx)
	707	+ dma_release_channel(rspi->chan_tx);
	708	+ if (rspi->chan_rx)
	709	+ dma_release_channel(rspi->chan_rx);
	710	+}
	711	+
409	712	static int __devexit rspi_remove(struct platform_device *pdev)
410	713	{
411	714	struct rspi_data *rspi = dev_get_drvdata(&pdev->dev);
412	715
413	716	spi_unregister_master(rspi->master);
	717	+ rspi_release_dma(rspi);
414	718	free_irq(platform_get_irq(pdev, 0), rspi);
415	719	clk_put(rspi->clk);
416	720	iounmap(rspi->addr);
@@ -483,6 +787,9 @@ static int __devinit rspi_probe(struct platform_device *pdev) · 66 unmodified lines
483	787	goto error3;
484	788	}
485	789
	790	+ rspi->irq = irq;
	791	+ rspi_request_dma(rspi, pdev);
	792	+
486	793	ret = spi_register_master(master);
487	794	if (ret < 0) {
488	795	dev_err(&pdev->dev, "spi_register_master error.\n");
@@ -494,6 +801,7 @@ static int __devinit rspi_probe(struct platform_device *pdev) · 5 unmodified lines
494	801	return 0;
495	802
496	803	error4:
	804	+ rspi_release_dma(rspi);
497	805	free_irq(irq, rspi);
498	806	error3:
499	807	clk_put(rspi->clk);

drivers/spi/spi-sirf.c+8−12

@@ -19,7 +19,7 @@ · 18 unmodified lines
19	19	#include <linux/of_gpio.h>
20	20	#include <linux/spi/spi.h>
21	21	#include <linux/spi/spi_bitbang.h>
22		−#include <linux/pinctrl/pinmux.h>
	22	+#include <linux/pinctrl/consumer.h>
23	23
24	24	#define DRIVER_NAME "sirfsoc_spi"
25	25
@@ -127,7 +127,7 @@ struct sirfsoc_spi { · 101 unmodified lines
127	127	void __iomem *base;
128	128	u32 ctrl_freq; /* SPI controller clock speed */
129	129	struct clk *clk;
130		− struct pinmux *pmx;
	130	+ struct pinctrl *p;
131	131
132	132	/* rx & tx bufs from the spi_transfer */
133	133	const void *tx;
@@ -560,17 +560,15 @@ static int __devinit spi_sirfsoc_probe(struct platform_device *pdev) · 426 unmodified lines
560	560	master->bus_num = pdev->id;
561	561	sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
562	562
563		− sspi->pmx = pinmux_get(&pdev->dev, NULL);
564		− ret = IS_ERR(sspi->pmx);
	563	+ sspi->p = pinctrl_get_select_default(&pdev->dev);
	564	+ ret = IS_ERR(sspi->p);
565	565	if (ret)
566	566	goto free_master;
567	567
568		− pinmux_enable(sspi->pmx);
569		−
570	568	sspi->clk = clk_get(&pdev->dev, NULL);
571	569	if (IS_ERR(sspi->clk)) {
572	570	ret = -EINVAL;
573		− goto free_pmx;
	571	+ goto free_pin;
574	572	}
575	573	clk_enable(sspi->clk);
576	574	sspi->ctrl_freq = clk_get_rate(sspi->clk);
@@ -598,9 +596,8 @@ static int __devinit spi_sirfsoc_probe(struct platform_device *pdev) · 21 unmodified lines
598	596	free_clk:
599	597	clk_disable(sspi->clk);
600	598	clk_put(sspi->clk);
601		−free_pmx:
602		− pinmux_disable(sspi->pmx);
603		− pinmux_put(sspi->pmx);
	599	+free_pin:
	600	+ pinctrl_put(sspi->p);
604	601	free_master:
605	602	spi_master_put(master);
606	603	err_cs:
@@ -623,8 +620,7 @@ static int __devexit spi_sirfsoc_remove(struct platform_device *pdev) · 16 unmodified lines
623	620	}
624	621	clk_disable(sspi->clk);
625	622	clk_put(sspi->clk);
626		− pinmux_disable(sspi->pmx);
627		− pinmux_put(sspi->pmx);
	623	+ pinctrl_put(sspi->p);
628	624	spi_master_put(master);
629	625	return 0;
630	626	}

drivers/spi/spi-topcliff-pch.c+1−2

@@ -1438,7 +1438,6 @@ static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev) · 1437 unmodified lines
1438	1438	plat_dev->id, data->io_remap_addr);
1439	1439
1440	1440	/* initialize members of SPI master */
1441		− master->bus_num = -1;
1442	1441	master->num_chipselect = PCH_MAX_CS;
1443	1442	master->setup = pch_spi_setup;
1444	1443	master->transfer = pch_spi_transfer;
@@ -1779,7 +1778,7 @@ static struct pci_driver pch_spi_pcidev_driver = { · 334 unmodified lines
1779	1778	.name = "pch_spi",
1780	1779	.id_table = pch_spi_pcidev_id,
1781	1780	.probe = pch_spi_probe,
1782		− .remove = pch_spi_remove,
	1781	+ .remove = __devexit_p(pch_spi_remove),
1783	1782	.suspend = pch_spi_suspend,
1784	1783	.resume = pch_spi_resume,
1785	1784	};

drivers/spi/spi.c+95−3

@@ -2,6 +2,7 @@ · 1 unmodified line
2	2	* SPI init/core code
3	3	*
4	4	* Copyright (C) 2005 David Brownell
	5	+ * Copyright (C) 2008 Secret Lab Technologies Ltd.
5	6	*
6	7	* This program is free software; you can redistribute it and/or modify
7	8	* it under the terms of the GNU General Public License as published by
@@ -19,15 +20,16 @@ · 11 unmodified lines
19	20	*/
20	21
21	22	#include <linux/kernel.h>
	23	+#include <linux/kmod.h>
22	24	#include <linux/device.h>
23	25	#include <linux/init.h>
24	26	#include <linux/cache.h>
25	27	#include <linux/mutex.h>
26	28	#include <linux/of_device.h>
	29	+#include <linux/of_irq.h>
27	30	#include <linux/slab.h>
28	31	#include <linux/mod_devicetable.h>
29	32	#include <linux/spi/spi.h>
30		−#include <linux/of_spi.h>
31	33	#include <linux/pm_runtime.h>
32	34	#include <linux/export.h>
33	35	#include <linux/sched.h>
@@ -530,7 +532,7 @@ static void spi_pump_messages(struct kthread_work *work) · 496 unmodified lines
530	532	/* Lock queue and check for queue work */
531	533	spin_lock_irqsave(&master->queue_lock, flags);
532	534	if (list_empty(&master->queue) \|\| !master->running) {
533		− if (master->busy) {
	535	+ if (master->busy && master->unprepare_transfer_hardware) {
534	536	ret = master->unprepare_transfer_hardware(master);
535	537	if (ret) {
536	538	spin_unlock_irqrestore(&master->queue_lock, flags);
@@ -560,7 +562,7 @@ static void spi_pump_messages(struct kthread_work *work) · 23 unmodified lines
560	562	master->busy = true;
561	563	spin_unlock_irqrestore(&master->queue_lock, flags);
562	564
563		− if (!was_busy) {
	565	+ if (!was_busy && master->prepare_transfer_hardware) {
564	566	ret = master->prepare_transfer_hardware(master);
565	567	if (ret) {
566	568	dev_err(&master->dev,
@@ -798,6 +800,94 @@ err_init_queue: · 231 unmodified lines
798	800
799	801	/-------------------------------------------------------------------------/
800	802
	803	+#if defined(CONFIG_OF) && !defined(CONFIG_SPARC)
	804	+/**
	805	+ * of_register_spi_devices() - Register child devices onto the SPI bus
	806	+ * @master: Pointer to spi_master device
	807	+ *
	808	+ * Registers an spi_device for each child node of master node which has a 'reg'
	809	+ * property.
	810	+ */
	811	+static void of_register_spi_devices(struct spi_master *master)
	812	+{
	813	+ struct spi_device *spi;
	814	+ struct device_node *nc;
	815	+ const __be32 *prop;
	816	+ int rc;
	817	+ int len;
	818	+
	819	+ if (!master->dev.of_node)
	820	+ return;
	821	+
	822	+ for_each_child_of_node(master->dev.of_node, nc) {
	823	+ /* Alloc an spi_device */
	824	+ spi = spi_alloc_device(master);
	825	+ if (!spi) {
	826	+ dev_err(&master->dev, "spi_device alloc error for %s\n",
	827	+ nc->full_name);
	828	+ spi_dev_put(spi);
	829	+ continue;
	830	+ }
	831	+
	832	+ /* Select device driver */
	833	+ if (of_modalias_node(nc, spi->modalias,
	834	+ sizeof(spi->modalias)) < 0) {
	835	+ dev_err(&master->dev, "cannot find modalias for %s\n",
	836	+ nc->full_name);
	837	+ spi_dev_put(spi);
	838	+ continue;
	839	+ }
	840	+
	841	+ /* Device address */
	842	+ prop = of_get_property(nc, "reg", &len);
	843	+ if (!prop \|\| len < sizeof(*prop)) {
	844	+ dev_err(&master->dev, "%s has no 'reg' property\n",
	845	+ nc->full_name);
	846	+ spi_dev_put(spi);
	847	+ continue;
	848	+ }
	849	+ spi->chip_select = be32_to_cpup(prop);
	850	+
	851	+ /* Mode (clock phase/polarity/etc.) */
	852	+ if (of_find_property(nc, "spi-cpha", NULL))
	853	+ spi->mode \|= SPI_CPHA;
	854	+ if (of_find_property(nc, "spi-cpol", NULL))
	855	+ spi->mode \|= SPI_CPOL;
	856	+ if (of_find_property(nc, "spi-cs-high", NULL))
	857	+ spi->mode \|= SPI_CS_HIGH;
	858	+
	859	+ /* Device speed */
	860	+ prop = of_get_property(nc, "spi-max-frequency", &len);
	861	+ if (!prop \|\| len < sizeof(*prop)) {
	862	+ dev_err(&master->dev, "%s has no 'spi-max-frequency' property\n",
	863	+ nc->full_name);
	864	+ spi_dev_put(spi);
	865	+ continue;
	866	+ }
	867	+ spi->max_speed_hz = be32_to_cpup(prop);
	868	+
	869	+ /* IRQ */
	870	+ spi->irq = irq_of_parse_and_map(nc, 0);
	871	+
	872	+ /* Store a pointer to the node in the device structure */
	873	+ of_node_get(nc);
	874	+ spi->dev.of_node = nc;
	875	+
	876	+ /* Register the new device */
	877	+ request_module(spi->modalias);
	878	+ rc = spi_add_device(spi);
	879	+ if (rc) {
	880	+ dev_err(&master->dev, "spi_device register error %s\n",
	881	+ nc->full_name);
	882	+ spi_dev_put(spi);
	883	+ }
	884	+
	885	+ }
	886	+}
	887	+#else
	888	+static void of_register_spi_devices(struct spi_master *master) { }
	889	+#endif
	890	+
801	891	static void spi_master_release(struct device *dev)
802	892	{
803	893	struct spi_master *master;
@@ -846,6 +936,8 @@ struct spi_master spi_alloc_master(struct device dev, unsigned size) · 42 unmodified lines
846	936	return NULL;
847	937
848	938	device_initialize(&master->dev);
	939	+ master->bus_num = -1;
	940	+ master->num_chipselect = 1;
849	941	master->dev.class = &spi_master_class;
850	942	master->dev.parent = get_device(dev);
851	943	spi_master_set_devdata(master, &master[1]);

include/linux/of_spi.h+0−23

@@ -1,23 +0,0 @@
1		−/*
2		− * OpenFirmware SPI support routines
3		− * Copyright (C) 2008 Secret Lab Technologies Ltd.
4		− *
5		− * Support routines for deriving SPI device attachments from the device
6		− * tree.
7		− */
8		−
9		−#ifndef __LINUX_OF_SPI_H
10		−#define __LINUX_OF_SPI_H
11		−
12		−#include <linux/spi/spi.h>
13		−
14		−#if defined(CONFIG_OF_SPI) \|\| defined(CONFIG_OF_SPI_MODULE)
15		−extern void of_register_spi_devices(struct spi_master *master);
16		−#else
17		−static inline void of_register_spi_devices(struct spi_master *master)
18		−{
19		− return;
20		−}
21		−#endif /* CONFIG_OF_SPI */
22		−
23		−#endif /* __LINUX_OF_SPI */

include/linux/spi/rspi.h+31−0

@@ -0,0 +1,31 @@
	1	+/*
	2	+ * Renesas SPI driver
	3	+ *
	4	+ * Copyright (C) 2012 Renesas Solutions Corp.
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or modify
	7	+ * it under the terms of the GNU General Public License as published by
	8	+ * the Free Software Foundation; version 2 of the License.
	9	+ *
	10	+ * This program is distributed in the hope that it will be useful,
	11	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	+ * GNU General Public License for more details.
	14	+ *
	15	+ * You should have received a copy of the GNU General Public License
	16	+ * along with this program; if not, write to the Free Software
	17	+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	18	+ *
	19	+ */
	20	+
	21	+#ifndef __LINUX_SPI_RENESAS_SPI_H__
	22	+#define __LINUX_SPI_RENESAS_SPI_H__
	23	+
	24	+struct rspi_plat_data {
	25	+ unsigned int dma_tx_id;
	26	+ unsigned int dma_rx_id;
	27	+
	28	+ unsigned dma_width_16bit:1; /* DMAC read/write width = 16-bit */
	29	+};
	30	+
	31	+#endif