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accel/amdxdna: Add hardware context

The hardware can be shared among multiple user applications. The hardware resources are allocated/freed based on the request from user application via driver IOCTLs. DRM_IOCTL_AMDXDNA_CREATE_HWCTX Allocate tile columns and create a hardware context structure to track the usage and status of the resources. A hardware context ID is returned for XDNA command execution. DRM_IOCTL_AMDXDNA_DESTROY_HWCTX Release hardware context based on its ID. The tile columns belong to this hardware context will be reclaimed. DRM_IOCTL_AMDXDNA_CONFIG_HWCTX Config hardware context. Bind the hardware context to the required resources.

Lizhi Hou committed 1 year ago

Commit be462c91 parent c88d33210 files · +867 −1Browse files

Showing the changes to include/uapi (1 of 10 files). Show all

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include/uapi/drm/amdxdna_accel.h+131−0
@@ -6,17 +6,148 @@ · 5 unmodified lines
6#ifndef _UAPI_AMDXDNA_ACCEL_H_6#ifndef _UAPI_AMDXDNA_ACCEL_H_
7#define _UAPI_AMDXDNA_ACCEL_H_7#define _UAPI_AMDXDNA_ACCEL_H_
8 8
9#include <linux/stddef.h>
9#include "drm.h"10#include "drm.h"
10 11
11#if defined(__cplusplus)12#if defined(__cplusplus)
12extern "C" {13extern "C" {
13#endif14#endif
14 15
16#define AMDXDNA_INVALID_CTX_HANDLE 0
17
15enum amdxdna_device_type {18enum amdxdna_device_type {
16 AMDXDNA_DEV_TYPE_UNKNOWN = -1,19 AMDXDNA_DEV_TYPE_UNKNOWN = -1,
17 AMDXDNA_DEV_TYPE_KMQ,20 AMDXDNA_DEV_TYPE_KMQ,
18};21};
19 22
23enum amdxdna_drm_ioctl_id {
24 DRM_AMDXDNA_CREATE_HWCTX,
25 DRM_AMDXDNA_DESTROY_HWCTX,
26 DRM_AMDXDNA_CONFIG_HWCTX,
27};
28
29/**
30 * struct qos_info - QoS information for driver.
31 * @gops: Giga operations per second.
32 * @fps: Frames per second.
33 * @dma_bandwidth: DMA bandwidtha.
34 * @latency: Frame response latency.
35 * @frame_exec_time: Frame execution time.
36 * @priority: Request priority.
37 *
38 * User program can provide QoS hints to driver.
39 */
40struct amdxdna_qos_info {
41 __u32 gops;
42 __u32 fps;
43 __u32 dma_bandwidth;
44 __u32 latency;
45 __u32 frame_exec_time;
46 __u32 priority;
47};
48
49/**
50 * struct amdxdna_drm_create_hwctx - Create hardware context.
51 * @ext: MBZ.
52 * @ext_flags: MBZ.
53 * @qos_p: Address of QoS info.
54 * @umq_bo: BO handle for user mode queue(UMQ).
55 * @log_buf_bo: BO handle for log buffer.
56 * @max_opc: Maximum operations per cycle.
57 * @num_tiles: Number of AIE tiles.
58 * @mem_size: Size of AIE tile memory.
59 * @umq_doorbell: Returned offset of doorbell associated with UMQ.
60 * @handle: Returned hardware context handle.
61 * @syncobj_handle: Returned syncobj handle for command completion.
62 */
63struct amdxdna_drm_create_hwctx {
64 __u64 ext;
65 __u64 ext_flags;
66 __u64 qos_p;
67 __u32 umq_bo;
68 __u32 log_buf_bo;
69 __u32 max_opc;
70 __u32 num_tiles;
71 __u32 mem_size;
72 __u32 umq_doorbell;
73 __u32 handle;
74 __u32 syncobj_handle;
75};
76
77/**
78 * struct amdxdna_drm_destroy_hwctx - Destroy hardware context.
79 * @handle: Hardware context handle.
80 * @pad: Structure padding.
81 */
82struct amdxdna_drm_destroy_hwctx {
83 __u32 handle;
84 __u32 pad;
85};
86
87/**
88 * struct amdxdna_cu_config - configuration for one CU
89 * @cu_bo: CU configuration buffer bo handle.
90 * @cu_func: Function of a CU.
91 * @pad: Structure padding.
92 */
93struct amdxdna_cu_config {
94 __u32 cu_bo;
95 __u8 cu_func;
96 __u8 pad[3];
97};
98
99/**
100 * struct amdxdna_hwctx_param_config_cu - configuration for CUs in hardware context
101 * @num_cus: Number of CUs to configure.
102 * @pad: Structure padding.
103 * @cu_configs: Array of CU configurations of struct amdxdna_cu_config.
104 */
105struct amdxdna_hwctx_param_config_cu {
106 __u16 num_cus;
107 __u16 pad[3];
108 struct amdxdna_cu_config cu_configs[] __counted_by(num_cus);
109};
110
111enum amdxdna_drm_config_hwctx_param {
112 DRM_AMDXDNA_HWCTX_CONFIG_CU,
113 DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF,
114 DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF,
115 DRM_AMDXDNA_HWCTX_CONFIG_NUM
116};
117
118/**
119 * struct amdxdna_drm_config_hwctx - Configure hardware context.
120 * @handle: hardware context handle.
121 * @param_type: Value in enum amdxdna_drm_config_hwctx_param. Specifies the
122 * structure passed in via param_val.
123 * @param_val: A structure specified by the param_type struct member.
124 * @param_val_size: Size of the parameter buffer pointed to by the param_val.
125 * If param_val is not a pointer, driver can ignore this.
126 * @pad: Structure padding.
127 *
128 * Note: if the param_val is a pointer pointing to a buffer, the maximum size
129 * of the buffer is 4KiB(PAGE_SIZE).
130 */
131struct amdxdna_drm_config_hwctx {
132 __u32 handle;
133 __u32 param_type;
134 __u64 param_val;
135 __u32 param_val_size;
136 __u32 pad;
137};
138
139#define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \
140 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \
141 struct amdxdna_drm_create_hwctx)
142
143#define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \
144 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \
145 struct amdxdna_drm_destroy_hwctx)
146
147#define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \
148 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \
149 struct amdxdna_drm_config_hwctx)
150
20#if defined(__cplusplus)151#if defined(__cplusplus)
21} /* extern c end */152} /* extern c end */
22#endif153#endif