Pull drm updates from Dave Airlie: "The biggest thing in this is the AMD Navi GPU support, this again contains a bunch of header files that are large. These are the new AMD RX5700 GPUs that just recently became available. New drivers: - ST-Ericsson MCDE driver - Ingenic JZ47xx SoC UAPI change: - HDR source metadata property Core: - HDR inforframes and EDID parsing - drm hdmi infoframe unpacking - remove prime sg_table caching into dma-buf - New gem vram helpers to reduce driver code - Lots of drmP.h removal - reservation fencing fix - documentation updates - drm_fb_helper_connector removed - mode name command handler rewrite fbcon: - Remove the fbcon notifiers ttm: - forward progress fixes dma-buf: - make mmap call optional - debugfs refcount fixes - dma-fence free with pending signals fix - each dma-buf gets an inode Panels: - Lots of additional panel bindings amdgpu: - initial navi10 support - avoid hw reset - HDR metadata support - new thermal sensors for vega asics - RAS fixes - use HMM rather than MMU notifier - xgmi topology via kfd - SR-IOV fixes - driver reload fixes - DC use a core bpc attribute - Aux fixes for DC - Bandwidth calc updates for DC - Clock handling refactor - kfd VEGAM support vmwgfx: - Coherent memory support changes i915: - HDR Support - HDMI i2c link - Icelake multi-segmented gamma support - GuC firmware update - Mule Creek Canyon PCH support for EHL - EHL platform updtes - move i915.alpha_support to i915.force_probe - runtime PM refactoring - VBT parsing refactoring - DSI fixes - struct mutex dependency reduction - GEM code reorg mali-dp: - Komeda driver features msm: - dsi vs EPROBE_DEFER fixes - msm8998 snapdragon 835 support - a540 gpu support - mdp5 and dpu interconnect support exynos: - drmP.h removal tegra: - misc fixes tda998x: - audio support improvements - pixel repeated mode support - quantisation range handling corrections - HDMI vendor info fix armada: - interlace support fix - overlay/video plane register handling refactor - add gamma support rockchip: - RX3328 support panfrost: - expose perf counters via hidden ioctls vkms: - enumerate CRC sources list ast: - rework BO handling mgag200: - rework BO handling dw-hdmi: - suspend/resume support rcar-du: - R8A774A1 Soc Support - LVDS dual-link mode support - Additional formats - Misc fixes omapdrm: - DSI command mode display support stm - fb modifier support - runtime PM support sun4i: - use vmap ops vc4: - binner bo binding rework v3d: - compute shader support - resync/sync fixes - job management refactoring lima: - NULL pointer in irq handler fix - scheduler default timeout virtio: - fence seqno support - trace events bochs: - misc fixes tc458767: - IRQ/HDP handling sii902x: - HDMI audio support atmel-hlcdc: - misc fixes meson: - zpos support" * tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm: (1815 commits) Revert "Merge branch 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux into drm-next" Revert "mm: adjust apply_to_pfn_range interface for dropped token." mm: adjust apply_to_pfn_range interface for dropped token. drm/amdgpu/navi10: add uclk activity sensor drm/amdgpu: properly guard the generic discovery code drm/amdgpu: add missing documentation on new module parameters drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writeback drm/amd/display: avoid 64-bit division drm/amdgpu/psp11: simplify the ucode register logic drm/amdgpu: properly guard DC support in navi code drm/amd/powerplay: vega20: fix uninitialized variable use drm/amd/display: dcn20: include linux/delay.h amdgpu: make pmu support optional drm/amd/powerplay: Zero initialize current_rpm in vega20_get_fan_speed_percent drm/amd/powerplay: Zero initialize freq in smu_v11_0_get_current_clk_freq drm/amd/powerplay: Use memset to initialize metrics structs drm/amdgpu/mes10.1: Fix header guard drm/amd/powerplay: add temperature sensor support for navi10 drm/amdgpu: fix scheduler timeout calc drm/amdgpu: Prepare for hmm_range_register API change (v2) ...
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| @@ -35,7 +35,10 @@ struct dma_buf_sync { · 34 unmodified lines | ||
| 35 | 35 | #define DMA_BUF_SYNC_VALID_FLAGS_MASK \ |
| 36 | 36 | (DMA_BUF_SYNC_RW | DMA_BUF_SYNC_END) |
| 37 | 37 | |
| 38 | +#define DMA_BUF_NAME_LEN 32 | |
| 39 | + | |
| 38 | 40 | #define DMA_BUF_BASE 'b' |
| 39 | 41 | #define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync) |
| 42 | +#define DMA_BUF_SET_NAME _IOW(DMA_BUF_BASE, 1, const char *) | |
| 40 | 43 | |
| 41 | 44 | #endif |
| @@ -35,9 +35,10 @@ struct kfd_ioctl_get_version_args { · 34 unmodified lines | ||
| 35 | 35 | }; |
| 36 | 36 | |
| 37 | 37 | /* For kfd_ioctl_create_queue_args.queue_type. */ |
| 38 | −#define KFD_IOC_QUEUE_TYPE_COMPUTE 0 | |
| 39 | −#define KFD_IOC_QUEUE_TYPE_SDMA 1 | |
| 40 | −#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2 | |
| 38 | +#define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0 | |
| 39 | +#define KFD_IOC_QUEUE_TYPE_SDMA 0x1 | |
| 40 | +#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 | |
| 41 | +#define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 | |
| 41 | 42 | |
| 42 | 43 | #define KFD_MAX_QUEUE_PERCENTAGE 100 |
| 43 | 44 | #define KFD_MAX_QUEUE_PRIORITY 15 |
| @@ -338,6 +339,7 @@ struct kfd_ioctl_acquire_vm_args { · 294 unmodified lines | ||
| 338 | 339 | #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1) |
| 339 | 340 | #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2) |
| 340 | 341 | #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3) |
| 342 | +#define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4) | |
| 341 | 343 | /* Allocation flags: attributes/access options */ |
| 342 | 344 | #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31) |
| 343 | 345 | #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) |
| @@ -408,6 +410,21 @@ struct kfd_ioctl_unmap_memory_from_gpu_args { · 64 unmodified lines | ||
| 408 | 410 | __u32 n_success; /* to/from KFD */ |
| 409 | 411 | }; |
| 410 | 412 | |
| 413 | +/* Allocate GWS for specific queue | |
| 414 | + * | |
| 415 | + * @gpu_id: device identifier | |
| 416 | + * @queue_id: queue's id that GWS is allocated for | |
| 417 | + * @num_gws: how many GWS to allocate | |
| 418 | + * @first_gws: index of the first GWS allocated. | |
| 419 | + * only support contiguous GWS allocation | |
| 420 | + */ | |
| 421 | +struct kfd_ioctl_alloc_queue_gws_args { | |
| 422 | + __u32 gpu_id; /* to KFD */ | |
| 423 | + __u32 queue_id; /* to KFD */ | |
| 424 | + __u32 num_gws; /* to KFD */ | |
| 425 | + __u32 first_gws; /* from KFD */ | |
| 426 | +}; | |
| 427 | + | |
| 411 | 428 | struct kfd_ioctl_get_dmabuf_info_args { |
| 412 | 429 | __u64 size; /* from KFD */ |
| 413 | 430 | __u64 metadata_ptr; /* to KFD */ |
| @@ -426,6 +443,13 @@ struct kfd_ioctl_import_dmabuf_args { · 12 unmodified lines | ||
| 426 | 443 | __u32 dmabuf_fd; /* to KFD */ |
| 427 | 444 | }; |
| 428 | 445 | |
| 446 | +/* Register offset inside the remapped mmio page | |
| 447 | + */ | |
| 448 | +enum kfd_mmio_remap { | |
| 449 | + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, | |
| 450 | + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, | |
| 451 | +}; | |
| 452 | + | |
| 429 | 453 | #define AMDKFD_IOCTL_BASE 'K' |
| 430 | 454 | #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) |
| 431 | 455 | #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) |
| @@ -520,7 +544,10 @@ struct kfd_ioctl_import_dmabuf_args { · 88 unmodified lines | ||
| 520 | 544 | #define AMDKFD_IOC_IMPORT_DMABUF \ |
| 521 | 545 | AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) |
| 522 | 546 | |
| 547 | +#define AMDKFD_IOC_ALLOC_QUEUE_GWS \ | |
| 548 | + AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args) | |
| 549 | + | |
| 523 | 550 | #define AMDKFD_COMMAND_START 0x01 |
| 524 | −#define AMDKFD_COMMAND_END 0x1E | |
| 551 | +#define AMDKFD_COMMAND_END 0x1F | |
| 525 | 552 | |
| 526 | 553 | #endif |
| @@ -91,5 +91,6 @@ · 90 unmodified lines | ||
| 91 | 91 | #define UDF_SUPER_MAGIC 0x15013346 |
| 92 | 92 | #define BALLOON_KVM_MAGIC 0x13661366 |
| 93 | 93 | #define ZSMALLOC_MAGIC 0x58295829 |
| 94 | +#define DMA_BUF_MAGIC 0x444d4142 /* "DMAB" */ | |
| 94 | 95 | |
| 95 | 96 | #endif /* __LINUX_MAGIC_H__ */ |