History

Merge branch 'mtd/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull mtd fixes from Miquel Raynal. * 'mtd/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: mtd: rawnand: stm32_fmc2: fix broken ECC mtd: spi-nor: Fix address width on flash chips > 16MB mtd: spi-nor: Don't copy self-pointing struct around mtd: rawnand: ifc: Move the ECC engine initialization to the right place mtd: rawnand: mxc: Move the ECC engine initialization to the right place

Linus Torvalds committed 6 years ago

Commit bf3e7622 parents 44d8062 9efac6c4 files · +44 −44Browse files

Unified · Split

4 files
  1. drivers/mtd/nand/raw/fsl_ifc_nand.c +24 −19
  2. drivers/mtd/nand/raw/mxc_nand.c +5 −12
  3. drivers/mtd/nand/raw/stm32_fmc2_nand.c +8 −7
  4. drivers/mtd/spi-nor/core.c +7 −6
drivers/mtd/nand/raw/fsl_ifc_nand.c+24−19
@@ -707,6 +707,30 @@ static int fsl_ifc_attach_chip(struct nand_chip *chip) · 706 unmodified lines
707{707{
708 struct mtd_info *mtd = nand_to_mtd(chip);708 struct mtd_info *mtd = nand_to_mtd(chip);
709 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);709 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
710 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
711 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
712 u32 csor;
713
714 csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
715
716 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
717 if (csor & CSOR_NAND_ECC_DEC_EN) {
718 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
719 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
720
721 /* Hardware generates ECC per 512 Bytes */
722 chip->ecc.size = 512;
723 if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
724 chip->ecc.bytes = 8;
725 chip->ecc.strength = 4;
726 } else {
727 chip->ecc.bytes = 16;
728 chip->ecc.strength = 8;
729 }
730 } else {
731 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
732 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
733 }
710 734
711 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,735 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
712 nanddev_ntargets(&chip->base));736 nanddev_ntargets(&chip->base));
@@ -910,25 +934,6 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) · 197 unmodified lines
910 return -ENODEV;934 return -ENODEV;
911 }935 }
912 936
913 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
914 if (csor & CSOR_NAND_ECC_DEC_EN) {
915 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
916 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
917
918 /* Hardware generates ECC per 512 Bytes */
919 chip->ecc.size = 512;
920 if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
921 chip->ecc.bytes = 8;
922 chip->ecc.strength = 4;
923 } else {
924 chip->ecc.bytes = 16;
925 chip->ecc.strength = 8;
926 }
927 } else {
928 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
929 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
930 }
931
932 ret = fsl_ifc_sram_init(priv);937 ret = fsl_ifc_sram_init(priv);
933 if (ret)938 if (ret)
934 return ret;939 return ret;
drivers/mtd/nand/raw/mxc_nand.c+5−12
@@ -1681,6 +1681,11 @@ static int mxcnd_attach_chip(struct nand_chip *chip) · 1680 unmodified lines
1681 struct mxc_nand_host *host = nand_get_controller_data(chip);1681 struct mxc_nand_host *host = nand_get_controller_data(chip);
1682 struct device *dev = mtd->dev.parent;1682 struct device *dev = mtd->dev.parent;
1683 1683
1684 chip->ecc.bytes = host->devtype_data->eccbytes;
1685 host->eccsize = host->devtype_data->eccsize;
1686 chip->ecc.size = 512;
1687 mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1688
1684 switch (chip->ecc.engine_type) {1689 switch (chip->ecc.engine_type) {
1685 case NAND_ECC_ENGINE_TYPE_ON_HOST:1690 case NAND_ECC_ENGINE_TYPE_ON_HOST:
1686 chip->ecc.read_page = mxc_nand_read_page;1691 chip->ecc.read_page = mxc_nand_read_page;
@@ -1836,19 +1841,7 @@ static int mxcnd_probe(struct platform_device *pdev) · 149 unmodified lines
1836 if (host->devtype_data->axi_offset)1841 if (host->devtype_data->axi_offset)
1837 host->regs_axi = host->base + host->devtype_data->axi_offset;1842 host->regs_axi = host->base + host->devtype_data->axi_offset;
1838 1843
1839 this->ecc.bytes = host->devtype_data->eccbytes;
1840 host->eccsize = host->devtype_data->eccsize;
1841
1842 this->legacy.select_chip = host->devtype_data->select_chip;1844 this->legacy.select_chip = host->devtype_data->select_chip;
1843 this->ecc.size = 512;
1844 mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1845
1846 if (host->pdata.hw_ecc) {
1847 this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1848 } else {
1849 this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
1850 this->ecc.algo = NAND_ECC_ALGO_HAMMING;
1851 }
1852 1845
1853 /* NAND bus width determines access functions used by upper layer */1846 /* NAND bus width determines access functions used by upper layer */
1854 if (host->pdata.width == 2)1847 if (host->pdata.width == 2)
drivers/mtd/nand/raw/stm32_fmc2_nand.c+8−7
@@ -1708,6 +1708,13 @@ static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip) · 1707 unmodified lines
1708 return -EINVAL;1708 return -EINVAL;
1709 }1709 }
1710 1710
1711 /* Default ECC settings in case they are not set in the device tree */
1712 if (!chip->ecc.size)
1713 chip->ecc.size = FMC2_ECC_STEP_SIZE;
1714
1715 if (!chip->ecc.strength)
1716 chip->ecc.strength = FMC2_ECC_BCH8;
1717
1711 ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps,1718 ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps,
1712 mtd->oobsize - FMC2_BBM_LEN);1719 mtd->oobsize - FMC2_BBM_LEN);
1713 if (ret) {1720 if (ret) {
@@ -1727,8 +1734,7 @@ static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip) · 13 unmodified lines
1727 1734
1728 mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops);1735 mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops);
1729 1736
1730 if (chip->options & NAND_BUSWIDTH_16)1737 stm32_fmc2_nfc_setup(chip);
1731 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1732 1738
1733 return 0;1739 return 0;
1734}1740}
@@ -1952,11 +1958,6 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev) · 217 unmodified lines
1952 chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |1958 chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
1953 NAND_USES_DMA;1959 NAND_USES_DMA;
1954 1960
1955 /* Default ECC settings */
1956 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1957 chip->ecc.size = FMC2_ECC_STEP_SIZE;
1958 chip->ecc.strength = FMC2_ECC_BCH8;
1959
1960 /* Scan to find existence of the device */1961 /* Scan to find existence of the device */
1961 ret = nand_scan(chip, nand->ncs);1962 ret = nand_scan(chip, nand->ncs);
1962 if (ret)1963 if (ret)
drivers/mtd/spi-nor/core.c+7−6
@@ -2701,11 +2701,10 @@ static void spi_nor_sfdp_init_params(struct spi_nor *nor) · 2700 unmodified lines
2701 2701
2702 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));2702 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
2703 2703
2704 if (spi_nor_parse_sfdp(nor, &sfdp_params)) {2704 if (spi_nor_parse_sfdp(nor, nor->params)) {
2705 memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
2705 nor->addr_width = 0;2706 nor->addr_width = 0;
2706 nor->flags &= ~SNOR_F_4B_OPCODES;2707 nor->flags &= ~SNOR_F_4B_OPCODES;
2707 } else {
2708 memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
2709 }2708 }
2710}2709}
2711 2710
@@ -3009,13 +3008,15 @@ static int spi_nor_set_addr_width(struct spi_nor *nor) · 297 unmodified lines
3009 /* already configured from SFDP */3008 /* already configured from SFDP */
3010 } else if (nor->info->addr_width) {3009 } else if (nor->info->addr_width) {
3011 nor->addr_width = nor->info->addr_width;3010 nor->addr_width = nor->info->addr_width;
3012 } else if (nor->mtd.size > 0x1000000) {
3013 /* enable 4-byte addressing if the device exceeds 16MiB */
3014 nor->addr_width = 4;
3015 } else {3011 } else {
3016 nor->addr_width = 3;3012 nor->addr_width = 3;
3017 }3013 }
3018 3014
3015 if (nor->addr_width == 3 && nor->mtd.size > 0x1000000) {
3016 /* enable 4-byte addressing if the device exceeds 16MiB */
3017 nor->addr_width = 4;
3018 }
3019
3019 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {3020 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
3020 dev_dbg(nor->dev, "address width is too large: %u\n",3021 dev_dbg(nor->dev, "address width is too large: %u\n",
3021 nor->addr_width);3022 nor->addr_width);