Pull edac updates from Mauro Carvalho Chehab: "Nothing really exiting here: just one bug fix at sb_edac, and some changes to allow other drivers to use some shared PCI addresses" * tag 'edac/v3.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac: sb_edac: Claim a different PCI device Move Intel SNB device ids from sb_edac to pci_ids.h sb_edac: avoid INTERNAL ERROR message in EDAC with unspecified channel
Unified · Split
| @@ -52,36 +52,6 @@ static int probed; · 51 unmodified lines | ||
| 52 | 52 | #define GET_BITFIELD(v, lo, hi) \ |
| 53 | 53 | (((v) & GENMASK_ULL(hi, lo)) >> (lo)) |
| 54 | 54 | |
| 55 | −/* | |
| 56 | − * sbridge Memory Controller Registers | |
| 57 | − */ | |
| 58 | − | |
| 59 | −/* | |
| 60 | − * FIXME: For now, let's order by device function, as it makes | |
| 61 | − * easier for driver's development process. This table should be | |
| 62 | − * moved to pci_id.h when submitted upstream | |
| 63 | − */ | |
| 64 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */ | |
| 65 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */ | |
| 66 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */ | |
| 67 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */ | |
| 68 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */ | |
| 69 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */ | |
| 70 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */ | |
| 71 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */ | |
| 72 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */ | |
| 73 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */ | |
| 74 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */ | |
| 75 | − | |
| 76 | − /* | |
| 77 | − * Currently, unused, but will be needed in the future | |
| 78 | − * implementations, as they hold the error counters | |
| 79 | − */ | |
| 80 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */ | |
| 81 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */ | |
| 82 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */ | |
| 83 | −#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */ | |
| 84 | − | |
| 85 | 55 | /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ |
| 86 | 56 | static const u32 sbridge_dram_rule[] = { |
| 87 | 57 | 0x80, 0x88, 0x90, 0x98, 0xa0, |
| @@ -283,8 +253,9 @@ static const u32 correrrthrsld[] = { · 195 unmodified lines | ||
| 283 | 253 | * sbridge structs |
| 284 | 254 | */ |
| 285 | 255 | |
| 286 | −#define NUM_CHANNELS 4 | |
| 287 | −#define MAX_DIMMS 3 /* Max DIMMS per channel */ | |
| 256 | +#define NUM_CHANNELS 4 | |
| 257 | +#define MAX_DIMMS 3 /* Max DIMMS per channel */ | |
| 258 | +#define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */ | |
| 288 | 259 | |
| 289 | 260 | enum type { |
| 290 | 261 | SANDY_BRIDGE, |
| @@ -529,7 +500,7 @@ static const struct pci_id_table pci_dev_descr_haswell_table[] = { · 238 unmodified lines | ||
| 529 | 500 | * pci_device_id table for which devices we are looking for |
| 530 | 501 | */ |
| 531 | 502 | static const struct pci_device_id sbridge_pci_tbl[] = { |
| 532 | − {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)}, | |
| 503 | + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)}, | |
| 533 | 504 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)}, |
| 534 | 505 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)}, |
| 535 | 506 | {0,} /* 0 terminated list. */ |
| @@ -1991,6 +1962,9 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci, · 1455 unmodified lines | ||
| 1991 | 1962 | |
| 1992 | 1963 | /* FIXME: need support for channel mask */ |
| 1993 | 1964 | |
| 1965 | + if (channel == CHANNEL_UNSPECIFIED) | |
| 1966 | + channel = -1; | |
| 1967 | + | |
| 1994 | 1968 | /* Call the helper to output message */ |
| 1995 | 1969 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
| 1996 | 1970 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, |
| @@ -2820,7 +2820,22 @@ · 2819 unmodified lines | ||
| 2820 | 2820 | #define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43 |
| 2821 | 2821 | #define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44 |
| 2822 | 2822 | #define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45 |
| 2823 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */ | |
| 2824 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */ | |
| 2825 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */ | |
| 2826 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */ | |
| 2827 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */ | |
| 2828 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */ | |
| 2829 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */ | |
| 2830 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */ | |
| 2831 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */ | |
| 2832 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */ | |
| 2833 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */ | |
| 2834 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */ | |
| 2823 | 2835 | #define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0 |
| 2836 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */ | |
| 2837 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */ | |
| 2838 | +#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */ | |
| 2824 | 2839 | #define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f |
| 2825 | 2840 | #define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 |
| 2826 | 2841 | #define PCI_DEVICE_ID_INTEL_5100_19 0x65f3 |