iommu/vt-d: Allow zero SAGAW if second-stage not supported

The VT-d spec states (in section 11.4.2) that hardware implementations reporting second-stage translation support (SSTS) field as Clear also report the SAGAW field as 0. Fix an inappropriate check in alloc_iommu().

Lu Baolu committed 3 years ago

Commit bfd3c6b1 parent c7d62451 file · +2 −1Browse files

Unified · Split

drivers/iommu/intel/dmar.c+2−1

@@ -1071,7 +1071,8 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd) · 1070 unmodified lines
1071	}	1071	}
1072		1072
1073	err = -EINVAL;	1073	err = -EINVAL;
1074	if (cap_sagaw(iommu->cap) == 0) {	1074	if (!cap_sagaw(iommu->cap) &&
		1075	(!ecap_smts(iommu->ecap) \|\| ecap_slts(iommu->ecap))) {
1075	pr_info("%s: No supported address widths. Not attempting DMA translation.\n",	1076	pr_info("%s: No supported address widths. Not attempting DMA translation.\n",
1076	iommu->name);	1077	iommu->name);
1077	drhd->ignored = 1;	1078	drhd->ignored = 1;