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dmaengine: idxd: Init and probe for Intel data accelerators

The idxd driver introduces the Intel Data Stream Accelerator [1] that will be available on future Intel Xeon CPUs. One of the kernel access point for the driver is through the dmaengine subsystem. It will initially provide the DMA copy service to the kernel. Some of the main functionality introduced with this accelerator are: shared virtual memory (SVM) support, and descriptor submission using Intel CPU instructions movdir64b and enqcmds. There will be additional accelerator devices that share the same driver with variations to capabilities. This commit introduces the probe and initialization component of the driver. [1]: https://software.intel.com/en-us/download/intel-data-streaming-accelerator-preliminary-architecture-specification

Dave Jiang committed 6 years ago

Commit bfe1d561 parent e81274c10 files · +2093 −0Browse files

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include/uapi/linux/idxd.h+228−0
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1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3#ifndef _USR_IDXD_H_
4#define _USR_IDXD_H_
5
6#ifdef __KERNEL__
7#include <linux/types.h>
8#else
9#include <stdint.h>
10#endif
11
12/* Descriptor flags */
13#define IDXD_OP_FLAG_FENCE 0x0001
14#define IDXD_OP_FLAG_BOF 0x0002
15#define IDXD_OP_FLAG_CRAV 0x0004
16#define IDXD_OP_FLAG_RCR 0x0008
17#define IDXD_OP_FLAG_RCI 0x0010
18#define IDXD_OP_FLAG_CRSTS 0x0020
19#define IDXD_OP_FLAG_CR 0x0080
20#define IDXD_OP_FLAG_CC 0x0100
21#define IDXD_OP_FLAG_ADDR1_TCS 0x0200
22#define IDXD_OP_FLAG_ADDR2_TCS 0x0400
23#define IDXD_OP_FLAG_ADDR3_TCS 0x0800
24#define IDXD_OP_FLAG_CR_TCS 0x1000
25#define IDXD_OP_FLAG_STORD 0x2000
26#define IDXD_OP_FLAG_DRDBK 0x4000
27#define IDXD_OP_FLAG_DSTS 0x8000
28
29/* Opcode */
30enum dsa_opcode {
31 DSA_OPCODE_NOOP = 0,
32 DSA_OPCODE_BATCH,
33 DSA_OPCODE_DRAIN,
34 DSA_OPCODE_MEMMOVE,
35 DSA_OPCODE_MEMFILL,
36 DSA_OPCODE_COMPARE,
37 DSA_OPCODE_COMPVAL,
38 DSA_OPCODE_CR_DELTA,
39 DSA_OPCODE_AP_DELTA,
40 DSA_OPCODE_DUALCAST,
41 DSA_OPCODE_CRCGEN = 0x10,
42 DSA_OPCODE_COPY_CRC,
43 DSA_OPCODE_DIF_CHECK,
44 DSA_OPCODE_DIF_INS,
45 DSA_OPCODE_DIF_STRP,
46 DSA_OPCODE_DIF_UPDT,
47 DSA_OPCODE_CFLUSH = 0x20,
48};
49
50/* Completion record status */
51enum dsa_completion_status {
52 DSA_COMP_NONE = 0,
53 DSA_COMP_SUCCESS,
54 DSA_COMP_SUCCESS_PRED,
55 DSA_COMP_PAGE_FAULT_NOBOF,
56 DSA_COMP_PAGE_FAULT_IR,
57 DSA_COMP_BATCH_FAIL,
58 DSA_COMP_BATCH_PAGE_FAULT,
59 DSA_COMP_DR_OFFSET_NOINC,
60 DSA_COMP_DR_OFFSET_ERANGE,
61 DSA_COMP_DIF_ERR,
62 DSA_COMP_BAD_OPCODE = 0x10,
63 DSA_COMP_INVALID_FLAGS,
64 DSA_COMP_NOZERO_RESERVE,
65 DSA_COMP_XFER_ERANGE,
66 DSA_COMP_DESC_CNT_ERANGE,
67 DSA_COMP_DR_ERANGE,
68 DSA_COMP_OVERLAP_BUFFERS,
69 DSA_COMP_DCAST_ERR,
70 DSA_COMP_DESCLIST_ALIGN,
71 DSA_COMP_INT_HANDLE_INVAL,
72 DSA_COMP_CRA_XLAT,
73 DSA_COMP_CRA_ALIGN,
74 DSA_COMP_ADDR_ALIGN,
75 DSA_COMP_PRIV_BAD,
76 DSA_COMP_TRAFFIC_CLASS_CONF,
77 DSA_COMP_PFAULT_RDBA,
78 DSA_COMP_HW_ERR1,
79 DSA_COMP_HW_ERR_DRB,
80 DSA_COMP_TRANSLATION_FAIL,
81};
82
83#define DSA_COMP_STATUS_MASK 0x7f
84#define DSA_COMP_STATUS_WRITE 0x80
85
86struct dsa_batch_desc {
87 uint32_t pasid:20;
88 uint32_t rsvd:11;
89 uint32_t priv:1;
90 uint32_t flags:24;
91 uint32_t opcode:8;
92 uint64_t completion_addr;
93 uint64_t desc_list_addr;
94 uint64_t rsvd1;
95 uint32_t desc_count;
96 uint16_t interrupt_handle;
97 uint16_t rsvd2;
98 uint8_t rsvd3[24];
99} __attribute__((packed));
100
101struct dsa_hw_desc {
102 uint32_t pasid:20;
103 uint32_t rsvd:11;
104 uint32_t priv:1;
105 uint32_t flags:24;
106 uint32_t opcode:8;
107 uint64_t completion_addr;
108 union {
109 uint64_t src_addr;
110 uint64_t rdback_addr;
111 uint64_t pattern;
112 };
113 union {
114 uint64_t dst_addr;
115 uint64_t rdback_addr2;
116 uint64_t src2_addr;
117 uint64_t comp_pattern;
118 };
119 uint32_t xfer_size;
120 uint16_t int_handle;
121 uint16_t rsvd1;
122 union {
123 uint8_t expected_res;
124 struct {
125 uint64_t delta_addr;
126 uint32_t max_delta_size;
127 };
128 uint32_t delta_rec_size;
129 uint64_t dest2;
130 /* CRC */
131 struct {
132 uint32_t crc_seed;
133 uint32_t crc_rsvd;
134 uint64_t seed_addr;
135 };
136 /* DIF check or strip */
137 struct {
138 uint8_t src_dif_flags;
139 uint8_t dif_chk_res;
140 uint8_t dif_chk_flags;
141 uint8_t dif_chk_res2[5];
142 uint32_t chk_ref_tag_seed;
143 uint16_t chk_app_tag_mask;
144 uint16_t chk_app_tag_seed;
145 };
146 /* DIF insert */
147 struct {
148 uint8_t dif_ins_res;
149 uint8_t dest_dif_flag;
150 uint8_t dif_ins_flags;
151 uint8_t dif_ins_res2[13];
152 uint32_t ins_ref_tag_seed;
153 uint16_t ins_app_tag_mask;
154 uint16_t ins_app_tag_seed;
155 };
156 /* DIF update */
157 struct {
158 uint8_t src_upd_flags;
159 uint8_t upd_dest_flags;
160 uint8_t dif_upd_flags;
161 uint8_t dif_upd_res[5];
162 uint32_t src_ref_tag_seed;
163 uint16_t src_app_tag_mask;
164 uint16_t src_app_tag_seed;
165 uint32_t dest_ref_tag_seed;
166 uint16_t dest_app_tag_mask;
167 uint16_t dest_app_tag_seed;
168 };
169
170 uint8_t op_specific[24];
171 };
172} __attribute__((packed));
173
174struct dsa_raw_desc {
175 uint64_t field[8];
176} __attribute__((packed));
177
178/*
179 * The status field will be modified by hardware, therefore it should be
180 * volatile and prevent the compiler from optimize the read.
181 */
182struct dsa_completion_record {
183 volatile uint8_t status;
184 union {
185 uint8_t result;
186 uint8_t dif_status;
187 };
188 uint16_t rsvd;
189 uint32_t bytes_completed;
190 uint64_t fault_addr;
191 union {
192 uint16_t delta_rec_size;
193 uint16_t crc_val;
194
195 /* DIF check & strip */
196 struct {
197 uint32_t dif_chk_ref_tag;
198 uint16_t dif_chk_app_tag_mask;
199 uint16_t dif_chk_app_tag;
200 };
201
202 /* DIF insert */
203 struct {
204 uint64_t dif_ins_res;
205 uint32_t dif_ins_ref_tag;
206 uint16_t dif_ins_app_tag_mask;
207 uint16_t dif_ins_app_tag;
208 };
209
210 /* DIF update */
211 struct {
212 uint32_t dif_upd_src_ref_tag;
213 uint16_t dif_upd_src_app_tag_mask;
214 uint16_t dif_upd_src_app_tag;
215 uint32_t dif_upd_dest_ref_tag;
216 uint16_t dif_upd_dest_app_tag_mask;
217 uint16_t dif_upd_dest_app_tag;
218 };
219
220 uint8_t op_specific[16];
221 };
222} __attribute__((packed));
223
224struct dsa_raw_completion_record {
225 uint64_t field[4];
226} __attribute__((packed));
227
228#endif