PCI/ATS: Cache PRI Capability offset

Previously each PRI interface searched for the PRI Capability. Cache the capability offset the first time we use it instead of searching each time. [bhelgaas: commit log, reorder patch to later, call pci_pri_init() from pci_init_capabilities()] Link: https://lore.kernel.org/r/0c5495d376faf6dbb8eb2165204c474438aaae65.156 7029860.git.sathyanarayanan.kuppuswamy@linux.intel.com Link: https://lore.kernel.org/r/20190905193146.90250-5-helgaas@kernel.org Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Kuppuswamy Sathyanarayanan committed 7 years ago

Commit c0651901 parent 3ad62194 files · +36 −25Browse files

Unified · Split

4 files

drivers/pci/ats.c +26 −25
drivers/pci/pci.h +6 −0
drivers/pci/probe.c +3 −0
include/linux/pci.h +1 −0

drivers/pci/ats.c+26−25

@@ -159,6 +159,11 @@ int pci_ats_page_aligned(struct pci_dev *pdev) · 158 unmodified lines
159	159	EXPORT_SYMBOL_GPL(pci_ats_page_aligned);
160	160
161	161	#ifdef CONFIG_PCI_PRI
	162	+void pci_pri_init(struct pci_dev *pdev)
	163	+{
	164	+ pdev->pri_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
	165	+}
	166	+
162	167	/**
163	168	* pci_enable_pri - Enable PRI capability
164	169	* @ pdev: PCI device structure
@@ -169,7 +174,7 @@ int pci_enable_pri(struct pci_dev *pdev, u32 reqs) · 4 unmodified lines
169	174	{
170	175	u16 control, status;
171	176	u32 max_requests;
172		− int pos;
	177	+ int pri = pdev->pri_cap;
173	178
174	179	/*
175	180	* VFs must not implement the PRI Capability. If their PF
@@ -185,21 +190,20 @@ int pci_enable_pri(struct pci_dev *pdev, u32 reqs) · 9 unmodified lines
185	190	if (WARN_ON(pdev->pri_enabled))
186	191	return -EBUSY;
187	192
188		− pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
189		− if (!pos)
	193	+ if (!pri)
190	194	return -EINVAL;
191	195
192		− pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
	196	+ pci_read_config_word(pdev, pri + PCI_PRI_STATUS, &status);
193	197	if (!(status & PCI_PRI_STATUS_STOPPED))
194	198	return -EBUSY;
195	199
196		− pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
	200	+ pci_read_config_dword(pdev, pri + PCI_PRI_MAX_REQ, &max_requests);
197	201	reqs = min(max_requests, reqs);
198	202	pdev->pri_reqs_alloc = reqs;
199		− pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
	203	+ pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
200	204
201	205	control = PCI_PRI_CTRL_ENABLE;
202		− pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
	206	+ pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
203	207
204	208	pdev->pri_enabled = 1;
205	209
@@ -216,7 +220,7 @@ EXPORT_SYMBOL_GPL(pci_enable_pri); · 10 unmodified lines
216	220	void pci_disable_pri(struct pci_dev *pdev)
217	221	{
218	222	u16 control;
219		− int pos;
	223	+ int pri = pdev->pri_cap;
220	224
221	225	/* VFs share the PF PRI */
222	226	if (pdev->is_virtfn)
@@ -225,13 +229,12 @@ void pci_disable_pri(struct pci_dev *pdev) · 2 unmodified lines
225	229	if (WARN_ON(!pdev->pri_enabled))
226	230	return;
227	231
228		− pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
229		− if (!pos)
	232	+ if (!pri)
230	233	return;
231	234
232		− pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
	235	+ pci_read_config_word(pdev, pri + PCI_PRI_CTRL, &control);
233	236	control &= ~PCI_PRI_CTRL_ENABLE;
234		− pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
	237	+ pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
235	238
236	239	pdev->pri_enabled = 0;
237	240	}
@@ -245,7 +248,7 @@ void pci_restore_pri_state(struct pci_dev *pdev) · 7 unmodified lines
245	248	{
246	249	u16 control = PCI_PRI_CTRL_ENABLE;
247	250	u32 reqs = pdev->pri_reqs_alloc;
248		− int pos;
	251	+ int pri = pdev->pri_cap;
249	252
250	253	if (pdev->is_virtfn)
251	254	return;
@@ -253,12 +256,11 @@ void pci_restore_pri_state(struct pci_dev *pdev) · 1 unmodified line
253	256	if (!pdev->pri_enabled)
254	257	return;
255	258
256		− pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
257		− if (!pos)
	259	+ if (!pri)
258	260	return;
259	261
260		− pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
261		− pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
	262	+ pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
	263	+ pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
262	264	}
263	265	EXPORT_SYMBOL_GPL(pci_restore_pri_state);
264	266
@@ -272,7 +274,7 @@ EXPORT_SYMBOL_GPL(pci_restore_pri_state); · 7 unmodified lines
272	274	int pci_reset_pri(struct pci_dev *pdev)
273	275	{
274	276	u16 control;
275		− int pos;
	277	+ int pri = pdev->pri_cap;
276	278
277	279	if (pdev->is_virtfn)
278	280	return 0;
@@ -280,12 +282,11 @@ int pci_reset_pri(struct pci_dev *pdev) · 1 unmodified line
280	282	if (WARN_ON(pdev->pri_enabled))
281	283	return -EBUSY;
282	284
283		− pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
284		− if (!pos)
	285	+ if (!pri)
285	286	return -EINVAL;
286	287
287	288	control = PCI_PRI_CTRL_RESET;
288		− pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
	289	+ pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
289	290
290	291	return 0;
291	292	}
@@ -301,16 +302,16 @@ EXPORT_SYMBOL_GPL(pci_reset_pri); · 9 unmodified lines
301	302	int pci_prg_resp_pasid_required(struct pci_dev *pdev)
302	303	{
303	304	u16 status;
304		− int pos;
	305	+ int pri;
305	306
306	307	if (pdev->is_virtfn)
307	308	pdev = pci_physfn(pdev);
308	309
309		− pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
310		− if (!pos)
	310	+ pri = pdev->pri_cap;
	311	+ if (!pri)
311	312	return 0;
312	313
313		− pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
	314	+ pci_read_config_word(pdev, pri + PCI_PRI_STATUS, &status);
314	315
315	316	if (status & PCI_PRI_STATUS_PASID)
316	317	return 1;

drivers/pci/pci.h+6−0

@@ -456,6 +456,12 @@ static inline void pci_ats_init(struct pci_dev *d) { } · 455 unmodified lines
456	456	static inline void pci_restore_ats_state(struct pci_dev *dev) { }
457	457	#endif /* CONFIG_PCI_ATS */
458	458
	459	+#ifdef CONFIG_PCI_PRI
	460	+void pci_pri_init(struct pci_dev *dev);
	461	+#else
	462	+static inline void pci_pri_init(struct pci_dev *dev) { }
	463	+#endif
	464	+
459	465	#ifdef CONFIG_PCI_IOV
460	466	int pci_iov_init(struct pci_dev *dev);
461	467	void pci_iov_release(struct pci_dev *dev);

drivers/pci/probe.c+3−0

@@ -2324,6 +2324,9 @@ static void pci_init_capabilities(struct pci_dev *dev) · 2323 unmodified lines
2324	2324	/* Address Translation Services */
2325	2325	pci_ats_init(dev);
2326	2326
	2327	+ /* Page Request Interface */
	2328	+ pci_pri_init(dev);
	2329	+
2327	2330	/* Enable ACS P2P upstream forwarding */
2328	2331	pci_enable_acs(dev);
2329	2332

include/linux/pci.h+1−0

@@ -454,6 +454,7 @@ struct pci_dev { · 453 unmodified lines
454	454	u8 ats_stu; /* ATS Smallest Translation Unit */
455	455	#endif
456	456	#ifdef CONFIG_PCI_PRI
	457	+ u16 pri_cap; /* PRI Capability offset */
457	458	u32 pri_reqs_alloc; /* Number of PRI requests allocated */
458	459	#endif
459	460	#ifdef CONFIG_PCI_PASID

PCI/ATS: Cache PRI Capability offset

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