Pull ARM SoC fixes from Olof Johansson: "Another week, another batch of fixes. All are small, contained, targeted fixes for explicit problems -- mostly build and boot failures across i.MX, OMAP, Renesas/Shmobile and Samsung." * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: imx6q: fix suspend regression caused by common clk migration ARM: OMAP4470: Fix OMAP4470 boot failure ARM: EXYNOS: Fix EXYNOS_DEV_DMA Kconfig entry ARM: OMAP2+: nand: fix build error when CONFIG_MTD_ONENAND_OMAP2=n ARM: shmobile: r8a7779: Route all interrupts to ARM ARM: shmobile: kzm9d: use late init machine hook ARM: shmobile: kzm9g: use late init machine hook ARM: mach-shmobile: armadillo800eva: Use late init machine hook ARM: SAMSUNG: Fix for S3C2412 EBI memory mapping ARM: mach-shmobile: add missing GPIO IRQ configuration on mackerel ARM: mach-shmobile: Fix build when SMP is enabled and EMEV2 is not enabled ARM: shmobile: sh7372: bugfix: chclr_offset base ARM: shmobile: sh73a0: bugfix: SY-DMAC number ARM: SAMSUNG: Should check for IS_ERR(clk) instead of NULL
Unified · Split
| @@ -212,7 +212,7 @@ config MACH_SMDKV310 · 211 unmodified lines | ||
| 212 | 212 | select EXYNOS_DEV_SYSMMU |
| 213 | 213 | select EXYNOS4_DEV_AHCI |
| 214 | 214 | select SAMSUNG_DEV_KEYPAD |
| 215 | − select EXYNOS4_DEV_DMA | |
| 215 | + select EXYNOS_DEV_DMA | |
| 216 | 216 | select SAMSUNG_DEV_PWM |
| 217 | 217 | select EXYNOS4_DEV_USB_OHCI |
| 218 | 218 | select EXYNOS4_SETUP_FIMD0 |
| @@ -264,7 +264,7 @@ config MACH_UNIVERSAL_C210 · 45 unmodified lines | ||
| 264 | 264 | select S5P_DEV_ONENAND |
| 265 | 265 | select S5P_DEV_TV |
| 266 | 266 | select EXYNOS_DEV_SYSMMU |
| 267 | − select EXYNOS4_DEV_DMA | |
| 267 | + select EXYNOS_DEV_DMA | |
| 268 | 268 | select EXYNOS_DEV_DRM |
| 269 | 269 | select EXYNOS4_SETUP_FIMD0 |
| 270 | 270 | select EXYNOS4_SETUP_I2C1 |
| @@ -303,7 +303,7 @@ config MACH_NURI · 32 unmodified lines | ||
| 303 | 303 | select S5P_DEV_MFC |
| 304 | 304 | select S5P_DEV_USB_EHCI |
| 305 | 305 | select S5P_SETUP_MIPIPHY |
| 306 | − select EXYNOS4_DEV_DMA | |
| 306 | + select EXYNOS_DEV_DMA | |
| 307 | 307 | select EXYNOS_DEV_DRM |
| 308 | 308 | select EXYNOS4_SETUP_FIMC |
| 309 | 309 | select EXYNOS4_SETUP_FIMD0 |
| @@ -341,7 +341,7 @@ config MACH_ORIGEN · 31 unmodified lines | ||
| 341 | 341 | select SAMSUNG_DEV_PWM |
| 342 | 342 | select EXYNOS_DEV_DRM |
| 343 | 343 | select EXYNOS_DEV_SYSMMU |
| 344 | − select EXYNOS4_DEV_DMA | |
| 344 | + select EXYNOS_DEV_DMA | |
| 345 | 345 | select EXYNOS4_DEV_USB_OHCI |
| 346 | 346 | select EXYNOS4_SETUP_FIMD0 |
| 347 | 347 | select EXYNOS4_SETUP_SDHCI |
| @@ -152,13 +152,14 @@ enum mx6q_clks { · 151 unmodified lines | ||
| 152 | 152 | ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, |
| 153 | 153 | usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, |
| 154 | 154 | pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, |
| 155 | − ssi2_ipg, ssi3_ipg, clk_max | |
| 155 | + ssi2_ipg, ssi3_ipg, rom, | |
| 156 | + clk_max | |
| 156 | 157 | }; |
| 157 | 158 | |
| 158 | 159 | static struct clk *clk[clk_max]; |
| 159 | 160 | |
| 160 | 161 | static enum mx6q_clks const clks_init_on[] __initconst = { |
| 161 | − mmdc_ch0_axi, mmdc_ch1_axi, | |
| 162 | + mmdc_ch0_axi, rom, | |
| 162 | 163 | }; |
| 163 | 164 | |
| 164 | 165 | int __init mx6q_clocks_init(void) |
| @@ -364,6 +365,7 @@ int __init mx6q_clocks_init(void) · 199 unmodified lines | ||
| 364 | 365 | clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); |
| 365 | 366 | clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); |
| 366 | 367 | clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); |
| 368 | + clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); | |
| 367 | 369 | clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); |
| 368 | 370 | clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); |
| 369 | 371 | clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); |
| @@ -97,11 +97,6 @@ __init board_onenand_init(struct mtd_partition *onenand_parts, · 96 unmodified lines | ||
| 97 | 97 | |
| 98 | 98 | gpmc_onenand_init(&board_onenand_data); |
| 99 | 99 | } |
| 100 | −#else | |
| 101 | −void | |
| 102 | −__init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) | |
| 103 | −{ | |
| 104 | −} | |
| 105 | 100 | #endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */ |
| 106 | 101 | |
| 107 | 102 | #if defined(CONFIG_MTD_NAND_OMAP2) || \ |
| @@ -3417,9 +3417,12 @@ int __init omap4xxx_clk_init(void) · 3416 unmodified lines | ||
| 3417 | 3417 | if (cpu_is_omap443x()) { |
| 3418 | 3418 | cpu_mask = RATE_IN_4430; |
| 3419 | 3419 | cpu_clkflg = CK_443X; |
| 3420 | − } else if (cpu_is_omap446x()) { | |
| 3420 | + } else if (cpu_is_omap446x() || cpu_is_omap447x()) { | |
| 3421 | 3421 | cpu_mask = RATE_IN_4460 | RATE_IN_4430; |
| 3422 | 3422 | cpu_clkflg = CK_446X | CK_443X; |
| 3423 | + | |
| 3424 | + if (cpu_is_omap447x()) | |
| 3425 | + pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); | |
| 3423 | 3426 | } else { |
| 3424 | 3427 | return 0; |
| 3425 | 3428 | } |
| @@ -779,6 +779,7 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva") · 778 unmodified lines | ||
| 779 | 779 | .init_irq = r8a7740_init_irq, |
| 780 | 780 | .handle_irq = shmobile_handle_irq_intc, |
| 781 | 781 | .init_machine = eva_init, |
| 782 | + .init_late = shmobile_init_late, | |
| 782 | 783 | .timer = &shmobile_timer, |
| 783 | 784 | .dt_compat = eva_boards_compat_dt, |
| 784 | 785 | MACHINE_END |
| @@ -80,6 +80,7 @@ DT_MACHINE_START(KZM9D_DT, "kzm9d") · 79 unmodified lines | ||
| 80 | 80 | .init_irq = emev2_init_irq, |
| 81 | 81 | .handle_irq = gic_handle_irq, |
| 82 | 82 | .init_machine = kzm9d_add_standard_devices, |
| 83 | + .init_late = shmobile_init_late, | |
| 83 | 84 | .timer = &shmobile_timer, |
| 84 | 85 | .dt_compat = kzm9d_boards_compat_dt, |
| 85 | 86 | MACHINE_END |
| @@ -455,6 +455,7 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g") · 454 unmodified lines | ||
| 455 | 455 | .init_irq = sh73a0_init_irq, |
| 456 | 456 | .handle_irq = gic_handle_irq, |
| 457 | 457 | .init_machine = kzm_init, |
| 458 | + .init_late = shmobile_init_late, | |
| 458 | 459 | .timer = &shmobile_timer, |
| 459 | 460 | .dt_compat = kzm9g_boards_compat_dt, |
| 460 | 461 | MACHINE_END |
| @@ -1512,6 +1512,9 @@ static void __init mackerel_init(void) · 1511 unmodified lines | ||
| 1512 | 1512 | gpio_request(GPIO_FN_SDHID0_1, NULL); |
| 1513 | 1513 | gpio_request(GPIO_FN_SDHID0_0, NULL); |
| 1514 | 1514 | |
| 1515 | + /* SDHI0 PORT172 card-detect IRQ26 */ | |
| 1516 | + gpio_request(GPIO_FN_IRQ26_172, NULL); | |
| 1517 | + | |
| 1515 | 1518 | #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) |
| 1516 | 1519 | /* enable SDHI1 */ |
| 1517 | 1520 | gpio_request(GPIO_FN_SDHICMD1, NULL); |
| @@ -475,9 +475,9 @@ static struct clk *late_main_clks[] = { · 474 unmodified lines | ||
| 475 | 475 | |
| 476 | 476 | enum { MSTP001, |
| 477 | 477 | MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, |
| 478 | − MSTP219, | |
| 478 | + MSTP219, MSTP218, | |
| 479 | 479 | MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, |
| 480 | − MSTP331, MSTP329, MSTP325, MSTP323, MSTP318, | |
| 480 | + MSTP331, MSTP329, MSTP325, MSTP323, | |
| 481 | 481 | MSTP314, MSTP313, MSTP312, MSTP311, |
| 482 | 482 | MSTP303, MSTP302, MSTP301, MSTP300, |
| 483 | 483 | MSTP411, MSTP410, MSTP403, |
| @@ -497,6 +497,7 @@ static struct clk mstp_clks[MSTP_NR] = { · 13 unmodified lines | ||
| 497 | 497 | [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */ |
| 498 | 498 | [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */ |
| 499 | 499 | [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ |
| 500 | + [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */ | |
| 500 | 501 | [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ |
| 501 | 502 | [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ |
| 502 | 503 | [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ |
| @@ -508,7 +509,6 @@ static struct clk mstp_clks[MSTP_NR] = { · 5 unmodified lines | ||
| 508 | 509 | [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ |
| 509 | 510 | [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */ |
| 510 | 511 | [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ |
| 511 | − [MSTP318] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* SY-DMAC */ | |
| 512 | 512 | [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */ |
| 513 | 513 | [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */ |
| 514 | 514 | [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */ |
| @@ -552,6 +552,7 @@ static struct clk_lookup lookups[] = { · 37 unmodified lines | ||
| 552 | 552 | CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */ |
| 553 | 553 | CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */ |
| 554 | 554 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */ |
| 555 | + CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */ | |
| 555 | 556 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ |
| 556 | 557 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ |
| 557 | 558 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ |
| @@ -563,7 +564,6 @@ static struct clk_lookup lookups[] = { · 5 unmodified lines | ||
| 563 | 564 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ |
| 564 | 565 | CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ |
| 565 | 566 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ |
| 566 | − CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP318]), /* SY-DMAC */ | |
| 567 | 567 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ |
| 568 | 568 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ |
| 569 | 569 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ |
| @@ -35,6 +35,9 @@ · 34 unmodified lines | ||
| 35 | 35 | #define INT2SMSKCR3 0xfe7822ac |
| 36 | 36 | #define INT2SMSKCR4 0xfe7822b0 |
| 37 | 37 | |
| 38 | +#define INT2NTSR0 0xfe700060 | |
| 39 | +#define INT2NTSR1 0xfe700064 | |
| 40 | + | |
| 38 | 41 | static int r8a7779_set_wake(struct irq_data *data, unsigned int on) |
| 39 | 42 | { |
| 40 | 43 | return 0; /* always allow wakeup */ |
| @@ -49,6 +52,10 @@ void __init r8a7779_init_irq(void) · 8 unmodified lines | ||
| 49 | 52 | gic_init(0, 29, gic_dist_base, gic_cpu_base); |
| 50 | 53 | gic_arch_extn.irq_set_wake = r8a7779_set_wake; |
| 51 | 54 | |
| 55 | + /* route all interrupts to ARM */ | |
| 56 | + __raw_writel(0xffffffff, INT2NTSR0); | |
| 57 | + __raw_writel(0x3fffffff, INT2NTSR1); | |
| 58 | + | |
| 52 | 59 | /* unmask all known interrupts in INTCS2 */ |
| 53 | 60 | __raw_writel(0xfffffff0, INT2SMSKCR0); |
| 54 | 61 | __raw_writel(0xfff7ffff, INT2SMSKCR1); |
| @@ -25,7 +25,12 @@ · 24 unmodified lines | ||
| 25 | 25 | #define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2() || \ |
| 26 | 26 | of_machine_is_compatible("renesas,sh73a0")) |
| 27 | 27 | #define is_r8a7779() machine_is_marzen() |
| 28 | + | |
| 29 | +#ifdef CONFIG_ARCH_EMEV2 | |
| 28 | 30 | #define is_emev2() of_machine_is_compatible("renesas,emev2") |
| 31 | +#else | |
| 32 | +#define is_emev2() (0) | |
| 33 | +#endif | |
| 29 | 34 | |
| 30 | 35 | static unsigned int __init shmobile_smp_get_core_count(void) |
| 31 | 36 | { |
| @@ -484,7 +484,7 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { · 483 unmodified lines | ||
| 484 | 484 | }, |
| 485 | 485 | }; |
| 486 | 486 | |
| 487 | −#define SH7372_CHCLR 0x220 | |
| 487 | +#define SH7372_CHCLR (0x220 - 0x20) | |
| 488 | 488 | |
| 489 | 489 | static const struct sh_dmae_channel sh7372_dmae_channels[] = { |
| 490 | 490 | { |
| @@ -22,7 +22,7 @@ · 21 unmodified lines | ||
| 22 | 22 | #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG |
| 23 | 23 | |
| 24 | 24 | #define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000) |
| 25 | −#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000) | |
| 25 | +#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00100000) | |
| 26 | 26 | |
| 27 | 27 | #define S3C2410_PA_UART (0x50000000) |
| 28 | 28 | #define S3C24XX_PA_UART S3C2410_PA_UART |
| @@ -25,7 +25,7 @@ static inline void arch_wdt_reset(void) · 24 unmodified lines | ||
| 25 | 25 | |
| 26 | 26 | __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ |
| 27 | 27 | |
| 28 | − if (s3c2410_wdtclk) | |
| 28 | + if (!IS_ERR(s3c2410_wdtclk)) | |
| 29 | 29 | clk_enable(s3c2410_wdtclk); |
| 30 | 30 | |
| 31 | 31 | /* put initial values into count and data */ |