Pull RISC-V updates from Palmer Dabbelt: - Support for various vector-accelerated crypto routines - Hibernation is now enabled for portable kernel builds - mmap_rnd_bits_max is larger on systems with larger VAs - Support for fast GUP - Support for membarrier-based instruction cache synchronization - Support for the Andes hart-level interrupt controller and PMU - Some cleanups around unaligned access speed probing and Kconfig settings - Support for ACPI LPI and CPPC - Various cleanus related to barriers - A handful of fixes * tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits) riscv: Fix syscall wrapper for >word-size arguments crypto: riscv - add vector crypto accelerated AES-CBC-CTS crypto: riscv - parallelize AES-CBC decryption riscv: Only flush the mm icache when setting an exec pte riscv: Use kcalloc() instead of kzalloc() riscv/barrier: Add missing space after ',' riscv/barrier: Consolidate fence definitions riscv/barrier: Define RISCV_FULL_BARRIER riscv/barrier: Define __{mb,rmb,wmb} RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ cpufreq: Move CPPC configs to common Kconfig and add RISC-V ACPI: RISC-V: Add CPPC driver ACPI: Enable ACPI_PROCESSOR for RISC-V ACPI: RISC-V: Add LPI driver cpuidle: RISC-V: Move few functions to arch/riscv riscv: Introduce set_compat_task() in asm/compat.h riscv: Introduce is_compat_thread() into compat.h riscv: add compile-time test into is_compat_task() riscv: Replace direct thread flag check with is_compat_task() riscv: Improve arch_get_mmap_end() macro ...
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| @@ -6647,7 +6647,9 @@ static void __sched notrace __schedule(unsigned int sched_mode) · 6646 unmodified lines | ||
| 6647 | 6647 | * if (signal_pending_state()) if (p->state & @state) |
| 6648 | 6648 | * |
| 6649 | 6649 | * Also, the membarrier system call requires a full memory barrier |
| 6650 | − * after coming from user-space, before storing to rq->curr. | |
| 6650 | + * after coming from user-space, before storing to rq->curr; this | |
| 6651 | + * barrier matches a full barrier in the proximity of the membarrier | |
| 6652 | + * system call exit. | |
| 6651 | 6653 | */ |
| 6652 | 6654 | rq_lock(rq, &rf); |
| 6653 | 6655 | smp_mb__after_spinlock(); |
| @@ -6718,12 +6720,20 @@ static void __sched notrace __schedule(unsigned int sched_mode) · 64 unmodified lines | ||
| 6718 | 6720 | * |
| 6719 | 6721 | * Here are the schemes providing that barrier on the |
| 6720 | 6722 | * various architectures: |
| 6721 | − * - mm ? switch_mm() : mmdrop() for x86, s390, sparc, PowerPC. | |
| 6722 | − * switch_mm() rely on membarrier_arch_switch_mm() on PowerPC. | |
| 6723 | + * - mm ? switch_mm() : mmdrop() for x86, s390, sparc, PowerPC, | |
| 6724 | + * RISC-V. switch_mm() relies on membarrier_arch_switch_mm() | |
| 6725 | + * on PowerPC and on RISC-V. | |
| 6723 | 6726 | * - finish_lock_switch() for weakly-ordered |
| 6724 | 6727 | * architectures where spin_unlock is a full barrier, |
| 6725 | 6728 | * - switch_to() for arm64 (weakly-ordered, spin_unlock |
| 6726 | 6729 | * is a RELEASE barrier), |
| 6730 | + * | |
| 6731 | + * The barrier matches a full barrier in the proximity of | |
| 6732 | + * the membarrier system call entry. | |
| 6733 | + * | |
| 6734 | + * On RISC-V, this barrier pairing is also needed for the | |
| 6735 | + * SYNC_CORE command when switching between processes, cf. | |
| 6736 | + * the inline comments in membarrier_arch_switch_mm(). | |
| 6727 | 6737 | */ |
| 6728 | 6738 | ++*switch_count; |
| 6729 | 6739 | |
| @@ -254,7 +254,7 @@ static int membarrier_global_expedited(void) · 253 unmodified lines | ||
| 254 | 254 | return 0; |
| 255 | 255 | |
| 256 | 256 | /* |
| 257 | − * Matches memory barriers around rq->curr modification in | |
| 257 | + * Matches memory barriers after rq->curr modification in | |
| 258 | 258 | * scheduler. |
| 259 | 259 | */ |
| 260 | 260 | smp_mb(); /* system call entry is not a mb. */ |
| @@ -304,7 +304,7 @@ static int membarrier_global_expedited(void) · 43 unmodified lines | ||
| 304 | 304 | |
| 305 | 305 | /* |
| 306 | 306 | * Memory barrier on the caller thread _after_ we finished |
| 307 | − * waiting for the last IPI. Matches memory barriers around | |
| 307 | + * waiting for the last IPI. Matches memory barriers before | |
| 308 | 308 | * rq->curr modification in scheduler. |
| 309 | 309 | */ |
| 310 | 310 | smp_mb(); /* exit from system call is not a mb */ |
| @@ -324,6 +324,7 @@ static int membarrier_private_expedited(int flags, int cpu_id) · 13 unmodified lines | ||
| 324 | 324 | MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY)) |
| 325 | 325 | return -EPERM; |
| 326 | 326 | ipi_func = ipi_sync_core; |
| 327 | + prepare_sync_core_cmd(mm); | |
| 327 | 328 | } else if (flags == MEMBARRIER_FLAG_RSEQ) { |
| 328 | 329 | if (!IS_ENABLED(CONFIG_RSEQ)) |
| 329 | 330 | return -EINVAL; |
| @@ -343,8 +344,12 @@ static int membarrier_private_expedited(int flags, int cpu_id) · 13 unmodified lines | ||
| 343 | 344 | return 0; |
| 344 | 345 | |
| 345 | 346 | /* |
| 346 | − * Matches memory barriers around rq->curr modification in | |
| 347 | + * Matches memory barriers after rq->curr modification in | |
| 347 | 348 | * scheduler. |
| 349 | + * | |
| 350 | + * On RISC-V, this barrier pairing is also needed for the | |
| 351 | + * SYNC_CORE command when switching between processes, cf. | |
| 352 | + * the inline comments in membarrier_arch_switch_mm(). | |
| 348 | 353 | */ |
| 349 | 354 | smp_mb(); /* system call entry is not a mb. */ |
| 350 | 355 | |
| @@ -420,7 +425,7 @@ out: · 69 unmodified lines | ||
| 420 | 425 | |
| 421 | 426 | /* |
| 422 | 427 | * Memory barrier on the caller thread _after_ we finished |
| 423 | − * waiting for the last IPI. Matches memory barriers around | |
| 428 | + * waiting for the last IPI. Matches memory barriers before | |
| 424 | 429 | * rq->curr modification in scheduler. |
| 425 | 430 | */ |
| 426 | 431 | smp_mb(); /* exit from system call is not a mb */ |