Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Palmer Dabbelt: - Support for various vector-accelerated crypto routines - Hibernation is now enabled for portable kernel builds - mmap_rnd_bits_max is larger on systems with larger VAs - Support for fast GUP - Support for membarrier-based instruction cache synchronization - Support for the Andes hart-level interrupt controller and PMU - Some cleanups around unaligned access speed probing and Kconfig settings - Support for ACPI LPI and CPPC - Various cleanus related to barriers - A handful of fixes * tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits) riscv: Fix syscall wrapper for >word-size arguments crypto: riscv - add vector crypto accelerated AES-CBC-CTS crypto: riscv - parallelize AES-CBC decryption riscv: Only flush the mm icache when setting an exec pte riscv: Use kcalloc() instead of kzalloc() riscv/barrier: Add missing space after ',' riscv/barrier: Consolidate fence definitions riscv/barrier: Define RISCV_FULL_BARRIER riscv/barrier: Define __{mb,rmb,wmb} RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ cpufreq: Move CPPC configs to common Kconfig and add RISC-V ACPI: RISC-V: Add CPPC driver ACPI: Enable ACPI_PROCESSOR for RISC-V ACPI: RISC-V: Add LPI driver cpuidle: RISC-V: Move few functions to arch/riscv riscv: Introduce set_compat_task() in asm/compat.h riscv: Introduce is_compat_thread() into compat.h riscv: add compile-time test into is_compat_task() riscv: Replace direct thread flag check with is_compat_task() riscv: Improve arch_get_mmap_end() macro ...

Linus Torvalds committed 2 years ago

Commit c150b802 parents 1e3cd03 a9ad732105 files · +5183 −747Browse files

Showing the changes to tools (8 of 105 files). Show all

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8 files

tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json +68 −0
tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json +127 −0
tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json +57 −0
tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json +77 −0
tools/perf/pmu-events/arch/riscv/mapfile.csv +1 −0
tools/testing/selftests/riscv/mm/mmap_bottomup.c +1 −22
tools/testing/selftests/riscv/mm/mmap_default.c +1 −22
tools/testing/selftests/riscv/mm/mmap_test.h +65 −42

tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json+68−0

@@ -0,0 +1,68 @@
	1	+[
	2	+ {
	3	+ "ArchStdEvent": "FW_MISALIGNED_LOAD"
	4	+ },
	5	+ {
	6	+ "ArchStdEvent": "FW_MISALIGNED_STORE"
	7	+ },
	8	+ {
	9	+ "ArchStdEvent": "FW_ACCESS_LOAD"
	10	+ },
	11	+ {
	12	+ "ArchStdEvent": "FW_ACCESS_STORE"
	13	+ },
	14	+ {
	15	+ "ArchStdEvent": "FW_ILLEGAL_INSN"
	16	+ },
	17	+ {
	18	+ "ArchStdEvent": "FW_SET_TIMER"
	19	+ },
	20	+ {
	21	+ "ArchStdEvent": "FW_IPI_SENT"
	22	+ },
	23	+ {
	24	+ "ArchStdEvent": "FW_IPI_RECEIVED"
	25	+ },
	26	+ {
	27	+ "ArchStdEvent": "FW_FENCE_I_SENT"
	28	+ },
	29	+ {
	30	+ "ArchStdEvent": "FW_FENCE_I_RECEIVED"
	31	+ },
	32	+ {
	33	+ "ArchStdEvent": "FW_SFENCE_VMA_SENT"
	34	+ },
	35	+ {
	36	+ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
	37	+ },
	38	+ {
	39	+ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
	40	+ },
	41	+ {
	42	+ "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
	43	+ },
	44	+ {
	45	+ "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
	46	+ },
	47	+ {
	48	+ "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
	49	+ },
	50	+ {
	51	+ "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
	52	+ },
	53	+ {
	54	+ "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
	55	+ },
	56	+ {
	57	+ "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
	58	+ },
	59	+ {
	60	+ "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
	61	+ },
	62	+ {
	63	+ "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
	64	+ },
	65	+ {
	66	+ "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
	67	+ }
	68	+]

tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json+127−0

@@ -0,0 +1,127 @@
	1	+[
	2	+ {
	3	+ "EventCode": "0x10",
	4	+ "EventName": "cycle_count",
	5	+ "BriefDescription": "Cycle count"
	6	+ },
	7	+ {
	8	+ "EventCode": "0x20",
	9	+ "EventName": "inst_count",
	10	+ "BriefDescription": "Retired instruction count"
	11	+ },
	12	+ {
	13	+ "EventCode": "0x30",
	14	+ "EventName": "int_load_inst",
	15	+ "BriefDescription": "Integer load instruction count"
	16	+ },
	17	+ {
	18	+ "EventCode": "0x40",
	19	+ "EventName": "int_store_inst",
	20	+ "BriefDescription": "Integer store instruction count"
	21	+ },
	22	+ {
	23	+ "EventCode": "0x50",
	24	+ "EventName": "atomic_inst",
	25	+ "BriefDescription": "Atomic instruction count"
	26	+ },
	27	+ {
	28	+ "EventCode": "0x60",
	29	+ "EventName": "sys_inst",
	30	+ "BriefDescription": "System instruction count"
	31	+ },
	32	+ {
	33	+ "EventCode": "0x70",
	34	+ "EventName": "int_compute_inst",
	35	+ "BriefDescription": "Integer computational instruction count"
	36	+ },
	37	+ {
	38	+ "EventCode": "0x80",
	39	+ "EventName": "condition_br",
	40	+ "BriefDescription": "Conditional branch instruction count"
	41	+ },
	42	+ {
	43	+ "EventCode": "0x90",
	44	+ "EventName": "taken_condition_br",
	45	+ "BriefDescription": "Taken conditional branch instruction count"
	46	+ },
	47	+ {
	48	+ "EventCode": "0xA0",
	49	+ "EventName": "jal_inst",
	50	+ "BriefDescription": "JAL instruction count"
	51	+ },
	52	+ {
	53	+ "EventCode": "0xB0",
	54	+ "EventName": "jalr_inst",
	55	+ "BriefDescription": "JALR instruction count"
	56	+ },
	57	+ {
	58	+ "EventCode": "0xC0",
	59	+ "EventName": "ret_inst",
	60	+ "BriefDescription": "Return instruction count"
	61	+ },
	62	+ {
	63	+ "EventCode": "0xD0",
	64	+ "EventName": "control_trans_inst",
	65	+ "BriefDescription": "Control transfer instruction count"
	66	+ },
	67	+ {
	68	+ "EventCode": "0xE0",
	69	+ "EventName": "ex9_inst",
	70	+ "BriefDescription": "EXEC.IT instruction count"
	71	+ },
	72	+ {
	73	+ "EventCode": "0xF0",
	74	+ "EventName": "int_mul_inst",
	75	+ "BriefDescription": "Integer multiplication instruction count"
	76	+ },
	77	+ {
	78	+ "EventCode": "0x100",
	79	+ "EventName": "int_div_rem_inst",
	80	+ "BriefDescription": "Integer division/remainder instruction count"
	81	+ },
	82	+ {
	83	+ "EventCode": "0x110",
	84	+ "EventName": "float_load_inst",
	85	+ "BriefDescription": "Floating-point load instruction count"
	86	+ },
	87	+ {
	88	+ "EventCode": "0x120",
	89	+ "EventName": "float_store_inst",
	90	+ "BriefDescription": "Floating-point store instruction count"
	91	+ },
	92	+ {
	93	+ "EventCode": "0x130",
	94	+ "EventName": "float_add_sub_inst",
	95	+ "BriefDescription": "Floating-point addition/subtraction instruction count"
	96	+ },
	97	+ {
	98	+ "EventCode": "0x140",
	99	+ "EventName": "float_mul_inst",
	100	+ "BriefDescription": "Floating-point multiplication instruction count"
	101	+ },
	102	+ {
	103	+ "EventCode": "0x150",
	104	+ "EventName": "float_fused_muladd_inst",
	105	+ "BriefDescription": "Floating-point fused multiply-add instruction count"
	106	+ },
	107	+ {
	108	+ "EventCode": "0x160",
	109	+ "EventName": "float_div_sqrt_inst",
	110	+ "BriefDescription": "Floating-point division or square-root instruction count"
	111	+ },
	112	+ {
	113	+ "EventCode": "0x170",
	114	+ "EventName": "other_float_inst",
	115	+ "BriefDescription": "Other floating-point instruction count"
	116	+ },
	117	+ {
	118	+ "EventCode": "0x180",
	119	+ "EventName": "int_mul_add_sub_inst",
	120	+ "BriefDescription": "Integer multiplication and add/sub instruction count"
	121	+ },
	122	+ {
	123	+ "EventCode": "0x190",
	124	+ "EventName": "retired_ops",
	125	+ "BriefDescription": "Retired operation count"
	126	+ }
	127	+]

tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json+57−0

@@ -0,0 +1,57 @@
	1	+[
	2	+ {
	3	+ "EventCode": "0x01",
	4	+ "EventName": "ilm_access",
	5	+ "BriefDescription": "ILM access"
	6	+ },
	7	+ {
	8	+ "EventCode": "0x11",
	9	+ "EventName": "dlm_access",
	10	+ "BriefDescription": "DLM access"
	11	+ },
	12	+ {
	13	+ "EventCode": "0x21",
	14	+ "EventName": "icache_access",
	15	+ "BriefDescription": "ICACHE access"
	16	+ },
	17	+ {
	18	+ "EventCode": "0x31",
	19	+ "EventName": "icache_miss",
	20	+ "BriefDescription": "ICACHE miss"
	21	+ },
	22	+ {
	23	+ "EventCode": "0x41",
	24	+ "EventName": "dcache_access",
	25	+ "BriefDescription": "DCACHE access"
	26	+ },
	27	+ {
	28	+ "EventCode": "0x51",
	29	+ "EventName": "dcache_miss",
	30	+ "BriefDescription": "DCACHE miss"
	31	+ },
	32	+ {
	33	+ "EventCode": "0x61",
	34	+ "EventName": "dcache_load_access",
	35	+ "BriefDescription": "DCACHE load access"
	36	+ },
	37	+ {
	38	+ "EventCode": "0x71",
	39	+ "EventName": "dcache_load_miss",
	40	+ "BriefDescription": "DCACHE load miss"
	41	+ },
	42	+ {
	43	+ "EventCode": "0x81",
	44	+ "EventName": "dcache_store_access",
	45	+ "BriefDescription": "DCACHE store access"
	46	+ },
	47	+ {
	48	+ "EventCode": "0x91",
	49	+ "EventName": "dcache_store_miss",
	50	+ "BriefDescription": "DCACHE store miss"
	51	+ },
	52	+ {
	53	+ "EventCode": "0xA1",
	54	+ "EventName": "dcache_wb",
	55	+ "BriefDescription": "DCACHE writeback"
	56	+ }
	57	+]

tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json+77−0

@@ -0,0 +1,77 @@
	1	+[
	2	+ {
	3	+ "EventCode": "0xB1",
	4	+ "EventName": "cycle_wait_icache_fill",
	5	+ "BriefDescription": "Cycles waiting for ICACHE fill data"
	6	+ },
	7	+ {
	8	+ "EventCode": "0xC1",
	9	+ "EventName": "cycle_wait_dcache_fill",
	10	+ "BriefDescription": "Cycles waiting for DCACHE fill data"
	11	+ },
	12	+ {
	13	+ "EventCode": "0xD1",
	14	+ "EventName": "uncached_ifetch_from_bus",
	15	+ "BriefDescription": "Uncached ifetch data access from bus"
	16	+ },
	17	+ {
	18	+ "EventCode": "0xE1",
	19	+ "EventName": "uncached_load_from_bus",
	20	+ "BriefDescription": "Uncached load data access from bus"
	21	+ },
	22	+ {
	23	+ "EventCode": "0xF1",
	24	+ "EventName": "cycle_wait_uncached_ifetch",
	25	+ "BriefDescription": "Cycles waiting for uncached ifetch data from bus"
	26	+ },
	27	+ {
	28	+ "EventCode": "0x101",
	29	+ "EventName": "cycle_wait_uncached_load",
	30	+ "BriefDescription": "Cycles waiting for uncached load data from bus"
	31	+ },
	32	+ {
	33	+ "EventCode": "0x111",
	34	+ "EventName": "main_itlb_access",
	35	+ "BriefDescription": "Main ITLB access"
	36	+ },
	37	+ {
	38	+ "EventCode": "0x121",
	39	+ "EventName": "main_itlb_miss",
	40	+ "BriefDescription": "Main ITLB miss"
	41	+ },
	42	+ {
	43	+ "EventCode": "0x131",
	44	+ "EventName": "main_dtlb_access",
	45	+ "BriefDescription": "Main DTLB access"
	46	+ },
	47	+ {
	48	+ "EventCode": "0x141",
	49	+ "EventName": "main_dtlb_miss",
	50	+ "BriefDescription": "Main DTLB miss"
	51	+ },
	52	+ {
	53	+ "EventCode": "0x151",
	54	+ "EventName": "cycle_wait_itlb_fill",
	55	+ "BriefDescription": "Cycles waiting for Main ITLB fill data"
	56	+ },
	57	+ {
	58	+ "EventCode": "0x161",
	59	+ "EventName": "pipe_stall_cycle_dtlb_miss",
	60	+ "BriefDescription": "Pipeline stall cycles caused by Main DTLB miss"
	61	+ },
	62	+ {
	63	+ "EventCode": "0x02",
	64	+ "EventName": "mispredict_condition_br",
	65	+ "BriefDescription": "Misprediction of conditional branches"
	66	+ },
	67	+ {
	68	+ "EventCode": "0x12",
	69	+ "EventName": "mispredict_take_condition_br",
	70	+ "BriefDescription": "Misprediction of taken conditional branches"
	71	+ },
	72	+ {
	73	+ "EventCode": "0x22",
	74	+ "EventName": "mispredict_target_ret_inst",
	75	+ "BriefDescription": "Misprediction of targets of Return instructions"
	76	+ }
	77	+]

tools/perf/pmu-events/arch/riscv/mapfile.csv+1−0

@@ -17,3 +17,4 @@ · 16 unmodified lines
17	17	0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
18	18	0x5b7-0x0-0x0,v1,thead/c900-legacy,core
19	19	0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
	20	+0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core

tools/testing/selftests/riscv/mm/mmap_bottomup.c+1−22

@@ -6,30 +6,9 @@ · 5 unmodified lines
6	6
7	7	TEST(infinite_rlimit)
8	8	{
9		−// Only works on 64 bit
10		−#if __riscv_xlen == 64
11		− struct addresses mmap_addresses;
12		−
13	9	EXPECT_EQ(BOTTOM_UP, memory_layout());
14	10
15		− do_mmaps(&mmap_addresses);
16		−
17		− EXPECT_NE(MAP_FAILED, mmap_addresses.no_hint);
18		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_37_addr);
19		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_38_addr);
20		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_46_addr);
21		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_47_addr);
22		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_55_addr);
23		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_56_addr);
24		−
25		− EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.no_hint);
26		− EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_37_addr);
27		− EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_38_addr);
28		− EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_46_addr);
29		− EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.on_47_addr);
30		− EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.on_55_addr);
31		− EXPECT_GT(1UL << 56, (unsigned long)mmap_addresses.on_56_addr);
32		−#endif
	11	+ TEST_MMAPS;
33	12	}
34	13
35	14	TEST_HARNESS_MAIN

tools/testing/selftests/riscv/mm/mmap_default.c+1−22

@@ -6,30 +6,9 @@ · 5 unmodified lines
6	6
7	7	TEST(default_rlimit)
8	8	{
9		−// Only works on 64 bit
10		−#if __riscv_xlen == 64
11		− struct addresses mmap_addresses;
12		−
13	9	EXPECT_EQ(TOP_DOWN, memory_layout());
14	10
15		− do_mmaps(&mmap_addresses);
16		−
17		− EXPECT_NE(MAP_FAILED, mmap_addresses.no_hint);
18		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_37_addr);
19		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_38_addr);
20		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_46_addr);
21		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_47_addr);
22		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_55_addr);
23		− EXPECT_NE(MAP_FAILED, mmap_addresses.on_56_addr);
24		−
25		− EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.no_hint);
26		− EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_37_addr);
27		− EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_38_addr);
28		− EXPECT_GT(1UL << 38, (unsigned long)mmap_addresses.on_46_addr);
29		− EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.on_47_addr);
30		− EXPECT_GT(1UL << 47, (unsigned long)mmap_addresses.on_55_addr);
31		− EXPECT_GT(1UL << 56, (unsigned long)mmap_addresses.on_56_addr);
32		−#endif
	11	+ TEST_MMAPS;
33	12	}
34	13
35	14	TEST_HARNESS_MAIN

tools/testing/selftests/riscv/mm/mmap_test.h+65−42

@@ -4,63 +4,86 @@ · 3 unmodified lines
4	4	#include <sys/mman.h>
5	5	#include <sys/resource.h>
6	6	#include <stddef.h>
	7	+#include <strings.h>
	8	+#include "../../kselftest_harness.h"
7	9
8	10	#define TOP_DOWN 0
9	11	#define BOTTOM_UP 1
10	12
11		−struct addresses {
12		− int *no_hint;
13		− int *on_37_addr;
14		− int *on_38_addr;
15		− int *on_46_addr;
16		− int *on_47_addr;
17		− int *on_55_addr;
18		− int *on_56_addr;
	13	+#if __riscv_xlen == 64
	14	+uint64_t random_addresses[] = {
	15	+ 0x19764f0d73b3a9f0, 0x016049584cecef59, 0x3580bdd3562f4acd,
	16	+ 0x1164219f20b17da0, 0x07d97fcb40ff2373, 0x76ec528921272ee7,
	17	+ 0x4dd48c38a3de3f70, 0x2e11415055f6997d, 0x14b43334ac476c02,
	18	+ 0x375a60795aff19f6, 0x47f3051725b8ee1a, 0x4e697cf240494a9f,
	19	+ 0x456b59b5c2f9e9d1, 0x101724379d63cb96, 0x7fe9ad31619528c1,
	20	+ 0x2f417247c495c2ea, 0x329a5a5b82943a5e, 0x06d7a9d6adcd3827,
	21	+ 0x327b0b9ee37f62d5, 0x17c7b1851dfd9b76, 0x006ebb6456ec2cd9,
	22	+ 0x00836cd14146a134, 0x00e5c4dcde7126db, 0x004c29feadf75753,
	23	+ 0x00d8b20149ed930c, 0x00d71574c269387a, 0x0006ebe4a82acb7a,
	24	+ 0x0016135df51f471b, 0x00758bdb55455160, 0x00d0bdd949b13b32,
	25	+ 0x00ecea01e7c5f54b, 0x00e37b071b9948b1, 0x0011fdd00ff57ab3,
	26	+ 0x00e407294b52f5ea, 0x00567748c200ed20, 0x000d073084651046,
	27	+ 0x00ac896f4365463c, 0x00eb0d49a0b26216, 0x0066a2564a982a31,
	28	+ 0x002e0d20237784ae, 0x0000554ff8a77a76, 0x00006ce07a54c012,
	29	+ 0x000009570516d799, 0x00000954ca15b84d, 0x0000684f0d453379,
	30	+ 0x00002ae5816302b5, 0x0000042403fb54bf, 0x00004bad7392bf30,
	31	+ 0x00003e73bfa4b5e3, 0x00005442c29978e0, 0x00002803f11286b6,
	32	+ 0x000073875d745fc6, 0x00007cede9cb8240, 0x000027df84cc6a4f,
	33	+ 0x00006d7e0e74242a, 0x00004afd0b836e02, 0x000047d0e837cd82,
	34	+ 0x00003b42405efeda, 0x00001531bafa4c95, 0x00007172cae34ac4,
	35	+};
	36	+#else
	37	+uint32_t random_addresses[] = {
	38	+ 0x8dc302e0, 0x929ab1e0, 0xb47683ba, 0xea519c73, 0xa19f1c90, 0xc49ba213,
	39	+ 0x8f57c625, 0xadfe5137, 0x874d4d95, 0xaa20f09d, 0xcf21ebfc, 0xda7737f1,
	40	+ 0xcedf392a, 0x83026c14, 0xccedca52, 0xc6ccf826, 0xe0cd9415, 0x997472ca,
	41	+ 0xa21a44c1, 0xe82196f5, 0xa23fd66b, 0xc28d5590, 0xd009cdce, 0xcf0be646,
	42	+ 0x8fc8c7ff, 0xe2a85984, 0xa3d3236b, 0x89a0619d, 0xc03db924, 0xb5d4cc1b,
	43	+ 0xb96ee04c, 0xd191da48, 0xb432a000, 0xaa2bebbc, 0xa2fcb289, 0xb0cca89b,
	44	+ 0xb0c18d6a, 0x88f58deb, 0xa4d42d1c, 0xe4d74e86, 0x99902b09, 0x8f786d31,
	45	+ 0xbec5e381, 0x9a727e65, 0xa9a65040, 0xa880d789, 0x8f1b335e, 0xfc821c1e,
	46	+ 0x97e34be4, 0xbbef84ed, 0xf447d197, 0xfd7ceee2, 0xe632348d, 0xee4590f4,
	47	+ 0x958992a5, 0xd57e05d6, 0xfd240970, 0xc5b0dcff, 0xd96da2c2, 0xa7ae041d,
19	48	};
	49	+#endif
20	50
21	51	// Only works on 64 bit
22	52	#if __riscv_xlen == 64
23		−static inline void do_mmaps(struct addresses *mmap_addresses)
24		−{
25		− /*
26		− * Place all of the hint addresses on the boundaries of mmap
27		− * sv39, sv48, sv57
28		− * User addresses end at 1<<38, 1<<47, 1<<56 respectively
29		− */
30		− void on_37_bits = (void )(1UL << 37);
31		− void on_38_bits = (void )(1UL << 38);
32		− void on_46_bits = (void )(1UL << 46);
33		− void on_47_bits = (void )(1UL << 47);
34		− void on_55_bits = (void )(1UL << 55);
35		− void on_56_bits = (void )(1UL << 56);
	53	+#define PROT (PROT_READ \| PROT_WRITE)
	54	+#define FLAGS (MAP_PRIVATE \| MAP_ANONYMOUS)
36	55
37		− int prot = PROT_READ \| PROT_WRITE;
38		− int flags = MAP_PRIVATE \| MAP_ANONYMOUS;
	56	+/* mmap must return a value that doesn't use more bits than the hint address. */
	57	+static inline unsigned long get_max_value(unsigned long input)
	58	+{
	59	+ unsigned long max_bit = (1UL << (((sizeof(unsigned long) * 8) - 1 -
	60	+ __builtin_clzl(input))));
39	61
40		− mmap_addresses->no_hint =
41		− mmap(NULL, 5 * sizeof(int), prot, flags, 0, 0);
42		− mmap_addresses->on_37_addr =
43		− mmap(on_37_bits, 5 * sizeof(int), prot, flags, 0, 0);
44		− mmap_addresses->on_38_addr =
45		− mmap(on_38_bits, 5 * sizeof(int), prot, flags, 0, 0);
46		− mmap_addresses->on_46_addr =
47		− mmap(on_46_bits, 5 * sizeof(int), prot, flags, 0, 0);
48		− mmap_addresses->on_47_addr =
49		− mmap(on_47_bits, 5 * sizeof(int), prot, flags, 0, 0);
50		− mmap_addresses->on_55_addr =
51		− mmap(on_55_bits, 5 * sizeof(int), prot, flags, 0, 0);
52		− mmap_addresses->on_56_addr =
53		− mmap(on_56_bits, 5 * sizeof(int), prot, flags, 0, 0);
	62	+ return max_bit + (max_bit - 1);
54	63	}
	64	+
	65	+#define TEST_MMAPS \
	66	+ ({ \
	67	+ void *mmap_addr; \
	68	+ for (int i = 0; i < ARRAY_SIZE(random_addresses); i++) { \
	69	+ mmap_addr = mmap((void *)random_addresses[i], \
	70	+ 5 * sizeof(int), PROT, FLAGS, 0, 0); \
	71	+ EXPECT_NE(MAP_FAILED, mmap_addr); \
	72	+ EXPECT_GE((void *)get_max_value(random_addresses[i]), \
	73	+ mmap_addr); \
	74	+ mmap_addr = mmap((void *)random_addresses[i], \
	75	+ 5 * sizeof(int), PROT, FLAGS, 0, 0); \
	76	+ EXPECT_NE(MAP_FAILED, mmap_addr); \
	77	+ EXPECT_GE((void *)get_max_value(random_addresses[i]), \
	78	+ mmap_addr); \
	79	+ } \
	80	+ })
55	81	#endif /* __riscv_xlen == 64 */
56	82
57	83	static inline int memory_layout(void)
58	84	{
59		− int prot = PROT_READ \| PROT_WRITE;
60		− int flags = MAP_PRIVATE \| MAP_ANONYMOUS;
61		−
62		− void *value1 = mmap(NULL, sizeof(int), prot, flags, 0, 0);
63		− void *value2 = mmap(NULL, sizeof(int), prot, flags, 0, 0);
	85	+ void *value1 = mmap(NULL, sizeof(int), PROT, FLAGS, 0, 0);
	86	+ void *value2 = mmap(NULL, sizeof(int), PROT, FLAGS, 0, 0);
64	87
65	88	return value2 > value1;
66	89	}