History

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie: "Exynos, i915 and msm fixes and one core fix. exynos: hdmi power off and mixer issues msm: iommu, build fixes, i915: regression races and warning fixes" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (22 commits) drm/i915: vlv_prepare_pll is only needed in case of non DSI interfaces drm: fix NULL pointer access by wrong ioctl drm/exynos: enable vsync interrupt while waiting for vblank drm/exynos: soft reset mixer before reconfigure after power-on drm/exynos: allow multiple layer updates per vsync for mixer drm/i915: Hold the table lock whilst walking the file's idr and counting the objects in debugfs drm/i915: BDW: Adding Reserved PCI IDs. drm/i915: Only mark the ctx as initialised after a SET_CONTEXT operation drm/exynos: stop mixer before gating clocks during poweroff drm/exynos: set power state variable after enabling clocks and power drm/exynos: disable unused windows on apply drm/exynos: Fix de-registration ordering drm/exynos: change zero to NULL for sparse drm/exynos: dpi: Fix NULL pointer dereference with legacy bindings drm/exynos: hdmi: fix power order issue drm/i915: default to having backlight if VBT not available drm/i915: cache hw power well enabled state drm/msm: fix IOMMU cleanup for -EPROBE_DEFER drm/msm: use PAGE_ALIGNED instead of IS_ALIGNED(PAGE_SIZE) drm/msm/hdmi: set hdp clock rate before prepare_enable ...

Linus Torvalds committed 12 years ago

Commit c163b522 parents 3493860 0fcb70c26 files · +169 −70Browse files

Unified · Split

26 files
  1. drivers/gpu/drm/drm_drv.c +2 −1
  2. drivers/gpu/drm/exynos/exynos_drm_dpi.c +1 −1
  3. drivers/gpu/drm/exynos/exynos_drm_drv.c +4 −4
  4. drivers/gpu/drm/exynos/exynos_drm_drv.h +1 −1
  5. drivers/gpu/drm/exynos/exynos_drm_fimd.c +2 −0
  6. drivers/gpu/drm/exynos/exynos_hdmi.c +19 −0
  7. drivers/gpu/drm/exynos/exynos_mixer.c +35 −15
  8. drivers/gpu/drm/exynos/regs-mixer.h +1 −0
  9. drivers/gpu/drm/i915/i915_debugfs.c +2 −0
  10. drivers/gpu/drm/i915/i915_drv.h +2 −0
  11. drivers/gpu/drm/i915/i915_gem_context.c +5 −3
  12. drivers/gpu/drm/i915/intel_bios.c +3 −3
  13. drivers/gpu/drm/i915/intel_display.c +7 −6
  14. drivers/gpu/drm/i915/intel_drv.h +2 −2
  15. drivers/gpu/drm/i915/intel_pm.c +15 −22
  16. drivers/gpu/drm/msm/hdmi/hdmi.c +2 −0
  17. drivers/gpu/drm/msm/hdmi/hdmi.h +1 −0
  18. drivers/gpu/drm/msm/hdmi/hdmi_connector.c +8 −0
  19. drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c +17 −5
  20. drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +1 −0
  21. drivers/gpu/drm/msm/msm_drv.c +1 −1
  22. drivers/gpu/drm/msm/msm_fbdev.c +1 −1
  23. drivers/gpu/drm/msm/msm_gem.c +6 −0
  24. drivers/gpu/drm/msm/msm_iommu.c +20 −3
  25. drivers/gpu/drm/msm/msm_mmu.h +1 −0
  26. include/drm/i915_pciids.h +10 −2
drivers/gpu/drm/drm_drv.c+2−1
@@ -419,8 +419,9 @@ long drm_ioctl(struct file *filp, · 418 unmodified lines
419419 retcode = -EFAULT;
420420 goto err_i1;
421421 }
422− } else
422+ } else if (cmd & IOC_OUT) {
423423 memset(kdata, 0, usize);
424+ }
424425
425426 if (ioctl->flags & DRM_UNLOCKED)
426427 retcode = func(dev, kdata, file_priv);
drivers/gpu/drm/exynos/exynos_drm_dpi.c+1−1
@@ -40,7 +40,7 @@ exynos_dpi_detect(struct drm_connector *connector, bool force) · 39 unmodified lines
4040 {
4141 struct exynos_dpi *ctx = connector_to_dpi(connector);
4242
43− if (!ctx->panel->connector)
43+ if (ctx->panel && !ctx->panel->connector)
4444 drm_panel_attach(ctx->panel, &ctx->connector);
4545
4646 return connector_status_connected;
drivers/gpu/drm/exynos/exynos_drm_drv.c+4−4
@@ -765,24 +765,24 @@ static int exynos_drm_init(void) · 764 unmodified lines
765765
766766 return 0;
767767
768−err_unregister_pd:
769− platform_device_unregister(exynos_drm_pdev);
770−
771768 err_remove_vidi:
772769 #ifdef CONFIG_DRM_EXYNOS_VIDI
773770 exynos_drm_remove_vidi();
771+
772+err_unregister_pd:
774773 #endif
774+ platform_device_unregister(exynos_drm_pdev);
775775
776776 return ret;
777777 }
778778
779779 static void exynos_drm_exit(void)
780780 {
781+ platform_driver_unregister(&exynos_drm_platform_driver);
781782 #ifdef CONFIG_DRM_EXYNOS_VIDI
782783 exynos_drm_remove_vidi();
783784 #endif
784785 platform_device_unregister(exynos_drm_pdev);
785− platform_driver_unregister(&exynos_drm_platform_driver);
786786 }
787787
788788 module_init(exynos_drm_init);
drivers/gpu/drm/exynos/exynos_drm_drv.h+1−1
@@ -343,7 +343,7 @@ struct exynos_drm_display * exynos_dpi_probe(struct device *dev); · 342 unmodified lines
343343 int exynos_dpi_remove(struct device *dev);
344344 #else
345345 static inline struct exynos_drm_display *
346−exynos_dpi_probe(struct device *dev) { return 0; }
346+exynos_dpi_probe(struct device *dev) { return NULL; }
347347 static inline int exynos_dpi_remove(struct device *dev) { return 0; }
348348 #endif
349349
drivers/gpu/drm/exynos/exynos_drm_fimd.c+2−0
@@ -741,6 +741,8 @@ static void fimd_apply(struct exynos_drm_manager *mgr) · 740 unmodified lines
741741 win_data = &ctx->win_data[i];
742742 if (win_data->enabled)
743743 fimd_win_commit(mgr, i);
744+ else
745+ fimd_win_disable(mgr, i);
744746 }
745747
746748 fimd_commit(mgr);
drivers/gpu/drm/exynos/exynos_hdmi.c+19−0
@@ -2090,6 +2090,11 @@ out: · 2089 unmodified lines
20902090
20912091 static void hdmi_dpms(struct exynos_drm_display *display, int mode)
20922092 {
2093+ struct hdmi_context *hdata = display->ctx;
2094+ struct drm_encoder *encoder = hdata->encoder;
2095+ struct drm_crtc *crtc = encoder->crtc;
2096+ struct drm_crtc_helper_funcs *funcs = NULL;
2097+
20932098 DRM_DEBUG_KMS("mode %d\n", mode);
20942099
20952100 switch (mode) {
@@ -2099,6 +2104,20 @@ static void hdmi_dpms(struct exynos_drm_display *display, int mode) · 3 unmodified lines
20992104 case DRM_MODE_DPMS_STANDBY:
21002105 case DRM_MODE_DPMS_SUSPEND:
21012106 case DRM_MODE_DPMS_OFF:
2107+ /*
2108+ * The SFRs of VP and Mixer are updated by Vertical Sync of
2109+ * Timing generator which is a part of HDMI so the sequence
2110+ * to disable TV Subsystem should be as following,
2111+ * VP -> Mixer -> HDMI
2112+ *
2113+ * Below codes will try to disable Mixer and VP(if used)
2114+ * prior to disabling HDMI.
2115+ */
2116+ if (crtc)
2117+ funcs = crtc->helper_private;
2118+ if (funcs && funcs->dpms)
2119+ (*funcs->dpms)(crtc, mode);
2120+
21022121 hdmi_poweroff(display);
21032122 break;
21042123 default:
drivers/gpu/drm/exynos/exynos_mixer.c+35−15
@@ -377,6 +377,20 @@ static void mixer_run(struct mixer_context *ctx) · 376 unmodified lines
377377 mixer_regs_dump(ctx);
378378 }
379379
380+static void mixer_stop(struct mixer_context *ctx)
381+{
382+ struct mixer_resources *res = &ctx->mixer_res;
383+ int timeout = 20;
384+
385+ mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN);
386+
387+ while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
388+ --timeout)
389+ usleep_range(10000, 12000);
390+
391+ mixer_regs_dump(ctx);
392+}
393+
380394 static void vp_video_buffer(struct mixer_context *ctx, int win)
381395 {
382396 struct mixer_resources *res = &ctx->mixer_res;
@@ -497,13 +511,8 @@ static void vp_video_buffer(struct mixer_context *ctx, int win) · 114 unmodified lines
497511 static void mixer_layer_update(struct mixer_context *ctx)
498512 {
499513 struct mixer_resources *res = &ctx->mixer_res;
500− u32 val;
501−
502− val = mixer_reg_read(res, MXR_CFG);
503514
504− /* allow one update per vsync only */
505− if (!(val & MXR_CFG_LAYER_UPDATE_COUNT_MASK))
506− mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
515+ mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
507516 }
508517
509518 static void mixer_graph_buffer(struct mixer_context *ctx, int win)
@@ -1010,6 +1019,8 @@ static void mixer_wait_for_vblank(struct exynos_drm_manager *mgr) · 500 unmodified lines
10101019 }
10111020 mutex_unlock(&mixer_ctx->mixer_mutex);
10121021
1022+ drm_vblank_get(mgr->crtc->dev, mixer_ctx->pipe);
1023+
10131024 atomic_set(&mixer_ctx->wait_vsync_event, 1);
10141025
10151026 /*
@@ -1020,6 +1031,8 @@ static void mixer_wait_for_vblank(struct exynos_drm_manager *mgr) · 4 unmodified lines
10201031 !atomic_read(&mixer_ctx->wait_vsync_event),
10211032 HZ/20))
10221033 DRM_DEBUG_KMS("vblank wait timed out.\n");
1034+
1035+ drm_vblank_put(mgr->crtc->dev, mixer_ctx->pipe);
10231036 }
10241037
10251038 static void mixer_window_suspend(struct exynos_drm_manager *mgr)
@@ -1061,7 +1074,7 @@ static void mixer_poweron(struct exynos_drm_manager *mgr) · 35 unmodified lines
10611074 mutex_unlock(&ctx->mixer_mutex);
10621075 return;
10631076 }
1064− ctx->powered = true;
1077+
10651078 mutex_unlock(&ctx->mixer_mutex);
10661079
10671080 pm_runtime_get_sync(ctx->dev);
@@ -1072,6 +1085,12 @@ static void mixer_poweron(struct exynos_drm_manager *mgr) · 4 unmodified lines
10721085 clk_prepare_enable(res->sclk_mixer);
10731086 }
10741087
1088+ mutex_lock(&ctx->mixer_mutex);
1089+ ctx->powered = true;
1090+ mutex_unlock(&ctx->mixer_mutex);
1091+
1092+ mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
1093+
10751094 mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
10761095 mixer_win_reset(ctx);
10771096
@@ -1084,14 +1103,21 @@ static void mixer_poweroff(struct exynos_drm_manager *mgr) · 6 unmodified lines
10841103 struct mixer_resources *res = &ctx->mixer_res;
10851104
10861105 mutex_lock(&ctx->mixer_mutex);
1087− if (!ctx->powered)
1088− goto out;
1106+ if (!ctx->powered) {
1107+ mutex_unlock(&ctx->mixer_mutex);
1108+ return;
1109+ }
10891110 mutex_unlock(&ctx->mixer_mutex);
10901111
1112+ mixer_stop(ctx);
10911113 mixer_window_suspend(mgr);
10921114
10931115 ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
10941116
1117+ mutex_lock(&ctx->mixer_mutex);
1118+ ctx->powered = false;
1119+ mutex_unlock(&ctx->mixer_mutex);
1120+
10951121 clk_disable_unprepare(res->mixer);
10961122 if (ctx->vp_enabled) {
10971123 clk_disable_unprepare(res->vp);
@@ -1099,12 +1125,6 @@ static void mixer_poweroff(struct exynos_drm_manager *mgr) · 1 unmodified line
10991125 }
11001126
11011127 pm_runtime_put_sync(ctx->dev);
1102−
1103− mutex_lock(&ctx->mixer_mutex);
1104− ctx->powered = false;
1105−
1106−out:
1107− mutex_unlock(&ctx->mixer_mutex);
11081128 }
11091129
11101130 static void mixer_dpms(struct exynos_drm_manager *mgr, int mode)
drivers/gpu/drm/exynos/regs-mixer.h+1−0
@@ -78,6 +78,7 @@ · 77 unmodified lines
7878 #define MXR_STATUS_BIG_ENDIAN (1 << 3)
7979 #define MXR_STATUS_ENDIAN_MASK (1 << 3)
8080 #define MXR_STATUS_SYNC_ENABLE (1 << 2)
81+#define MXR_STATUS_REG_IDLE (1 << 1)
8182 #define MXR_STATUS_REG_RUN (1 << 0)
8283
8384 /* bits for MXR_CFG */
drivers/gpu/drm/i915/i915_debugfs.c+2−0
@@ -446,7 +446,9 @@ static int i915_gem_object_info(struct seq_file *m, void* data) · 445 unmodified lines
446446
447447 memset(&stats, 0, sizeof(stats));
448448 stats.file_priv = file->driver_priv;
449+ spin_lock(&file->table_lock);
449450 idr_for_each(&file->object_idr, per_file_stats, &stats);
451+ spin_unlock(&file->table_lock);
450452 /*
451453 * Although we have a valid reference on file->pid, that does
452454 * not guarantee that the task_struct who called get_pid() is
drivers/gpu/drm/i915/i915_drv.h+2−0
@@ -977,6 +977,8 @@ struct i915_power_well { · 976 unmodified lines
977977 bool always_on;
978978 /* power well enable/disable usage count */
979979 int count;
980+ /* cached hw enabled state */
981+ bool hw_enabled;
980982 unsigned long domains;
981983 unsigned long data;
982984 const struct i915_power_well_ops *ops;
drivers/gpu/drm/i915/i915_gem_context.c+5−3
@@ -598,6 +598,7 @@ static int do_switch(struct intel_engine_cs *ring, · 597 unmodified lines
598598 struct intel_context *from = ring->last_context;
599599 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(to);
600600 u32 hw_flags = 0;
601+ bool uninitialized = false;
601602 int ret, i;
602603
603604 if (from != NULL && ring == &dev_priv->ring[RCS]) {
@@ -696,19 +697,20 @@ static int do_switch(struct intel_engine_cs *ring, · 92 unmodified lines
696697 i915_gem_context_unreference(from);
697698 }
698699
700+ uninitialized = !to->is_initialized && from == NULL;
701+ to->is_initialized = true;
702+
699703 done:
700704 i915_gem_context_reference(to);
701705 ring->last_context = to;
702706 to->last_ring = ring;
703707
704− if (ring->id == RCS && !to->is_initialized && from == NULL) {
708+ if (uninitialized) {
705709 ret = i915_gem_render_state_init(ring);
706710 if (ret)
707711 DRM_ERROR("init render state: %d\n", ret);
708712 }
709713
710− to->is_initialized = true;
711−
712714 return 0;
713715
714716 unpin_out:
drivers/gpu/drm/i915/intel_bios.c+3−3
@@ -315,9 +315,6 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv, struct bdb_header *bdb) · 314 unmodified lines
315315 const struct bdb_lfp_backlight_data *backlight_data;
316316 const struct bdb_lfp_backlight_data_entry *entry;
317317
318− /* Err to enabling backlight if no backlight block. */
319− dev_priv->vbt.backlight.present = true;
320−
321318 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
322319 if (!backlight_data)
323320 return;
@@ -1088,6 +1085,9 @@ init_vbt_defaults(struct drm_i915_private *dev_priv) · 764 unmodified lines
10881085
10891086 dev_priv->vbt.crt_ddc_pin = GMBUS_PORT_VGADDC;
10901087
1088+ /* Default to having backlight */
1089+ dev_priv->vbt.backlight.present = true;
1090+
10911091 /* LFP panel data */
10921092 dev_priv->vbt.lvds_dither = 1;
10931093 dev_priv->vbt.lvds_vbt = 0;
drivers/gpu/drm/i915/intel_display.c+7−6
@@ -4564,7 +4564,10 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) · 4563 unmodified lines
45644564 if (intel_crtc->active)
45654565 return;
45664566
4567− vlv_prepare_pll(intel_crtc);
4567+ is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4568+
4569+ if (!is_dsi && !IS_CHERRYVIEW(dev))
4570+ vlv_prepare_pll(intel_crtc);
45684571
45694572 /* Set up the display plane register */
45704573 dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4598,8 +4601,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) · 27 unmodified lines
45984601 if (encoder->pre_pll_enable)
45994602 encoder->pre_pll_enable(encoder);
46004603
4601− is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4602−
46034604 if (!is_dsi) {
46044605 if (IS_CHERRYVIEW(dev))
46054606 chv_enable_pll(intel_crtc);
@@ -12411,8 +12412,8 @@ intel_display_capture_error_state(struct drm_device *dev) · 7805 unmodified lines
1241112412
1241212413 for_each_pipe(i) {
1241312414 error->pipe[i].power_domain_on =
12414− intel_display_power_enabled_sw(dev_priv,
12415− POWER_DOMAIN_PIPE(i));
12415+ intel_display_power_enabled_unlocked(dev_priv,
12416+ POWER_DOMAIN_PIPE(i));
1241612417 if (!error->pipe[i].power_domain_on)
1241712418 continue;
1241812419
@@ -12447,7 +12448,7 @@ intel_display_capture_error_state(struct drm_device *dev) · 28 unmodified lines
1244712448 enum transcoder cpu_transcoder = transcoders[i];
1244812449
1244912450 error->transcoder[i].power_domain_on =
12450− intel_display_power_enabled_sw(dev_priv,
12451+ intel_display_power_enabled_unlocked(dev_priv,
1245112452 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
1245212453 if (!error->transcoder[i].power_domain_on)
1245312454 continue;
drivers/gpu/drm/i915/intel_drv.h+2−2
@@ -950,8 +950,8 @@ int intel_power_domains_init(struct drm_i915_private *); · 949 unmodified lines
950950 void intel_power_domains_remove(struct drm_i915_private *);
951951 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
952952 enum intel_display_power_domain domain);
953−bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
954− enum intel_display_power_domain domain);
953+bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
954+ enum intel_display_power_domain domain);
955955 void intel_display_power_get(struct drm_i915_private *dev_priv,
956956 enum intel_display_power_domain domain);
957957 void intel_display_power_put(struct drm_i915_private *dev_priv,
drivers/gpu/drm/i915/intel_pm.c+15−22
@@ -5603,8 +5603,8 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, · 5602 unmodified lines
56035603 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
56045604 }
56055605
5606−bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
5607− enum intel_display_power_domain domain)
5606+bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
5607+ enum intel_display_power_domain domain)
56085608 {
56095609 struct i915_power_domains *power_domains;
56105610 struct i915_power_well *power_well;
@@ -5615,16 +5615,19 @@ bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv, · 4 unmodified lines
56155615 return false;
56165616
56175617 power_domains = &dev_priv->power_domains;
5618+
56185619 is_enabled = true;
5620+
56195621 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
56205622 if (power_well->always_on)
56215623 continue;
56225624
5623− if (!power_well->count) {
5625+ if (!power_well->hw_enabled) {
56245626 is_enabled = false;
56255627 break;
56265628 }
56275629 }
5630+
56285631 return is_enabled;
56295632 }
56305633
@@ -5632,30 +5635,15 @@ bool intel_display_power_enabled(struct drm_i915_private *dev_priv, · 1 unmodified line
56325635 enum intel_display_power_domain domain)
56335636 {
56345637 struct i915_power_domains *power_domains;
5635− struct i915_power_well *power_well;
5636− bool is_enabled;
5637− int i;
5638−
5639− if (dev_priv->pm.suspended)
5640− return false;
5638+ bool ret;
56415639
56425640 power_domains = &dev_priv->power_domains;
56435641
5644− is_enabled = true;
5645−
56465642 mutex_lock(&power_domains->lock);
5647− for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5648− if (power_well->always_on)
5649− continue;
5650−
5651− if (!power_well->ops->is_enabled(dev_priv, power_well)) {
5652− is_enabled = false;
5653− break;
5654− }
5655− }
5643+ ret = intel_display_power_enabled_unlocked(dev_priv, domain);
56565644 mutex_unlock(&power_domains->lock);
56575645
5658− return is_enabled;
5646+ return ret;
56595647 }
56605648
56615649 /*
@@ -5976,6 +5964,7 @@ void intel_display_power_get(struct drm_i915_private *dev_priv, · 314 unmodified lines
59765964 if (!power_well->count++) {
59775965 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
59785966 power_well->ops->enable(dev_priv, power_well);
5967+ power_well->hw_enabled = true;
59795968 }
59805969
59815970 check_power_well_state(dev_priv, power_well);
@@ -6005,6 +5994,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, · 23 unmodified lines
60055994
60065995 if (!--power_well->count && i915.disable_power_well) {
60075996 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
5997+ power_well->hw_enabled = false;
60085998 power_well->ops->disable(dev_priv, power_well);
60095999 }
60106000
@@ -6267,8 +6257,11 @@ static void intel_power_domains_resume(struct drm_i915_private *dev_priv) · 256 unmodified lines
62676257 int i;
62686258
62696259 mutex_lock(&power_domains->lock);
6270− for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
6260+ for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
62716261 power_well->ops->sync_hw(dev_priv, power_well);
6262+ power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
6263+ power_well);
6264+ }
62726265 mutex_unlock(&power_domains->lock);
62736266 }
62746267
drivers/gpu/drm/msm/hdmi/hdmi.c+2−0
@@ -277,6 +277,7 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data) · 276 unmodified lines
277277 static const char *hpd_reg_names[] = {"hpd-gdsc", "hpd-5v"};
278278 static const char *pwr_reg_names[] = {"core-vdda", "core-vcc"};
279279 static const char *hpd_clk_names[] = {"iface_clk", "core_clk", "mdp_core_clk"};
280+ static unsigned long hpd_clk_freq[] = {0, 19200000, 0};
280281 static const char *pwr_clk_names[] = {"extp_clk", "alt_iface_clk"};
281282
282283 config.phy_init = hdmi_phy_8x74_init;
@@ -286,6 +287,7 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data) · 3 unmodified lines
286287 config.pwr_reg_names = pwr_reg_names;
287288 config.pwr_reg_cnt = ARRAY_SIZE(pwr_reg_names);
288289 config.hpd_clk_names = hpd_clk_names;
290+ config.hpd_freq = hpd_clk_freq;
289291 config.hpd_clk_cnt = ARRAY_SIZE(hpd_clk_names);
290292 config.pwr_clk_names = pwr_clk_names;
291293 config.pwr_clk_cnt = ARRAY_SIZE(pwr_clk_names);
drivers/gpu/drm/msm/hdmi/hdmi.h+1−0
@@ -87,6 +87,7 @@ struct hdmi_platform_config { · 86 unmodified lines
8787
8888 /* clks that need to be on for hpd: */
8989 const char **hpd_clk_names;
90+ const long unsigned *hpd_freq;
9091 int hpd_clk_cnt;
9192
9293 /* clks that need to be on for screen pwr (ie pixel clk): */
drivers/gpu/drm/msm/hdmi/hdmi_connector.c+8−0
@@ -127,6 +127,14 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector) · 126 unmodified lines
127127 }
128128
129129 for (i = 0; i < config->hpd_clk_cnt; i++) {
130+ if (config->hpd_freq && config->hpd_freq[i]) {
131+ ret = clk_set_rate(hdmi->hpd_clks[i],
132+ config->hpd_freq[i]);
133+ if (ret)
134+ dev_warn(dev->dev, "failed to set clk %s (%d)\n",
135+ config->hpd_clk_names[i], ret);
136+ }
137+
130138 ret = clk_prepare_enable(hdmi->hpd_clks[i]);
131139 if (ret) {
132140 dev_err(dev->dev, "failed to enable hpd clk: %s (%d)\n",
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c+17−5
@@ -20,6 +20,10 @@ · 19 unmodified lines
2020 #include "msm_mmu.h"
2121 #include "mdp5_kms.h"
2222
23+static const char *iommu_ports[] = {
24+ "mdp_0",
25+};
26+
2327 static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev);
2428
2529 static int mdp5_hw_init(struct msm_kms *kms)
@@ -104,6 +108,12 @@ static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file) · 78 unmodified lines
104108 static void mdp5_destroy(struct msm_kms *kms)
105109 {
106110 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
111+ struct msm_mmu *mmu = mdp5_kms->mmu;
112+
113+ if (mmu) {
114+ mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
115+ mmu->funcs->destroy(mmu);
116+ }
107117 kfree(mdp5_kms);
108118 }
109119
@@ -216,10 +226,6 @@ fail: · 106 unmodified lines
216226 return ret;
217227 }
218228
219−static const char *iommu_ports[] = {
220− "mdp_0",
221−};
222−
223229 static int get_clk(struct platform_device *pdev, struct clk **clkp,
224230 const char *name)
225231 {
@@ -317,17 +323,23 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) · 91 unmodified lines
317323 mmu = msm_iommu_new(dev, config->iommu);
318324 if (IS_ERR(mmu)) {
319325 ret = PTR_ERR(mmu);
326+ dev_err(dev->dev, "failed to init iommu: %d\n", ret);
320327 goto fail;
321328 }
329+
322330 ret = mmu->funcs->attach(mmu, iommu_ports,
323331 ARRAY_SIZE(iommu_ports));
324− if (ret)
332+ if (ret) {
333+ dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
334+ mmu->funcs->destroy(mmu);
325335 goto fail;
336+ }
326337 } else {
327338 dev_info(dev->dev, "no iommu, fallback to phys "
328339 "contig buffers for scanout\n");
329340 mmu = NULL;
330341 }
342+ mdp5_kms->mmu = mmu;
331343
332344 mdp5_kms->id = msm_register_mmu(dev, mmu);
333345 if (mdp5_kms->id < 0) {
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h+1−0
@@ -33,6 +33,7 @@ struct mdp5_kms { · 32 unmodified lines
3333
3434 /* mapper-id used to request GEM buffer mapped for scanout: */
3535 int id;
36+ struct msm_mmu *mmu;
3637
3738 /* for tracking smp allocation amongst pipes: */
3839 mdp5_smp_state_t smp_state;
drivers/gpu/drm/msm/msm_drv.c+1−1
@@ -159,7 +159,7 @@ static int msm_unload(struct drm_device *dev) · 158 unmodified lines
159159 static int get_mdp_ver(struct platform_device *pdev)
160160 {
161161 #ifdef CONFIG_OF
162− const static struct of_device_id match_types[] = { {
162+ static const struct of_device_id match_types[] = { {
163163 .compatible = "qcom,mdss_mdp",
164164 .data = (void *)5,
165165 }, {
drivers/gpu/drm/msm/msm_fbdev.c+1−1
@@ -59,7 +59,7 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, · 58 unmodified lines
5959 struct drm_framebuffer *fb = NULL;
6060 struct fb_info *fbi = NULL;
6161 struct drm_mode_fb_cmd2 mode_cmd = {0};
62− dma_addr_t paddr;
62+ uint32_t paddr;
6363 int ret, size;
6464
6565 sizes->surface_bpp = 32;
drivers/gpu/drm/msm/msm_gem.c+6−0
@@ -278,6 +278,7 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, · 277 unmodified lines
278278 uint32_t *iova)
279279 {
280280 struct msm_gem_object *msm_obj = to_msm_bo(obj);
281+ struct drm_device *dev = obj->dev;
281282 int ret = 0;
282283
283284 if (!msm_obj->domain[id].iova) {
@@ -285,6 +286,11 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, · 1 unmodified line
285286 struct msm_mmu *mmu = priv->mmus[id];
286287 struct page **pages = get_pages(obj);
287288
289+ if (!mmu) {
290+ dev_err(dev->dev, "null MMU pointer\n");
291+ return -EINVAL;
292+ }
293+
288294 if (IS_ERR(pages))
289295 return PTR_ERR(pages);
290296
drivers/gpu/drm/msm/msm_iommu.c+20−3
@@ -28,7 +28,7 @@ static int msm_fault_handler(struct iommu_domain *iommu, struct device *dev, · 27 unmodified lines
2828 unsigned long iova, int flags, void *arg)
2929 {
3030 DBG("*** fault: iova=%08lx, flags=%d", iova, flags);
31− return 0;
31+ return -ENOSYS;
3232 }
3333
3434 static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt)
@@ -40,8 +40,10 @@ static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt) · 5 unmodified lines
4040 for (i = 0; i < cnt; i++) {
4141 struct device *msm_iommu_get_ctx(const char *ctx_name);
4242 struct device *ctx = msm_iommu_get_ctx(names[i]);
43− if (IS_ERR_OR_NULL(ctx))
43+ if (IS_ERR_OR_NULL(ctx)) {
44+ dev_warn(dev->dev, "couldn't get %s context", names[i]);
4445 continue;
46+ }
4547 ret = iommu_attach_device(iommu->domain, ctx);
4648 if (ret) {
4749 dev_warn(dev->dev, "could not attach iommu to %s", names[i]);
@@ -52,6 +54,20 @@ static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt) · 4 unmodified lines
5254 return 0;
5355 }
5456
57+static void msm_iommu_detach(struct msm_mmu *mmu, const char **names, int cnt)
58+{
59+ struct msm_iommu *iommu = to_msm_iommu(mmu);
60+ int i;
61+
62+ for (i = 0; i < cnt; i++) {
63+ struct device *msm_iommu_get_ctx(const char *ctx_name);
64+ struct device *ctx = msm_iommu_get_ctx(names[i]);
65+ if (IS_ERR_OR_NULL(ctx))
66+ continue;
67+ iommu_detach_device(iommu->domain, ctx);
68+ }
69+}
70+
5571 static int msm_iommu_map(struct msm_mmu *mmu, uint32_t iova,
5672 struct sg_table *sgt, unsigned len, int prot)
5773 {
@@ -110,7 +126,7 @@ static int msm_iommu_unmap(struct msm_mmu *mmu, uint32_t iova, · 52 unmodified lines
110126
111127 VERB("unmap[%d]: %08x(%x)", i, iova, bytes);
112128
113− BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE));
129+ BUG_ON(!PAGE_ALIGNED(bytes));
114130
115131 da += bytes;
116132 }
@@ -127,6 +143,7 @@ static void msm_iommu_destroy(struct msm_mmu *mmu) · 10 unmodified lines
127143
128144 static const struct msm_mmu_funcs funcs = {
129145 .attach = msm_iommu_attach,
146+ .detach = msm_iommu_detach,
130147 .map = msm_iommu_map,
131148 .unmap = msm_iommu_unmap,
132149 .destroy = msm_iommu_destroy,
drivers/gpu/drm/msm/msm_mmu.h+1−0
@@ -22,6 +22,7 @@ · 21 unmodified lines
2222
2323 struct msm_mmu_funcs {
2424 int (*attach)(struct msm_mmu *mmu, const char **names, int cnt);
25+ void (*detach)(struct msm_mmu *mmu, const char **names, int cnt);
2526 int (*map)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt,
2627 unsigned len, int prot);
2728 int (*unmap)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt,
include/drm/i915_pciids.h+10−2
@@ -237,13 +237,21 @@ · 236 unmodified lines
237237 #define INTEL_BDW_GT3D_IDS(info) \
238238 _INTEL_BDW_D_IDS(3, info)
239239
240+#define INTEL_BDW_RSVDM_IDS(info) \
241+ _INTEL_BDW_M_IDS(4, info)
242+
243+#define INTEL_BDW_RSVDD_IDS(info) \
244+ _INTEL_BDW_D_IDS(4, info)
245+
240246 #define INTEL_BDW_M_IDS(info) \
241247 INTEL_BDW_GT12M_IDS(info), \
242− INTEL_BDW_GT3M_IDS(info)
248+ INTEL_BDW_GT3M_IDS(info), \
249+ INTEL_BDW_RSVDM_IDS(info)
243250
244251 #define INTEL_BDW_D_IDS(info) \
245252 INTEL_BDW_GT12D_IDS(info), \
246− INTEL_BDW_GT3D_IDS(info)
253+ INTEL_BDW_GT3D_IDS(info), \
254+ INTEL_BDW_RSVDD_IDS(info)
247255
248256 #define INTEL_CHV_IDS(info) \
249257 INTEL_VGA_DEVICE(0x22b0, info), \

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