lael-labs/linux

include/uapi/asm-generic/errno.h+2−0

 #define	EMULTIHOP	72	/* Multihop attempted */
 #define	EDOTDOT		73	/* RFS specific error */
 #define	EBADMSG		74	/* Not a data message */
+#define	EFSBADCRC	EBADMSG	/* Bad CRC detected */
 #define	EOVERFLOW	75	/* Value too large for defined data type */
 #define	ENOTUNIQ	76	/* Name not unique on network */
 #define	EBADFD		77	/* File descriptor in bad state */
 #define	EINPROGRESS	115	/* Operation now in progress */
 #define	ESTALE		116	/* Stale file handle */
 #define	EUCLEAN		117	/* Structure needs cleaning */
+#define	EFSCORRUPTED	EUCLEAN	/* Filesystem is corrupted */
 #define	ENOTNAM		118	/* Not a XENIX named type file */
 #define	ENAVAIL		119	/* No XENIX semaphores available */
 #define	EISNAM		120	/* Is a named type file */

include/uapi/asm-generic/unistd.h+4−1

 #define __NR_listns 470
 __SYSCALL(__NR_listns, sys_listns)
+#define __NR_rseq_slice_yield 471
+__SYSCALL(__NR_rseq_slice_yield, sys_rseq_slice_yield)
 #undef __NR_syscalls
-#define __NR_syscalls 471
+#define __NR_syscalls 472
 /*
  * 32 bit systems traditionally used different

include/uapi/drm/amdgpu_drm.h+20−6

  *
  * %AMDGPU_GEM_DOMAIN_DOORBELL	Doorbell. It is an MMIO region for
  * signalling user mode queues.
- *
- * %AMDGPU_GEM_DOMAIN_MMIO_REMAP	MMIO remap page (special mapping for HDP flushing).
  */
 #define AMDGPU_GEM_DOMAIN_CPU		0x1
 #define AMDGPU_GEM_DOMAIN_GTT		0x2
 #define AMDGPU_GEM_DOMAIN_GWS		0x10
 #define AMDGPU_GEM_DOMAIN_OA		0x20
 #define AMDGPU_GEM_DOMAIN_DOORBELL	0x40
-#define AMDGPU_GEM_DOMAIN_MMIO_REMAP	0x80
 #define AMDGPU_GEM_DOMAIN_MASK		(AMDGPU_GEM_DOMAIN_CPU | \
 					 AMDGPU_GEM_DOMAIN_GTT | \
 					 AMDGPU_GEM_DOMAIN_VRAM | \
 					 AMDGPU_GEM_DOMAIN_GDS | \
 					 AMDGPU_GEM_DOMAIN_GWS | \
 					 AMDGPU_GEM_DOMAIN_OA |	\
-					 AMDGPU_GEM_DOMAIN_DOORBELL | \
+					 AMDGPU_GEM_DOMAIN_DOORBELL)
-					 AMDGPU_GEM_DOMAIN_MMIO_REMAP)
 /* Flag that CPU access will be required for the case of VRAM domain */
 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED	(1 << 0)
 #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
 /* executable mapping, new for VI */
 #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
-/* partially resident texture */
+/* unmapped page of partially resident textures */
 #define AMDGPU_VM_PAGE_PRT		(1 << 4)
 /* MTYPE flags use bit 5 to 8 */
 #define AMDGPU_VM_MTYPE_MASK		(0xf << 5)
 #define AMDGPU_VRAM_TYPE_LPDDR4 11
 #define AMDGPU_VRAM_TYPE_LPDDR5 12
 #define AMDGPU_VRAM_TYPE_HBM3E 13
+#define AMDGPU_VRAM_TYPE_HBM4 14
 struct drm_amdgpu_info_device {
 	/** PCI Device ID */
 	__u32 csa_alignment;
 };
+struct drm_amdgpu_info_uq_metadata_compute {
+	/* EOP size for gfx11 */
+	__u32 eop_size;
+	/* EOP base virtual alignment for gfx11 */
+	__u32 eop_alignment;
+};
+struct drm_amdgpu_info_uq_metadata_sdma {
+	/* context save area size for sdma6 */
+	__u32 csa_size;
+	/* context save area base virtual alignment for sdma6 */
+	__u32 csa_alignment;
+};
 struct drm_amdgpu_info_uq_metadata {
 	union {
 		struct drm_amdgpu_info_uq_metadata_gfx gfx;
+		struct drm_amdgpu_info_uq_metadata_compute compute;
+		struct drm_amdgpu_info_uq_metadata_sdma sdma;
 	};
 };
 #define AMDGPU_FAMILY_GC_10_3_6			149 /* GC 10.3.6 */
 #define AMDGPU_FAMILY_GC_10_3_7			151 /* GC 10.3.7 */
 #define AMDGPU_FAMILY_GC_11_5_0			150 /* GC 11.5.0 */
+#define AMDGPU_FAMILY_GC_11_5_4			154 /* GC 11.5.4 */
 #define AMDGPU_FAMILY_GC_12_0_0			152 /* GC 12.0.0 */
 #if defined(__cplusplus)

include/uapi/drm/amdxdna_accel.h+8−0

@@ -19,6 +19,14 @@ extern "C" { · 18 unmodified lines
19	#define AMDXDNA_INVALID_BO_HANDLE 0	19	#define AMDXDNA_INVALID_BO_HANDLE 0
20	#define AMDXDNA_INVALID_FENCE_HANDLE 0	20	#define AMDXDNA_INVALID_FENCE_HANDLE 0
21		21
		22	/*
		23	* Define hardware context priority
		24	*/
		25	#define AMDXDNA_QOS_REALTIME_PRIORITY 0x100
		26	#define AMDXDNA_QOS_HIGH_PRIORITY 0x180
		27	#define AMDXDNA_QOS_NORMAL_PRIORITY 0x200
		28	#define AMDXDNA_QOS_LOW_PRIORITY 0x280
		29
22	enum amdxdna_device_type {	30	enum amdxdna_device_type {
23	AMDXDNA_DEV_TYPE_UNKNOWN = -1,	31	AMDXDNA_DEV_TYPE_UNKNOWN = -1,
24	AMDXDNA_DEV_TYPE_KMQ,	32	AMDXDNA_DEV_TYPE_KMQ,

include/uapi/drm/panfrost_drm.h+75−1

@@ -24,6 +24,8 @@ extern "C" { · 23 unmodified lines
24	#define DRM_PANFROST_SET_LABEL_BO 0x09	24	#define DRM_PANFROST_SET_LABEL_BO 0x09
25	#define DRM_PANFROST_JM_CTX_CREATE 0x0a	25	#define DRM_PANFROST_JM_CTX_CREATE 0x0a
26	#define DRM_PANFROST_JM_CTX_DESTROY 0x0b	26	#define DRM_PANFROST_JM_CTX_DESTROY 0x0b
		27	#define DRM_PANFROST_SYNC_BO 0x0c
		28	#define DRM_PANFROST_QUERY_BO_INFO 0x0d
27		29
28	#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit)	30	#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit)
29	#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo)	31	#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo)
@@ -35,6 +37,8 @@ extern "C" { · 5 unmodified lines
35	#define DRM_IOCTL_PANFROST_SET_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SET_LABEL_BO, struct drm_panfrost_set_label_bo)	37	#define DRM_IOCTL_PANFROST_SET_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SET_LABEL_BO, struct drm_panfrost_set_label_bo)
36	#define DRM_IOCTL_PANFROST_JM_CTX_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_CREATE, struct drm_panfrost_jm_ctx_create)	38	#define DRM_IOCTL_PANFROST_JM_CTX_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_CREATE, struct drm_panfrost_jm_ctx_create)
37	#define DRM_IOCTL_PANFROST_JM_CTX_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_DESTROY, struct drm_panfrost_jm_ctx_destroy)	39	#define DRM_IOCTL_PANFROST_JM_CTX_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_DESTROY, struct drm_panfrost_jm_ctx_destroy)
		40	#define DRM_IOCTL_PANFROST_SYNC_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SYNC_BO, struct drm_panfrost_sync_bo)
		41	#define DRM_IOCTL_PANFROST_QUERY_BO_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_QUERY_BO_INFO, struct drm_panfrost_query_bo_info)
38		42
39	/*	43	/*
40	* Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module	44	* Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module
@@ -120,9 +124,12 @@ struct drm_panfrost_wait_bo { · 79 unmodified lines
120	__s64 timeout_ns;	124	__s64 timeout_ns;
121	};	125	};
122		126
123	/* Valid flags to pass to drm_panfrost_create_bo */	127	/* Valid flags to pass to drm_panfrost_create_bo.
		128	* PANFROST_BO_WB_MMAP can't be set if PANFROST_BO_HEAP is.
		129	*/
124	#define PANFROST_BO_NOEXEC 1	130	#define PANFROST_BO_NOEXEC 1
125	#define PANFROST_BO_HEAP 2	131	#define PANFROST_BO_HEAP 2
		132	#define PANFROST_BO_WB_MMAP 4
126		133
127	/**	134	/**
128	* struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs.	135	* struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs.
@@ -228,6 +235,13 @@ enum drm_panfrost_param { · 99 unmodified lines
228	DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP,	235	DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP,
229	DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP_FREQUENCY,	236	DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP_FREQUENCY,
230	DRM_PANFROST_PARAM_ALLOWED_JM_CTX_PRIORITIES,	237	DRM_PANFROST_PARAM_ALLOWED_JM_CTX_PRIORITIES,
		238	DRM_PANFROST_PARAM_SELECTED_COHERENCY,
		239	};
		240
		241	enum drm_panfrost_gpu_coherency {
		242	DRM_PANFROST_GPU_COHERENCY_ACE_LITE = 0,
		243	DRM_PANFROST_GPU_COHERENCY_ACE = 1,
		244	DRM_PANFROST_GPU_COHERENCY_NONE = 31,
231	};	245	};
232		246
233	struct drm_panfrost_get_param {	247	struct drm_panfrost_get_param {
@@ -301,6 +315,66 @@ struct drm_panfrost_set_label_bo { · 67 unmodified lines
301	__u64 label;	315	__u64 label;
302	};	316	};
303		317
		318	/* Valid flags to pass to drm_panfrost_bo_sync_op */
		319	#define PANFROST_BO_SYNC_CPU_CACHE_FLUSH 0
		320	#define PANFROST_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE 1
		321
		322	/**
		323	* struct drm_panthor_bo_flush_map_op - BO map sync op
		324	*/
		325	struct drm_panfrost_bo_sync_op {
		326	/** @handle: Handle of the buffer object to sync. */
		327	__u32 handle;
		328
		329	/** @type: Type of sync operation. */
		330	__u32 type;
		331
		332	/**
		333	* @offset: Offset into the BO at which the sync range starts.
		334	*
		335	* This will be rounded down to the nearest cache line as needed.
		336	*/
		337	__u32 offset;
		338
		339	/**
		340	* @size: Size of the range to sync
		341	*
		342	* @size + @offset will be rounded up to the nearest cache line as
		343	* needed.
		344	*/
		345	__u32 size;
		346	};
		347
		348	/**
		349	* struct drm_panfrost_sync_bo - ioctl argument for syncing BO maps
		350	*/
		351	struct drm_panfrost_sync_bo {
		352	/** Array of struct drm_panfrost_bo_sync_op */
		353	__u64 ops;
		354
		355	/** Number of BO sync ops */
		356	__u32 op_count;
		357
		358	__u32 pad;
		359	};
		360
		361	/** BO comes from a different subsystem. */
		362	#define DRM_PANFROST_BO_IS_IMPORTED (1 << 0)
		363
		364	struct drm_panfrost_query_bo_info {
		365	/** Handle of the object being queried. */
		366	__u32 handle;
		367
		368	/** Extra flags that are not coming from the BO_CREATE ioctl(). */
		369	__u32 extra_flags;
		370
		371	/** Flags passed at creation time. */
		372	__u32 create_flags;
		373
		374	/** Will be zero on return. */
		375	__u32 pad;
		376	};
		377
304	/* Definitions for coredump decoding in user space */	378	/* Definitions for coredump decoding in user space */
305	#define PANFROSTDUMP_MAJOR 1	379	#define PANFROSTDUMP_MAJOR 1
306	#define PANFROSTDUMP_MINOR 0	380	#define PANFROSTDUMP_MINOR 0

include/uapi/drm/panthor_drm.h+154−3

@@ -144,6 +144,16 @@ enum drm_panthor_ioctl_id { · 143 unmodified lines
144	* pgoff_t size.	144	* pgoff_t size.
145	*/	145	*/
146	DRM_PANTHOR_SET_USER_MMIO_OFFSET,	146	DRM_PANTHOR_SET_USER_MMIO_OFFSET,
		147
		148	/** @DRM_PANTHOR_BO_SYNC: Sync BO data to/from the device */
		149	DRM_PANTHOR_BO_SYNC,
		150
		151	/**
		152	* @DRM_PANTHOR_BO_QUERY_INFO: Query information about a BO.
		153	*
		154	* This is useful for imported BOs.
		155	*/
		156	DRM_PANTHOR_BO_QUERY_INFO,
147	};	157	};
148		158
149	/**	159	/**
@@ -245,6 +255,26 @@ enum drm_panthor_dev_query_type { · 95 unmodified lines
245	DRM_PANTHOR_DEV_QUERY_GROUP_PRIORITIES_INFO,	255	DRM_PANTHOR_DEV_QUERY_GROUP_PRIORITIES_INFO,
246	};	256	};
247		257
		258	/**
		259	* enum drm_panthor_gpu_coherency: Type of GPU coherency
		260	*/
		261	enum drm_panthor_gpu_coherency {
		262	/**
		263	* @DRM_PANTHOR_GPU_COHERENCY_ACE_LITE: ACE Lite coherency.
		264	*/
		265	DRM_PANTHOR_GPU_COHERENCY_ACE_LITE = 0,
		266
		267	/**
		268	* @DRM_PANTHOR_GPU_COHERENCY_ACE: ACE coherency.
		269	*/
		270	DRM_PANTHOR_GPU_COHERENCY_ACE = 1,
		271
		272	/**
		273	* @DRM_PANTHOR_GPU_COHERENCY_NONE: No coherency.
		274	*/
		275	DRM_PANTHOR_GPU_COHERENCY_NONE = 31,
		276	};
		277
248	/**	278	/**
249	* struct drm_panthor_gpu_info - GPU information	279	* struct drm_panthor_gpu_info - GPU information
250	*	280	*
@@ -301,7 +331,16 @@ struct drm_panthor_gpu_info { · 50 unmodified lines
301	*/	331	*/
302	__u32 thread_max_barrier_size;	332	__u32 thread_max_barrier_size;
303		333
304	/** @coherency_features: Coherency features. */	334	/**
		335	* @coherency_features: Coherency features.
		336	*
		337	* Combination of drm_panthor_gpu_coherency flags.
		338	*
		339	* Note that this is just what the coherency protocols supported by the
		340	* GPU, but the actual coherency in place depends on the SoC
		341	* integration and is reflected by
		342	* drm_panthor_gpu_info::selected_coherency.
		343	*/
305	__u32 coherency_features;	344	__u32 coherency_features;
306		345
307	/** @texture_features: Texture features. */	346	/** @texture_features: Texture features. */
@@ -310,8 +349,12 @@ struct drm_panthor_gpu_info { · 2 unmodified lines
310	/** @as_present: Bitmask encoding the number of address-space exposed by the MMU. */	349	/** @as_present: Bitmask encoding the number of address-space exposed by the MMU. */
311	__u32 as_present;	350	__u32 as_present;
312		351
313	/** @pad0: MBZ. */	352	/**
314	__u32 pad0;	353	* @selected_coherency: Coherency selected for this device.
		354	*
		355	* One of drm_panthor_gpu_coherency.
		356	*/
		357	__u32 selected_coherency;
315		358
316	/** @shader_present: Bitmask encoding the shader cores exposed by the GPU. */	359	/** @shader_present: Bitmask encoding the shader cores exposed by the GPU. */
317	__u64 shader_present;	360	__u64 shader_present;
@@ -638,6 +681,15 @@ struct drm_panthor_vm_get_state { · 320 unmodified lines
638	enum drm_panthor_bo_flags {	681	enum drm_panthor_bo_flags {
639	/** @DRM_PANTHOR_BO_NO_MMAP: The buffer object will never be CPU-mapped in userspace. */	682	/** @DRM_PANTHOR_BO_NO_MMAP: The buffer object will never be CPU-mapped in userspace. */
640	DRM_PANTHOR_BO_NO_MMAP = (1 << 0),	683	DRM_PANTHOR_BO_NO_MMAP = (1 << 0),
		684
		685	/**
		686	* @DRM_PANTHOR_BO_WB_MMAP: Force "Write-Back Cacheable" CPU mapping.
		687	*
		688	* CPU map the buffer object in userspace by forcing the "Write-Back
		689	* Cacheable" cacheability attribute. The mapping otherwise uses the
		690	* "Non-Cacheable" attribute if the GPU is not IO coherent.
		691	*/
		692	DRM_PANTHOR_BO_WB_MMAP = (1 << 1),
641	};	693	};
642		694
643	/**	695	/**
@@ -1040,6 +1092,101 @@ struct drm_panthor_set_user_mmio_offset { · 396 unmodified lines
1040	__u64 offset;	1092	__u64 offset;
1041	};	1093	};
1042		1094
		1095	/**
		1096	* enum drm_panthor_bo_sync_op_type - BO sync type
		1097	*/
		1098	enum drm_panthor_bo_sync_op_type {
		1099	/** @DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH: Flush CPU caches. */
		1100	DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH = 0,
		1101
		1102	/** @DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE: Flush and invalidate CPU caches. */
		1103	DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE = 1,
		1104	};
		1105
		1106	/**
		1107	* struct drm_panthor_bo_sync_op - BO map sync op
		1108	*/
		1109	struct drm_panthor_bo_sync_op {
		1110	/** @handle: Handle of the buffer object to sync. */
		1111	__u32 handle;
		1112
		1113	/** @type: Type of operation. */
		1114	__u32 type;
		1115
		1116	/**
		1117	* @offset: Offset into the BO at which the sync range starts.
		1118	*
		1119	* This will be rounded down to the nearest cache line as needed.
		1120	*/
		1121	__u64 offset;
		1122
		1123	/**
		1124	* @size: Size of the range to sync
		1125	*
		1126	* @size + @offset will be rounded up to the nearest cache line as
		1127	* needed.
		1128	*/
		1129	__u64 size;
		1130	};
		1131
		1132	/**
		1133	* struct drm_panthor_bo_sync - BO map sync request
		1134	*/
		1135	struct drm_panthor_bo_sync {
		1136	/**
		1137	* @ops: Array of struct drm_panthor_bo_sync_op sync operations.
		1138	*/
		1139	struct drm_panthor_obj_array ops;
		1140	};
		1141
		1142	/**
		1143	* enum drm_panthor_bo_extra_flags - Set of flags returned on a BO_QUERY_INFO request
		1144	*
		1145	* Those are flags reflecting BO properties that are not directly coming from the flags
		1146	* passed are creation time, or information on BOs that were imported from other drivers.
		1147	*/
		1148	enum drm_panthor_bo_extra_flags {
		1149	/**
		1150	* @DRM_PANTHOR_BO_IS_IMPORTED: BO has been imported from an external driver.
		1151	*
		1152	* Note that imported dma-buf handles are not flagged as imported if they
		1153	* where exported by panthor. Only buffers that are coming from other drivers
		1154	* (dma heaps, other GPUs, display controllers, V4L, ...).
		1155	*
		1156	* It's also important to note that all imported BOs are mapped cached and can't
		1157	* be considered IO-coherent even if the GPU is. This means they require explicit
		1158	* syncs that must go through the DRM_PANTHOR_BO_SYNC ioctl (userland cache
		1159	* maintenance is not allowed in that case, because extra operations might be
		1160	* needed to make changes visible to the CPU/device, like buffer migration when the
		1161	* exporter is a GPU with its own VRAM).
		1162	*/
		1163	DRM_PANTHOR_BO_IS_IMPORTED = (1 << 0),
		1164	};
		1165
		1166	/**
		1167	* struct drm_panthor_bo_query_info - Query BO info
		1168	*/
		1169	struct drm_panthor_bo_query_info {
		1170	/** @handle: Handle of the buffer object to query flags on. */
		1171	__u32 handle;
		1172
		1173	/**
		1174	* @extra_flags: Combination of enum drm_panthor_bo_extra_flags flags.
		1175	*/
		1176	__u32 extra_flags;
		1177
		1178	/**
		1179	* @create_flags: Flags passed at creation time.
		1180	*
		1181	* Combination of enum drm_panthor_bo_flags flags.
		1182	* Will be zero if the buffer comes from a different driver.
		1183	*/
		1184	__u32 create_flags;
		1185
		1186	/** @pad: Will be zero on return. */
		1187	__u32 pad;
		1188	};
		1189
1043	/**	1190	/**
1044	* DRM_IOCTL_PANTHOR() - Build a Panthor IOCTL number	1191	* DRM_IOCTL_PANTHOR() - Build a Panthor IOCTL number
1045	* @__access: Access type. Must be R, W or RW.	1192	* @__access: Access type. Must be R, W or RW.
@@ -1086,6 +1233,10 @@ enum { · 40 unmodified lines
1086	DRM_IOCTL_PANTHOR(WR, BO_SET_LABEL, bo_set_label),	1233	DRM_IOCTL_PANTHOR(WR, BO_SET_LABEL, bo_set_label),
1087	DRM_IOCTL_PANTHOR_SET_USER_MMIO_OFFSET =	1234	DRM_IOCTL_PANTHOR_SET_USER_MMIO_OFFSET =
1088	DRM_IOCTL_PANTHOR(WR, SET_USER_MMIO_OFFSET, set_user_mmio_offset),	1235	DRM_IOCTL_PANTHOR(WR, SET_USER_MMIO_OFFSET, set_user_mmio_offset),
		1236	DRM_IOCTL_PANTHOR_BO_SYNC =
		1237	DRM_IOCTL_PANTHOR(WR, BO_SYNC, bo_sync),
		1238	DRM_IOCTL_PANTHOR_BO_QUERY_INFO =
		1239	DRM_IOCTL_PANTHOR(WR, BO_QUERY_INFO, bo_query_info),
1089	};	1240	};
1090		1241
1091	#if defined(__cplusplus)	1242	#if defined(__cplusplus)

include/uapi/drm/rocket_accel.h+74−24

  *
  */
 struct drm_rocket_create_bo {
-	/** Input: Size of the requested BO. */
+	/**
+	 * @size: Input: Size of the requested BO.
+	 */
 	__u32 size;
-	/** Output: GEM handle for the BO. */
+	/**
+	 * @handle: Output: GEM handle for the BO.
+	 */
 	__u32 handle;
 	/**
-	 * Output: DMA address for the BO in the NPU address space.  This address
+	 * @dma_address: Output: DMA address for the BO in the NPU address
-	 * is private to the DRM fd and is valid for the lifetime of the GEM
+	 * space.  This address is private to the DRM fd and is valid for
-	 * handle.
+	 * the lifetime of the GEM handle.
 	 */
 	__u64 dma_address;
-	/** Output: Offset into the drm node to use for subsequent mmap call. */
+	/**
+	 * @offset: Output: Offset into the drm node to use for subsequent
+	 * mmap call.
+	 */
 	__u64 offset;
 };
  * synchronization.
  */
 struct drm_rocket_prep_bo {
-	/** Input: GEM handle of the buffer object. */
+	/**
+	 * @handle: Input: GEM handle of the buffer object.
+	 */
 	__u32 handle;
-	/** Reserved, must be zero. */
+	/**
+	 * @reserved: Reserved, must be zero.
+	 */
 	__u32 reserved;
-	/** Input: Amount of time to wait for NPU jobs. */
+	/**
+	 * @timeout_ns: Input: Amount of time to wait for NPU jobs.
+	 */
 	__s64 timeout_ns;
 };
  * Synchronize caches for NPU access.
  */
 struct drm_rocket_fini_bo {
-	/** Input: GEM handle of the buffer object. */
+	/**
+	 * @handle: Input: GEM handle of the buffer object.
+	 */
 	__u32 handle;
-	/** Reserved, must be zero. */
+	/**
+	 * @reserved: Reserved, must be zero.
+	 */
 	__u32 reserved;
 };
  * A task is the smallest unit of work that can be run on the NPU.
  */
 struct drm_rocket_task {
-	/** Input: DMA address to NPU mapping of register command buffer */
+	/**
+	 * @regcmd: Input: DMA address to NPU mapping of register command buffer
+	 */
 	__u32 regcmd;
-	/** Input: Number of commands in the register command buffer */
+	/**
+	 * @regcmd_count: Input: Number of commands in the register command
+	 * buffer
+	 */
 	__u32 regcmd_count;
 };
  * sequentially on the same core, to benefit from memory residency in SRAM.
  */
 struct drm_rocket_job {
-	/** Input: Pointer to an array of struct drm_rocket_task. */
+	/**
+	 * @tasks: Input: Pointer to an array of struct drm_rocket_task.
+	 */
 	__u64 tasks;
-	/** Input: Pointer to a u32 array of the BOs that are read by the job. */
+	/**
+	 * @in_bo_handles: Input: Pointer to a u32 array of the BOs that
+	 * are read by the job.
+	 */
 	__u64 in_bo_handles;
-	/** Input: Pointer to a u32 array of the BOs that are written to by the job. */
+	/**
+	 * @out_bo_handles: Input: Pointer to a u32 array of the BOs that
+	 * are written to by the job.
+	 */
 	__u64 out_bo_handles;
-	/** Input: Number of tasks passed in. */
+	/**
+	 * @task_count: Input: Number of tasks passed in.
+	 */
 	__u32 task_count;
-	/** Input: Size in bytes of the structs in the @tasks field. */
+	/**
+	 * @task_struct_size: Input: Size in bytes of the structs in the
+	 * @tasks field.
+	 */
 	__u32 task_struct_size;
-	/** Input: Number of input BO handles passed in (size is that times 4). */
+	/**
+	 * @in_bo_handle_count: Input: Number of input BO handles passed in
+	 * (size is that times 4).
+	 */
 	__u32 in_bo_handle_count;
-	/** Input: Number of output BO handles passed in (size is that times 4). */
+	/**
+	 * @out_bo_handle_count: Input: Number of output BO handles passed in
+	 * (size is that times 4).
+	 */
 	__u32 out_bo_handle_count;
 };
  * The kernel will schedule the execution of these jobs in dependency order.
  */
 struct drm_rocket_submit {
-	/** Input: Pointer to an array of struct drm_rocket_job. */
+	/**
+	 * @jobs: Input: Pointer to an array of struct drm_rocket_job.
+	 */
 	__u64 jobs;
-	/** Input: Number of jobs passed in. */
+	/**
+	 * @job_count: Input: Number of jobs passed in.
+	 */
 	__u32 job_count;
-	/** Input: Size in bytes of the structs in the @jobs field. */
+	/**
+	 * @job_struct_size: Input: Size in bytes of the structs in the
+	 * @jobs field.
+	 */
 	__u32 job_struct_size;
-	/** Reserved, must be zero. */
+	/**
+	 * @reserved: Reserved, must be zero.
+	 */
 	__u64 reserved;
 };

include/uapi/drm/xe_drm.h+89−6

 #define DRM_XE_OBSERVATION		0x0b
 #define DRM_XE_MADVISE			0x0c
 #define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS	0x0d
+#define DRM_XE_EXEC_QUEUE_SET_PROPERTY	0x0e
 /* Must be kept compact -- no holes */
 #define DRM_IOCTL_XE_OBSERVATION		DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param)
 #define DRM_IOCTL_XE_MADVISE			DRM_IOW(DRM_COMMAND_BASE + DRM_XE_MADVISE, struct drm_xe_madvise)
 #define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS	DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr)
+#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY	DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
 /**
  * DOC: Xe IOCTL Extensions
 	/** @pad: MBZ */
 	__u32 pad;
-	/** @value: property value */
+	union {
-	__u64 value;
+		/** @value: property value */
+		__u64 value;
+		/** @ptr: pointer to user value */
+		__u64 ptr;
+	};
 	/** @reserved: Reserved */
 	__u64 reserved[2];
  *      has low latency hint support
  *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
  *      device has CPU address mirroring support
+ *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the
+ *      device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION.
+ *      This is exposed only on Xe2+.
  *  - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
  *    required by this device, typically SZ_4K or SZ_64K
  *  - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
 	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM	(1 << 0)
 	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY	(1 << 1)
 	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR	(1 << 2)
+	#define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3)
 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT		2
 #define DRM_XE_QUERY_CONFIG_VA_BITS			3
 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY	4
  *    need to use VRAM for display surfaces, therefore the kernel requires
  *    setting this flag for such objects, otherwise an error is thrown on
  *    small-bar systems.
+ *  - %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION - Allows userspace to
+ *    hint that compression (CCS) should be disabled for the buffer being
+ *    created. This can avoid unnecessary memory operations and CCS state
+ *    management.
+ *    On pre-Xe2 platforms, this flag is currently rejected as compression
+ *    control is not supported via PAT index. On Xe2+ platforms, compression
+ *    is controlled via PAT entries. If this flag is set, the driver will reject
+ *    any VM bind that requests a PAT index enabling compression for this BO.
+ *    Note: On dGPU platforms, there is currently no change in behavior with
+ *    this flag, but future improvements may leverage it. The current benefit is
+ *    primarily applicable to iGPU platforms.
  *
  * @cpu_caching supports the following values:
  *  - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING		(1 << 0)
 #define DRM_XE_GEM_CREATE_FLAG_SCANOUT			(1 << 1)
 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM	(1 << 2)
+#define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION		(1 << 3)
 	/**
 	 * @flags: Flags, currently a mask of memory instances of where BO can
 	 * be placed
  *    Given that going into a power-saving state kills PXP HWDRM sessions,
  *    runtime PM will be blocked while queues of this type are alive.
  *    All PXP queues will be killed if a PXP invalidation event occurs.
+ *  - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP - Create a multi-queue group
+ *    or add secondary queues to a multi-queue group.
+ *    If the extension's 'value' field has %DRM_XE_MULTI_GROUP_CREATE flag set,
+ *    then a new multi-queue group is created with this queue as the primary queue
+ *    (Q0). Otherwise, the queue gets added to the multi-queue group whose primary
+ *    queue's exec_queue_id is specified in the lower 32 bits of the 'value' field.
+ *    All the other non-relevant bits of extension's 'value' field while adding the
+ *    primary or the secondary queues of the group must be set to 0.
+ *  - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set the queue
+ *    priority within the multi-queue group. Current valid priority values are 0–2
+ *    (default is 1), with higher values indicating higher priority.
  *
  * The example below shows how to use @drm_xe_exec_queue_create to create
  * a simple exec_queue (no parallel submission) of class
 #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY		0
 #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE		1
 #define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE		2
+#define   DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE		3
+#define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP		4
+#define     DRM_XE_MULTI_GROUP_CREATE				(1ull << 63)
+#define   DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY	5
 	/** @extensions: Pointer to the first extension struct, if any */
 	__u64 extensions;
 	/** @DRM_XE_OA_UNIT_TYPE_OAM_SAG: OAM_SAG OA unit */
 	DRM_XE_OA_UNIT_TYPE_OAM_SAG,
+	/** @DRM_XE_OA_UNIT_TYPE_MERT: MERT OA unit */
+	DRM_XE_OA_UNIT_TYPE_MERT,
 };
 /**
 #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE	(1 << 2)
 #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS	(1 << 3)
 #define DRM_XE_OA_CAPS_OAM		(1 << 4)
+#define DRM_XE_OA_CAPS_OA_UNIT_GT_ID	(1 << 5)
 	/** @oa_timestamp_freq: OA timestamp freq */
 	__u64 oa_timestamp_freq;
+	/** @gt_id: gt id for this OA unit */
+	__u16 gt_id;
+	/** @reserved1: MBZ */
+	__u16 reserved1[3];
 	/** @reserved: MBZ */
-	__u64 reserved[4];
+	__u64 reserved[3];
 	/** @num_engines: number of engines in @eci array */
 	__u64 num_engines;
 		struct {
 #define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE	0
 #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM	-1
-			/** @preferred_mem_loc.devmem_fd: fd for preferred loc */
+			/**
+			 * @preferred_mem_loc.devmem_fd:
+			 * Device file-descriptor of the device where the
+			 * preferred memory is located, or one of the
+			 * above special values. Please also see
+			 * @preferred_mem_loc.region_instance below.
+			 */
 			__u32 devmem_fd;
 #define DRM_XE_MIGRATE_ALL_PAGES		0
 			/** @preferred_mem_loc.migration_policy: Page migration policy */
 			__u16 migration_policy;
-			/** @preferred_mem_loc.pad : MBZ */
+			/**
-			__u16 pad;
+			 * @preferred_mem_loc.region_instance : Region instance.
+			 * MBZ if @devmem_fd <= &DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE.
+			 * Otherwise should point to the desired device
+			 * VRAM instance of the device indicated by
+			 * @preferred_mem_loc.devmem_fd.
+			 */
+			__u16 region_instance;
 			/** @preferred_mem_loc.reserved : Reserved */
 			__u64 reserved;
 };
+/**
+ * struct drm_xe_exec_queue_set_property - exec queue set property
+ *
+ * Sets execution queue properties dynamically.
+ * Currently only %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY
+ * property can be dynamically set.
+ */
+struct drm_xe_exec_queue_set_property {
+	/** @extensions: Pointer to the first extension struct, if any */
+	__u64 extensions;
+	/** @exec_queue_id: Exec queue ID */
+	__u32 exec_queue_id;
+	/** @property: property to set */
+	__u32 property;
+	/** @value: property value */
+	__u64 value;
+	/** @reserved: Reserved */
+	__u64 reserved[2];
+};
 #if defined(__cplusplus)
 }
 #endif

include/uapi/linux/android/binder.h+1−1

@@ -278,7 +278,7 @@ enum { · 277 unmodified lines
278	* NOTE: Two special error codes you should check for when calling	278	* NOTE: Two special error codes you should check for when calling
279	* in to the driver are:	279	* in to the driver are:
280	*	280	*
281	* EINTR -- The operation has been interupted. This should be	281	* EINTR -- The operation has been interrupted. This should be
282	* handled by retrying the ioctl() until a different error code	282	* handled by retrying the ioctl() until a different error code
283	* is returned.	283	* is returned.
284	*	284	*

include/uapi/linux/blkzoned.h+4−2

 	BLK_ZONE_COND_FULL	= 0xE,
 	BLK_ZONE_COND_OFFLINE	= 0xF,
-	BLK_ZONE_COND_ACTIVE	= 0xFF,
+	BLK_ZONE_COND_ACTIVE	= 0xFF, /* added in Linux 6.19 */
+#define BLK_ZONE_COND_ACTIVE	BLK_ZONE_COND_ACTIVE
 };
 /**
 	BLK_ZONE_REP_CAPACITY	= (1U << 0),
 	/* Input flags */
-	BLK_ZONE_REP_CACHED	= (1U << 31),
+	BLK_ZONE_REP_CACHED	= (1U << 31), /* added in Linux 6.19 */
+#define BLK_ZONE_REP_CACHED	BLK_ZONE_REP_CACHED
 };
 /**

include/uapi/linux/bpf.h+28−0

 	BPF_CGROUP_ITER_DESCENDANTS_PRE,	/* walk descendants in pre-order. */
 	BPF_CGROUP_ITER_DESCENDANTS_POST,	/* walk descendants in post-order. */
 	BPF_CGROUP_ITER_ANCESTORS_UP,		/* walk ancestors upward. */
+	/*
+	 * Walks the immediate children of the specified parent
+	 * cgroup_subsys_state. Unlike BPF_CGROUP_ITER_DESCENDANTS_PRE,
+	 * BPF_CGROUP_ITER_DESCENDANTS_POST, and BPF_CGROUP_ITER_ANCESTORS_UP
+	 * the iterator does not include the specified parent as one of the
+	 * returned iterator elements.
+	 */
+	BPF_CGROUP_ITER_CHILDREN,
 };
 union bpf_iter_link_info {
  *		Number of bytes read from the stream on success, or -1 if an
  *		error occurred (in which case, *errno* is set appropriately).
  *
+ * BPF_PROG_ASSOC_STRUCT_OPS
+ * 	Description
+ * 		Associate a BPF program with a struct_ops map. The struct_ops
+ * 		map is identified by *map_fd* and the BPF program is
+ * 		identified by *prog_fd*.
+ *
+ * 	Return
+ * 		0 on success or -1 if an error occurred (in which case,
+ * 		*errno* is set appropriately).
+ *
  * NOTES
  *	eBPF objects (maps and programs) can be shared between processes.
  *
 	BPF_PROG_BIND_MAP,
 	BPF_TOKEN_CREATE,
 	BPF_PROG_STREAM_READ_BY_FD,
+	BPF_PROG_ASSOC_STRUCT_OPS,
 	__MAX_BPF_CMD,
 };
 	BPF_NETKIT_PEER,
 	BPF_TRACE_KPROBE_SESSION,
 	BPF_TRACE_UPROBE_SESSION,
+	BPF_TRACE_FSESSION,
 	__MAX_BPF_ATTACH_TYPE
 };
 	BPF_NOEXIST	= 1, /* create new element if it didn't exist */
 	BPF_EXIST	= 2, /* update existing element */
 	BPF_F_LOCK	= 4, /* spin_lock-ed map_lookup/map_update */
+	BPF_F_CPU	= 8, /* cpu flag for percpu maps, upper 32-bit of flags is a cpu number */
+	BPF_F_ALL_CPUS	= 16, /* update value across all CPUs for percpu maps */
 };
 /* flags for BPF_MAP_CREATE command */
 		__u32		prog_fd;
 	} prog_stream_read;
+	struct {
+		__u32		map_fd;
+		__u32		prog_fd;
+		__u32		flags;
+	} prog_assoc_struct_ops;
 } __attribute__((aligned(8)));
 /* The description below is an attempt at providing documentation to eBPF

include/uapi/linux/btrfs.h+1−0

@@ -336,6 +336,7 @@ struct btrfs_ioctl_fs_info_args { · 335 unmodified lines
336	#define BTRFS_FEATURE_INCOMPAT_EXTENT_TREE_V2 (1ULL << 13)	336	#define BTRFS_FEATURE_INCOMPAT_EXTENT_TREE_V2 (1ULL << 13)
337	#define BTRFS_FEATURE_INCOMPAT_RAID_STRIPE_TREE (1ULL << 14)	337	#define BTRFS_FEATURE_INCOMPAT_RAID_STRIPE_TREE (1ULL << 14)
338	#define BTRFS_FEATURE_INCOMPAT_SIMPLE_QUOTA (1ULL << 16)	338	#define BTRFS_FEATURE_INCOMPAT_SIMPLE_QUOTA (1ULL << 16)
		339	#define BTRFS_FEATURE_INCOMPAT_REMAP_TREE (1ULL << 17)
339		340
340	struct btrfs_ioctl_feature_flags {	341	struct btrfs_ioctl_feature_flags {
341	__u64 compat_flags;	342	__u64 compat_flags;

include/uapi/linux/btrfs_tree.h+32−2

 /* Tracks RAID stripes in block groups. */
 #define BTRFS_RAID_STRIPE_TREE_OBJECTID 12ULL
+/* Holds details of remapped addresses after relocation. */
+#define BTRFS_REMAP_TREE_OBJECTID 13ULL
 /* device stats in the device tree */
 #define BTRFS_DEV_STATS_OBJECTID 0ULL
 #define BTRFS_RAID_STRIPE_KEY	230
+#define BTRFS_IDENTITY_REMAP_KEY 	234
+#define BTRFS_REMAP_KEY		 	235
+#define BTRFS_REMAP_BACKREF_KEY	 	236
 /*
  * Records the overall state of the qgroups.
  * There's only one instance of this key present,
 	__u8 metadata_uuid[BTRFS_FSID_SIZE];
 	__u64 nr_global_roots;
+	__le64 remap_root;
+	__le64 remap_root_generation;
+	__u8 remap_root_level;
 	/* Future expansion */
-	__le64 reserved[27];
+	__u8 reserved[199];
 	__u8 sys_chunk_array[BTRFS_SYSTEM_CHUNK_ARRAY_SIZE];
 	struct btrfs_root_backup super_roots[BTRFS_NUM_BACKUP_ROOTS];
 #define BTRFS_BLOCK_GROUP_RAID6         (1ULL << 8)
 #define BTRFS_BLOCK_GROUP_RAID1C3       (1ULL << 9)
 #define BTRFS_BLOCK_GROUP_RAID1C4       (1ULL << 10)
+#define BTRFS_BLOCK_GROUP_REMAPPED      (1ULL << 11)
+#define BTRFS_BLOCK_GROUP_METADATA_REMAP (1ULL << 12)
 #define BTRFS_BLOCK_GROUP_RESERVED	(BTRFS_AVAIL_ALLOC_BIT_SINGLE | \
 					 BTRFS_SPACE_INFO_GLOBAL_RSV)
 #define BTRFS_BLOCK_GROUP_TYPE_MASK	(BTRFS_BLOCK_GROUP_DATA |    \
 					 BTRFS_BLOCK_GROUP_SYSTEM |  \
-					 BTRFS_BLOCK_GROUP_METADATA)
+					 BTRFS_BLOCK_GROUP_METADATA | \
+					 BTRFS_BLOCK_GROUP_METADATA_REMAP)
 #define BTRFS_BLOCK_GROUP_PROFILE_MASK	(BTRFS_BLOCK_GROUP_RAID0 |   \
 					 BTRFS_BLOCK_GROUP_RAID1 |   \
 	__le64 flags;
 } __attribute__ ((__packed__));
+struct btrfs_block_group_item_v2 {
+	__le64 used;
+	__le64 chunk_objectid;
+	__le64 flags;
+	__le64 remap_bytes;
+	__le32 identity_remap_count;
+} __attribute__ ((__packed__));
 struct btrfs_free_space_info {
 	__le32 extent_count;
 	__le32 flags;
 	__u8 encryption;
 } __attribute__ ((__packed__));
+/*
+ * For a range identified by a BTRFS_REMAP_KEY item in the remap tree, gives
+ * the address that the start of the range will get remapped to.  This
+ * structure is also shared by BTRFS_REMAP_BACKREF_KEY.
+ */
+struct btrfs_remap_item {
+	__le64 address;
+} __attribute__ ((__packed__));
 #endif /* _BTRFS_CTREE_H_ */

include/uapi/linux/comedi.h+1−1

@@ -640,7 +640,7 @@ struct comedi_chaninfo { · 639 unmodified lines
640		640
641	/**	641	/**
642	* struct comedi_rangeinfo - used to retrieve the range table for a channel	642	* struct comedi_rangeinfo - used to retrieve the range table for a channel
643	* @range_type: Encodes subdevice index (bits 27:24), channel index	643	* @range_type: Encodes subdevice index (bits 31:24), channel index
644	* (bits 23:16) and range table length (bits 15:0).	644	* (bits 23:16) and range table length (bits 15:0).
645	* @range_ptr: Pointer to array of @struct comedi_krange to be filled	645	* @range_ptr: Pointer to array of @struct comedi_krange to be filled
646	* in with the range table for the channel or subdevice.	646	* in with the range table for the channel or subdevice.

include/uapi/linux/dev_energymodel.h+82−0

@@ -0,0 +1,82 @@
	1	/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
	2	/* Do not edit directly, auto-generated from: */
	3	/* Documentation/netlink/specs/dev-energymodel.yaml */
	4	/* YNL-GEN uapi header */
	5	/* To regenerate run: tools/net/ynl/ynl-regen.sh */
	6
	7	#ifndef _UAPI_LINUX_DEV_ENERGYMODEL_H
	8	#define _UAPI_LINUX_DEV_ENERGYMODEL_H
	9
	10	#define DEV_ENERGYMODEL_FAMILY_NAME "dev-energymodel"
	11	#define DEV_ENERGYMODEL_FAMILY_VERSION 1
	12
	13	/**
	14	* enum dev_energymodel_perf_state_flags
	15	* @DEV_ENERGYMODEL_PERF_STATE_FLAGS_PERF_STATE_INEFFICIENT: The performance
	16	* state is inefficient. There is in this perf-domain, another performance
	17	* state with a higher frequency but a lower or equal power cost.
	18	*/
	19	enum dev_energymodel_perf_state_flags {
	20	DEV_ENERGYMODEL_PERF_STATE_FLAGS_PERF_STATE_INEFFICIENT = 1,
	21	};
	22
	23	/**
	24	* enum dev_energymodel_perf_domain_flags
	25	* @DEV_ENERGYMODEL_PERF_DOMAIN_FLAGS_PERF_DOMAIN_MICROWATTS: The power values
	26	* are in micro-Watts or some other scale.
	27	* @DEV_ENERGYMODEL_PERF_DOMAIN_FLAGS_PERF_DOMAIN_SKIP_INEFFICIENCIES: Skip
	28	* inefficient states when estimating energy consumption.
	29	* @DEV_ENERGYMODEL_PERF_DOMAIN_FLAGS_PERF_DOMAIN_ARTIFICIAL: The power values
	30	* are artificial and might be created by platform missing real power
	31	* information.
	32	*/
	33	enum dev_energymodel_perf_domain_flags {
	34	DEV_ENERGYMODEL_PERF_DOMAIN_FLAGS_PERF_DOMAIN_MICROWATTS = 1,
	35	DEV_ENERGYMODEL_PERF_DOMAIN_FLAGS_PERF_DOMAIN_SKIP_INEFFICIENCIES = 2,
	36	DEV_ENERGYMODEL_PERF_DOMAIN_FLAGS_PERF_DOMAIN_ARTIFICIAL = 4,
	37	};
	38
	39	enum {
	40	DEV_ENERGYMODEL_A_PERF_DOMAIN_PAD = 1,
	41	DEV_ENERGYMODEL_A_PERF_DOMAIN_PERF_DOMAIN_ID,
	42	DEV_ENERGYMODEL_A_PERF_DOMAIN_FLAGS,
	43	DEV_ENERGYMODEL_A_PERF_DOMAIN_CPUS,
	44
	45	__DEV_ENERGYMODEL_A_PERF_DOMAIN_MAX,
	46	DEV_ENERGYMODEL_A_PERF_DOMAIN_MAX = (__DEV_ENERGYMODEL_A_PERF_DOMAIN_MAX - 1)
	47	};
	48
	49	enum {
	50	DEV_ENERGYMODEL_A_PERF_TABLE_PERF_DOMAIN_ID = 1,
	51	DEV_ENERGYMODEL_A_PERF_TABLE_PERF_STATE,
	52
	53	__DEV_ENERGYMODEL_A_PERF_TABLE_MAX,
	54	DEV_ENERGYMODEL_A_PERF_TABLE_MAX = (__DEV_ENERGYMODEL_A_PERF_TABLE_MAX - 1)
	55	};
	56
	57	enum {
	58	DEV_ENERGYMODEL_A_PERF_STATE_PAD = 1,
	59	DEV_ENERGYMODEL_A_PERF_STATE_PERFORMANCE,
	60	DEV_ENERGYMODEL_A_PERF_STATE_FREQUENCY,
	61	DEV_ENERGYMODEL_A_PERF_STATE_POWER,
	62	DEV_ENERGYMODEL_A_PERF_STATE_COST,
	63	DEV_ENERGYMODEL_A_PERF_STATE_FLAGS,
	64
	65	__DEV_ENERGYMODEL_A_PERF_STATE_MAX,
	66	DEV_ENERGYMODEL_A_PERF_STATE_MAX = (__DEV_ENERGYMODEL_A_PERF_STATE_MAX - 1)
	67	};
	68
	69	enum {
	70	DEV_ENERGYMODEL_CMD_GET_PERF_DOMAINS = 1,
	71	DEV_ENERGYMODEL_CMD_GET_PERF_TABLE,
	72	DEV_ENERGYMODEL_CMD_PERF_DOMAIN_CREATED,
	73	DEV_ENERGYMODEL_CMD_PERF_DOMAIN_UPDATED,
	74	DEV_ENERGYMODEL_CMD_PERF_DOMAIN_DELETED,
	75
	76	__DEV_ENERGYMODEL_CMD_MAX,
	77	DEV_ENERGYMODEL_CMD_MAX = (__DEV_ENERGYMODEL_CMD_MAX - 1)
	78	};
	79
	80	#define DEV_ENERGYMODEL_MCGRP_EVENT "event"
	81
	82	#endif /* _UAPI_LINUX_DEV_ENERGYMODEL_H */

include/uapi/linux/dpll.h+1−0

@@ -253,6 +253,7 @@ enum dpll_a_pin { · 252 unmodified lines
253	DPLL_A_PIN_ESYNC_PULSE,	253	DPLL_A_PIN_ESYNC_PULSE,
254	DPLL_A_PIN_REFERENCE_SYNC,	254	DPLL_A_PIN_REFERENCE_SYNC,
255	DPLL_A_PIN_PHASE_ADJUST_GRAN,	255	DPLL_A_PIN_PHASE_ADJUST_GRAN,
		256	DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT,
256		257
257	__DPLL_A_PIN_MAX,	258	__DPLL_A_PIN_MAX,
258	DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)	259	DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)

include/uapi/linux/elf.h+2−0

 #define NT_RISCV_VECTOR	0x901		/* RISC-V vector registers */
 #define NN_RISCV_TAGGED_ADDR_CTRL "LINUX"
 #define NT_RISCV_TAGGED_ADDR_CTRL 0x902	/* RISC-V tagged address control (prctl()) */
+#define NN_RISCV_USER_CFI	"LINUX"
+#define NT_RISCV_USER_CFI	0x903		/* RISC-V shadow stack state */
 #define NN_LOONGARCH_CPUCFG	"LINUX"
 #define NT_LOONGARCH_CPUCFG	0xa00	/* LoongArch CPU config registers */
 #define NN_LOONGARCH_CSR	"LINUX"

include/uapi/linux/energy_model.h+0−63

@@ -1,63 +0,0 @@
1	/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2	/* Do not edit directly, auto-generated from: */
3	/* Documentation/netlink/specs/em.yaml */
4	/* YNL-GEN uapi header */
5	/* To regenerate run: tools/net/ynl/ynl-regen.sh */
6
7	#ifndef _UAPI_LINUX_ENERGY_MODEL_H
8	#define _UAPI_LINUX_ENERGY_MODEL_H
9
10	#define EM_FAMILY_NAME "em"
11	#define EM_FAMILY_VERSION 1
12
13	enum {
14	EM_A_PDS_PD = 1,
15
16	__EM_A_PDS_MAX,
17	EM_A_PDS_MAX = (__EM_A_PDS_MAX - 1)
18	};
19
20	enum {
21	EM_A_PD_PAD = 1,
22	EM_A_PD_PD_ID,
23	EM_A_PD_FLAGS,
24	EM_A_PD_CPUS,
25
26	__EM_A_PD_MAX,
27	EM_A_PD_MAX = (__EM_A_PD_MAX - 1)
28	};
29
30	enum {
31	EM_A_PD_TABLE_PD_ID = 1,
32	EM_A_PD_TABLE_PS,
33
34	__EM_A_PD_TABLE_MAX,
35	EM_A_PD_TABLE_MAX = (__EM_A_PD_TABLE_MAX - 1)
36	};
37
38	enum {
39	EM_A_PS_PAD = 1,
40	EM_A_PS_PERFORMANCE,
41	EM_A_PS_FREQUENCY,
42	EM_A_PS_POWER,
43	EM_A_PS_COST,
44	EM_A_PS_FLAGS,
45
46	__EM_A_PS_MAX,
47	EM_A_PS_MAX = (__EM_A_PS_MAX - 1)
48	};
49
50	enum {
51	EM_CMD_GET_PDS = 1,
52	EM_CMD_GET_PD_TABLE,
53	EM_CMD_PD_CREATED,
54	EM_CMD_PD_UPDATED,
55	EM_CMD_PD_DELETED,
56
57	__EM_CMD_MAX,
58	EM_CMD_MAX = (__EM_CMD_MAX - 1)
59	};
60
61	#define EM_MCGRP_EVENT "event"
62
63	#endif /* _UAPI_LINUX_ENERGY_MODEL_H */

include/uapi/linux/ethtool.h+21−7

 #define _UAPI_LINUX_ETHTOOL_H
 #include <linux/const.h>
+#include <linux/typelimits.h>
 #include <linux/types.h>
 #include <linux/if_ether.h>
-#ifndef __KERNEL__
-#include <limits.h> /* for INT_MAX */
-#endif
 /* All structures exposed to userland should be defined such that they
  * have the same layout for 32-bit and 64-bit userland.
  */
 	ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED,
 	ETHTOOL_LINK_EXT_STATE_OVERHEAT,
 	ETHTOOL_LINK_EXT_STATE_MODULE,
+	ETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION,
+	ETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN,
 };
 /* More information in addition to ETHTOOL_LINK_EXT_STATE_AUTONEG. */
  * struct ethtool_gstrings - string set for data tagging
  * @cmd: Command number = %ETHTOOL_GSTRINGS
  * @string_set: String set ID; one of &enum ethtool_stringset
- * @len: On return, the number of strings in the string set
+ * @len: Number of strings in the string set
  * @data: Buffer for strings.  Each string is null-padded to a size of
  *	%ETH_GSTRING_LEN.
  *
  * Users must use %ETHTOOL_GSSET_INFO to find the number of strings in
  * the string set.  They must allocate a buffer of the appropriate
  * size immediately following this structure.
+ *
+ * Setting @len on input is optional (though preferred), but must be zeroed
+ * otherwise.
+ * When set, @len will return the requested count if it matches the actual
+ * count; otherwise, it will be zero.
+ * This prevents issues when the number of strings is different than the
+ * userspace allocation.
  */
 struct ethtool_gstrings {
 	__u32	cmd;
 /**
  * struct ethtool_stats - device-specific statistics
  * @cmd: Command number = %ETHTOOL_GSTATS
- * @n_stats: On return, the number of statistics
+ * @n_stats: Number of statistics
  * @data: Array of statistics
  *
  * Users must use %ETHTOOL_GSSET_INFO or %ETHTOOL_GDRVINFO to find the
  * number of statistics that will be returned.  They must allocate a
  * buffer of the appropriate size (8 * number of statistics)
  * immediately following this structure.
+ *
+ * Setting @n_stats on input is optional (though preferred), but must be zeroed
+ * otherwise.
+ * When set, @n_stats will return the requested count if it matches the actual
+ * count; otherwise, it will be zero.
+ * This prevents issues when the number of stats is different than the
+ * userspace allocation.
  */
 struct ethtool_stats {
 	__u32	cmd;
 #define SPEED_40000		40000
 #define SPEED_50000		50000
 #define SPEED_56000		56000
+#define SPEED_80000		80000
 #define SPEED_100000		100000
 #define SPEED_200000		200000
 #define SPEED_400000		400000
 static inline int ethtool_validate_speed(__u32 speed)
 {
-	return speed <= INT_MAX || speed == (__u32)SPEED_UNKNOWN;
+	return speed <= __KERNEL_INT_MAX || speed == (__u32)SPEED_UNKNOWN;
 }
 /* Duplex, half or full. */

include/uapi/linux/ext4.h+1−1

@@ -139,7 +139,7 @@ struct ext4_tune_sb_params { · 138 unmodified lines
139	__u32 clear_feature_incompat_mask;	139	__u32 clear_feature_incompat_mask;
140	__u32 clear_feature_ro_compat_mask;	140	__u32 clear_feature_ro_compat_mask;
141	__u8 mount_opts[64];	141	__u8 mount_opts[64];
142	__u8 pad[64];	142	__u8 pad[68];
143	};	143	};
144		144
145	#define EXT4_TUNE_FL_ERRORS_BEHAVIOR 0x00000001	145	#define EXT4_TUNE_FL_ERRORS_BEHAVIOR 0x00000001

include/uapi/linux/fs.h+1−0

@@ -253,6 +253,7 @@ struct file_attr { · 252 unmodified lines
253	#define FS_XFLAG_FILESTREAM 0x00004000 /* use filestream allocator */	253	#define FS_XFLAG_FILESTREAM 0x00004000 /* use filestream allocator */
254	#define FS_XFLAG_DAX 0x00008000 /* use DAX for IO */	254	#define FS_XFLAG_DAX 0x00008000 /* use DAX for IO */
255	#define FS_XFLAG_COWEXTSIZE 0x00010000 /* CoW extent size allocator hint */	255	#define FS_XFLAG_COWEXTSIZE 0x00010000 /* CoW extent size allocator hint */
		256	#define FS_XFLAG_VERITY 0x00020000 /* fs-verity enabled */
256	#define FS_XFLAG_HASATTR 0x80000000 /* no DIFLAG for this */	257	#define FS_XFLAG_HASATTR 0x80000000 /* no DIFLAG for this */
257		258
258	/* the read-only stuff doesn't really belong here, but any other place is	259	/* the read-only stuff doesn't really belong here, but any other place is

include/uapi/linux/hyperv.h+1−1

@@ -362,7 +362,7 @@ struct hv_kvp_exchg_msg_value { · 361 unmodified lines
362	__u8 value[HV_KVP_EXCHANGE_MAX_VALUE_SIZE];	362	__u8 value[HV_KVP_EXCHANGE_MAX_VALUE_SIZE];
363	__u32 value_u32;	363	__u32 value_u32;
364	__u64 value_u64;	364	__u64 value_u64;
365	};	365	} __attribute__((packed));
366	} __attribute__((packed));	366	} __attribute__((packed));
367		367
368	struct hv_kvp_msg_enumerate {	368	struct hv_kvp_msg_enumerate {

include/uapi/linux/idxd.h+133−137

@@ -3,11 +3,7 @@ · 2 unmodified lines
3	#ifndef _USR_IDXD_H_	3	#ifndef _USR_IDXD_H_
4	#define _USR_IDXD_H_	4	#define _USR_IDXD_H_
5		5
6	#ifdef __KERNEL__
7	#include <linux/types.h>	6	#include <linux/types.h>
8	#else
9	#include <stdint.h>
10	#endif
11		7
12	/* Driver command error status */	8	/* Driver command error status */
13	enum idxd_scmd_stat {	9	enum idxd_scmd_stat {
@@ -176,132 +172,132 @@ enum iax_completion_status { · 162 unmodified lines
176	#define DSA_COMP_STATUS(status) ((status) & DSA_COMP_STATUS_MASK)	172	#define DSA_COMP_STATUS(status) ((status) & DSA_COMP_STATUS_MASK)
177		173
178	struct dsa_hw_desc {	174	struct dsa_hw_desc {
179	uint32_t pasid:20;	175	__u32 pasid:20;
180	uint32_t rsvd:11;	176	__u32 rsvd:11;
181	uint32_t priv:1;	177	__u32 priv:1;
182	uint32_t flags:24;	178	__u32 flags:24;
183	uint32_t opcode:8;	179	__u32 opcode:8;
184	uint64_t completion_addr;	180	__u64 completion_addr;
185	union {	181	union {
186	uint64_t src_addr;	182	__u64 src_addr;
187	uint64_t rdback_addr;	183	__u64 rdback_addr;
188	uint64_t pattern;	184	__u64 pattern;
189	uint64_t desc_list_addr;	185	__u64 desc_list_addr;
190	uint64_t pattern_lower;	186	__u64 pattern_lower;
191	uint64_t transl_fetch_addr;	187	__u64 transl_fetch_addr;
192	};	188	};
193	union {	189	union {
194	uint64_t dst_addr;	190	__u64 dst_addr;
195	uint64_t rdback_addr2;	191	__u64 rdback_addr2;
196	uint64_t src2_addr;	192	__u64 src2_addr;
197	uint64_t comp_pattern;	193	__u64 comp_pattern;
198	};	194	};
199	union {	195	union {
200	uint32_t xfer_size;	196	__u32 xfer_size;
201	uint32_t desc_count;	197	__u32 desc_count;
202	uint32_t region_size;	198	__u32 region_size;
203	};	199	};
204	uint16_t int_handle;	200	__u16 int_handle;
205	uint16_t rsvd1;	201	__u16 rsvd1;
206	union {	202	union {
207	uint8_t expected_res;	203	__u8 expected_res;
208	/* create delta record */	204	/* create delta record */
209	struct {	205	struct {
210	uint64_t delta_addr;	206	__u64 delta_addr;
211	uint32_t max_delta_size;	207	__u32 max_delta_size;
212	uint32_t delt_rsvd;	208	__u32 delt_rsvd;
213	uint8_t expected_res_mask;	209	__u8 expected_res_mask;
214	};	210	};
215	uint32_t delta_rec_size;	211	__u32 delta_rec_size;
216	uint64_t dest2;	212	__u64 dest2;
217	/* CRC */	213	/* CRC */
218	struct {	214	struct {
219	uint32_t crc_seed;	215	__u32 crc_seed;
220	uint32_t crc_rsvd;	216	__u32 crc_rsvd;
221	uint64_t seed_addr;	217	__u64 seed_addr;
222	};	218	};
223	/* DIF check or strip */	219	/* DIF check or strip */
224	struct {	220	struct {
225	uint8_t src_dif_flags;	221	__u8 src_dif_flags;
226	uint8_t dif_chk_res;	222	__u8 dif_chk_res;
227	uint8_t dif_chk_flags;	223	__u8 dif_chk_flags;
228	uint8_t dif_chk_res2[5];	224	__u8 dif_chk_res2[5];
229	uint32_t chk_ref_tag_seed;	225	__u32 chk_ref_tag_seed;
230	uint16_t chk_app_tag_mask;	226	__u16 chk_app_tag_mask;
231	uint16_t chk_app_tag_seed;	227	__u16 chk_app_tag_seed;
232	};	228	};
233	/* DIF insert */	229	/* DIF insert */
234	struct {	230	struct {
235	uint8_t dif_ins_res;	231	__u8 dif_ins_res;
236	uint8_t dest_dif_flag;	232	__u8 dest_dif_flag;
237	uint8_t dif_ins_flags;	233	__u8 dif_ins_flags;
238	uint8_t dif_ins_res2[13];	234	__u8 dif_ins_res2[13];
239	uint32_t ins_ref_tag_seed;	235	__u32 ins_ref_tag_seed;
240	uint16_t ins_app_tag_mask;	236	__u16 ins_app_tag_mask;
241	uint16_t ins_app_tag_seed;	237	__u16 ins_app_tag_seed;
242	};	238	};
243	/* DIF update */	239	/* DIF update */
244	struct {	240	struct {
245	uint8_t src_upd_flags;	241	__u8 src_upd_flags;
246	uint8_t upd_dest_flags;	242	__u8 upd_dest_flags;
247	uint8_t dif_upd_flags;	243	__u8 dif_upd_flags;
248	uint8_t dif_upd_res[5];	244	__u8 dif_upd_res[5];
249	uint32_t src_ref_tag_seed;	245	__u32 src_ref_tag_seed;
250	uint16_t src_app_tag_mask;	246	__u16 src_app_tag_mask;
251	uint16_t src_app_tag_seed;	247	__u16 src_app_tag_seed;
252	uint32_t dest_ref_tag_seed;	248	__u32 dest_ref_tag_seed;
253	uint16_t dest_app_tag_mask;	249	__u16 dest_app_tag_mask;
254	uint16_t dest_app_tag_seed;	250	__u16 dest_app_tag_seed;
255	};	251	};
256		252
257	/* Fill */	253	/* Fill */
258	uint64_t pattern_upper;	254	__u64 pattern_upper;
259		255
260	/* Translation fetch */	256	/* Translation fetch */
261	struct {	257	struct {
262	uint64_t transl_fetch_res;	258	__u64 transl_fetch_res;
263	uint32_t region_stride;	259	__u32 region_stride;
264	};	260	};
265		261
266	/* DIX generate */	262	/* DIX generate */
267	struct {	263	struct {
268	uint8_t dix_gen_res;	264	__u8 dix_gen_res;
269	uint8_t dest_dif_flags;	265	__u8 dest_dif_flags;
270	uint8_t dif_flags;	266	__u8 dif_flags;
271	uint8_t dix_gen_res2[13];	267	__u8 dix_gen_res2[13];
272	uint32_t ref_tag_seed;	268	__u32 ref_tag_seed;
273	uint16_t app_tag_mask;	269	__u16 app_tag_mask;
274	uint16_t app_tag_seed;	270	__u16 app_tag_seed;
275	};	271	};
276		272
277	uint8_t op_specific[24];	273	__u8 op_specific[24];
278	};	274	};
279	} __attribute__((packed));	275	} __attribute__((packed));
280		276
281	struct iax_hw_desc {	277	struct iax_hw_desc {
282	uint32_t pasid:20;	278	__u32 pasid:20;
283	uint32_t rsvd:11;	279	__u32 rsvd:11;
284	uint32_t priv:1;	280	__u32 priv:1;
285	uint32_t flags:24;	281	__u32 flags:24;
286	uint32_t opcode:8;	282	__u32 opcode:8;
287	uint64_t completion_addr;	283	__u64 completion_addr;
288	uint64_t src1_addr;	284	__u64 src1_addr;
289	uint64_t dst_addr;	285	__u64 dst_addr;
290	uint32_t src1_size;	286	__u32 src1_size;
291	uint16_t int_handle;	287	__u16 int_handle;
292	union {	288	union {
293	uint16_t compr_flags;	289	__u16 compr_flags;
294	uint16_t decompr_flags;	290	__u16 decompr_flags;
295	};	291	};
296	uint64_t src2_addr;	292	__u64 src2_addr;
297	uint32_t max_dst_size;	293	__u32 max_dst_size;
298	uint32_t src2_size;	294	__u32 src2_size;
299	uint32_t filter_flags;	295	__u32 filter_flags;
300	uint32_t num_inputs;	296	__u32 num_inputs;
301	} __attribute__((packed));	297	} __attribute__((packed));
302		298
303	struct dsa_raw_desc {	299	struct dsa_raw_desc {
304	uint64_t field[8];	300	__u64 field[8];
305	} __attribute__((packed));	301	} __attribute__((packed));
306		302
307	/*	303	/*
@@ -309,91 +305,91 @@ struct dsa_raw_desc { · 1 unmodified line
309	* volatile and prevent the compiler from optimize the read.	305	* volatile and prevent the compiler from optimize the read.
310	*/	306	*/
311	struct dsa_completion_record {	307	struct dsa_completion_record {
312	volatile uint8_t status;	308	volatile __u8 status;
313	union {	309	union {
314	uint8_t result;	310	__u8 result;
315	uint8_t dif_status;	311	__u8 dif_status;
316	};	312	};
317	uint8_t fault_info;	313	__u8 fault_info;
318	uint8_t rsvd;	314	__u8 rsvd;
319	union {	315	union {
320	uint32_t bytes_completed;	316	__u32 bytes_completed;
321	uint32_t descs_completed;	317	__u32 descs_completed;
322	};	318	};
323	uint64_t fault_addr;	319	__u64 fault_addr;
324	union {	320	union {
325	/* common record */	321	/* common record */
326	struct {	322	struct {
327	uint32_t invalid_flags:24;	323	__u32 invalid_flags:24;
328	uint32_t rsvd2:8;	324	__u32 rsvd2:8;
329	};	325	};
330		326
331	uint32_t delta_rec_size;	327	__u32 delta_rec_size;
332	uint64_t crc_val;	328	__u64 crc_val;
333		329
334	/* DIF check & strip */	330	/* DIF check & strip */
335	struct {	331	struct {
336	uint32_t dif_chk_ref_tag;	332	__u32 dif_chk_ref_tag;
337	uint16_t dif_chk_app_tag_mask;	333	__u16 dif_chk_app_tag_mask;
338	uint16_t dif_chk_app_tag;	334	__u16 dif_chk_app_tag;
339	};	335	};
340		336
341	/* DIF insert */	337	/* DIF insert */
342	struct {	338	struct {
343	uint64_t dif_ins_res;	339	__u64 dif_ins_res;
344	uint32_t dif_ins_ref_tag;	340	__u32 dif_ins_ref_tag;
345	uint16_t dif_ins_app_tag_mask;	341	__u16 dif_ins_app_tag_mask;
346	uint16_t dif_ins_app_tag;	342	__u16 dif_ins_app_tag;
347	};	343	};
348		344
349	/* DIF update */	345	/* DIF update */
350	struct {	346	struct {
351	uint32_t dif_upd_src_ref_tag;	347	__u32 dif_upd_src_ref_tag;
352	uint16_t dif_upd_src_app_tag_mask;	348	__u16 dif_upd_src_app_tag_mask;
353	uint16_t dif_upd_src_app_tag;	349	__u16 dif_upd_src_app_tag;
354	uint32_t dif_upd_dest_ref_tag;	350	__u32 dif_upd_dest_ref_tag;
355	uint16_t dif_upd_dest_app_tag_mask;	351	__u16 dif_upd_dest_app_tag_mask;
356	uint16_t dif_upd_dest_app_tag;	352	__u16 dif_upd_dest_app_tag;
357	};	353	};
358		354
359	/* DIX generate */	355	/* DIX generate */
360	struct {	356	struct {
361	uint64_t dix_gen_res;	357	__u64 dix_gen_res;
362	uint32_t dix_ref_tag;	358	__u32 dix_ref_tag;
363	uint16_t dix_app_tag_mask;	359	__u16 dix_app_tag_mask;
364	uint16_t dix_app_tag;	360	__u16 dix_app_tag;
365	};	361	};
366		362
367	uint8_t op_specific[16];	363	__u8 op_specific[16];
368	};	364	};
369	} __attribute__((packed));	365	} __attribute__((packed));
370		366
371	struct dsa_raw_completion_record {	367	struct dsa_raw_completion_record {
372	uint64_t field[4];	368	__u64 field[4];
373	} __attribute__((packed));	369	} __attribute__((packed));
374		370
375	struct iax_completion_record {	371	struct iax_completion_record {
376	volatile uint8_t status;	372	volatile __u8 status;
377	uint8_t error_code;	373	__u8 error_code;
378	uint8_t fault_info;	374	__u8 fault_info;
379	uint8_t rsvd;	375	__u8 rsvd;
380	uint32_t bytes_completed;	376	__u32 bytes_completed;
381	uint64_t fault_addr;	377	__u64 fault_addr;
382	uint32_t invalid_flags;	378	__u32 invalid_flags;
383	uint32_t rsvd2;	379	__u32 rsvd2;
384	uint32_t output_size;	380	__u32 output_size;
385	uint8_t output_bits;	381	__u8 output_bits;
386	uint8_t rsvd3;	382	__u8 rsvd3;
387	uint16_t xor_csum;	383	__u16 xor_csum;
388	uint32_t crc;	384	__u32 crc;
389	uint32_t min;	385	__u32 min;
390	uint32_t max;	386	__u32 max;
391	uint32_t sum;	387	__u32 sum;
392	uint64_t rsvd4[2];	388	__u64 rsvd4[2];
393	} __attribute__((packed));	389	} __attribute__((packed));
394		390
395	struct iax_raw_completion_record {	391	struct iax_raw_completion_record {
396	uint64_t field[8];	392	__u64 field[8];
397	} __attribute__((packed));	393	} __attribute__((packed));
398		394
399	#endif	395	#endif

include/uapi/linux/if_alg.h+1−1

@@ -42,7 +42,7 @@ struct sockaddr_alg_new { · 41 unmodified lines
42		42
43	struct af_alg_iv {	43	struct af_alg_iv {
44	__u32 ivlen;	44	__u32 ivlen;
45	__u8 iv[];	45	__u8 iv[] __counted_by(ivlen);
46	};	46	};
47		47
48	/* Socket options */	48	/* Socket options */

include/uapi/linux/if_link.h+1−0

@@ -1443,6 +1443,7 @@ enum { · 1442 unmodified lines
1443	IFLA_GENEVE_DF,	1443	IFLA_GENEVE_DF,
1444	IFLA_GENEVE_INNER_PROTO_INHERIT,	1444	IFLA_GENEVE_INNER_PROTO_INHERIT,
1445	IFLA_GENEVE_PORT_RANGE,	1445	IFLA_GENEVE_PORT_RANGE,
		1446	IFLA_GENEVE_GRO_HINT,
1446	__IFLA_GENEVE_MAX	1447	__IFLA_GENEVE_MAX
1447	};	1448	};
1448	#define IFLA_GENEVE_MAX (__IFLA_GENEVE_MAX - 1)	1449	#define IFLA_GENEVE_MAX (__IFLA_GENEVE_MAX - 1)

include/uapi/linux/io_uring.h+31−1

  */
 #define IORING_SETUP_SQE_MIXED		(1U << 19)
+/*
+ * When set, io_uring ignores SQ head and tail and fetches SQEs to submit
+ * starting from index 0 instead from the index stored in the head pointer.
+ * IOW, the user should place all SQE at the beginning of the SQ memory
+ * before issuing a submission syscall.
+ *
+ * It requires IORING_SETUP_NO_SQARRAY and is incompatible with
+ * IORING_SETUP_SQPOLL. The user must also never change the SQ head and tail
+ * values and keep it set to 0. Any other value is undefined behaviour.
+ */
+#define IORING_SETUP_SQ_REWIND		(1U << 20)
 enum io_uring_op {
 	IORING_OP_NOP,
 	IORING_OP_READV,
 	/* auxiliary zcrx configuration, see enum zcrx_ctrl_op */
 	IORING_REGISTER_ZCRX_CTRL		= 36,
+	/* register bpf filtering programs */
+	IORING_REGISTER_BPF_FILTER		= 37,
 	/* this goes last */
 	IORING_REGISTER_LAST,
 	__u32 resv2[3];
 };
+struct io_uring_task_restriction {
+	__u16 flags;
+	__u16 nr_res;
+	__u32 resv[3];
+	__DECLARE_FLEX_ARRAY(struct io_uring_restriction, restrictions);
+};
 struct io_uring_clock_register {
 	__u32	clockid;
 	__u32	__resv[3];
 	ZCRX_REG_IMPORT	= 1,
 };
+enum zcrx_features {
+	/*
+	 * The user can ask for the desired rx page size by passing the
+	 * value in struct io_uring_zcrx_ifq_reg::rx_buf_len.
+	 */
+	ZCRX_FEATURE_RX_PAGE_SIZE	= 1 << 0,
+};
 /*
  * Argument for IORING_REGISTER_ZCRX_IFQ
  */
 	struct io_uring_zcrx_offsets offsets;
 	__u32	zcrx_id;
-	__u32	__resv2;
+	__u32	rx_buf_len;
 	__u64	__resv[3];
 };

include/uapi/linux/io_uring/bpf_filter.h+68−0

@@ -0,0 +1,68 @@
	1	/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
	2	/*
	3	* Header file for the io_uring BPF filters.
	4	*/
	5	#ifndef LINUX_IO_URING_BPF_FILTER_H
	6	#define LINUX_IO_URING_BPF_FILTER_H
	7
	8	#include <linux/types.h>
	9
	10	/*
	11	* Struct passed to filters.
	12	*/
	13	struct io_uring_bpf_ctx {
	14	__u64 user_data;
	15	__u8 opcode;
	16	__u8 sqe_flags;
	17	__u8 pdu_size; /* size of aux data for filter */
	18	__u8 pad[5];
	19	union {
	20	struct {
	21	__u32 family;
	22	__u32 type;
	23	__u32 protocol;
	24	} socket;
	25	struct {
	26	__u64 flags;
	27	__u64 mode;
	28	__u64 resolve;
	29	} open;
	30	};
	31	};
	32
	33	enum {
	34	/*
	35	* If set, any currently unset opcode will have a deny filter attached
	36	*/
	37	IO_URING_BPF_FILTER_DENY_REST = 1,
	38	/*
	39	* If set, if kernel and application don't agree on pdu_size for
	40	* the given opcode, fail the registration of the filter.
	41	*/
	42	IO_URING_BPF_FILTER_SZ_STRICT = 2,
	43	};
	44
	45	struct io_uring_bpf_filter {
	46	__u32 opcode; /* io_uring opcode to filter */
	47	__u32 flags;
	48	__u32 filter_len; /* number of BPF instructions */
	49	__u8 pdu_size; /* expected pdu size for opcode */
	50	__u8 resv[3];
	51	__u64 filter_ptr; /* pointer to BPF filter */
	52	__u64 resv2[5];
	53	};
	54
	55	enum {
	56	IO_URING_BPF_CMD_FILTER = 1,
	57	};
	58
	59	struct io_uring_bpf {
	60	__u16 cmd_type; /* IO_URING_BPF_* values */
	61	__u16 cmd_flags; /* none so far */
	62	__u32 resv;
	63	union {
	64	struct io_uring_bpf_filter filter;
	65	};
	66	};
	67
	68	#endif

include/uapi/linux/io_uring/query.h+5−1

 /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
 /*
  * Header file for the io_uring query interface.
+ *
+ * Copyright (C) 2026 Pavel Begunkov <asml.silence@gmail.com>
+ * Copyright (C) Meta Platforms, Inc.
  */
 #ifndef LINUX_IO_URING_QUERY_H
 #define LINUX_IO_URING_QUERY_H
 	__u64 area_flags;
 	/* The number of supported ZCRX_CTRL_* opcodes */
 	__u32 nr_ctrl_opcodes;
-	__u32 __resv1;
+	/* Bitmask of ZCRX_FEATURE_* indicating which features are available */
+	__u32 features;
 	/* The refill ring header size */
 	__u32 rq_hdr_size;
 	/* The alignment for the header */

include/uapi/linux/iommufd.h+39−0

@@ -465,16 +465,27 @@ struct iommu_hwpt_arm_smmuv3 { · 464 unmodified lines
465	__aligned_le64 ste[2];	465	__aligned_le64 ste[2];
466	};	466	};
467		467
		468	/**
		469	* struct iommu_hwpt_amd_guest - AMD IOMMU guest I/O page table data
		470	* (IOMMU_HWPT_DATA_AMD_GUEST)
		471	* @dte: Guest Device Table Entry (DTE)
		472	*/
		473	struct iommu_hwpt_amd_guest {
		474	__aligned_u64 dte[4];
		475	};
		476
468	/**	477	/**
469	* enum iommu_hwpt_data_type - IOMMU HWPT Data Type	478	* enum iommu_hwpt_data_type - IOMMU HWPT Data Type
470	* @IOMMU_HWPT_DATA_NONE: no data	479	* @IOMMU_HWPT_DATA_NONE: no data
471	* @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table	480	* @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table
472	* @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table	481	* @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table
		482	* @IOMMU_HWPT_DATA_AMD_GUEST: AMD IOMMU guest page table
473	*/	483	*/
474	enum iommu_hwpt_data_type {	484	enum iommu_hwpt_data_type {
475	IOMMU_HWPT_DATA_NONE = 0,	485	IOMMU_HWPT_DATA_NONE = 0,
476	IOMMU_HWPT_DATA_VTD_S1 = 1,	486	IOMMU_HWPT_DATA_VTD_S1 = 1,
477	IOMMU_HWPT_DATA_ARM_SMMUV3 = 2,	487	IOMMU_HWPT_DATA_ARM_SMMUV3 = 2,
		488	IOMMU_HWPT_DATA_AMD_GUEST = 3,
478	};	489	};
479		490
480	/**	491	/**
@@ -623,6 +634,32 @@ struct iommu_hw_info_tegra241_cmdqv { · 142 unmodified lines
623	__u8 __reserved;	634	__u8 __reserved;
624	};	635	};
625		636
		637	/**
		638	* struct iommu_hw_info_amd - AMD IOMMU device info
		639	*
		640	* @efr : Value of AMD IOMMU Extended Feature Register (EFR)
		641	* @efr2: Value of AMD IOMMU Extended Feature 2 Register (EFR2)
		642	*
		643	* Please See description of these registers in the following sections of
		644	* the AMD I/O Virtualization Technology (IOMMU) Specification.
		645	* (https://docs.amd.com/v/u/en-US/48882_3.10_PUB)
		646	*
		647	* - MMIO Offset 0030h IOMMU Extended Feature Register
		648	* - MMIO Offset 01A0h IOMMU Extended Feature 2 Register
		649	*
		650	* Note: The EFR and EFR2 are raw values reported by hardware.
		651	* VMM is responsible to determine the appropriate flags to be exposed to
		652	* the VM since cetertain features are not currently supported by the kernel
		653	* for HW-vIOMMU.
		654	*
		655	* Current VMM-allowed list of feature flags are:
		656	* - EFR[GTSup, GASup, GioSup, PPRSup, EPHSup, GATS, GLX, PASmax]
		657	*/
		658	struct iommu_hw_info_amd {
		659	__aligned_u64 efr;
		660	__aligned_u64 efr2;
		661	};
		662
626	/**	663	/**
627	* enum iommu_hw_info_type - IOMMU Hardware Info Types	664	* enum iommu_hw_info_type - IOMMU Hardware Info Types
628	* @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware	665	* @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware
@@ -632,6 +669,7 @@ struct iommu_hw_info_tegra241_cmdqv { · 3 unmodified lines
632	* @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type	669	* @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type
633	* @IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM	670	* @IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM
634	* SMMUv3) info type	671	* SMMUv3) info type
		672	* @IOMMU_HW_INFO_TYPE_AMD: AMD IOMMU info type
635	*/	673	*/
636	enum iommu_hw_info_type {	674	enum iommu_hw_info_type {
637	IOMMU_HW_INFO_TYPE_NONE = 0,	675	IOMMU_HW_INFO_TYPE_NONE = 0,
@@ -639,6 +677,7 @@ enum iommu_hw_info_type { · 1 unmodified line
639	IOMMU_HW_INFO_TYPE_INTEL_VTD = 1,	677	IOMMU_HW_INFO_TYPE_INTEL_VTD = 1,
640	IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,	678	IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,
641	IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,	679	IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,
		680	IOMMU_HW_INFO_TYPE_AMD = 4,
642	};	681	};
643		682
644	/**	683	/**

include/uapi/linux/kfd_ioctl.h+13−3

  * - 1.16 - Add contiguous VRAM allocation flag
  * - 1.17 - Add SDMA queue creation with target SDMA engine ID
  * - 1.18 - Rename pad in set_memory_policy_args to misc_process_flag
+ * - 1.19 - Add a new ioctl to craete secondary kfd processes
+ * - 1.20 - Trap handler support for expert scheduling mode available
+ * - 1.21 - Debugger support to subscribe to LDS out-of-address exceptions
+ * - 1.22 - Add queue creation with metadata ring base address
  */
 #define KFD_IOCTL_MAJOR_VERSION 1
-#define KFD_IOCTL_MINOR_VERSION 18
+#define KFD_IOCTL_MINOR_VERSION 22
 struct kfd_ioctl_get_version_args {
 	__u32 major_version;	/* from KFD */
 	__u32 ctx_save_restore_size;	/* to KFD */
 	__u32 ctl_stack_size;		/* to KFD */
 	__u32 sdma_engine_id;		/* to KFD */
-	__u32 pad;
+	__u32 metadata_ring_size;	/* to KFD */
 };
 struct kfd_ioctl_destroy_queue_args {
 	__u32 num_xcc;
 	__u32 capability;
 	__u32 debug_prop;
+	__u32 capability2;
+	__u32 pad;
 };
 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
 enum kfd_dbg_trap_flags {
 	KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP = 1,
 	KFD_DBG_TRAP_FLAG_SINGLE_ALU_OP = 2,
+	KFD_DBG_TRAP_FLAG_LDS_OUT_OF_ADDR_RANGE = 4
 };
 /* Trap exceptions */
 #define AMDKFD_IOC_DBG_TRAP			\
 		AMDKFD_IOWR(0x26, struct kfd_ioctl_dbg_trap_args)
+#define AMDKFD_IOC_CREATE_PROCESS		\
+		AMDKFD_IO(0x27)
 #define AMDKFD_COMMAND_START		0x01
-#define AMDKFD_COMMAND_END		0x27
+#define AMDKFD_COMMAND_END		0x28
 #endif

include/uapi/linux/kfd_sysfs.h+2−1

@@ -64,7 +64,8 @@ · 63 unmodified lines
64	#define HSA_CAP_RESERVED 0x000f8000	64	#define HSA_CAP_RESERVED 0x000f8000
65		65
66	#define HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED 0x00000001	66	#define HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED 0x00000001
67	#define HSA_CAP2_RESERVED 0xfffffffe	67	#define HSA_CAP2_TRAP_DEBUG_LDS_OUT_OF_ADDR_RANGE_SUPPORTED 0x00000002
		68	#define HSA_CAP2_RESERVED 0xfffffffc
68		69
69	/* debug_prop bits in node properties */	70	/* debug_prop bits in node properties */
70	#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_MASK 0x0000000f	71	#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_MASK 0x0000000f

include/uapi/linux/kvm.h+23−1

 	} u;
 };
+struct kvm_exit_snp_req_certs {
+	__u64 gpa;
+	__u64 npages;
+	__u64 ret;
+};
 #define KVM_S390_GET_SKEYS_NONE   1
 #define KVM_S390_SKEYS_MAX        1048576
 #define KVM_EXIT_MEMORY_FAULT     39
 #define KVM_EXIT_TDX              40
 #define KVM_EXIT_ARM_SEA          41
+#define KVM_EXIT_ARM_LDST64B      42
+#define KVM_EXIT_SNP_REQ_CERTS    43
 /* For KVM_EXIT_INTERNAL_ERROR */
 /* Emulate instruction failed. */
 		} eoi;
 		/* KVM_EXIT_HYPERV */
 		struct kvm_hyperv_exit hyperv;
-		/* KVM_EXIT_ARM_NISV */
+		/* KVM_EXIT_ARM_NISV / KVM_EXIT_ARM_LDST64B */
 		struct {
 			__u64 esr_iss;
 			__u64 fault_ipa;
 			__u64 gva;
 			__u64 gpa;
 		} arm_sea;
+		/* KVM_EXIT_SNP_REQ_CERTS */
+		struct kvm_exit_snp_req_certs snp_req_certs;
 		/* Fix the size of the union. */
 		char padding[256];
 	};
 #define KVM_CAP_GUEST_MEMFD_FLAGS 244
 #define KVM_CAP_ARM_SEA_TO_USER 245
 #define KVM_CAP_S390_USER_OPEREXEC 246
+#define KVM_CAP_S390_KEYOP 247
 struct kvm_irq_routing_irqchip {
 	__u32 irqchip;
 	__s32	tablefd;
 };
+#define KVM_S390_KEYOP_ISKE 0x01
+#define KVM_S390_KEYOP_RRBE 0x02
+#define KVM_S390_KEYOP_SSKE 0x03
+struct kvm_s390_keyop {
+	__u64 guest_addr;
+	__u8  key;
+	__u8  operation;
+	__u8  pad[6];
+};
 /*
  * KVM_CREATE_VCPU receives as a parameter the vcpu slot, and returns
  * a vcpu fd.
 #define KVM_S390_UCAS_MAP        _IOW(KVMIO, 0x50, struct kvm_s390_ucas_mapping)
 #define KVM_S390_UCAS_UNMAP      _IOW(KVMIO, 0x51, struct kvm_s390_ucas_mapping)
 #define KVM_S390_VCPU_FAULT	 _IOW(KVMIO, 0x52, unsigned long)
+#define KVM_S390_KEYOP           _IOWR(KVMIO, 0x53, struct kvm_s390_keyop)
 /* Device model IOC */
 #define KVM_CREATE_IRQCHIP        _IO(KVMIO,   0x60)

include/uapi/linux/landlock.h+39−28

  *     future nested domains, not the one being created. It can also be used
  *     with a @ruleset_fd value of -1 to mute subdomain logs without creating a
  *     domain.
+ *
+ * The following flag supports policy enforcement in multithreaded processes:
+ *
+ * %LANDLOCK_RESTRICT_SELF_TSYNC
+ *     Applies the new Landlock configuration atomically to all threads of the
+ *     current process, including the Landlock domain and logging
+ *     configuration. This overrides the Landlock configuration of sibling
+ *     threads, irrespective of previously established Landlock domains and
+ *     logging configurations on these threads.
+ *
+ *     If the calling thread is running with no_new_privs, this operation
+ *     enables no_new_privs on the sibling threads as well.
  */
 /* clang-format off */
 #define LANDLOCK_RESTRICT_SELF_LOG_SAME_EXEC_OFF		(1U << 0)
 #define LANDLOCK_RESTRICT_SELF_LOG_NEW_EXEC_ON			(1U << 1)
 #define LANDLOCK_RESTRICT_SELF_LOG_SUBDOMAINS_OFF		(1U << 2)
+#define LANDLOCK_RESTRICT_SELF_TSYNC				(1U << 3)
 /* clang-format on */
 /**
 	 * It should be noted that port 0 passed to :manpage:`bind(2)` will bind
 	 * to an available port from the ephemeral port range.  This can be
 	 * configured with the ``/proc/sys/net/ipv4/ip_local_port_range`` sysctl
-	 * (also used for IPv6).
+	 * (also used for IPv6), and within that range, on a per-socket basis
+	 * with ``setsockopt(IP_LOCAL_PORT_RANGE)``.
 	 *
-	 * A Landlock rule with port 0 and the ``LANDLOCK_ACCESS_NET_BIND_TCP``
+	 * A Landlock rule with port 0 and the %LANDLOCK_ACCESS_NET_BIND_TCP
 	 * right means that requesting to bind on port 0 is allowed and it will
-	 * automatically translate to binding on the related port range.
+	 * automatically translate to binding on a kernel-assigned ephemeral
+	 * port.
 	 */
 	__u64 port;
 };
  *   :manpage:`ftruncate(2)`, :manpage:`creat(2)`, or :manpage:`open(2)` with
  *   ``O_TRUNC``.  This access right is available since the third version of the
  *   Landlock ABI.
+ * - %LANDLOCK_ACCESS_FS_IOCTL_DEV: Invoke :manpage:`ioctl(2)` commands on an opened
+ *   character or block device.
+ *
+ *   This access right applies to all `ioctl(2)` commands implemented by device
+ *   drivers.  However, the following common IOCTL commands continue to be
+ *   invokable independent of the %LANDLOCK_ACCESS_FS_IOCTL_DEV right:
+ *
+ *   * IOCTL commands targeting file descriptors (``FIOCLEX``, ``FIONCLEX``),
+ *   * IOCTL commands targeting file descriptions (``FIONBIO``, ``FIOASYNC``),
+ *   * IOCTL commands targeting file systems (``FIFREEZE``, ``FITHAW``,
+ *     ``FIGETBSZ``, ``FS_IOC_GETFSUUID``, ``FS_IOC_GETFSSYSFSPATH``)
+ *   * Some IOCTL commands which do not make sense when used with devices, but
+ *     whose implementations are safe and return the right error codes
+ *     (``FS_IOC_FIEMAP``, ``FICLONE``, ``FICLONERANGE``, ``FIDEDUPERANGE``)
+ *
+ *   This access right is available since the fifth version of the Landlock
+ *   ABI.
  *
  * Whether an opened file can be truncated with :manpage:`ftruncate(2)` or used
  * with `ioctl(2)` is determined during :manpage:`open(2)`, in the same way as
  *   If multiple requirements are not met, the ``EACCES`` error code takes
  *   precedence over ``EXDEV``.
  *
- * The following access right applies both to files and directories:
- *
- * - %LANDLOCK_ACCESS_FS_IOCTL_DEV: Invoke :manpage:`ioctl(2)` commands on an opened
- *   character or block device.
- *
- *   This access right applies to all `ioctl(2)` commands implemented by device
- *   drivers.  However, the following common IOCTL commands continue to be
- *   invokable independent of the %LANDLOCK_ACCESS_FS_IOCTL_DEV right:
- *
- *   * IOCTL commands targeting file descriptors (``FIOCLEX``, ``FIONCLEX``),
- *   * IOCTL commands targeting file descriptions (``FIONBIO``, ``FIOASYNC``),
- *   * IOCTL commands targeting file systems (``FIFREEZE``, ``FITHAW``,
- *     ``FIGETBSZ``, ``FS_IOC_GETFSUUID``, ``FS_IOC_GETFSSYSFSPATH``)
- *   * Some IOCTL commands which do not make sense when used with devices, but
- *     whose implementations are safe and return the right error codes
- *     (``FS_IOC_FIEMAP``, ``FICLONE``, ``FICLONERANGE``, ``FIDEDUPERANGE``)
- *
- *   This access right is available since the fifth version of the Landlock
- *   ABI.
- *
  * .. warning::
  *
  *   It is currently not possible to restrict some file-related actions
  * These flags enable to restrict a sandboxed process to a set of network
  * actions.
  *
- * This is supported since Landlock ABI version 4.
- *
  * The following access rights apply to TCP port numbers:
  *
- * - %LANDLOCK_ACCESS_NET_BIND_TCP: Bind a TCP socket to a local port.
+ * - %LANDLOCK_ACCESS_NET_BIND_TCP: Bind TCP sockets to the given local
- * - %LANDLOCK_ACCESS_NET_CONNECT_TCP: Connect an active TCP socket to
+ *   port. Support added in Landlock ABI version 4.
- *   a remote port.
+ * - %LANDLOCK_ACCESS_NET_CONNECT_TCP: Connect TCP sockets to the given
+ *   remote port. Support added in Landlock ABI version 4.
  */
 /* clang-format off */
 #define LANDLOCK_ACCESS_NET_BIND_TCP			(1ULL << 0)

include/uapi/linux/magic.h+1−0

@@ -104,5 +104,6 @@ · 103 unmodified lines
104	#define SECRETMEM_MAGIC 0x5345434d /* "SECM" */	104	#define SECRETMEM_MAGIC 0x5345434d /* "SECM" */
105	#define PID_FS_MAGIC 0x50494446 /* "PIDF" */	105	#define PID_FS_MAGIC 0x50494446 /* "PIDF" */
106	#define GUEST_MEMFD_MAGIC 0x474d454d /* "GMEM" */	106	#define GUEST_MEMFD_MAGIC 0x474d454d /* "GMEM" */
		107	#define NULL_FS_MAGIC 0x4E554C4C /* "NULL" */
107		108
108	#endif /* __LINUX_MAGIC_H__ */	109	#endif /* __LINUX_MAGIC_H__ */

include/uapi/linux/media/arm/mali-c55-config.h+0−9

@@ -194,15 +194,6 @@ struct mali_c55_stats_buffer { · 193 unmodified lines
194	__u32 reserved3[15];	194	__u32 reserved3[15];
195	} __attribute__((packed));	195	} __attribute__((packed));
196		196
197	/**
198	* enum mali_c55_param_buffer_version - Mali-C55 parameters block versioning
199	*
200	* @MALI_C55_PARAM_BUFFER_V1: First version of Mali-C55 parameters block
201	*/
202	enum mali_c55_param_buffer_version {
203	MALI_C55_PARAM_BUFFER_V1,
204	};
205
206	/**	197	/**
207	* enum mali_c55_param_block_type - Enumeration of Mali-C55 parameter blocks	198	* enum mali_c55_param_block_type - Enumeration of Mali-C55 parameter blocks
208	*	199	*

include/uapi/linux/mempolicy.h+3−0

@@ -39,6 +39,9 @@ enum { · 38 unmodified lines
39	#define MPOL_MODE_FLAGS \	39	#define MPOL_MODE_FLAGS \
40	(MPOL_F_STATIC_NODES \| MPOL_F_RELATIVE_NODES \| MPOL_F_NUMA_BALANCING)	40	(MPOL_F_STATIC_NODES \| MPOL_F_RELATIVE_NODES \| MPOL_F_NUMA_BALANCING)
41		41
		42	/* Whether the nodemask is specified by users */
		43	#define MPOL_USER_NODEMASK_FLAGS (MPOL_F_STATIC_NODES \| MPOL_F_RELATIVE_NODES)
		44
42	/* Flags for get_mempolicy */	45	/* Flags for get_mempolicy */
43	#define MPOL_F_NODE (1<<0) /* return next IL mode instead of node mask */	46	#define MPOL_F_NODE (1<<0) /* return next IL mode instead of node mask */
44	#define MPOL_F_ADDR (1<<1) /* look up vma using address */	47	#define MPOL_F_ADDR (1<<1) /* look up vma using address */

include/uapi/linux/mount.h+11−2

 /*
  * open_tree() flags.
  */
-#define OPEN_TREE_CLONE		1		/* Clone the target tree and attach the clone */
+#define OPEN_TREE_CLONE		(1 << 0)	/* Clone the target tree and attach the clone */
+#define OPEN_TREE_NAMESPACE	(1 << 1)	/* Clone the target tree into a new mount namespace */
 #define OPEN_TREE_CLOEXEC	O_CLOEXEC	/* Close the file on execve() */
 /*
  */
 struct mnt_id_req {
 	__u32 size;
-	__u32 mnt_ns_fd;
+	union {
+		__u32 mnt_ns_fd;
+		__u32 mnt_fd;
+	};
 	__u64 mnt_id;
 	__u64 param;
 	__u64 mnt_ns_id;
 #define LSMT_ROOT		0xffffffffffffffff	/* root mount */
 #define LISTMOUNT_REVERSE	(1 << 0) /* List later mounts first */
+/*
+ * @flag bits for statmount(2)
+ */
+#define STATMOUNT_BY_FD		0x00000001U	/* want mountinfo for given fd */
 #endif /* _UAPI_LINUX_MOUNT_H */

include/uapi/linux/mptcp_pm.h+1−1

@@ -11,7 +11,7 @@ · 10 unmodified lines
11	#define MPTCP_PM_VER 1	11	#define MPTCP_PM_VER 1
12		12
13	/**	13	/**
14	* enum mptcp_event_type	14	* enum mptcp_event_type - Netlink MPTCP event types
15	* @MPTCP_EVENT_UNSPEC: unused event	15	* @MPTCP_EVENT_UNSPEC: unused event
16	* @MPTCP_EVENT_CREATED: A new MPTCP connection has been created. It is the	16	* @MPTCP_EVENT_CREATED: A new MPTCP connection has been created. It is the
17	* good time to allocate memory and send ADD_ADDR if needed. Depending on the	17	* good time to allocate memory and send ADD_ADDR if needed. Depending on the

include/uapi/linux/mshv.h+2−0

@@ -27,6 +27,8 @@ enum { · 26 unmodified lines
27	MSHV_PT_BIT_X2APIC,	27	MSHV_PT_BIT_X2APIC,
28	MSHV_PT_BIT_GPA_SUPER_PAGES,	28	MSHV_PT_BIT_GPA_SUPER_PAGES,
29	MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES,	29	MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES,
		30	MSHV_PT_BIT_NESTED_VIRTUALIZATION,
		31	MSHV_PT_BIT_SMT_ENABLED_GUEST,
30	MSHV_PT_BIT_COUNT,	32	MSHV_PT_BIT_COUNT,
31	};	33	};
32		34

include/uapi/linux/netfilter_bridge.h+7−6

@@ -5,15 +5,16 @@ · 4 unmodified lines
5	/* bridge-specific defines for netfilter.	5	/* bridge-specific defines for netfilter.
6	*/	6	*/
7		7
		8	#ifndef __KERNEL__
		9	#include <netinet/if_ether.h> /* for __UAPI_DEF_ETHHDR if defined */
		10	#endif
		11
8	#include <linux/in.h>	12	#include <linux/in.h>
9	#include <linux/netfilter.h>	13	#include <linux/netfilter.h>
10	#include <linux/if_ether.h>	14	#include <linux/if_ether.h>
11	#include <linux/if_vlan.h>	15	#include <linux/if_vlan.h>
12	#include <linux/if_pppox.h>	16	#include <linux/if_pppox.h>
13		17	#include <linux/typelimits.h>
14	#ifndef __KERNEL__
15	#include <limits.h> /* for INT_MIN, INT_MAX */
16	#endif
17		18
18	/* Bridge Hooks */	19	/* Bridge Hooks */
19	/* After promisc drops, checksum checks. */	20	/* After promisc drops, checksum checks. */
@@ -31,14 +32,14 @@ · 11 unmodified lines
31	#define NF_BR_NUMHOOKS 6	32	#define NF_BR_NUMHOOKS 6
32		33
33	enum nf_br_hook_priorities {	34	enum nf_br_hook_priorities {
34	NF_BR_PRI_FIRST = INT_MIN,	35	NF_BR_PRI_FIRST = __KERNEL_INT_MIN,
35	NF_BR_PRI_NAT_DST_BRIDGED = -300,	36	NF_BR_PRI_NAT_DST_BRIDGED = -300,
36	NF_BR_PRI_FILTER_BRIDGED = -200,	37	NF_BR_PRI_FILTER_BRIDGED = -200,
37	NF_BR_PRI_BRNF = 0,	38	NF_BR_PRI_BRNF = 0,
38	NF_BR_PRI_NAT_DST_OTHER = 100,	39	NF_BR_PRI_NAT_DST_OTHER = 100,
39	NF_BR_PRI_FILTER_OTHER = 200,	40	NF_BR_PRI_FILTER_OTHER = 200,
40	NF_BR_PRI_NAT_SRC = 300,	41	NF_BR_PRI_NAT_SRC = 300,
41	NF_BR_PRI_LAST = INT_MAX,	42	NF_BR_PRI_LAST = __KERNEL_INT_MAX,
42	};	43	};
43		44
44	#endif /* _UAPI__LINUX_BRIDGE_NETFILTER_H */	45	#endif /* _UAPI__LINUX_BRIDGE_NETFILTER_H */

include/uapi/linux/netfilter_ipv4.h+4−5

 #include <linux/netfilter.h>
+#include <linux/typelimits.h>
 /* only for userspace compatibility */
 #ifndef __KERNEL__
-#include <limits.h> /* for INT_MIN, INT_MAX */
 /* IP Hooks */
 /* After promisc drops, checksum checks. */
 #define NF_IP_PRE_ROUTING	0
 #endif /* ! __KERNEL__ */
 enum nf_ip_hook_priorities {
-	NF_IP_PRI_FIRST = INT_MIN,
+	NF_IP_PRI_FIRST = __KERNEL_INT_MIN,
 	NF_IP_PRI_RAW_BEFORE_DEFRAG = -450,
 	NF_IP_PRI_CONNTRACK_DEFRAG = -400,
 	NF_IP_PRI_RAW = -300,
 	NF_IP_PRI_NAT_SRC = 100,
 	NF_IP_PRI_SELINUX_LAST = 225,
 	NF_IP_PRI_CONNTRACK_HELPER = 300,
-	NF_IP_PRI_CONNTRACK_CONFIRM = INT_MAX,
+	NF_IP_PRI_CONNTRACK_CONFIRM = __KERNEL_INT_MAX,
-	NF_IP_PRI_LAST = INT_MAX,
+	NF_IP_PRI_LAST = __KERNEL_INT_MAX,
 };
 /* Arguments for setsockopt SOL_IP: */

include/uapi/linux/netfilter_ipv6.h+3−4

 #include <linux/netfilter.h>
+#include <linux/typelimits.h>
 /* only for userspace compatibility */
 #ifndef __KERNEL__
-#include <limits.h> /* for INT_MIN, INT_MAX */
 /* IP6 Hooks */
 /* After promisc drops, checksum checks. */
 #define NF_IP6_PRE_ROUTING	0
 enum nf_ip6_hook_priorities {
-	NF_IP6_PRI_FIRST = INT_MIN,
+	NF_IP6_PRI_FIRST = __KERNEL_INT_MIN,
 	NF_IP6_PRI_RAW_BEFORE_DEFRAG = -450,
 	NF_IP6_PRI_CONNTRACK_DEFRAG = -400,
 	NF_IP6_PRI_RAW = -300,
 	NF_IP6_PRI_NAT_SRC = 100,
 	NF_IP6_PRI_SELINUX_LAST = 225,
 	NF_IP6_PRI_CONNTRACK_HELPER = 300,
-	NF_IP6_PRI_LAST = INT_MAX,
+	NF_IP6_PRI_LAST = __KERNEL_INT_MAX,
 };

include/uapi/linux/nfs.h+1−1

@@ -55,7 +55,7 @@ · 54 unmodified lines
55	NFSERR_NODEV = 19, /* v2 v3 v4 */	55	NFSERR_NODEV = 19, /* v2 v3 v4 */
56	NFSERR_NOTDIR = 20, /* v2 v3 v4 */	56	NFSERR_NOTDIR = 20, /* v2 v3 v4 */
57	NFSERR_ISDIR = 21, /* v2 v3 v4 */	57	NFSERR_ISDIR = 21, /* v2 v3 v4 */
58	NFSERR_INVAL = 22, /* v2 v3 v4 */	58	NFSERR_INVAL = 22, /* v3 v4 */
59	NFSERR_FBIG = 27, /* v2 v3 v4 */	59	NFSERR_FBIG = 27, /* v2 v3 v4 */
60	NFSERR_NOSPC = 28, /* v2 v3 v4 */	60	NFSERR_NOSPC = 28, /* v2 v3 v4 */
61	NFSERR_ROFS = 30, /* v2 v3 v4 */	61	NFSERR_ROFS = 30, /* v2 v3 v4 */

include/uapi/linux/nfsd_netlink.h+1−0

@@ -35,6 +35,7 @@ enum { · 34 unmodified lines
35	NFSD_A_SERVER_GRACETIME,	35	NFSD_A_SERVER_GRACETIME,
36	NFSD_A_SERVER_LEASETIME,	36	NFSD_A_SERVER_LEASETIME,
37	NFSD_A_SERVER_SCOPE,	37	NFSD_A_SERVER_SCOPE,
		38	NFSD_A_SERVER_MIN_THREADS,
38		39
39	__NFSD_A_SERVER_MAX,	40	__NFSD_A_SERVER_MAX,
40	NFSD_A_SERVER_MAX = (__NFSD_A_SERVER_MAX - 1)	41	NFSD_A_SERVER_MAX = (__NFSD_A_SERVER_MAX - 1)

include/uapi/linux/nilfs2_api.h+2−2

@@ -58,7 +58,7 @@ NILFS_CPINFO_FNS(INVALID, invalid) · 57 unmodified lines
58	NILFS_CPINFO_FNS(MINOR, minor)	58	NILFS_CPINFO_FNS(MINOR, minor)
59		59
60	/**	60	/**
61	* nilfs_suinfo - segment usage information	61	* struct nilfs_suinfo - segment usage information
62	* @sui_lastmod: timestamp of last modification	62	* @sui_lastmod: timestamp of last modification
63	* @sui_nblocks: number of written blocks in segment	63	* @sui_nblocks: number of written blocks in segment
64	* @sui_flags: segment usage flags	64	* @sui_flags: segment usage flags
@@ -93,7 +93,7 @@ static inline int nilfs_suinfo_clean(const struct nilfs_suinfo *si) · 28 unmodified lines
93	}	93	}
94		94
95	/**	95	/**
96	* nilfs_suinfo_update - segment usage information update	96	* struct nilfs_suinfo_update - segment usage information update
97	* @sup_segnum: segment number	97	* @sup_segnum: segment number
98	* @sup_flags: flags for which fields are active in sup_sui	98	* @sup_flags: flags for which fields are active in sup_sui
99	* @sup_reserved: reserved necessary for alignment	99	* @sup_reserved: reserved necessary for alignment

include/uapi/linux/nilfs2_ondisk.h+97−66

@@ -133,73 +133,104 @@ struct nilfs_super_root { · 132 unmodified lines
133		133
134	/**	134	/**
135	* struct nilfs_super_block - structure of super block on disk	135	* struct nilfs_super_block - structure of super block on disk
		136	* @s_rev_level: Revision level
		137	* @s_minor_rev_level: minor revision level
		138	* @s_magic: Magic signature
		139	* @s_bytes: Bytes count of CRC calculation for
		140	* this structure. s_reserved is excluded.
		141	* @s_flags: flags
		142	* @s_crc_seed: Seed value of CRC calculation
		143	* @s_sum: Check sum of super block
		144	* @s_log_block_size: Block size represented as follows:
		145	* blocksize = 1 << (s_log_block_size + 10)
		146	* @s_nsegments: Number of segments in filesystem
		147	* @s_dev_size: block device size in bytes
		148	* @s_first_data_block: 1st seg disk block number
		149	* @s_blocks_per_segment: number of blocks per full segment
		150	* @s_r_segments_percentage: Reserved segments percentage
		151	* @s_last_cno: Last checkpoint number
		152	* @s_last_pseg: disk block addr pseg written last
		153	* @s_last_seq: seq. number of seg written last
		154	* @s_free_blocks_count: Free blocks count
		155	* @s_ctime: Creation time (execution time of newfs)
		156	* @s_mtime: Mount time
		157	* @s_wtime: Write time
		158	* @s_mnt_count: Mount count
		159	* @s_max_mnt_count: Maximal mount count
		160	* @s_state: File system state
		161	* @s_errors: Behaviour when detecting errors
		162	* @s_lastcheck: time of last check
		163	* @s_checkinterval: max. time between checks
		164	* @s_creator_os: OS
		165	* @s_def_resuid: Default uid for reserved blocks
		166	* @s_def_resgid: Default gid for reserved blocks
		167	* @s_first_ino: First non-reserved inode
		168	* @s_inode_size: Size of an inode
		169	* @s_dat_entry_size: Size of a dat entry
		170	* @s_checkpoint_size: Size of a checkpoint
		171	* @s_segment_usage_size: Size of a segment usage
		172	* @s_uuid: 128-bit uuid for volume
		173	* @s_volume_name: volume name
		174	* @s_c_interval: Commit interval of segment
		175	* @s_c_block_max: Threshold of data amount for the
		176	* segment construction
		177	* @s_feature_compat: Compatible feature set
		178	* @s_feature_compat_ro: Read-only compatible feature set
		179	* @s_feature_incompat: Incompatible feature set
		180	* @s_reserved: padding to the end of the block
136	*/	181	*/
137	struct nilfs_super_block {	182	struct nilfs_super_block {
138	/00/ __le32 s_rev_level; /* Revision level */	183	/00/ __le32 s_rev_level;
139	__le16 s_minor_rev_level; /* minor revision level */	184	__le16 s_minor_rev_level;
140	__le16 s_magic; /* Magic signature */	185	__le16 s_magic;
141		186
142	__le16 s_bytes; /*	187	__le16 s_bytes;
143	* Bytes count of CRC calculation	188	__le16 s_flags;
144	* for this structure. s_reserved	189	__le32 s_crc_seed;
145	* is excluded.	190	/10/ __le32 s_sum;
146	*/	191
147	__le16 s_flags; /* flags */	192	__le32 s_log_block_size;
148	__le32 s_crc_seed; /* Seed value of CRC calculation */	193	__le64 s_nsegments;
149	/10/ __le32 s_sum; /* Check sum of super block */	194	/20/ __le64 s_dev_size;
150		195	__le64 s_first_data_block;
151	__le32 s_log_block_size; /*	196	/30/ __le32 s_blocks_per_segment;
152	* Block size represented as follows	197	__le32 s_r_segments_percentage;
153	* blocksize =	198
154	* 1 << (s_log_block_size + 10)	199	__le64 s_last_cno;
155	*/	200	/40/ __le64 s_last_pseg;
156	__le64 s_nsegments; /* Number of segments in filesystem */	201	__le64 s_last_seq;
157	/20/ __le64 s_dev_size; /* block device size in bytes */	202	/50/ __le64 s_free_blocks_count;
158	__le64 s_first_data_block; /* 1st seg disk block number */	203
159	/30/ __le32 s_blocks_per_segment; /* number of blocks per full segment */	204	__le64 s_ctime;
160	__le32 s_r_segments_percentage; /* Reserved segments percentage */	205	/60/ __le64 s_mtime;
161		206	__le64 s_wtime;
162	__le64 s_last_cno; /* Last checkpoint number */	207	/70/ __le16 s_mnt_count;
163	/40/ __le64 s_last_pseg; /* disk block addr pseg written last */	208	__le16 s_max_mnt_count;
164	__le64 s_last_seq; /* seq. number of seg written last */	209	__le16 s_state;
165	/50/ __le64 s_free_blocks_count; /* Free blocks count */	210	__le16 s_errors;
166		211	__le64 s_lastcheck;
167	__le64 s_ctime; /*	212
168	* Creation time (execution time of	213	/80/ __le32 s_checkinterval;
169	* newfs)	214	__le32 s_creator_os;
170	*/	215	__le16 s_def_resuid;
171	/60/ __le64 s_mtime; /* Mount time */	216	__le16 s_def_resgid;
172	__le64 s_wtime; /* Write time */	217	__le32 s_first_ino;
173	/70/ __le16 s_mnt_count; /* Mount count */	218
174	__le16 s_max_mnt_count; /* Maximal mount count */	219	/90/ __le16 s_inode_size;
175	__le16 s_state; /* File system state */	220	__le16 s_dat_entry_size;
176	__le16 s_errors; /* Behaviour when detecting errors */	221	__le16 s_checkpoint_size;
177	__le64 s_lastcheck; /* time of last check */	222	__le16 s_segment_usage_size;
178		223
179	/80/ __le32 s_checkinterval; /* max. time between checks */	224	/98/ __u8 s_uuid[16];
180	__le32 s_creator_os; /* OS */	225	/A8/ char s_volume_name[80] __kernel_nonstring;
181	__le16 s_def_resuid; /* Default uid for reserved blocks */	226
182	__le16 s_def_resgid; /* Default gid for reserved blocks */	227	/F8/ __le32 s_c_interval;
183	__le32 s_first_ino; /* First non-reserved inode */	228	__le32 s_c_block_max;
184		229
185	/90/ __le16 s_inode_size; /* Size of an inode */	230	/100/ __le64 s_feature_compat;
186	__le16 s_dat_entry_size; /* Size of a dat entry */	231	__le64 s_feature_compat_ro;
187	__le16 s_checkpoint_size; /* Size of a checkpoint */	232	__le64 s_feature_incompat;
188	__le16 s_segment_usage_size; /* Size of a segment usage */	233	__u32 s_reserved[186];
189
190	/98/ __u8 s_uuid[16]; /* 128-bit uuid for volume */
191	/A8/ char s_volume_name[80] /* volume name */
192	__kernel_nonstring;
193
194	/F8/ __le32 s_c_interval; /* Commit interval of segment */
195	__le32 s_c_block_max; /*
196	* Threshold of data amount for
197	* the segment construction
198	*/
199	/100/ __le64 s_feature_compat; /* Compatible feature set */
200	__le64 s_feature_compat_ro; /* Read-only compatible feature set */
201	__le64 s_feature_incompat; /* Incompatible feature set */
202	__u32 s_reserved[186]; /* padding to the end of the block */
203	};	234	};
204		235
205	/*	236	/*
@@ -449,7 +480,7 @@ struct nilfs_btree_node { · 243 unmodified lines
449	/**	480	/**
450	* struct nilfs_direct_node - header of built-in bmap array	481	* struct nilfs_direct_node - header of built-in bmap array
451	* @dn_flags: flags	482	* @dn_flags: flags
452	* @dn_pad: padding	483	* @pad: padding
453	*/	484	*/
454	struct nilfs_direct_node {	485	struct nilfs_direct_node {
455	__u8 dn_flags;	486	__u8 dn_flags;

include/uapi/linux/nl80211.h+107−5

  * Copyright 2008 Jouni Malinen <jouni.malinen@atheros.com>
  * Copyright 2008 Colin McCabe <colin@cozybit.com>
  * Copyright 2015-2017	Intel Deutschland GmbH
- * Copyright (C) 2018-2025 Intel Corporation
+ * Copyright (C) 2018-2026 Intel Corporation
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  *	index. If the userspace includes more RNR elements than number of
  *	MBSSID elements then these will be added in every EMA beacon.
  *
- * @NL80211_ATTR_MLO_LINK_DISABLED: Flag attribute indicating that the link is
+ * @NL80211_ATTR_MLO_LINK_DISABLED: Unused. It was used to indicate that a link
- *	disabled.
+ *	is disabled during association. However, the AP will send the
+ *	information by including a TTLM in the association response.
  *
  * @NL80211_ATTR_BSS_DUMP_INCLUDE_USE_DATA: Include BSS usage data, i.e.
  *	include BSSes that can only be used in restricted scenarios and/or
  *	primary channel is 2 MHz wide, and the control channel designates
  *	the 1 MHz primary subchannel within that 2 MHz primary.
  *
+ * @NL80211_ATTR_EPP_PEER: A flag attribute to indicate if the peer is an EPP
+ *	STA. Used with %NL80211_CMD_NEW_STA and %NL80211_CMD_ADD_LINK_STA
+ *
+ * @NL80211_ATTR_UHR_CAPABILITY: UHR Capability information element (from
+ *	association request when used with NL80211_CMD_NEW_STATION). Can be set
+ *	only if HE/EHT are also available.
+ * @NL80211_ATTR_DISABLE_UHR: Force UHR capable interfaces to disable
+ *	this feature during association. This is a flag attribute.
+ *	Currently only supported in mac80211 drivers.
+ *
  * @NUM_NL80211_ATTR: total number of nl80211_attrs available
  * @NL80211_ATTR_MAX: highest attribute number currently defined
  * @__NL80211_ATTR_AFTER_LAST: internal use
 	NL80211_ATTR_S1G_PRIMARY_2MHZ,
+	NL80211_ATTR_EPP_PEER,
+	NL80211_ATTR_UHR_CAPABILITY,
+	NL80211_ATTR_DISABLE_UHR,
 	/* add attributes here, update the policy in nl80211.c */
 	__NL80211_ATTR_AFTER_LAST,
  * @NL80211_RATE_INFO_4_MHZ_WIDTH: 4 MHz S1G rate
  * @NL80211_RATE_INFO_8_MHZ_WIDTH: 8 MHz S1G rate
  * @NL80211_RATE_INFO_16_MHZ_WIDTH: 16 MHz S1G rate
+ * @NL80211_RATE_INFO_UHR_MCS: UHR MCS index (u8, 0-15, 17, 19, 20, 23)
+ *	Note that the other EHT attributes (such as @NL80211_RATE_INFO_EHT_NSS)
+ *	are used in conjunction with this where applicable
+ * @NL80211_RATE_INFO_UHR_ELR: UHR ELR flag, which restricts NSS to 1,
+ *	MCS to 0 or 1, and GI to %NL80211_RATE_INFO_EHT_GI_1_6.
+ * @NL80211_RATE_INFO_UHR_IM: UHR Interference Mitigation flag
  * @__NL80211_RATE_INFO_AFTER_LAST: internal use
  */
 enum nl80211_rate_info {
 	NL80211_RATE_INFO_4_MHZ_WIDTH,
 	NL80211_RATE_INFO_8_MHZ_WIDTH,
 	NL80211_RATE_INFO_16_MHZ_WIDTH,
+	NL80211_RATE_INFO_UHR_MCS,
+	NL80211_RATE_INFO_UHR_ELR,
+	NL80211_RATE_INFO_UHR_IM,
 	/* keep last */
 	__NL80211_RATE_INFO_AFTER_LAST,
  *	capabilities element
  * @NL80211_BAND_IFTYPE_ATTR_EHT_CAP_PPE: EHT PPE thresholds information as
  *	defined in EHT capabilities element
+ * @NL80211_BAND_IFTYPE_ATTR_UHR_CAP_MAC: UHR MAC capabilities as in UHR
+ *	capabilities element
+ * @NL80211_BAND_IFTYPE_ATTR_UHR_CAP_PHY: UHR PHY capabilities as in UHR
+ *	capabilities element
  * @__NL80211_BAND_IFTYPE_ATTR_AFTER_LAST: internal use
  * @NL80211_BAND_IFTYPE_ATTR_MAX: highest band attribute currently defined
  */
 	NL80211_BAND_IFTYPE_ATTR_EHT_CAP_PHY,
 	NL80211_BAND_IFTYPE_ATTR_EHT_CAP_MCS_SET,
 	NL80211_BAND_IFTYPE_ATTR_EHT_CAP_PPE,
+	NL80211_BAND_IFTYPE_ATTR_UHR_CAP_MAC,
+	NL80211_BAND_IFTYPE_ATTR_UHR_CAP_PHY,
 	/* keep last */
 	__NL80211_BAND_IFTYPE_ATTR_AFTER_LAST,
  *	channel in current regulatory domain.
  * @NL80211_FREQUENCY_ATTR_NO_16MHZ: 16 MHz operation is not allowed on this
  *	channel in current regulatory domain.
+ * @NL80211_FREQUENCY_ATTR_S1G_NO_PRIMARY: Channel is not permitted for use
+ *	as a primary channel. Does not prevent the channel from existing
+ *	as a non-primary subchannel. Only applicable to S1G channels.
+ * @NL80211_FREQUENCY_ATTR_NO_UHR: UHR operation is not allowed on this channel
+ *	in current regulatory domain.
  * @NL80211_FREQUENCY_ATTR_MAX: highest frequency attribute number
  *	currently defined
  * @__NL80211_FREQUENCY_ATTR_AFTER_LAST: internal use
 	NL80211_FREQUENCY_ATTR_NO_4MHZ,
 	NL80211_FREQUENCY_ATTR_NO_8MHZ,
 	NL80211_FREQUENCY_ATTR_NO_16MHZ,
+	NL80211_FREQUENCY_ATTR_S1G_NO_PRIMARY,
+	NL80211_FREQUENCY_ATTR_NO_UHR,
 	/* keep last */
 	__NL80211_FREQUENCY_ATTR_AFTER_LAST,
  *	despite NO_IR configuration.
  * @NL80211_RRF_ALLOW_20MHZ_ACTIVITY: Allow activity in 20 MHz bandwidth,
  *	despite NO_IR configuration.
+ * @NL80211_RRF_NO_UHR: UHR operation not allowed
  */
 enum nl80211_reg_rule_flags {
 	NL80211_RRF_NO_OFDM                 = 1 << 0,
 	NL80211_RRF_NO_6GHZ_AFC_CLIENT      = 1 << 23,
 	NL80211_RRF_ALLOW_6GHZ_VLP_AP       = 1 << 24,
 	NL80211_RRF_ALLOW_20MHZ_ACTIVITY    = 1 << 25,
+	NL80211_RRF_NO_UHR		    = 1 << 26,
 };
 #define NL80211_RRF_PASSIVE_SCAN	NL80211_RRF_NO_IR
  * @NL80211_AUTHTYPE_FILS_SK: Fast Initial Link Setup shared key
  * @NL80211_AUTHTYPE_FILS_SK_PFS: Fast Initial Link Setup shared key with PFS
  * @NL80211_AUTHTYPE_FILS_PK: Fast Initial Link Setup public key
+ * @NL80211_AUTHTYPE_EPPKE: Enhanced Privacy Protection Key Exchange
  * @__NL80211_AUTHTYPE_NUM: internal
  * @NL80211_AUTHTYPE_MAX: maximum valid auth algorithm
  * @NL80211_AUTHTYPE_AUTOMATIC: determine automatically (if necessary by
 	NL80211_AUTHTYPE_FILS_SK,
 	NL80211_AUTHTYPE_FILS_SK_PFS,
 	NL80211_AUTHTYPE_FILS_PK,
+	NL80211_AUTHTYPE_EPPKE,
 	/* keep last */
 	__NL80211_AUTHTYPE_NUM,
  * @NL80211_EXT_FEATURE_BEACON_RATE_EHT: Driver supports beacon rate
  *	configuration (AP/mesh) with EHT rates.
  *
+ * @NL80211_EXT_FEATURE_EPPKE: Driver supports Enhanced Privacy Protection
+ *	Key Exchange (EPPKE) with user space SME (NL80211_CMD_AUTHENTICATE)
+ *	in non-AP STA mode.
+ *
+ * @NL80211_EXT_FEATURE_ASSOC_FRAME_ENCRYPTION: This specifies that the
+ *	driver supports encryption of (Re)Association Request and Response
+ *	frames in both non‑AP STA and AP mode as specified in
+ *	"IEEE P802.11bi/D3.0, 12.16.6".
+ *
  * @NUM_NL80211_EXT_FEATURES: number of extended features.
  * @MAX_NL80211_EXT_FEATURES: highest extended feature index.
  */
 	NL80211_EXT_FEATURE_DFS_CONCURRENT,
 	NL80211_EXT_FEATURE_SPP_AMSDU_SUPPORT,
 	NL80211_EXT_FEATURE_BEACON_RATE_EHT,
+	NL80211_EXT_FEATURE_EPPKE,
+	NL80211_EXT_FEATURE_ASSOC_FRAME_ENCRYPTION,
 	/* add new features before the definition below */
 	NUM_NL80211_EXT_FEATURES,
  *	address that can take values from 50-6F-9A-01-00-00 to
  *	50-6F-9A-01-FF-FF. This attribute is optional. If not present,
  *	a random Cluster ID will be chosen.
+ *	This attribute will be ignored in NL80211_CMD_CHANGE_NAN_CONFIG
+ *	since after NAN was started, the cluster ID can no longer change.
  * @NL80211_NAN_CONF_EXTRA_ATTRS: Additional NAN attributes to be
  *	published in the beacons. This is an optional byte array.
  * @NL80211_NAN_CONF_VENDOR_ELEMS: Vendor-specific elements that will
  *	trigger based ranging measurement is supported
  * @NL80211_PMSR_FTM_CAPA_ATTR_NON_TRIGGER_BASED: flag attribute indicating
  *	if non-trigger-based ranging measurement is supported
+ * @NL80211_PMSR_FTM_CAPA_ATTR_6GHZ_SUPPORT: flag attribute indicating if
+ *	ranging on the 6 GHz band is supported
+ * @NL80211_PMSR_FTM_CAPA_ATTR_MAX_TX_LTF_REP: u32 attribute indicating
+ *	the maximum number of LTF repetitions the device can transmit in the
+ *	preamble of the ranging NDP (zero means only one LTF, no repetitions)
+ * @NL80211_PMSR_FTM_CAPA_ATTR_MAX_RX_LTF_REP: u32 attribute indicating
+ *	the maximum number of LTF repetitions the device can receive in the
+ *	preamble of the ranging NDP (zero means only one LTF, no repetitions)
+ * @NL80211_PMSR_FTM_CAPA_ATTR_MAX_TX_STS: u32 attribute indicating
+ *	the maximum number of space-time streams supported for ranging NDP TX
+ *	(zero-based)
+ * @NL80211_PMSR_FTM_CAPA_ATTR_MAX_RX_STS: u32 attribute indicating
+ *	the maximum number of space-time streams supported for ranging NDP RX
+ *	(zero-based)
+ * @NL80211_PMSR_FTM_CAPA_ATTR_MAX_TOTAL_LTF_TX: u32 attribute indicating the
+ *	maximum total number of LTFs the device can transmit. The total number
+ *	of LTFs is (number of LTF repetitions) * (number of space-time streams).
+ *	This limits the allowed combinations of LTF repetitions and STS.
+ * @NL80211_PMSR_FTM_CAPA_ATTR_MAX_TOTAL_LTF_RX: u32 attribute indicating the
+ *	maximum total number of LTFs the device can receive. The total number
+ *	of LTFs is (number of LTF repetitions) * (number of space-time streams).
+ *	This limits the allowed combinations of LTF repetitions and STS.
+ * @NL80211_PMSR_FTM_CAPA_ATTR_RSTA_SUPPORT: flag attribute indicating the
+ *	device supports operating as the RSTA in PMSR FTM request
  *
  * @NUM_NL80211_PMSR_FTM_CAPA_ATTR: internal
  * @NL80211_PMSR_FTM_CAPA_ATTR_MAX: highest attribute number
 	NL80211_PMSR_FTM_CAPA_ATTR_MAX_FTMS_PER_BURST,
 	NL80211_PMSR_FTM_CAPA_ATTR_TRIGGER_BASED,
 	NL80211_PMSR_FTM_CAPA_ATTR_NON_TRIGGER_BASED,
+	NL80211_PMSR_FTM_CAPA_ATTR_6GHZ_SUPPORT,
+	NL80211_PMSR_FTM_CAPA_ATTR_MAX_TX_LTF_REP,
+	NL80211_PMSR_FTM_CAPA_ATTR_MAX_RX_LTF_REP,
+	NL80211_PMSR_FTM_CAPA_ATTR_MAX_TX_STS,
+	NL80211_PMSR_FTM_CAPA_ATTR_MAX_RX_STS,
+	NL80211_PMSR_FTM_CAPA_ATTR_MAX_TOTAL_LTF_TX,
+	NL80211_PMSR_FTM_CAPA_ATTR_MAX_TOTAL_LTF_RX,
+	NL80211_PMSR_FTM_CAPA_ATTR_RSTA_SUPPORT,
 	/* keep last */
 	NUM_NL80211_PMSR_FTM_CAPA_ATTR,
  *	&enum nl80211_preamble), optional for DMG (u32)
  * @NL80211_PMSR_FTM_REQ_ATTR_NUM_BURSTS_EXP: number of bursts exponent as in
  *	802.11-2016 9.4.2.168 "Fine Timing Measurement Parameters element"
- *	(u8, 0-15, optional with default 15 i.e. "no preference")
+ *	(u8, 0-15, optional with default 15 i.e. "no preference". No limit for
+ *	 non-EDCA ranging)
  * @NL80211_PMSR_FTM_REQ_ATTR_BURST_PERIOD: interval between bursts in units
  *	of 100ms (u16, optional with default 0)
  * @NL80211_PMSR_FTM_REQ_ATTR_BURST_DURATION: burst duration, as in 802.11-2016
  *	Table 9-257 "Burst Duration field encoding" (u8, 0-15, optional with
- *	default 15 i.e. "no preference")
+ *	default 15 i.e. "no preference"). For non-EDCA ranging, this is the
+ *	burst duration in milliseconds (optional with default 0, i.e. let the
+ *	device decide).
  * @NL80211_PMSR_FTM_REQ_ATTR_FTMS_PER_BURST: number of successful FTM frames
  *	requested per burst
  *	(u8, 0-31, optional with default 0 i.e. "no preference")
  * @NL80211_PMSR_FTM_REQ_ATTR_BSS_COLOR: optional. The BSS color of the
  *	responder. Only valid if %NL80211_PMSR_FTM_REQ_ATTR_NON_TRIGGER_BASED
  *	or %NL80211_PMSR_FTM_REQ_ATTR_TRIGGER_BASED is set.
+ * @NL80211_PMSR_FTM_REQ_ATTR_RSTA: optional. Request to perform the measurement
+ *	as the RSTA (flag). When set, the device is expected to dwell on the
+ *	channel specified in %NL80211_PMSR_PEER_ATTR_CHAN until it receives the
+ *	FTM request from the peer or the timeout specified by
+ *	%NL80211_ATTR_TIMEOUT has expired.
+ *	Only valid if %NL80211_PMSR_FTM_REQ_ATTR_LMR_FEEDBACK is set (so the
+ *	RSTA will have the measurement results to report back in the FTM
+ *	response).
  *
  * @NUM_NL80211_PMSR_FTM_REQ_ATTR: internal
  * @NL80211_PMSR_FTM_REQ_ATTR_MAX: highest attribute number
 	NL80211_PMSR_FTM_REQ_ATTR_NON_TRIGGER_BASED,
 	NL80211_PMSR_FTM_REQ_ATTR_LMR_FEEDBACK,
 	NL80211_PMSR_FTM_REQ_ATTR_BSS_COLOR,
+	NL80211_PMSR_FTM_REQ_ATTR_RSTA,
 	/* keep last */
 	NUM_NL80211_PMSR_FTM_REQ_ATTR,
  *	9.4.2.22.1) starting with the Measurement Token, with Measurement
  *	Type 11.
  * @NL80211_PMSR_FTM_RESP_ATTR_PAD: ignore, for u64/s64 padding only
+ * @NL80211_PMSR_FTM_RESP_ATTR_BURST_PERIOD: actual burst period used by
+ *	the responder (similar to request, u16)
  *
  * @NUM_NL80211_PMSR_FTM_RESP_ATTR: internal
  * @NL80211_PMSR_FTM_RESP_ATTR_MAX: highest attribute number
 	NL80211_PMSR_FTM_RESP_ATTR_LCI,
 	NL80211_PMSR_FTM_RESP_ATTR_CIVICLOC,
 	NL80211_PMSR_FTM_RESP_ATTR_PAD,
+	NL80211_PMSR_FTM_RESP_ATTR_BURST_PERIOD,
 	/* keep last */
 	NUM_NL80211_PMSR_FTM_RESP_ATTR,

include/uapi/linux/pci.h+7−0

@@ -39,4 +39,11 @@ · 38 unmodified lines
39	#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE \| 0x02) /* Set mmap state to MEM space. */	39	#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE \| 0x02) /* Set mmap state to MEM space. */
40	#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE \| 0x03) /* Enable/disable write-combining. */	40	#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE \| 0x03) /* Enable/disable write-combining. */
41		41
		42	enum pci_hotplug_event {
		43	PCI_HOTPLUG_LINK_UP,
		44	PCI_HOTPLUG_LINK_DOWN,
		45	PCI_HOTPLUG_CARD_PRESENT,
		46	PCI_HOTPLUG_CARD_NOT_PRESENT,
		47	};
		48
42	#endif /* _UAPILINUX_PCI_H */	49	#endif /* _UAPILINUX_PCI_H */

include/uapi/linux/pci_regs.h+64−5

@@ -132,6 +132,11 @@ · 131 unmodified lines
132	#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */	132	#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
133	#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */	133	#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
134	#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */	134	#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
		135	/* Masks for dword-sized processing of Bus Number and Sec Latency Timer fields */
		136	#define PCI_PRIMARY_BUS_MASK 0x000000ff
		137	#define PCI_SECONDARY_BUS_MASK 0x0000ff00
		138	#define PCI_SUBORDINATE_BUS_MASK 0x00ff0000
		139	#define PCI_SEC_LATENCY_TIMER_MASK 0xff000000
135	#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */	140	#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
136	#define PCI_IO_LIMIT 0x1d	141	#define PCI_IO_LIMIT 0x1d
137	#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */	142	#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
@@ -1253,11 +1258,6 @@ · 1115 unmodified lines
1253	#define PCI_DEV3_STA 0x0c /* Device 3 Status Register */	1258	#define PCI_DEV3_STA 0x0c /* Device 3 Status Register */
1254	#define PCI_DEV3_STA_SEGMENT 0x8 /* Segment Captured (end-to-end flit-mode detected) */	1259	#define PCI_DEV3_STA_SEGMENT 0x8 /* Segment Captured (end-to-end flit-mode detected) */
1255		1260
1256	/* Compute Express Link (CXL r3.1, sec 8.1.5) */
1257	#define PCI_DVSEC_CXL_PORT 3
1258	#define PCI_DVSEC_CXL_PORT_CTL 0x0c
1259	#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
1260
1261	/* Integrity and Data Encryption Extended Capability */	1261	/* Integrity and Data Encryption Extended Capability */
1262	#define PCI_IDE_CAP 0x04	1262	#define PCI_IDE_CAP 0x04
1263	#define PCI_IDE_CAP_LINK 0x1 /* Link IDE Stream Supported */	1263	#define PCI_IDE_CAP_LINK 0x1 /* Link IDE Stream Supported */
@@ -1338,4 +1338,63 @@ · 74 unmodified lines
1338	#define PCI_IDE_SEL_ADDR_3(x) (28 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE)	1338	#define PCI_IDE_SEL_ADDR_3(x) (28 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE)
1339	#define PCI_IDE_SEL_BLOCK_SIZE(nr_assoc) (20 + PCI_IDE_SEL_ADDR_BLOCK_SIZE * (nr_assoc))	1339	#define PCI_IDE_SEL_BLOCK_SIZE(nr_assoc) (20 + PCI_IDE_SEL_ADDR_BLOCK_SIZE * (nr_assoc))
1340		1340
		1341	/*
		1342	* Compute Express Link (CXL r4.0, sec 8.1)
		1343	*
		1344	* Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state
		1345	* is "disconnected" (CXL r4.0, sec 9.12.3). Re-enumerate these
		1346	* registers on downstream link-up events.
		1347	*/
		1348
		1349	/* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */
		1350	#define PCI_DVSEC_CXL_DEVICE 0
		1351	#define PCI_DVSEC_CXL_CAP 0xA
		1352	#define PCI_DVSEC_CXL_MEM_CAPABLE _BITUL(2)
		1353	#define PCI_DVSEC_CXL_HDM_COUNT __GENMASK(5, 4)
		1354	#define PCI_DVSEC_CXL_CTRL 0xC
		1355	#define PCI_DVSEC_CXL_MEM_ENABLE _BITUL(2)
		1356	#define PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
		1357	#define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))
		1358	#define PCI_DVSEC_CXL_MEM_INFO_VALID _BITUL(0)
		1359	#define PCI_DVSEC_CXL_MEM_ACTIVE _BITUL(1)
		1360	#define PCI_DVSEC_CXL_MEM_SIZE_LOW __GENMASK(31, 28)
		1361	#define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
		1362	#define PCI_DVSEC_CXL_RANGE_BASE_LOW(i) (0x24 + (i * 0x10))
		1363	#define PCI_DVSEC_CXL_MEM_BASE_LOW __GENMASK(31, 28)
		1364
		1365	#define CXL_DVSEC_RANGE_MAX 2
		1366
		1367	/* CXL r4.0, 8.1.4: Non-CXL Function Map DVSEC */
		1368	#define PCI_DVSEC_CXL_FUNCTION_MAP 2
		1369
		1370	/* CXL r4.0, 8.1.5: Extensions DVSEC for Ports */
		1371	#define PCI_DVSEC_CXL_PORT 3
		1372	#define PCI_DVSEC_CXL_PORT_CTL 0x0c
		1373	#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
		1374
		1375	/* CXL r4.0, 8.1.6: GPF DVSEC for CXL Port */
		1376	#define PCI_DVSEC_CXL_PORT_GPF 4
		1377	#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL 0x0C
		1378	#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE __GENMASK(3, 0)
		1379	#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE __GENMASK(11, 8)
		1380	#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL 0xE
		1381	#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE __GENMASK(3, 0)
		1382	#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE __GENMASK(11, 8)
		1383
		1384	/* CXL r4.0, 8.1.7: GPF DVSEC for CXL Device */
		1385	#define PCI_DVSEC_CXL_DEVICE_GPF 5
		1386
		1387	/* CXL r4.0, 8.1.8: Flex Bus DVSEC */
		1388	#define PCI_DVSEC_CXL_FLEXBUS_PORT 7
		1389	#define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS 0xE
		1390	#define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE _BITUL(0)
		1391	#define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM _BITUL(2)
		1392
		1393	/* CXL r4.0, 8.1.9: Register Locator DVSEC */
		1394	#define PCI_DVSEC_CXL_REG_LOCATOR 8
		1395	#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1 0xC
		1396	#define PCI_DVSEC_CXL_REG_LOCATOR_BIR __GENMASK(2, 0)
		1397	#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID __GENMASK(15, 8)
		1398	#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW __GENMASK(31, 16)
		1399
1341	#endif /* LINUX_PCI_REGS_H */	1400	#endif /* LINUX_PCI_REGS_H */

include/uapi/linux/pcitest.h+1−0

@@ -22,6 +22,7 @@ · 21 unmodified lines
22	#define PCITEST_GET_IRQTYPE _IO('P', 0x9)	22	#define PCITEST_GET_IRQTYPE _IO('P', 0x9)
23	#define PCITEST_BARS _IO('P', 0xa)	23	#define PCITEST_BARS _IO('P', 0xa)
24	#define PCITEST_DOORBELL _IO('P', 0xb)	24	#define PCITEST_DOORBELL _IO('P', 0xb)
		25	#define PCITEST_BAR_SUBRANGE _IO('P', 0xc)
25	#define PCITEST_CLEAR_IRQ _IO('P', 0x10)	26	#define PCITEST_CLEAR_IRQ _IO('P', 0x10)
26		27
27	#define PCITEST_IRQ_TYPE_UNDEFINED -1	28	#define PCITEST_IRQ_TYPE_UNDEFINED -1

include/uapi/linux/perf_event.h+24−3

 			mem_snoopx  :  2, /* Snoop mode, ext */
 			mem_blk     :  3, /* Access blocked */
 			mem_hops    :  3, /* Hop level */
-			mem_rsvd    : 18;
+			mem_region  :  5, /* cache/memory regions */
+			mem_rsvd    : 13;
 	};
 };
 #elif defined(__BIG_ENDIAN_BITFIELD)
 union perf_mem_data_src {
 	__u64 val;
 	struct {
-		__u64	mem_rsvd    : 18,
+		__u64	mem_rsvd    : 13,
+			mem_region  :  5, /* cache/memory regions */
 			mem_hops    :  3, /* Hop level */
 			mem_blk     :  3, /* Access blocked */
 			mem_snoopx  :  2, /* Snoop mode, ext */
 #define PERF_MEM_LVLNUM_L4			0x0004 /* L4 */
 #define PERF_MEM_LVLNUM_L2_MHB			0x0005 /* L2 Miss Handling Buffer */
 #define PERF_MEM_LVLNUM_MSC			0x0006 /* Memory-side Cache */
-/* 0x007 available */
+#define PERF_MEM_LVLNUM_L0			0x0007 /* L0 */
 #define PERF_MEM_LVLNUM_UNC			0x0008 /* Uncached */
 #define PERF_MEM_LVLNUM_CXL			0x0009 /* CXL */
 #define PERF_MEM_LVLNUM_IO			0x000a /* I/O */
 /* 5-7 available */
 #define PERF_MEM_HOPS_SHIFT			43
+/* Cache/Memory region */
+#define PERF_MEM_REGION_NA		0x0  /* Invalid */
+#define PERF_MEM_REGION_RSVD		0x01 /* Reserved */
+#define PERF_MEM_REGION_L_SHARE		0x02 /* Local CA shared cache */
+#define PERF_MEM_REGION_L_NON_SHARE	0x03 /* Local CA non-shared cache */
+#define PERF_MEM_REGION_O_IO		0x04 /* Other CA IO agent */
+#define PERF_MEM_REGION_O_SHARE		0x05 /* Other CA shared cache */
+#define PERF_MEM_REGION_O_NON_SHARE	0x06 /* Other CA non-shared cache */
+#define PERF_MEM_REGION_MMIO		0x07 /* MMIO */
+#define PERF_MEM_REGION_MEM0		0x08 /* Memory region 0 */
+#define PERF_MEM_REGION_MEM1		0x09 /* Memory region 1 */
+#define PERF_MEM_REGION_MEM2		0x0a /* Memory region 2 */
+#define PERF_MEM_REGION_MEM3		0x0b /* Memory region 3 */
+#define PERF_MEM_REGION_MEM4		0x0c /* Memory region 4 */
+#define PERF_MEM_REGION_MEM5		0x0d /* Memory region 5 */
+#define PERF_MEM_REGION_MEM6		0x0e /* Memory region 6 */
+#define PERF_MEM_REGION_MEM7		0x0f /* Memory region 7 */
+#define PERF_MEM_REGION_SHIFT		46
 #define PERF_MEM_S(a, s) \
 	(((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)

include/uapi/linux/pkt_sched.h+1−0

@@ -1036,6 +1036,7 @@ enum { · 1035 unmodified lines
1036	TCA_CAKE_STATS_DROP_NEXT_US,	1036	TCA_CAKE_STATS_DROP_NEXT_US,
1037	TCA_CAKE_STATS_P_DROP,	1037	TCA_CAKE_STATS_P_DROP,
1038	TCA_CAKE_STATS_BLUE_TIMER_US,	1038	TCA_CAKE_STATS_BLUE_TIMER_US,
		1039	TCA_CAKE_STATS_ACTIVE_QUEUES,
1039	__TCA_CAKE_STATS_MAX	1040	__TCA_CAKE_STATS_MAX
1040	};	1041	};
1041	#define TCA_CAKE_STATS_MAX (__TCA_CAKE_STATS_MAX - 1)	1042	#define TCA_CAKE_STATS_MAX (__TCA_CAKE_STATS_MAX - 1)

include/uapi/linux/prctl.h+37−0

@@ -386,4 +386,41 @@ struct prctl_mm_map { · 385 unmodified lines
386	# define PR_FUTEX_HASH_SET_SLOTS 1	386	# define PR_FUTEX_HASH_SET_SLOTS 1
387	# define PR_FUTEX_HASH_GET_SLOTS 2	387	# define PR_FUTEX_HASH_GET_SLOTS 2
388		388
		389	/* RSEQ time slice extensions */
		390	#define PR_RSEQ_SLICE_EXTENSION 79
		391	# define PR_RSEQ_SLICE_EXTENSION_GET 1
		392	# define PR_RSEQ_SLICE_EXTENSION_SET 2
		393	/*
		394	* Bits for RSEQ_SLICE_EXTENSION_GET/SET
		395	* PR_RSEQ_SLICE_EXT_ENABLE: Enable
		396	*/
		397	# define PR_RSEQ_SLICE_EXT_ENABLE 0x01
		398
		399	/*
		400	* Get the current indirect branch tracking configuration for the current
		401	* thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS.
		402	*/
		403	#define PR_GET_INDIR_BR_LP_STATUS 80
		404
		405	/*
		406	* Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE will
		407	* enable cpu feature for user thread, to track all indirect branches and ensure
		408	* they land on arch defined landing pad instruction.
		409	* x86 - If enabled, an indirect branch must land on an ENDBRANCH instruction.
		410	* arch64 - If enabled, an indirect branch must land on a BTI instruction.
		411	* riscv - If enabled, an indirect branch must land on an lpad instruction.
		412	* PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect
		413	* branches will no more be tracked by cpu to land on arch defined landing pad
		414	* instruction.
		415	*/
		416	#define PR_SET_INDIR_BR_LP_STATUS 81
		417	# define PR_INDIR_BR_LP_ENABLE (1UL << 0)
		418
		419	/*
		420	* Prevent further changes to the specified indirect branch tracking
		421	* configuration. All bits may be locked via this call, including
		422	* undefined bits.
		423	*/
		424	#define PR_LOCK_INDIR_BR_LP_STATUS 82
		425
389	#endif /* _LINUX_PRCTL_H */	426	#endif /* _LINUX_PRCTL_H */

include/uapi/linux/rseq.h+40−1

@@ -19,13 +19,20 @@ enum rseq_cpu_id_state { · 18 unmodified lines
19	};	19	};
20		20
21	enum rseq_flags {	21	enum rseq_flags {
22	RSEQ_FLAG_UNREGISTER = (1 << 0),	22	RSEQ_FLAG_UNREGISTER = (1 << 0),
		23	RSEQ_FLAG_SLICE_EXT_DEFAULT_ON = (1 << 1),
23	};	24	};
24		25
25	enum rseq_cs_flags_bit {	26	enum rseq_cs_flags_bit {
		27	/* Historical and unsupported bits */
26	RSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0,	28	RSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT = 0,
27	RSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1,	29	RSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT = 1,
28	RSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2,	30	RSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT = 2,
		31	/* (3) Intentional gap to put new bits into a separate byte */
		32
		33	/* User read only feature flags */
		34	RSEQ_CS_FLAG_SLICE_EXT_AVAILABLE_BIT = 4,
		35	RSEQ_CS_FLAG_SLICE_EXT_ENABLED_BIT = 5,
29	};	36	};
30		37
31	enum rseq_cs_flags {	38	enum rseq_cs_flags {
@@ -35,6 +42,11 @@ enum rseq_cs_flags { · 3 unmodified lines
35	(1U << RSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT),	42	(1U << RSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT),
36	RSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE =	43	RSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE =
37	(1U << RSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT),	44	(1U << RSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT),
		45
		46	RSEQ_CS_FLAG_SLICE_EXT_AVAILABLE =
		47	(1U << RSEQ_CS_FLAG_SLICE_EXT_AVAILABLE_BIT),
		48	RSEQ_CS_FLAG_SLICE_EXT_ENABLED =
		49	(1U << RSEQ_CS_FLAG_SLICE_EXT_ENABLED_BIT),
38	};	50	};
39		51
40	/*	52	/*
@@ -53,6 +65,27 @@ struct rseq_cs { · 12 unmodified lines
53	__u64 abort_ip;	65	__u64 abort_ip;
54	} __attribute__((aligned(4 * sizeof(__u64))));	66	} __attribute__((aligned(4 * sizeof(__u64))));
55		67
		68	/**
		69	* rseq_slice_ctrl - Time slice extension control structure
		70	* @all: Compound value
		71	* @request: Request for a time slice extension
		72	* @granted: Granted time slice extension
		73	*
		74	* @request is set by user space and can be cleared by user space or kernel
		75	* space. @granted is set and cleared by the kernel and must only be read
		76	* by user space.
		77	*/
		78	struct rseq_slice_ctrl {
		79	union {
		80	__u32 all;
		81	struct {
		82	__u8 request;
		83	__u8 granted;
		84	__u16 __reserved;
		85	};
		86	};
		87	};
		88
56	/*	89	/*
57	* struct rseq is aligned on 4 * 8 bytes to ensure it is always	90	* struct rseq is aligned on 4 * 8 bytes to ensure it is always
58	* contained within a single cache-line.	91	* contained within a single cache-line.
@@ -141,6 +174,12 @@ struct rseq { · 82 unmodified lines
141	*/	174	*/
142	__u32 mm_cid;	175	__u32 mm_cid;
143		176
		177	/*
		178	* Time slice extension control structure. CPU local updates from
		179	* kernel and user space.
		180	*/
		181	struct rseq_slice_ctrl slice_ctrl;
		182
144	/*	183	/*
145	* Flexible array member at end of structure, after last feature field.	184	* Flexible array member at end of structure, after last feature field.
146	*/	185	*/

include/uapi/linux/shm.h+0−3

 #include <linux/ipc.h>
 #include <linux/errno.h>
 #include <asm-generic/hugetlb_encode.h>
-#ifndef __KERNEL__
-#include <unistd.h>
-#endif
 /*
  * SHMMNI, SHMMAX and SHMALL are default upper limits which can be

include/uapi/linux/stddef.h+4−0

 #define __counted_by_be(m)
 #endif
+#ifndef __counted_by_ptr
+#define __counted_by_ptr(m)
+#endif
 #ifdef __KERNEL__
 #define __kernel_nonstring	__nonstring
 #else

include/uapi/linux/sysctl.h+1−2

@@ -92,7 +92,6 @@ enum · 91 unmodified lines
92	KERN_DOMAINNAME=8, /* string: domainname */	92	KERN_DOMAINNAME=8, /* string: domainname */
93		93
94	KERN_PANIC=15, /* int: panic timeout */	94	KERN_PANIC=15, /* int: panic timeout */
95	KERN_REALROOTDEV=16, /* real root device to mount after initrd */
96		95
97	KERN_SPARC_REBOOT=21, /* reboot command on Sparc */	96	KERN_SPARC_REBOOT=21, /* reboot command on Sparc */
98	KERN_CTLALTDEL=22, /* int: allow ctl-alt-del to reboot */	97	KERN_CTLALTDEL=22, /* int: allow ctl-alt-del to reboot */
@@ -183,7 +182,7 @@ enum · 84 unmodified lines
183	VM_LOWMEM_RESERVE_RATIO=20,/* reservation ratio for lower memory zones */	182	VM_LOWMEM_RESERVE_RATIO=20,/* reservation ratio for lower memory zones */
184	VM_MIN_FREE_KBYTES=21, /* Minimum free kilobytes to maintain */	183	VM_MIN_FREE_KBYTES=21, /* Minimum free kilobytes to maintain */
185	VM_MAX_MAP_COUNT=22, /* int: Maximum number of mmaps/address-space */	184	VM_MAX_MAP_COUNT=22, /* int: Maximum number of mmaps/address-space */
186	VM_LAPTOP_MODE=23, /* vm laptop mode */	185
187	VM_BLOCK_DUMP=24, /* block dump mode */	186	VM_BLOCK_DUMP=24, /* block dump mode */
188	VM_HUGETLB_GROUP=25, /* permitted hugetlb group */	187	VM_HUGETLB_GROUP=25, /* permitted hugetlb group */
189	VM_VFS_CACHE_PRESSURE=26, /* dcache/icache reclaim pressure */	188	VM_VFS_CACHE_PRESSURE=26, /* dcache/icache reclaim pressure */

include/uapi/linux/taskstats.h+12−1

 #define _LINUX_TASKSTATS_H
 #include <linux/types.h>
+#include <linux/time_types.h>
 /* Format for per-task data returned to userland when
  *	- a task exits
  */
-#define TASKSTATS_VERSION	16
+#define TASKSTATS_VERSION	17
 #define TS_COMM_LEN		32	/* should be >= TASK_COMM_LEN
 					 * in linux/sched.h */
 	__u64	irq_delay_max;
 	__u64	irq_delay_min;
+	/*v17: delay max timestamp record*/
+	struct __kernel_timespec cpu_delay_max_ts;
+	struct __kernel_timespec blkio_delay_max_ts;
+	struct __kernel_timespec swapin_delay_max_ts;
+	struct __kernel_timespec freepages_delay_max_ts;
+	struct __kernel_timespec thrashing_delay_max_ts;
+	struct __kernel_timespec compact_delay_max_ts;
+	struct __kernel_timespec wpcopy_delay_max_ts;
+	struct __kernel_timespec irq_delay_max_ts;
 };

include/uapi/linux/tcp.h+23−3

 #define TCPF_CA_Loss	(1<<TCP_CA_Loss)
 };
+/* Values for tcpi_ecn_mode after negotiation */
+#define TCPI_ECN_MODE_DISABLED		0x0
+#define TCPI_ECN_MODE_RFC3168		0x1
+#define TCPI_ECN_MODE_ACCECN		0x2
+#define TCPI_ECN_MODE_PENDING		0x3
+/* Values for accecn_opt_seen */
+#define TCP_ACCECN_OPT_NOT_SEEN		0x0
+#define TCP_ACCECN_OPT_EMPTY_SEEN	0x1
+#define TCP_ACCECN_OPT_COUNTER_SEEN	0x2
+#define TCP_ACCECN_OPT_FAIL_SEEN	0x3
+/* Values for accecn_fail_mode */
+#define TCP_ACCECN_ACE_FAIL_SEND	BIT(0)
+#define TCP_ACCECN_ACE_FAIL_RECV	BIT(1)
+#define TCP_ACCECN_OPT_FAIL_SEND	BIT(2)
+#define TCP_ACCECN_OPT_FAIL_RECV	BIT(3)
 struct tcp_info {
 	__u8	tcpi_state;
 	__u8	tcpi_ca_state;
 					 * in milliseconds, including any
 					 * unfinished recovery.
 					 */
-	__u32	tcpi_received_ce;    /* # of CE marks received */
+	__u32	tcpi_received_ce;    /* # of CE marked segments received */
 	__u32	tcpi_delivered_e1_bytes;  /* Accurate ECN byte counters */
 	__u32	tcpi_delivered_e0_bytes;
 	__u32	tcpi_delivered_ce_bytes;
 	__u32	tcpi_received_e1_bytes;
 	__u32	tcpi_received_e0_bytes;
 	__u32	tcpi_received_ce_bytes;
-	__u16	tcpi_accecn_fail_mode;
+	__u32	tcpi_ecn_mode:2,
-	__u16	tcpi_accecn_opt_seen;
+		tcpi_accecn_opt_seen:2,
+		tcpi_accecn_fail_mode:4,
+		tcpi_options2:24;
 };
 /* netlink attributes types for SCM_TIMESTAMPING_OPT_STATS */

include/uapi/linux/typelimits.h+8−0

@@ -0,0 +1,8 @@
	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
	2	#ifndef _UAPI_LINUX_TYPELIMITS_H
	3	#define _UAPI_LINUX_TYPELIMITS_H
	4
	5	#define __KERNEL_INT_MAX ((int)(~0U >> 1))
	6	#define __KERNEL_INT_MIN (-__KERNEL_INT_MAX - 1)
	7
	8	#endif /* _UAPI_LINUX_TYPELIMITS_H */

include/uapi/linux/ublk_cmd.h+120−1

@@ -55,7 +55,8 @@ · 54 unmodified lines
55	_IOWR('u', 0x15, struct ublksrv_ctrl_cmd)	55	_IOWR('u', 0x15, struct ublksrv_ctrl_cmd)
56	#define UBLK_U_CMD_QUIESCE_DEV \	56	#define UBLK_U_CMD_QUIESCE_DEV \
57	_IOWR('u', 0x16, struct ublksrv_ctrl_cmd)	57	_IOWR('u', 0x16, struct ublksrv_ctrl_cmd)
58		58	#define UBLK_U_CMD_TRY_STOP_DEV \
		59	_IOWR('u', 0x17, struct ublksrv_ctrl_cmd)
59	/*	60	/*
60	* 64bits are enough now, and it should be easy to extend in case of	61	* 64bits are enough now, and it should be easy to extend in case of
61	* running out of feature flags	62	* running out of feature flags
@@ -103,6 +104,30 @@ · 41 unmodified lines
103	#define UBLK_U_IO_UNREGISTER_IO_BUF \	104	#define UBLK_U_IO_UNREGISTER_IO_BUF \
104	_IOWR('u', 0x24, struct ublksrv_io_cmd)	105	_IOWR('u', 0x24, struct ublksrv_io_cmd)
105		106
		107	/*
		108	* return 0 if the command is run successfully, otherwise failure code
		109	* is returned
		110	*/
		111	#define UBLK_U_IO_PREP_IO_CMDS \
		112	_IOWR('u', 0x25, struct ublk_batch_io)
		113	/*
		114	* If failure code is returned, nothing in the command buffer is handled.
		115	* Otherwise, the returned value means how many bytes in command buffer
		116	* are handled actually, then number of handled IOs can be calculated with
		117	* `elem_bytes` for each IO. IOs in the remained bytes are not committed,
		118	* userspace has to check return value for dealing with partial committing
		119	* correctly.
		120	*/
		121	#define UBLK_U_IO_COMMIT_IO_CMDS \
		122	_IOWR('u', 0x26, struct ublk_batch_io)
		123
		124	/*
		125	* Fetch io commands to provided buffer in multishot style,
		126	* `IORING_URING_CMD_MULTISHOT` is required for this command.
		127	*/
		128	#define UBLK_U_IO_FETCH_IO_CMDS \
		129	_IOWR('u', 0x27, struct ublk_batch_io)
		130
106	/* only ABORT means that no re-fetch */	131	/* only ABORT means that no re-fetch */
107	#define UBLK_IO_RES_OK 0	132	#define UBLK_IO_RES_OK 0
108	#define UBLK_IO_RES_NEED_GET_DATA 1	133	#define UBLK_IO_RES_NEED_GET_DATA 1
@@ -134,6 +159,10 @@ · 25 unmodified lines
134	#define UBLKSRV_IO_BUF_TOTAL_BITS (UBLK_QID_OFF + UBLK_QID_BITS)	159	#define UBLKSRV_IO_BUF_TOTAL_BITS (UBLK_QID_OFF + UBLK_QID_BITS)
135	#define UBLKSRV_IO_BUF_TOTAL_SIZE (1ULL << UBLKSRV_IO_BUF_TOTAL_BITS)	160	#define UBLKSRV_IO_BUF_TOTAL_SIZE (1ULL << UBLKSRV_IO_BUF_TOTAL_BITS)
136		161
		162	/* Copy to/from request integrity buffer instead of data buffer */
		163	#define UBLK_INTEGRITY_FLAG_OFF 62
		164	#define UBLKSRV_IO_INTEGRITY_FLAG (1ULL << UBLK_INTEGRITY_FLAG_OFF)
		165
137	/*	166	/*
138	* ublk server can register data buffers for incoming I/O requests with a sparse	167	* ublk server can register data buffers for incoming I/O requests with a sparse
139	* io_uring buffer table. The request buffer can then be used as the data buffer	168	* io_uring buffer table. The request buffer can then be used as the data buffer
@@ -311,6 +340,36 @@ · 171 unmodified lines
311	*/	340	*/
312	#define UBLK_F_BUF_REG_OFF_DAEMON (1ULL << 14)	341	#define UBLK_F_BUF_REG_OFF_DAEMON (1ULL << 14)
313		342
		343	/*
		344	* Support the following commands for delivering & committing io command
		345	* in batch.
		346	*
		347	* - UBLK_U_IO_PREP_IO_CMDS
		348	* - UBLK_U_IO_COMMIT_IO_CMDS
		349	* - UBLK_U_IO_FETCH_IO_CMDS
		350	* - UBLK_U_IO_REGISTER_IO_BUF
		351	* - UBLK_U_IO_UNREGISTER_IO_BUF
		352	*
		353	* The existing UBLK_U_IO_FETCH_REQ, UBLK_U_IO_COMMIT_AND_FETCH_REQ and
		354	* UBLK_U_IO_NEED_GET_DATA uring_cmd are not supported for this feature.
		355	*/
		356	#define UBLK_F_BATCH_IO (1ULL << 15)
		357
		358	/*
		359	* ublk device supports requests with integrity/metadata buffer.
		360	* Requires UBLK_F_USER_COPY.
		361	*/
		362	#define UBLK_F_INTEGRITY (1ULL << 16)
		363
		364	/*
		365	* The device supports the UBLK_CMD_TRY_STOP_DEV command, which
		366	* allows stopping the device only if there are no openers.
		367	*/
		368	#define UBLK_F_SAFE_STOP_DEV (1ULL << 17)
		369
		370	/* Disable automatic partition scanning when device is started */
		371	#define UBLK_F_NO_AUTO_PART_SCAN (1ULL << 18)
		372
314	/* device state */	373	/* device state */
315	#define UBLK_S_DEV_DEAD 0	374	#define UBLK_S_DEV_DEAD 0
316	#define UBLK_S_DEV_LIVE 1	375	#define UBLK_S_DEV_LIVE 1
@@ -408,6 +467,8 @@ struct ublksrv_ctrl_dev_info { · 91 unmodified lines
408	* passed in.	467	* passed in.
409	*/	468	*/
410	#define UBLK_IO_F_NEED_REG_BUF (1U << 17)	469	#define UBLK_IO_F_NEED_REG_BUF (1U << 17)
		470	/* Request has an integrity data buffer */
		471	#define UBLK_IO_F_INTEGRITY (1UL << 18)
411		472
412	/*	473	/*
413	* io cmd is described by this structure, and stored in share memory, indexed	474	* io cmd is described by this structure, and stored in share memory, indexed
@@ -525,6 +586,51 @@ struct ublksrv_io_cmd { · 111 unmodified lines
525	};	586	};
526	};	587	};
527		588
		589	struct ublk_elem_header {
		590	__u16 tag; /* IO tag */
		591
		592	/*
		593	* Buffer index for incoming io command, only valid iff
		594	* UBLK_F_AUTO_BUF_REG is set
		595	*/
		596	__u16 buf_index;
		597	__s32 result; /* I/O completion result (commit only) */
		598	};
		599
		600	/*
		601	* uring_cmd buffer structure for batch commands
		602	*
		603	* buffer includes multiple elements, which number is specified by
		604	* `nr_elem`. Each element buffer is organized in the following order:
		605	*
		606	* struct ublk_elem_buffer {
		607	* // Mandatory fields (8 bytes)
		608	* struct ublk_elem_header header;
		609	*
		610	* // Optional fields (8 bytes each, included based on flags)
		611	*
		612	* // Buffer address (if UBLK_BATCH_F_HAS_BUF_ADDR) for copying data
		613	* // between ublk request and ublk server buffer
		614	* __u64 buf_addr;
		615	*
		616	* // returned Zone append LBA (if UBLK_BATCH_F_HAS_ZONE_LBA)
		617	* __u64 zone_lba;
		618	* }
		619	*
		620	* Used for `UBLK_U_IO_PREP_IO_CMDS` and `UBLK_U_IO_COMMIT_IO_CMDS`
		621	*/
		622	struct ublk_batch_io {
		623	__u16 q_id;
		624	#define UBLK_BATCH_F_HAS_ZONE_LBA (1 << 0)
		625	#define UBLK_BATCH_F_HAS_BUF_ADDR (1 << 1)
		626	#define UBLK_BATCH_F_AUTO_BUF_REG_FALLBACK (1 << 2)
		627	__u16 flags;
		628	__u16 nr_elem;
		629	__u8 elem_bytes;
		630	__u8 reserved;
		631	__u64 reserved2;
		632	};
		633
528	struct ublk_param_basic {	634	struct ublk_param_basic {
529	#define UBLK_ATTR_READ_ONLY (1 << 0)	635	#define UBLK_ATTR_READ_ONLY (1 << 0)
530	#define UBLK_ATTR_ROTATIONAL (1 << 1)	636	#define UBLK_ATTR_ROTATIONAL (1 << 1)
@@ -600,6 +706,17 @@ struct ublk_param_segment { · 69 unmodified lines
600	__u8 pad[2];	706	__u8 pad[2];
601	};	707	};
602		708
		709	struct ublk_param_integrity {
		710	__u32 flags; /* LBMD_PI_CAP_* from linux/fs.h */
		711	__u16 max_integrity_segments; /* 0 means no limit */
		712	__u8 interval_exp;
		713	__u8 metadata_size; /* UBLK_PARAM_TYPE_INTEGRITY requires nonzero */
		714	__u8 pi_offset;
		715	__u8 csum_type; /* LBMD_PI_CSUM_* from linux/fs.h */
		716	__u8 tag_size;
		717	__u8 pad[5];
		718	};
		719
603	struct ublk_params {	720	struct ublk_params {
604	/*	721	/*
605	* Total length of parameters, userspace has to set 'len' for both	722	* Total length of parameters, userspace has to set 'len' for both
@@ -614,6 +731,7 @@ struct ublk_params { · 8 unmodified lines
614	#define UBLK_PARAM_TYPE_ZONED (1 << 3)	731	#define UBLK_PARAM_TYPE_ZONED (1 << 3)
615	#define UBLK_PARAM_TYPE_DMA_ALIGN (1 << 4)	732	#define UBLK_PARAM_TYPE_DMA_ALIGN (1 << 4)
616	#define UBLK_PARAM_TYPE_SEGMENT (1 << 5)	733	#define UBLK_PARAM_TYPE_SEGMENT (1 << 5)
		734	#define UBLK_PARAM_TYPE_INTEGRITY (1 << 6) /* requires UBLK_F_INTEGRITY */
617	__u32 types; /* types of parameter included */	735	__u32 types; /* types of parameter included */
618		736
619	struct ublk_param_basic basic;	737	struct ublk_param_basic basic;
@@ -622,6 +740,7 @@ struct ublk_params { · 2 unmodified lines
622	struct ublk_param_zoned zoned;	740	struct ublk_param_zoned zoned;
623	struct ublk_param_dma_align dma;	741	struct ublk_param_dma_align dma;
624	struct ublk_param_segment seg;	742	struct ublk_param_segment seg;
		743	struct ublk_param_integrity integrity;
625	};	744	};
626		745
627	#endif	746	#endif

include/uapi/linux/v4l2-controls.h+63−0

@@ -1192,6 +1192,8 @@ enum v4l2_flash_strobe_source { · 1191 unmodified lines
1192		1192
1193	#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11)	1193	#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11)
1194	#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12)	1194	#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12)
		1195	#define V4L2_CID_FLASH_DURATION (V4L2_CID_FLASH_CLASS_BASE + 13)
		1196	#define V4L2_CID_FLASH_STROBE_OE (V4L2_CID_FLASH_CLASS_BASE + 14)
1195		1197
1196		1198
1197	/* JPEG-class control IDs */	1199	/* JPEG-class control IDs */
@@ -2099,6 +2101,8 @@ struct v4l2_ctrl_mpeg2_quantisation { · 901 unmodified lines
2099	#define V4L2_CID_STATELESS_HEVC_DECODE_MODE (V4L2_CID_CODEC_STATELESS_BASE + 405)	2101	#define V4L2_CID_STATELESS_HEVC_DECODE_MODE (V4L2_CID_CODEC_STATELESS_BASE + 405)
2100	#define V4L2_CID_STATELESS_HEVC_START_CODE (V4L2_CID_CODEC_STATELESS_BASE + 406)	2102	#define V4L2_CID_STATELESS_HEVC_START_CODE (V4L2_CID_CODEC_STATELESS_BASE + 406)
2101	#define V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS (V4L2_CID_CODEC_STATELESS_BASE + 407)	2103	#define V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS (V4L2_CID_CODEC_STATELESS_BASE + 407)
		2104	#define V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS (V4L2_CID_CODEC_STATELESS_BASE + 408)
		2105	#define V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS (V4L2_CID_CODEC_STATELESS_BASE + 409)
2102		2106
2103	enum v4l2_stateless_hevc_decode_mode {	2107	enum v4l2_stateless_hevc_decode_mode {
2104	V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED,	2108	V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED,
@@ -2554,6 +2558,65 @@ struct v4l2_ctrl_hevc_scaling_matrix { · 449 unmodified lines
2554	__u8 scaling_list_dc_coef_32x32[2];	2558	__u8 scaling_list_dc_coef_32x32[2];
2555	};	2559	};
2556		2560
		2561	#define V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED 0x1
		2562
		2563	/*
		2564	* struct v4l2_ctrl_hevc_ext_sps_st_rps - HEVC short term RPS parameters
		2565	*
		2566	* Dynamic size 1-dimension array for short term RPS. The number of elements
		2567	* is v4l2_ctrl_hevc_sps::num_short_term_ref_pic_sets. It can contain up to 65 elements.
		2568	*
		2569	* @delta_idx_minus1: Specifies the delta compare to the index. See details in section 7.4.8
		2570	* "Short-term reference picture set semantics" of the specification.
		2571	* @delta_rps_sign: Sign of the delta as specified in section 7.4.8 "Short-term reference picture
		2572	* set semantics" of the specification.
		2573	* @abs_delta_rps_minus1: Absolute delta RPS as specified in section 7.4.8 "Short-term reference
		2574	* picture set semantics" of the specification.
		2575	* @num_negative_pics: Number of short-term RPS entries that have picture order count values less
		2576	* than the picture order count value of the current picture.
		2577	* @num_positive_pics: Number of short-term RPS entries that have picture order count values
		2578	* greater than the picture order count value of the current picture.
		2579	* @used_by_curr_pic: Bit j specifies if short-term RPS j is used by the current picture.
		2580	* @use_delta_flag: Bit j equals to 1 specifies that the j-th entry in the source candidate
		2581	* short-term RPS is included in this candidate short-term RPS.
		2582	* @delta_poc_s0_minus1: Specifies the negative picture order count delta for the i-th entry in
		2583	* the short-term RPS. See details in section 7.4.8 "Short-term reference
		2584	* picture set semantics" of the specification.
		2585	* @delta_poc_s1_minus1: Specifies the positive picture order count delta for the i-th entry in
		2586	* the short-term RPS. See details in section 7.4.8 "Short-term reference
		2587	* picture set semantics" of the specification.
		2588	* @flags: See V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_{}
		2589	*/
		2590	struct v4l2_ctrl_hevc_ext_sps_st_rps {
		2591	__u8 delta_idx_minus1;
		2592	__u8 delta_rps_sign;
		2593	__u8 num_negative_pics;
		2594	__u8 num_positive_pics;
		2595	__u32 used_by_curr_pic;
		2596	__u32 use_delta_flag;
		2597	__u16 abs_delta_rps_minus1;
		2598	__u16 delta_poc_s0_minus1[16];
		2599	__u16 delta_poc_s1_minus1[16];
		2600	__u16 flags;
		2601	};
		2602
		2603	#define V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT 0x1
		2604
		2605	/*
		2606	* struct v4l2_ctrl_hevc_ext_sps_lt_rps - HEVC long term RPS parameters
		2607	*
		2608	* Dynamic size 1-dimension array for long term RPS. The number of elements
		2609	* is v4l2_ctrl_hevc_sps::num_long_term_ref_pics_sps. It can contain up to 65 elements.
		2610	*
		2611	* @lt_ref_pic_poc_lsb_sps: picture order count modulo MaxPicOrderCntLsb of the i-th candidate
		2612	* long-term reference picture.
		2613	* @flags: See V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_{}
		2614	*/
		2615	struct v4l2_ctrl_hevc_ext_sps_lt_rps {
		2616	__u16 lt_ref_pic_poc_lsb_sps;
		2617	__u16 flags;
		2618	};
		2619
2557	/* Stateless VP9 controls */	2620	/* Stateless VP9 controls */
2558		2621
2559	#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED 0x1	2622	#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED 0x1

include/uapi/linux/vbox_vmmdev_types.h+2−2

@@ -236,7 +236,7 @@ struct vmmdev_hgcm_function_parameter32 { · 235 unmodified lines
236	/** Relative to the request header. */	236	/** Relative to the request header. */
237	__u32 offset;	237	__u32 offset;
238	} page_list;	238	} page_list;
239	} u;	239	} __packed u;
240	} __packed;	240	} __packed;
241	VMMDEV_ASSERT_SIZE(vmmdev_hgcm_function_parameter32, 4 + 8);	241	VMMDEV_ASSERT_SIZE(vmmdev_hgcm_function_parameter32, 4 + 8);
242		242
@@ -251,7 +251,7 @@ struct vmmdev_hgcm_function_parameter64 { · 8 unmodified lines
251	union {	251	union {
252	__u64 phys_addr;	252	__u64 phys_addr;
253	__u64 linear_addr;	253	__u64 linear_addr;
254	} u;	254	} __packed u;
255	} __packed pointer;	255	} __packed pointer;
256	struct {	256	struct {
257	/** Size of the buffer described by the page list. */	257	/** Size of the buffer described by the page list. */

include/uapi/linux/vduse.h+80−5

 #define VDUSE_API_VERSION	0
+/* VQ groups and ASID support */
+#define VDUSE_API_VERSION_1	1
 /*
  * Get the version of VDUSE API that kernel supported (VDUSE_API_VERSION).
  * This is used for future extension.
  * @features: virtio features
  * @vq_num: the number of virtqueues
  * @vq_align: the allocation alignment of virtqueue's metadata
+ * @ngroups: number of vq groups that VDUSE device declares
+ * @nas: number of address spaces that VDUSE device declares
  * @reserved: for future use, needs to be initialized to zero
  * @config_size: the size of the configuration space
  * @config: the buffer of the configuration space
 	__u64 features;
 	__u32 vq_num;
 	__u32 vq_align;
-	__u32 reserved[13];
+	__u32 ngroups; /* if VDUSE_API_VERSION >= 1 */
+	__u32 nas; /* if VDUSE_API_VERSION >= 1 */
+	__u32 reserved[11];
 	__u32 config_size;
 	__u8 config[];
 };
  * struct vduse_vq_config - basic configuration of a virtqueue
  * @index: virtqueue index
  * @max_size: the max size of virtqueue
- * @reserved: for future use, needs to be initialized to zero
+ * @reserved1: for future use, needs to be initialized to zero
+ * @group: virtqueue group
+ * @reserved2: for future use, needs to be initialized to zero
  *
  * Structure used by VDUSE_VQ_SETUP ioctl to setup a virtqueue.
  */
 struct vduse_vq_config {
 	__u32 index;
 	__u16 max_size;
-	__u16 reserved[13];
+	__u16 reserved1;
+	__u32 group;
+	__u16 reserved2[10];
 };
 /*
 	__u16 last_used_idx;
 };
+/**
+ * struct vduse_vq_group_asid - virtqueue group ASID
+ * @group: Index of the virtqueue group
+ * @asid: Address space ID of the group
+ */
+struct vduse_vq_group_asid {
+	__u32 group;
+	__u32 asid;
+};
 /**
  * struct vduse_vq_info - information of a virtqueue
  * @index: virtqueue index
  * @uaddr: start address of userspace memory, it must be aligned to page size
  * @iova: start of the IOVA region
  * @size: size of the IOVA region
+ * @asid: Address space ID of the IOVA region
  * @reserved: for future use, needs to be initialized to zero
  *
  * Structure used by VDUSE_IOTLB_REG_UMEM and VDUSE_IOTLB_DEREG_UMEM
 	__u64 uaddr;
 	__u64 iova;
 	__u64 size;
-	__u64 reserved[3];
+	__u32 asid;
+	__u32 reserved[5];
 };
 /* Register userspace memory for IOVA regions */
  * @start: start of the IOVA region
  * @last: last of the IOVA region
  * @capability: capability of the IOVA region
+ * @asid: Address space ID of the IOVA region, only if device API version >= 1
  * @reserved: for future use, needs to be initialized to zero
  *
  * Structure used by VDUSE_IOTLB_GET_INFO ioctl to get information of
 	__u64 last;
 #define VDUSE_IOVA_CAP_UMEM (1 << 0)
 	__u64 capability;
-	__u64 reserved[3];
+	__u32 asid; /* Only if device API version >= 1 */
+	__u32 reserved[5];
 };
 /*
  */
 #define VDUSE_IOTLB_GET_INFO	_IOWR(VDUSE_BASE, 0x1a, struct vduse_iova_info)
+/**
+ * struct vduse_iotlb_entry_v2 - entry of IOTLB to describe one IOVA region
+ *
+ * @v1: the original vduse_iotlb_entry
+ * @asid: address space ID of the IOVA region
+ * @reserved: for future use, needs to be initialized to zero
+ *
+ * Structure used by VDUSE_IOTLB_GET_FD2 ioctl to find an overlapped IOVA region.
+ */
+struct vduse_iotlb_entry_v2 {
+	__u64 offset;
+	__u64 start;
+	__u64 last;
+	__u8 perm;
+	__u8 padding[7];
+	__u32 asid;
+	__u32 reserved[11];
+};
+/*
+ * Same as VDUSE_IOTLB_GET_FD but with vduse_iotlb_entry_v2 argument that
+ * support extra fields.
+ */
+#define VDUSE_IOTLB_GET_FD2	_IOWR(VDUSE_BASE, 0x1b, struct vduse_iotlb_entry_v2)
 /* The control messages definition for read(2)/write(2) on /dev/vduse/$NAME */
 /**
  * @VDUSE_SET_STATUS: set the device status
  * @VDUSE_UPDATE_IOTLB: Notify userspace to update the memory mapping for
  *                      specified IOVA range via VDUSE_IOTLB_GET_FD ioctl
+ * @VDUSE_SET_VQ_GROUP_ASID: Notify userspace to update the address space of a
+ *                           virtqueue group.
  */
 enum vduse_req_type {
 	VDUSE_GET_VQ_STATE,
 	VDUSE_SET_STATUS,
 	VDUSE_UPDATE_IOTLB,
+	VDUSE_SET_VQ_GROUP_ASID,
 };
 /**
 	__u64 last;
 };
+/**
+ * struct vduse_iova_range_v2 - IOVA range [start, last] if API_VERSION >= 1
+ * @start: start of the IOVA range
+ * @last: last of the IOVA range
+ * @asid: address space ID of the IOVA range
+ */
+struct vduse_iova_range_v2 {
+	__u64 start;
+	__u64 last;
+	__u32 asid;
+	__u32 padding;
+};
 /**
  * struct vduse_dev_request - control request
  * @type: request type
  * @vq_state: virtqueue state, only index field is available
  * @s: device status
  * @iova: IOVA range for updating
+ * @iova_v2: IOVA range for updating if API_VERSION >= 1
+ * @vq_group_asid: ASID of a virtqueue group
  * @padding: padding
  *
  * Structure used by read(2) on /dev/vduse/$NAME.
 		struct vduse_vq_state vq_state;
 		struct vduse_dev_status s;
 		struct vduse_iova_range iova;
+		/* Following members but padding exist only if vduse api
+		 * version >= 1
+		 */
+		struct vduse_iova_range_v2 iova_v2;
+		struct vduse_vq_group_asid vq_group_asid;
 		__u32 padding[32];
 	};
 };

include/uapi/linux/vfio.h+4−0

  * hwpt corresponding to the given pt_id.
  *
  * Return: 0 on success, -errno on failure.
+ *
+ * When a device is resetting, -EBUSY will be returned to reject any concurrent
+ * attachment to the resetting device itself or any sibling device in the IOMMU
+ * group having the resetting device.
  */
 struct vfio_device_attach_iommufd_pt {
 	__u32	argsz;

include/uapi/linux/videodev2.h+3−0

 #define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */
 #define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */
 #define V4L2_PIX_FMT_AV1_FRAME v4l2_fourcc('A', 'V', '1', 'F') /* AV1 parsed frame */
+#define V4L2_PIX_FMT_AV1      v4l2_fourcc('A', 'V', '0', '1') /* AV1 */
 #define V4L2_PIX_FMT_SPK      v4l2_fourcc('S', 'P', 'K', '0') /* Sorenson Spark */
 #define V4L2_PIX_FMT_RV30     v4l2_fourcc('R', 'V', '3', '0') /* RealVideo 8 */
 #define V4L2_PIX_FMT_RV40     v4l2_fourcc('R', 'V', '4', '0') /* RealVideo 9 & 10 */
 	V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS	= 0x0272,
 	V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX	= 0x0273,
 	V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS	= 0x0274,
+	V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS	= 0x0275,
+	V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS	= 0x0276,
 	V4L2_CTRL_TYPE_AV1_SEQUENCE	    = 0x280,
 	V4L2_CTRL_TYPE_AV1_TILE_GROUP_ENTRY = 0x281,

include/uapi/linux/virtio_ring.h+1−4

  * SUCH DAMAGE.
  *
  * Copyright Rusty Russell IBM Corporation 2007. */
-#ifndef __KERNEL__
-#include <stdint.h>
-#endif
 #include <linux/types.h>
 #include <linux/virtio_types.h>
 	vr->num = num;
 	vr->desc = p;
 	vr->avail = (struct vring_avail *)((char *)p + num * sizeof(struct vring_desc));
-	vr->used = (void *)(((uintptr_t)&vr->avail->ring[num] + sizeof(__virtio16)
+	vr->used = (void *)(((unsigned long)&vr->avail->ring[num] + sizeof(__virtio16)
 		+ align-1) & ~(align - 1));
 }

include/uapi/linux/vmclock-abi.h+20−0

@@ -115,6 +115,17 @@ struct vmclock_abi { · 114 unmodified lines
115	* bit again after the update, using the about-to-be-valid fields.	115	* bit again after the update, using the about-to-be-valid fields.
116	*/	116	*/
117	#define VMCLOCK_FLAG_TIME_MONOTONIC (1 << 7)	117	#define VMCLOCK_FLAG_TIME_MONOTONIC (1 << 7)
		118	/*
		119	* If the VM_GEN_COUNTER_PRESENT flag is set, the hypervisor will
		120	* bump the vm_generation_counter field every time the guest is
		121	* loaded from some save state (restored from a snapshot).
		122	*/
		123	#define VMCLOCK_FLAG_VM_GEN_COUNTER_PRESENT (1 << 8)
		124	/*
		125	* If the NOTIFICATION_PRESENT flag is set, the hypervisor will send
		126	* a notification every time it updates seq_count to a new even number.
		127	*/
		128	#define VMCLOCK_FLAG_NOTIFICATION_PRESENT (1 << 9)
118		129
119	__u8 pad[2];	130	__u8 pad[2];
120	__u8 clock_status;	131	__u8 clock_status;
@@ -177,6 +188,15 @@ struct vmclock_abi { · 56 unmodified lines
177	__le64 time_frac_sec; /* Units of 1/2^64 of a second */	188	__le64 time_frac_sec; /* Units of 1/2^64 of a second */
178	__le64 time_esterror_nanosec;	189	__le64 time_esterror_nanosec;
179	__le64 time_maxerror_nanosec;	190	__le64 time_maxerror_nanosec;
		191
		192	/*
		193	* This field changes to another non-repeating value when the guest
		194	* has been loaded from a snapshot. In addition to handling a
		195	* disruption in time (which will also be signalled through the
		196	* disruption_marker field), a guest may wish to discard UUIDs,
		197	* reset network connections, reseed entropy, etc.
		198	*/
		199	__le64 vm_generation_counter;
180	};	200	};
181		201
182	#endif /* __VMCLOCK_ABI_H__ */	202	#endif /* __VMCLOCK_ABI_H__ */

include/uapi/rdma/bnxt_re-abi.h+16−0

@@ -56,6 +56,7 @@ enum { · 55 unmodified lines
56	BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED = 0x08ULL,	56	BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED = 0x08ULL,
57	BNXT_RE_UCNTX_CMASK_POW2_DISABLED = 0x10ULL,	57	BNXT_RE_UCNTX_CMASK_POW2_DISABLED = 0x10ULL,
58	BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED = 0x40,	58	BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED = 0x40,
		59	BNXT_RE_UCNTX_CMASK_QP_RATE_LIMIT_ENABLED = 0x80ULL,
59	};	60	};
60		61
61	enum bnxt_re_wqe_mode {	62	enum bnxt_re_wqe_mode {
@@ -215,4 +216,19 @@ enum bnxt_re_toggle_mem_methods { · 153 unmodified lines
215	BNXT_RE_METHOD_GET_TOGGLE_MEM = (1U << UVERBS_ID_NS_SHIFT),	216	BNXT_RE_METHOD_GET_TOGGLE_MEM = (1U << UVERBS_ID_NS_SHIFT),
216	BNXT_RE_METHOD_RELEASE_TOGGLE_MEM,	217	BNXT_RE_METHOD_RELEASE_TOGGLE_MEM,
217	};	218	};
		219
		220	struct bnxt_re_packet_pacing_caps {
		221	__u32 qp_rate_limit_min;
		222	__u32 qp_rate_limit_max; /* In kbps */
		223	/* Corresponding bit will be set if qp type from
		224	* 'enum ib_qp_type' is supported, e.g.
		225	* supported_qpts \|= 1 << IB_QPT_RC
		226	*/
		227	__u32 supported_qpts;
		228	__u32 reserved;
		229	};
		230
		231	struct bnxt_re_query_device_ex_resp {
		232	struct bnxt_re_packet_pacing_caps packet_pacing_caps;
		233	};
218	#endif /* __BNXT_RE_UVERBS_ABI_H__*/	234	#endif /* __BNXT_RE_UVERBS_ABI_H__*/

include/uapi/rdma/ib_user_ioctl_cmds.h+16−0

 	UVERBS_OBJECT_COUNTERS,
 	UVERBS_OBJECT_ASYNC_EVENT,
 	UVERBS_OBJECT_DMAH,
+	UVERBS_OBJECT_DMABUF,
 };
 enum {
 	UVERBS_METHOD_QUERY_CONTEXT,
 	UVERBS_METHOD_QUERY_GID_TABLE,
 	UVERBS_METHOD_QUERY_GID_ENTRY,
+	UVERBS_METHOD_QUERY_PORT_SPEED,
 };
 enum uverbs_attrs_invoke_write_cmd_attr_ids {
 	UVERBS_ATTR_QUERY_PORT_RESP,
 };
+enum uverbs_attrs_query_port_speed_cmd_attr_ids {
+	UVERBS_ATTR_QUERY_PORT_SPEED_PORT_NUM,
+	UVERBS_ATTR_QUERY_PORT_SPEED_RESP,
+};
 enum uverbs_attrs_get_context_attr_ids {
 	UVERBS_ATTR_GET_CONTEXT_NUM_COMP_VECTORS,
 	UVERBS_ATTR_GET_CONTEXT_CORE_SUPPORT,
 	UVERBS_METHOD_DMAH_FREE,
 };
+enum uverbs_attrs_alloc_dmabuf_cmd_attr_ids {
+	UVERBS_ATTR_ALLOC_DMABUF_HANDLE,
+	UVERBS_ATTR_ALLOC_DMABUF_PGOFF,
+};
+enum uverbs_methods_dmabuf {
+	UVERBS_METHOD_DMABUF_ALLOC,
+};
 enum uverbs_attrs_reg_dm_mr_cmd_attr_ids {
 	UVERBS_ATTR_REG_DM_MR_HANDLE,
 	UVERBS_ATTR_REG_DM_MR_OFFSET,

include/uapi/rdma/mana-abi.h+3−0

@@ -17,6 +17,9 @@ · 16 unmodified lines
17	#define MANA_IB_UVERBS_ABI_VERSION 1	17	#define MANA_IB_UVERBS_ABI_VERSION 1
18		18
19	enum mana_ib_create_cq_flags {	19	enum mana_ib_create_cq_flags {
		20	/* Reserved for backward compatibility. Legacy
		21	* kernel versions use it to create CQs in RNIC
		22	*/
20	MANA_IB_CREATE_RNIC_CQ = 1 << 0,	23	MANA_IB_CREATE_RNIC_CQ = 1 << 0,
21	};	24	};
22		25

include/uapi/scsi/scsi_bsg_ufs.h+8−9

@@ -94,16 +94,15 @@ struct utp_upiu_header { · 93 unmodified lines
94	};	94	};
95		95
96	/**	96	/**
97	* struct utp_upiu_query - upiu request buffer structure for	97	* struct utp_upiu_query - QUERY REQUEST UPIU structure.
98	* query request.	98	* @opcode: query function to perform B-0
99	* @opcode: command to perform B-0	99	* @idn: descriptor or attribute identification number B-1
100	* @idn: a value that indicates the particular type of data B-1	100	* @index: Index that further identifies which data to access B-2
101	* @index: Index to further identify data B-2	101	* @selector: Index that further identifies which data to access B-3
102	* @selector: Index to further identify data B-3
103	* @reserved_osf: spec reserved field B-4,5	102	* @reserved_osf: spec reserved field B-4,5
104	* @length: number of descriptor bytes to read/write B-6,7	103	* @length: number of descriptor bytes to read or write B-6,7
105	* @value: Attribute value to be written DW-5	104	* @value: if @opcode == UPIU_QUERY_OPCODE_WRITE_ATTR, the value to be written B-6,7
106	* @reserved: spec reserved DW-6,7	105	* @reserved: reserved for future use DW-6,7
107	*/	106	*/
108	struct utp_upiu_query {	107	struct utp_upiu_query {
109	__u8 opcode;	108	__u8 opcode;

include/uapi/sound/sof/tokens.h+6−0

 #define SOF_TKN_SCHED_LP_MODE			207
 #define SOF_TKN_SCHED_MEM_USAGE			208
 #define SOF_TKN_SCHED_USE_CHAIN_DMA		209
+#define SOF_TKN_SCHED_KCPS			210
+#define SOF_TKN_SCHED_DIRECTION			211
+#define SOF_TKN_SCHED_DIRECTION_VALID		212
 /* volume */
 #define SOF_TKN_VOLUME_RAMP_STEP_TYPE		250
 #define SOF_TKN_COMP_NO_WNAME_IN_KCONTROL_NAME	417
 #define SOF_TKN_COMP_SCHED_DOMAIN		418
+#define SOF_TKN_COMP_DOMAIN_ID			419
+#define SOF_TKN_COMP_HEAP_BYTES_REQUIREMENT	420
+#define SOF_TKN_COMP_STACK_BYTES_REQUIREMENT	421
 /* SSP */
 #define SOF_TKN_INTEL_SSP_CLKS_CONTROL		500