Pull cxl updates from Dan Williams: "Compute Express Link (CXL) updates for 6.0: - Introduce a 'struct cxl_region' object with support for provisioning and assembling persistent memory regions. - Introduce alloc_free_mem_region() to accompany the existing request_free_mem_region() as a method to allocate physical memory capacity out of an existing resource. - Export insert_resource_expand_to_fit() for the CXL subsystem to late-publish CXL platform windows in iomem_resource. - Add a polled mode PCI DOE (Data Object Exchange) driver service and use it in cxl_pci to retrieve the CDAT (Coherent Device Attribute Table)" * tag 'cxl-for-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (74 commits) cxl/hdm: Fix skip allocations vs multiple pmem allocations cxl/region: Disallow region granularity != window granularity cxl/region: Fix x1 interleave to greater than x1 interleave routing cxl/region: Move HPA setup to cxl_region_attach() cxl/region: Fix decoder interleave programming Documentation: cxl: remove dangling kernel-doc reference cxl/region: describe targets and nr_targets members of cxl_region_params cxl/regions: add padding for cxl_rr_ep_add nested lists cxl/region: Fix IS_ERR() vs NULL check cxl/region: Fix region reference target accounting cxl/region: Fix region commit uninitialized variable warning cxl/region: Fix port setup uninitialized variable warnings cxl/region: Stop initializing interleave granularity cxl/hdm: Fix DPA reservation vs cxl_endpoint_decoder lifetime cxl/acpi: Minimize granularity for x1 interleaves cxl/region: Delete 'region' attribute from root decoders cxl/acpi: Autoload driver for 'cxl_acpi' test devices cxl/region: decrement ->nr_targets on error in cxl_region_attach() cxl/region: prevent underflow in ways_to_cxl() cxl/region: uninitialized variable in alloc_hpa() ...
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| @@ -737,7 +737,8 @@ · 736 unmodified lines | |||
| 737 | #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ | 737 | #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ |
| 738 | #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ | 738 | #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ |
| 739 | #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ | 739 | #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ |
| 740 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT | 740 | #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ |
| 741 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE | ||
| 741 | 742 | ||
| 742 | #define PCI_EXT_CAP_DSN_SIZEOF 12 | 743 | #define PCI_EXT_CAP_DSN_SIZEOF 12 |
| 743 | #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 | 744 | #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 |
| @@ -1103,4 +1104,30 @@ · 359 unmodified lines | |||
| 1103 | #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 | 1104 | #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 |
| 1104 | #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 | 1105 | #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 |
| 1105 | 1106 | ||
| 1107 | /* Data Object Exchange */ | ||
| 1108 | #define PCI_DOE_CAP 0x04 /* DOE Capabilities Register */ | ||
| 1109 | #define PCI_DOE_CAP_INT_SUP 0x00000001 /* Interrupt Support */ | ||
| 1110 | #define PCI_DOE_CAP_INT_MSG_NUM 0x00000ffe /* Interrupt Message Number */ | ||
| 1111 | #define PCI_DOE_CTRL 0x08 /* DOE Control Register */ | ||
| 1112 | #define PCI_DOE_CTRL_ABORT 0x00000001 /* DOE Abort */ | ||
| 1113 | #define PCI_DOE_CTRL_INT_EN 0x00000002 /* DOE Interrupt Enable */ | ||
| 1114 | #define PCI_DOE_CTRL_GO 0x80000000 /* DOE Go */ | ||
| 1115 | #define PCI_DOE_STATUS 0x0c /* DOE Status Register */ | ||
| 1116 | #define PCI_DOE_STATUS_BUSY 0x00000001 /* DOE Busy */ | ||
| 1117 | #define PCI_DOE_STATUS_INT_STATUS 0x00000002 /* DOE Interrupt Status */ | ||
| 1118 | #define PCI_DOE_STATUS_ERROR 0x00000004 /* DOE Error */ | ||
| 1119 | #define PCI_DOE_STATUS_DATA_OBJECT_READY 0x80000000 /* Data Object Ready */ | ||
| 1120 | #define PCI_DOE_WRITE 0x10 /* DOE Write Data Mailbox Register */ | ||
| 1121 | #define PCI_DOE_READ 0x14 /* DOE Read Data Mailbox Register */ | ||
| 1122 | |||
| 1123 | /* DOE Data Object - note not actually registers */ | ||
| 1124 | #define PCI_DOE_DATA_OBJECT_HEADER_1_VID 0x0000ffff | ||
| 1125 | #define PCI_DOE_DATA_OBJECT_HEADER_1_TYPE 0x00ff0000 | ||
| 1126 | #define PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH 0x0003ffff | ||
| 1127 | |||
| 1128 | #define PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX 0x000000ff | ||
| 1129 | #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID 0x0000ffff | ||
| 1130 | #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000 | ||
| 1131 | #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 | ||
| 1132 | |||
| 1106 | #endif /* LINUX_PCI_REGS_H */ | 1133 | #endif /* LINUX_PCI_REGS_H */ |