Merge tag 'gpio-updates-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux

Pull gpio updates from Bartosz Golaszewski: "The gpio-sim module is back, this time without any changes to configfs. This results in a less elegant user-space interface but I never got any follow-up on the committable items and didn't want to delay this module for several more months. Other than that we have support for several new models and some support going away. We started working on converting GPIO drivers to using fwnode exclusively in order to limit references to OF symbols to gpiolib-of.c exclusively. We also have regular tweaks and improvements all over the place. Summary: - new testing module: gpio-sim that is scheduled to replace gpio-mockup - initial changes aiming at converting all GPIO drivers to using the fwnode interface and limiting any references to OF symbols to gpiolib-of.c - add support for Tegra234 and Tegra241 to gpio-tegra186 - add support for new models (SSD201 and SSD202D) to gpio-msc313 - add basic support for interrupts to gpio-aggregator - add support for AMDIF031 HID device to gpio-amdpt - drop support for unused platforms in gpio-xlp - cleanup leftovers from the removal of the legacy Samsung Exynos GPIO driver - use raw spinlocks in gpio-aspeed and gpio-aspeed-sgpio to make PREEMPT_RT happy - generalize the common 'ngpios' device property by reading it in the core gpiolib code so that we can remove duplicate reads from drivers - allow line names from device properties to override names set by drivers - code shrink in gpiod_add_lookup_table() - add new model to the DT bindings for gpio-vf610 - convert DT bindings for tegra devices to YAML - improvements to interrupt handling in gpio-rcar and gpio-rockchip - updates to intel drivers from Andy (details in the merge commit) - some minor tweaks, improvements and coding-style fixes all around the subsystem" * tag 'gpio-updates-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (59 commits) gpio: rcar: Propagate errors from devm_request_irq() gpio: rcar: Use platform_get_irq() to get the interrupt gpio: ts5500: Use platform_get_irq() to get the interrupt gpio: dwapb: Switch to use fwnode instead of of_node gpiolib: acpi: make fwnode take precedence in struct gpio_chip dt-bindings: gpio: samsung: drop unused bindings gpio: max3191x: Use bitmap_free() to free bitmap gpio: regmap: Switch to use fwnode instead of of_node gpio: tegra186: Add support for Tegra241 dt-bindings: gpio: Add Tegra241 support gpio: brcmstb: Use local variable to access OF node gpio: Remove unused local OF node pointers gpio: sim: add missing fwnode_handle_put() in gpio_sim_probe() gpio: msc313: Add support for SSD201 and SSD202D gpio: msc313: Code clean ups dt-bindings: gpio: msc313: Add offsets for ssd20xd dt-bindings: gpio: msc313: Add compatible for ssd20xd gpio: sim: fix uninitialized ret variable gpio: Propagate firmware node from a parent device gpio: Setup parent device and get rid of unnecessary of_node assignment ...

Linus Torvalds committed 4 years ago

Commit c288ea62 parents 1151e3c ffe31c975 files · +3415 −634Browse files

Unified · Split

75 files

Documentation/admin-guide/gpio/gpio-sim.rst +134 −0
Documentation/devicetree/bindings/gpio/gpio-samsung.txt +0 −41
Documentation/devicetree/bindings/gpio/gpio-vf610.yaml +3 −0
Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml +3 −1
Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt +0 −165
Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml +214 −0
Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt +0 −40
Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.yaml +110 −0
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +2 −1
drivers/gpio/Kconfig +12 −6
drivers/gpio/Makefile +1 −0
drivers/gpio/gpio-adnp.c +0 −1
drivers/gpio/gpio-aggregator.c +10 −1
drivers/gpio/gpio-amdpt.c +6 −6
drivers/gpio/gpio-arizona.c +2 −3
drivers/gpio/gpio-aspeed-sgpio.c +16 −16
drivers/gpio/gpio-aspeed.c +26 −26
drivers/gpio/gpio-bcm-kona.c +1 −1
drivers/gpio/gpio-bd71828.c +0 −1
drivers/gpio/gpio-brcmstb.c +1 −2
drivers/gpio/gpio-creg-snps.c +1 −1
drivers/gpio/gpio-davinci.c +0 −1
drivers/gpio/gpio-dwapb.c +7 −8
drivers/gpio/gpio-eic-sprd.c +0 −1
drivers/gpio/gpio-em.c +0 −1
drivers/gpio/gpio-ge.c +0 −1
drivers/gpio/gpio-grgpio.c +0 −1
drivers/gpio/gpio-gw-pld.c +0 −2
drivers/gpio/gpio-lpc32xx.c +1 −1
drivers/gpio/gpio-max3191x.c +1 −1
drivers/gpio/gpio-ml-ioh.c +26 −26
drivers/gpio/gpio-msc313.c +262 −4
drivers/gpio/gpio-mt7621.c +2 −4
drivers/gpio/gpio-mvebu.c +0 −1
drivers/gpio/gpio-omap.c +0 −3
drivers/gpio/gpio-palmas.c +1 −3
drivers/gpio/gpio-pch.c +20 −22
drivers/gpio/gpio-pmic-eic-sprd.c +0 −1
drivers/gpio/gpio-pxa.c +3 −5
drivers/gpio/gpio-raspberrypi-exp.c +0 −1
drivers/gpio/gpio-rcar.c +6 −10
drivers/gpio/gpio-rda.c +0 −3
drivers/gpio/gpio-regmap.c +1 −5
drivers/gpio/gpio-rockchip.c +18 −3
drivers/gpio/gpio-sama5d2-piobu.c +0 −1
drivers/gpio/gpio-sch.c +1 −1
drivers/gpio/gpio-sim.c +1592 −0
drivers/gpio/gpio-sprd.c +0 −1
drivers/gpio/gpio-sta2x11.c +1 −1
drivers/gpio/gpio-stmpe.c +0 −1
drivers/gpio/gpio-tc3589x.c +0 −1
drivers/gpio/gpio-tegra186.c +128 −1
drivers/gpio/gpio-tps65218.c +0 −3
drivers/gpio/gpio-tps6586x.c +2 −3
drivers/gpio/gpio-tps65910.c +3 −3
drivers/gpio/gpio-ts5500.c +4 −7
drivers/gpio/gpio-twl6040.c +2 −3
drivers/gpio/gpio-vf610.c +0 −1
drivers/gpio/gpio-wm831x.c +2 −3
drivers/gpio/gpio-xlp.c +11 −136
drivers/gpio/gpiolib-acpi.c +25 −29
drivers/gpio/gpiolib-of.c +3 −0
drivers/gpio/gpiolib.c +58 −15
include/dt-bindings/gpio/msc313-gpio.h +71 −0
include/dt-bindings/gpio/tegra234-gpio.h +63 −0
include/dt-bindings/gpio/tegra241-gpio.h +42 −0
include/linux/gpio/consumer.h +0 −2
include/linux/gpio/driver.h +2 −0
include/linux/gpio/machine.h +2 −0
tools/testing/selftests/gpio/.gitignore +2 −0
tools/testing/selftests/gpio/Makefile +2 −2
tools/testing/selftests/gpio/config +1 −0
tools/testing/selftests/gpio/gpio-chip-info.c +57 −0
tools/testing/selftests/gpio/gpio-line-name.c +55 −0
tools/testing/selftests/gpio/gpio-sim.sh +396 −0

Documentation/admin-guide/gpio/gpio-sim.rst+134−0

@@ -0,0 +1,134 @@
	1	+.. SPDX-License-Identifier: GPL-2.0-or-later
	2	+
	3	+Configfs GPIO Simulator
	4	+=======================
	5	+
	6	+The configfs GPIO Simulator (gpio-sim) provides a way to create simulated GPIO
	7	+chips for testing purposes. The lines exposed by these chips can be accessed
	8	+using the standard GPIO character device interface as well as manipulated
	9	+using sysfs attributes.
	10	+
	11	+Creating simulated chips
	12	+------------------------
	13	+
	14	+The gpio-sim module registers a configfs subsystem called ``'gpio-sim'``. For
	15	+details of the configfs filesystem, please refer to the configfs documentation.
	16	+
	17	+The user can create a hierarchy of configfs groups and items as well as modify
	18	+values of exposed attributes. Once the chip is instantiated, this hierarchy
	19	+will be translated to appropriate device properties. The general structure is:
	20	+
	21	+Group: ``/config/gpio-sim``
	22	+
	23	+This is the top directory of the gpio-sim configfs tree.
	24	+
	25	+Group: ``/config/gpio-sim/gpio-device``
	26	+
	27	+Attribute: ``/config/gpio-sim/gpio-device/dev_name``
	28	+
	29	+Attribute: ``/config/gpio-sim/gpio-device/live``
	30	+
	31	+This is a directory representing a GPIO platform device. The ``'dev_name'``
	32	+attribute is read-only and allows the user-space to read the platform device
	33	+name (e.g. ``'gpio-sim.0'``). The ``'live'`` attribute allows to trigger the
	34	+actual creation of the device once it's fully configured. The accepted values
	35	+are: ``'1'`` to enable the simulated device and ``'0'`` to disable and tear
	36	+it down.
	37	+
	38	+Group: ``/config/gpio-sim/gpio-device/gpio-bankX``
	39	+
	40	+Attribute: ``/config/gpio-sim/gpio-device/gpio-bankX/chip_name``
	41	+
	42	+Attribute: ``/config/gpio-sim/gpio-device/gpio-bankX/num_lines``
	43	+
	44	+This group represents a bank of GPIOs under the top platform device. The
	45	+``'chip_name'`` attribute is read-only and allows the user-space to read the
	46	+device name of the bank device. The ``'num_lines'`` attribute allows to specify
	47	+the number of lines exposed by this bank.
	48	+
	49	+Group: ``/config/gpio-sim/gpio-device/gpio-bankX/lineY``
	50	+
	51	+Attribute: ``/config/gpio-sim/gpio-device/gpio-bankX/lineY/name``
	52	+
	53	+This group represents a single line at the offset Y. The 'name' attribute
	54	+allows to set the line name as represented by the 'gpio-line-names' property.
	55	+
	56	+Item: ``/config/gpio-sim/gpio-device/gpio-bankX/lineY/hog``
	57	+
	58	+Attribute: ``/config/gpio-sim/gpio-device/gpio-bankX/lineY/hog/name``
	59	+
	60	+Attribute: ``/config/gpio-sim/gpio-device/gpio-bankX/lineY/hog/direction``
	61	+
	62	+This item makes the gpio-sim module hog the associated line. The ``'name'``
	63	+attribute specifies the in-kernel consumer name to use. The ``'direction'``
	64	+attribute specifies the hog direction and must be one of: ``'input'``,
	65	+``'output-high'`` and ``'output-low'``.
	66	+
	67	+Inside each bank directory, there's a set of attributes that can be used to
	68	+configure the new chip. Additionally the user can ``mkdir()`` subdirectories
	69	+inside the chip's directory that allow to pass additional configuration for
	70	+specific lines. The name of those subdirectories must take the form of:
	71	+``'line<offset>'`` (e.g. ``'line0'``, ``'line20'``, etc.) as the name will be
	72	+used by the module to assign the config to the specific line at given offset.
	73	+
	74	+Once the confiuration is complete, the ``'live'`` attribute must be set to 1 in
	75	+order to instantiate the chip. It can be set back to 0 to destroy the simulated
	76	+chip. The module will synchronously wait for the new simulated device to be
	77	+successfully probed and if this doesn't happen, writing to ``'live'`` will
	78	+result in an error.
	79	+
	80	+Simulated GPIO chips can also be defined in device-tree. The compatible string
	81	+must be: ``"gpio-simulator"``. Supported properties are:
	82	+
	83	+ ``"gpio-sim,label"`` - chip label
	84	+
	85	+Other standard GPIO properties (like ``"gpio-line-names"``, ``"ngpios"`` or
	86	+``"gpio-hog"``) are also supported. Please refer to the GPIO documentation for
	87	+details.
	88	+
	89	+An example device-tree code defining a GPIO simulator:
	90	+
	91	+.. code-block :: none
	92	+
	93	+ gpio-sim {
	94	+ compatible = "gpio-simulator";
	95	+
	96	+ bank0 {
	97	+ gpio-controller;
	98	+ #gpio-cells = <2>;
	99	+ ngpios = <16>;
	100	+ gpio-sim,label = "dt-bank0";
	101	+ gpio-line-names = "", "sim-foo", "", "sim-bar";
	102	+ };
	103	+
	104	+ bank1 {
	105	+ gpio-controller;
	106	+ #gpio-cells = <2>;
	107	+ ngpios = <8>;
	108	+ gpio-sim,label = "dt-bank1";
	109	+
	110	+ line3 {
	111	+ gpio-hog;
	112	+ gpios = <3 0>;
	113	+ output-high;
	114	+ line-name = "sim-hog-from-dt";
	115	+ };
	116	+ };
	117	+ };
	118	+
	119	+Manipulating simulated lines
	120	+----------------------------
	121	+
	122	+Each simulated GPIO chip creates a separate sysfs group under its device
	123	+directory for each exposed line
	124	+(e.g. ``/sys/devices/platform/gpio-sim.X/gpiochipY/``). The name of each group
	125	+is of the form: ``'sim_gpioX'`` where X is the offset of the line. Inside each
	126	+group there are two attibutes:
	127	+
	128	+ ``pull`` - allows to read and set the current simulated pull setting for
	129	+ every line, when writing the value must be one of: ``'pull-up'``,
	130	+ ``'pull-down'``
	131	+
	132	+ ``value`` - allows to read the current value of the line which may be
	133	+ different from the pull if the line is being driven from
	134	+ user-space

Documentation/devicetree/bindings/gpio/gpio-samsung.txt+0−41

@@ -1,41 +0,0 @@
1		−Samsung Exynos4 GPIO Controller
2		−
3		−Required properties:
4		−- compatible: Compatible property value should be "samsung,exynos4-gpio>".
5		−
6		−- reg: Physical base address of the controller and length of memory mapped
7		− region.
8		−
9		−- #gpio-cells: Should be 4. The syntax of the gpio specifier used by client nodes
10		− should be the following with values derived from the SoC user manual.
11		− <[phandle of the gpio controller node]
12		− [pin number within the gpio controller]
13		− [mux function]
14		− [flags and pull up/down]
15		− [drive strength]>
16		−
17		− Values for gpio specifier:
18		− - Pin number: is a value between 0 to 7.
19		− - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled.
20		− 1 - Pull Down Enabled.
21		− 3 - Pull Up Enabled.
22		− Bit 16 (0x00010000) - Input is active low.
23		− - Drive Strength: 0 - 1x,
24		− 1 - 3x,
25		− 2 - 2x,
26		− 3 - 4x
27		−
28		−- gpio-controller: Specifies that the node is a gpio controller.
29		−- #address-cells: should be 1.
30		−- #size-cells: should be 1.
31		−
32		−Example:
33		−
34		− gpa0: gpio-controller@11400000 {
35		− #address-cells = <1>;
36		− #size-cells = <1>;
37		− compatible = "samsung,exynos4-gpio";
38		− reg = <0x11400000 0x20>;
39		− #gpio-cells = <4>;
40		− gpio-controller;
41		− };

Documentation/devicetree/bindings/gpio/gpio-vf610.yaml+3−0

@@ -24,6 +24,9 @@ properties: · 23 unmodified lines
24	24	- items:
25	25	- const: fsl,imx7ulp-gpio
26	26	- const: fsl,vf610-gpio
	27	+ - items:
	28	+ - const: fsl,imx8ulp-gpio
	29	+ - const: fsl,imx7ulp-gpio
27	30
28	31	reg:
29	32	description: The first reg tuple represents the PORT module, the second tuple

Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml+3−1

@@ -14,7 +14,9 @@ properties: · 13 unmodified lines
14	14	pattern: "^gpio@[0-9a-f]+$"
15	15
16	16	compatible:
17		− const: mstar,msc313-gpio
	17	+ enum:
	18	+ - mstar,msc313-gpio
	19	+ - sstar,ssd20xd-gpio
18	20
19	21	reg:
20	22	maxItems: 1

Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt+0−165

@@ -1,165 +0,0 @@
1		−NVIDIA Tegra186 GPIO controllers
2		−
3		−Tegra186 contains two GPIO controllers; a main controller and an "AON"
4		−controller. This binding document applies to both controllers. The register
5		−layouts for the controllers share many similarities, but also some significant
6		−differences. Hence, this document describes closely related but different
7		−bindings and compatible values.
8		−
9		−The Tegra186 GPIO controller allows software to set the IO direction of, and
10		−read/write the value of, numerous GPIO signals. Routing of GPIO signals to
11		−package balls is under the control of a separate pin controller HW block. Two
12		−major sets of registers exist:
13		−
14		−a) Security registers, which allow configuration of allowed access to the GPIO
15		−register set. These registers exist in a single contiguous block of physical
16		−address space. The size of this block, and the security features available,
17		−varies between the different GPIO controllers.
18		−
19		−Access to this set of registers is not necessary in all circumstances. Code
20		−that wishes to configure access to the GPIO registers needs access to these
21		−registers to do so. Code which simply wishes to read or write GPIO data does not
22		−need access to these registers.
23		−
24		−b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
25		−controllers, these registers are exposed via multiple "physical aliases" in
26		−address space, each of which access the same underlying state. See the hardware
27		−documentation for rationale. Any particular GPIO client is expected to access
28		−just one of these physical aliases.
29		−
30		−Tegra HW documentation describes a unified naming convention for all GPIOs
31		−implemented by the SoC. Each GPIO is assigned to a port, and a port may control
32		−a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
33		−name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
34		−or GPIO_PCC3.
35		−
36		−The number of ports implemented by each GPIO controller varies. The number of
37		−implemented GPIOs within each port varies. GPIO registers within a controller
38		−are grouped and laid out according to the port they affect.
39		−
40		−The mapping from port name to the GPIO controller that implements that port, and
41		−the mapping from port name to register offset within a controller, are both
42		−extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43		−describes the port-level mapping. In that file, the naming convention for ports
44		−matches the HW documentation. The values chosen for the names are alphabetically
45		−sorted within a particular controller. Drivers need to map between the DT GPIO
46		−IDs and HW register offsets using a lookup table.
47		−
48		−Each GPIO controller can generate a number of interrupt signals. Each signal
49		−represents the aggregate status for all GPIOs within a set of ports. Thus, the
50		−number of interrupt signals generated by a controller varies as a rough function
51		−of the number of ports it implements. Note that the HW documentation refers to
52		−both the overall controller HW module and the sets-of-ports as "controllers".
53		−
54		−Each GPIO controller in fact generates multiple interrupts signals for each set
55		−of ports. Each GPIO may be configured to feed into a specific one of the
56		−interrupt signals generated by a set-of-ports. The intent is for each generated
57		−signal to be routed to a different CPU, thus allowing different CPUs to each
58		−handle subsets of the interrupts within a port. The status of each of these
59		−per-port-set signals is reported via a separate register. Thus, a driver needs
60		−to know which status register to observe. This binding currently defines no
61		−configuration mechanism for this. By default, drivers should use register
62		−GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
63		−define a property to configure this.
64		−
65		−Required properties:
66		−- compatible
67		− Array of strings.
68		− One of:
69		− - "nvidia,tegra186-gpio".
70		− - "nvidia,tegra186-gpio-aon".
71		− - "nvidia,tegra194-gpio".
72		− - "nvidia,tegra194-gpio-aon".
73		−- reg-names
74		− Array of strings.
75		− Contains a list of names for the register spaces described by the reg
76		− property. May contain the following entries, in any order:
77		− - "gpio": Mandatory. GPIO control registers. This may cover either:
78		− a) The single physical alias that this OS should use.
79		− b) All physical aliases that exist in the controller. This is
80		− appropriate when the OS is responsible for managing assignment of
81		− the physical aliases.
82		− - "security": Optional. Security configuration registers.
83		− Users of this binding MUST look up entries in the reg property by name,
84		− using this reg-names property to do so.
85		−- reg
86		− Array of (physical base address, length) tuples.
87		− Must contain one entry per entry in the reg-names property, in a matching
88		− order.
89		−- interrupts
90		− Array of interrupt specifiers.
91		− The interrupt outputs from the HW block, one per set of ports, in the
92		− order the HW manual describes them. The number of entries required varies
93		− depending on compatible value:
94		− - "nvidia,tegra186-gpio": 6 entries.
95		− - "nvidia,tegra186-gpio-aon": 1 entry.
96		− - "nvidia,tegra194-gpio": 6 entries.
97		− - "nvidia,tegra194-gpio-aon": 1 entry.
98		−- gpio-controller
99		− Boolean.
100		− Marks the device node as a GPIO controller/provider.
101		−- #gpio-cells
102		− Single-cell integer.
103		− Must be <2>.
104		− Indicates how many cells are used in a consumer's GPIO specifier.
105		− In the specifier:
106		− - The first cell is the pin number.
107		− See <dt-bindings/gpio/tegra186-gpio.h>.
108		− - The second cell contains flags:
109		− - Bit 0 specifies polarity
110		− - 0: Active-high (normal).
111		− - 1: Active-low (inverted).
112		−- interrupt-controller
113		− Boolean.
114		− Marks the device node as an interrupt controller/provider.
115		−- #interrupt-cells
116		− Single-cell integer.
117		− Must be <2>.
118		− Indicates how many cells are used in a consumer's interrupt specifier.
119		− In the specifier:
120		− - The first cell is the GPIO number.
121		− See <dt-bindings/gpio/tegra186-gpio.h>.
122		− - The second cell is contains flags:
123		− - Bits [3:0] indicate trigger type and level:
124		− - 1: Low-to-high edge triggered.
125		− - 2: High-to-low edge triggered.
126		− - 4: Active high level-sensitive.
127		− - 8: Active low level-sensitive.
128		− Valid combinations are 1, 2, 3, 4, 8.
129		−
130		−Example:
131		−
132		−#include <dt-bindings/interrupt-controller/irq.h>
133		−
134		−gpio@2200000 {
135		− compatible = "nvidia,tegra186-gpio";
136		− reg-names = "security", "gpio";
137		− reg =
138		− <0x0 0x2200000 0x0 0x10000>,
139		− <0x0 0x2210000 0x0 0x10000>;
140		− interrupts =
141		− <0 47 IRQ_TYPE_LEVEL_HIGH>,
142		− <0 50 IRQ_TYPE_LEVEL_HIGH>,
143		− <0 53 IRQ_TYPE_LEVEL_HIGH>,
144		− <0 56 IRQ_TYPE_LEVEL_HIGH>,
145		− <0 59 IRQ_TYPE_LEVEL_HIGH>,
146		− <0 180 IRQ_TYPE_LEVEL_HIGH>;
147		− gpio-controller;
148		− #gpio-cells = <2>;
149		− interrupt-controller;
150		− #interrupt-cells = <2>;
151		−};
152		−
153		−gpio@c2f0000 {
154		− compatible = "nvidia,tegra186-gpio-aon";
155		− reg-names = "security", "gpio";
156		− reg =
157		− <0x0 0xc2f0000 0x0 0x1000>,
158		− <0x0 0xc2f1000 0x0 0x1000>;
159		− interrupts =
160		− <0 60 IRQ_TYPE_LEVEL_HIGH>;
161		− gpio-controller;
162		− #gpio-cells = <2>;
163		− interrupt-controller;
164		− #interrupt-cells = <2>;
165		−};

Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml+214−0

@@ -0,0 +1,214 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
	8	+
	9	+maintainers:
	10	+ - Thierry Reding <thierry.reding@gmail.com>
	11	+ - Jon Hunter <jonathanh@nvidia.com>
	12	+
	13	+description: \|
	14	+ Tegra186 contains two GPIO controllers; a main controller and an "AON"
	15	+ controller. This binding document applies to both controllers. The register
	16	+ layouts for the controllers share many similarities, but also some
	17	+ significant differences. Hence, this document describes closely related but
	18	+ different bindings and compatible values.
	19	+
	20	+ The Tegra186 GPIO controller allows software to set the IO direction of,
	21	+ and read/write the value of, numerous GPIO signals. Routing of GPIO signals
	22	+ to package balls is under the control of a separate pin controller hardware
	23	+ block. Two major sets of registers exist:
	24	+
	25	+ a) Security registers, which allow configuration of allowed access to the
	26	+ GPIO register set. These registers exist in a single contiguous block
	27	+ of physical address space. The size of this block, and the security
	28	+ features available, varies between the different GPIO controllers.
	29	+
	30	+ Access to this set of registers is not necessary in all circumstances.
	31	+ Code that wishes to configure access to the GPIO registers needs access
	32	+ to these registers to do so. Code which simply wishes to read or write
	33	+ GPIO data does not need access to these registers.
	34	+
	35	+ b) GPIO registers, which allow manipulation of the GPIO signals. In some
	36	+ GPIO controllers, these registers are exposed via multiple "physical
	37	+ aliases" in address space, each of which access the same underlying
	38	+ state. See the hardware documentation for rationale. Any particular
	39	+ GPIO client is expected to access just one of these physical aliases.
	40	+
	41	+ Tegra HW documentation describes a unified naming convention for all GPIOs
	42	+ implemented by the SoC. Each GPIO is assigned to a port, and a port may
	43	+ control a number of GPIOs. Thus, each GPIO is named according to an
	44	+ alphabetical port name and an integer GPIO name within the port. For
	45	+ example, GPIO_PA0, GPIO_PN6, or GPIO_PCC3.
	46	+
	47	+ The number of ports implemented by each GPIO controller varies. The number
	48	+ of implemented GPIOs within each port varies. GPIO registers within a
	49	+ controller are grouped and laid out according to the port they affect.
	50	+
	51	+ The mapping from port name to the GPIO controller that implements that
	52	+ port, and the mapping from port name to register offset within a
	53	+ controller, are both extremely non-linear. The header file
	54	+ <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
	55	+ that file, the naming convention for ports matches the HW documentation.
	56	+ The values chosen for the names are alphabetically sorted within a
	57	+ particular controller. Drivers need to map between the DT GPIO IDs and HW
	58	+ register offsets using a lookup table.
	59	+
	60	+ Each GPIO controller can generate a number of interrupt signals. Each
	61	+ signal represents the aggregate status for all GPIOs within a set of
	62	+ ports. Thus, the number of interrupt signals generated by a controller
	63	+ varies as a rough function of the number of ports it implements. Note
	64	+ that the HW documentation refers to both the overall controller HW
	65	+ module and the sets-of-ports as "controllers".
	66	+
	67	+ Each GPIO controller in fact generates multiple interrupts signals for
	68	+ each set of ports. Each GPIO may be configured to feed into a specific
	69	+ one of the interrupt signals generated by a set-of-ports. The intent is
	70	+ for each generated signal to be routed to a different CPU, thus allowing
	71	+ different CPUs to each handle subsets of the interrupts within a port.
	72	+ The status of each of these per-port-set signals is reported via a
	73	+ separate register. Thus, a driver needs to know which status register to
	74	+ observe. This binding currently defines no configuration mechanism for
	75	+ this. By default, drivers should use register
	76	+ GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
	77	+ define a property to configure this.
	78	+
	79	+properties:
	80	+ compatible:
	81	+ enum:
	82	+ - nvidia,tegra186-gpio
	83	+ - nvidia,tegra186-gpio-aon
	84	+ - nvidia,tegra194-gpio
	85	+ - nvidia,tegra194-gpio-aon
	86	+ - nvidia,tegra234-gpio
	87	+ - nvidia,tegra234-gpio-aon
	88	+
	89	+ reg-names:
	90	+ items:
	91	+ - const: security
	92	+ - const: gpio
	93	+ minItems: 1
	94	+
	95	+ reg:
	96	+ items:
	97	+ - description: Security configuration registers.
	98	+ - description: \|
	99	+ GPIO control registers. This may cover either:
	100	+
	101	+ a) The single physical alias that this OS should use.
	102	+ b) All physical aliases that exist in the controller. This is
	103	+ appropriate when the OS is responsible for managing assignment
	104	+ of the physical aliases.
	105	+ minItems: 1
	106	+
	107	+ interrupts:
	108	+ description: The interrupt outputs from the HW block, one per set of
	109	+ ports, in the order the HW manual describes them. The number of entries
	110	+ required varies depending on compatible value.
	111	+
	112	+ gpio-controller: true
	113	+
	114	+ "#gpio-cells":
	115	+ description: \|
	116	+ Indicates how many cells are used in a consumer's GPIO specifier. In the
	117	+ specifier:
	118	+
	119	+ - The first cell is the pin number.
	120	+ See <dt-bindings/gpio/tegra186-gpio.h>.
	121	+ - The second cell contains flags:
	122	+ - Bit 0 specifies polarity
	123	+ - 0: Active-high (normal).
	124	+ - 1: Active-low (inverted).
	125	+ const: 2
	126	+
	127	+ interrupt-controller: true
	128	+
	129	+ "#interrupt-cells":
	130	+ description: \|
	131	+ Indicates how many cells are used in a consumer's interrupt specifier.
	132	+ In the specifier:
	133	+
	134	+ - The first cell is the GPIO number.
	135	+ See <dt-bindings/gpio/tegra186-gpio.h>.
	136	+ - The second cell is contains flags:
	137	+ - Bits [3:0] indicate trigger type and level:
	138	+ - 1: Low-to-high edge triggered.
	139	+ - 2: High-to-low edge triggered.
	140	+ - 4: Active high level-sensitive.
	141	+ - 8: Active low level-sensitive.
	142	+
	143	+ Valid combinations are 1, 2, 3, 4, 8.
	144	+ const: 2
	145	+
	146	+allOf:
	147	+ - if:
	148	+ properties:
	149	+ compatible:
	150	+ contains:
	151	+ enum:
	152	+ - nvidia,tegra186-gpio
	153	+ - nvidia,tegra194-gpio
	154	+ - nvidia,tegra234-gpio
	155	+ then:
	156	+ properties:
	157	+ interrupts:
	158	+ minItems: 6
	159	+ maxItems: 48
	160	+
	161	+ - if:
	162	+ properties:
	163	+ compatible:
	164	+ contains:
	165	+ enum:
	166	+ - nvidia,tegra186-gpio-aon
	167	+ - nvidia,tegra194-gpio-aon
	168	+ - nvidia,tegra234-gpio-aon
	169	+ then:
	170	+ properties:
	171	+ interrupts:
	172	+ minItems: 1
	173	+ maxItems: 4
	174	+
	175	+required:
	176	+ - compatible
	177	+ - reg
	178	+ - reg-names
	179	+ - interrupts
	180	+
	181	+additionalProperties: false
	182	+
	183	+examples:
	184	+ - \|
	185	+ #include <dt-bindings/interrupt-controller/irq.h>
	186	+
	187	+ gpio@2200000 {
	188	+ compatible = "nvidia,tegra186-gpio";
	189	+ reg-names = "security", "gpio";
	190	+ reg = <0x2200000 0x10000>,
	191	+ <0x2210000 0x10000>;
	192	+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>,
	193	+ <0 50 IRQ_TYPE_LEVEL_HIGH>,
	194	+ <0 53 IRQ_TYPE_LEVEL_HIGH>,
	195	+ <0 56 IRQ_TYPE_LEVEL_HIGH>,
	196	+ <0 59 IRQ_TYPE_LEVEL_HIGH>,
	197	+ <0 180 IRQ_TYPE_LEVEL_HIGH>;
	198	+ gpio-controller;
	199	+ #gpio-cells = <2>;
	200	+ interrupt-controller;
	201	+ #interrupt-cells = <2>;
	202	+ };
	203	+
	204	+ gpio@c2f0000 {
	205	+ compatible = "nvidia,tegra186-gpio-aon";
	206	+ reg-names = "security", "gpio";
	207	+ reg = <0xc2f0000 0x1000>,
	208	+ <0xc2f1000 0x1000>;
	209	+ interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
	210	+ gpio-controller;
	211	+ #gpio-cells = <2>;
	212	+ interrupt-controller;
	213	+ #interrupt-cells = <2>;
	214	+ };

Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt+0−40

@@ -1,40 +0,0 @@
1		−NVIDIA Tegra GPIO controller
2		−
3		−Required properties:
4		−- compatible : "nvidia,tegra<chip>-gpio"
5		−- reg : Physical base address and length of the controller's registers.
6		−- interrupts : The interrupt outputs from the controller. For Tegra20,
7		− there should be 7 interrupts specified, and for Tegra30, there should
8		− be 8 interrupts specified.
9		−- #gpio-cells : Should be two. The first cell is the pin number and the
10		− second cell is used to specify optional parameters:
11		− - bit 0 specifies polarity (0 for normal, 1 for inverted)
12		−- gpio-controller : Marks the device node as a GPIO controller.
13		−- #interrupt-cells : Should be 2.
14		− The first cell is the GPIO number.
15		− The second cell is used to specify flags:
16		− bits[3:0] trigger type and level flags:
17		− 1 = low-to-high edge triggered.
18		− 2 = high-to-low edge triggered.
19		− 4 = active high level-sensitive.
20		− 8 = active low level-sensitive.
21		− Valid combinations are 1, 2, 3, 4, 8.
22		−- interrupt-controller : Marks the device node as an interrupt controller.
23		−
24		−Example:
25		−
26		−gpio: gpio@6000d000 {
27		− compatible = "nvidia,tegra20-gpio";
28		− reg = < 0x6000d000 0x1000 >;
29		− interrupts = < 0 32 0x04
30		− 0 33 0x04
31		− 0 34 0x04
32		− 0 35 0x04
33		− 0 55 0x04
34		− 0 87 0x04
35		− 0 89 0x04 >;
36		− #gpio-cells = <2>;
37		− gpio-controller;
38		− #interrupt-cells = <2>;
39		− interrupt-controller;
40		−};

Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.yaml+110−0

@@ -0,0 +1,110 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
	8	+
	9	+maintainers:
	10	+ - Thierry Reding <thierry.reding@gmail.com>
	11	+ - Jon Hunter <jonathanh@nvidia.com>
	12	+
	13	+properties:
	14	+ compatible:
	15	+ oneOf:
	16	+ - enum:
	17	+ - nvidia,tegra20-gpio
	18	+ - nvidia,tegra30-gpio
	19	+
	20	+ - items:
	21	+ - enum:
	22	+ - nvidia,tegra114-gpio
	23	+ - nvidia,tegra124-gpio
	24	+ - nvidia,tegra210-gpio
	25	+ - const: nvidia,tegra30-gpio
	26	+
	27	+ reg:
	28	+ maxItems: 1
	29	+
	30	+ interrupts:
	31	+ description: The interrupt outputs from the controller. For Tegra20,
	32	+ there should be 7 interrupts specified, and for Tegra30, there should
	33	+ be 8 interrupts specified.
	34	+
	35	+ "#gpio-cells":
	36	+ description: The first cell is the pin number and the second cell is used
	37	+ to specify the GPIO polarity (0 = active high, 1 = active low).
	38	+ const: 2
	39	+
	40	+ gpio-controller: true
	41	+
	42	+ gpio-ranges:
	43	+ maxItems: 1
	44	+
	45	+ "#interrupt-cells":
	46	+ description: \|
	47	+ Should be 2. The first cell is the GPIO number. The second cell is
	48	+ used to specify flags:
	49	+
	50	+ bits[3:0] trigger type and level flags:
	51	+ 1 = low-to-high edge triggered.
	52	+ 2 = high-to-low edge triggered.
	53	+ 4 = active high level-sensitive.
	54	+ 8 = active low level-sensitive.
	55	+
	56	+ Valid combinations are 1, 2, 3, 4, 8.
	57	+ const: 2
	58	+
	59	+ interrupt-controller: true
	60	+
	61	+allOf:
	62	+ - if:
	63	+ properties:
	64	+ compatible:
	65	+ contains:
	66	+ const: nvidia,tegra30-gpio
	67	+ then:
	68	+ properties:
	69	+ interrupts:
	70	+ minItems: 8
	71	+ maxItems: 8
	72	+ else:
	73	+ properties:
	74	+ interrupts:
	75	+ minItems: 7
	76	+ maxItems: 7
	77	+
	78	+required:
	79	+ - compatible
	80	+ - reg
	81	+ - interrupts
	82	+ - "#gpio-cells"
	83	+ - gpio-controller
	84	+ - "#interrupt-cells"
	85	+ - interrupt-controller
	86	+
	87	+additionalProperties:
	88	+ type: object
	89	+ required:
	90	+ - gpio-hog
	91	+
	92	+examples:
	93	+ - \|
	94	+ #include <dt-bindings/interrupt-controller/arm-gic.h>
	95	+
	96	+ gpio: gpio@6000d000 {
	97	+ compatible = "nvidia,tegra20-gpio";
	98	+ reg = <0x6000d000 0x1000>;
	99	+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	100	+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	101	+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	102	+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	103	+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	104	+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	105	+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	106	+ #gpio-cells = <2>;
	107	+ gpio-controller;
	108	+ #interrupt-cells = <2>;
	109	+ interrupt-controller;
	110	+ };

Documentation/devicetree/bindings/gpio/sifive,gpio.yaml+2−1

@@ -77,7 +77,8 @@ examples: · 76 unmodified lines
77	77	gpio@10060000 {
78	78	compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
79	79	interrupt-parent = <&plic>;
80		− interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
	80	+ interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>,
	81	+ <17>, <18>, <19>, <20>, <21>, <22>;
81	82	reg = <0x10060000 0x1000>;
82	83	clocks = <&tlclk PRCI_CLK_TLCLK>;
83	84	gpio-controller;

drivers/gpio/Kconfig+12−6

@@ -731,14 +731,12 @@ config GPIO_XILINX · 730 unmodified lines
731	731	Say yes here to support the Xilinx FPGA GPIO device.
732	732
733	733	config GPIO_XLP
734		− tristate "Netlogic XLP GPIO support"
735		− depends on OF_GPIO && (CPU_XLP \|\| ARCH_THUNDER2 \|\| COMPILE_TEST)
	734	+ tristate "Cavium ThunderX2 GPIO support"
	735	+ depends on ARCH_THUNDER2 \|\| COMPILE_TEST
736	736	select GPIOLIB_IRQCHIP
737	737	help
738		− This driver provides support for GPIO interface on Netlogic XLP MIPS64
739		− SoCs. Currently supported XLP variants are XLP8XX, XLP3XX, XLP2XX,
740		− XLP9XX and XLP5XX. The same GPIO controller block is also present in
741		− Cavium's ThunderX2 CN99XX SoCs.
	738	+ This driver provides support for GPIO interface on Cavium's ThunderX2
	739	+ CN99XX SoCs (Originally from Netlogic XLP).
742	740
743	741	If unsure, say N.
744	742
@@ -1683,6 +1681,14 @@ config GPIO_VIRTIO · 938 unmodified lines
1683	1681	These virtual GPIOs can be routed to real GPIOs or attached to
1684	1682	simulators on the host (like QEMU).
1685	1683
	1684	+config GPIO_SIM
	1685	+ tristate "GPIO Simulator Module"
	1686	+ select IRQ_SIM
	1687	+ select CONFIGFS_FS
	1688	+ help
	1689	+ This enables the GPIO simulator - a configfs-based GPIO testing
	1690	+ driver.
	1691	+
1686	1692	endmenu
1687	1693
1688	1694	endif

drivers/gpio/Makefile+1−0

@@ -132,6 +132,7 @@ obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o · 131 unmodified lines
132	132	obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
133	133	obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
134	134	obj-$(CONFIG_GPIO_SIFIVE) += gpio-sifive.o
	135	+obj-$(CONFIG_GPIO_SIM) += gpio-sim.o
135	136	obj-$(CONFIG_GPIO_SIOX) += gpio-siox.o
136	137	obj-$(CONFIG_GPIO_SL28CPLD) += gpio-sl28cpld.o
137	138	obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o

drivers/gpio/gpio-adnp.c+0−1

@@ -458,7 +458,6 @@ static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios, · 457 unmodified lines
458	458	chip->ngpio = num_gpios;
459	459	chip->label = adnp->client->name;
460	460	chip->parent = &adnp->client->dev;
461		− chip->of_node = chip->parent->of_node;
462	461	chip->owner = THIS_MODULE;
463	462
464	463	if (is_irq_controller) {

drivers/gpio/gpio-aggregator.c+10−1

@@ -371,6 +371,13 @@ static int gpio_fwd_set_config(struct gpio_chip *chip, unsigned int offset, · 370 unmodified lines
371	371	return gpiod_set_config(fwd->descs[offset], config);
372	372	}
373	373
	374	+static int gpio_fwd_to_irq(struct gpio_chip *chip, unsigned int offset)
	375	+{
	376	+ struct gpiochip_fwd *fwd = gpiochip_get_data(chip);
	377	+
	378	+ return gpiod_to_irq(fwd->descs[offset]);
	379	+}
	380	+
374	381	/**
375	382	* gpiochip_fwd_create() - Create a new GPIO forwarder
376	383	* @dev: Parent device pointer
@@ -411,7 +418,8 @@ static struct gpiochip_fwd gpiochip_fwd_create(struct device dev, · 34 unmodified lines
411	418	for (i = 0; i < ngpios; i++) {
412	419	struct gpio_chip *parent = gpiod_to_chip(descs[i]);
413	420
414		− dev_dbg(dev, "%u => gpio-%d\n", i, desc_to_gpio(descs[i]));
	421	+ dev_dbg(dev, "%u => gpio %d irq %d\n", i,
	422	+ desc_to_gpio(descs[i]), gpiod_to_irq(descs[i]));
415	423
416	424	if (gpiod_cansleep(descs[i]))
417	425	chip->can_sleep = true;
@@ -429,6 +437,7 @@ static struct gpiochip_fwd gpiochip_fwd_create(struct device dev, · 11 unmodified lines
429	437	chip->get_multiple = gpio_fwd_get_multiple_locked;
430	438	chip->set = gpio_fwd_set;
431	439	chip->set_multiple = gpio_fwd_set_multiple_locked;
	440	+ chip->to_irq = gpio_fwd_to_irq;
432	441	chip->base = -1;
433	442	chip->ngpio = ngpios;
434	443	fwd->descs = descs;

drivers/gpio/gpio-amdpt.c+6−6

@@ -14,6 +14,7 @@ · 13 unmodified lines
14	14	#include <linux/platform_device.h>
15	15
16	16	#define PT_TOTAL_GPIO 8
	17	+#define PT_TOTAL_GPIO_EX 24
17	18
18	19	/* PCI-E MMIO register offsets */
19	20	#define PT_DIRECTION_REG 0x00
@@ -103,10 +104,8 @@ static int pt_gpio_probe(struct platform_device *pdev) · 83 unmodified lines
103	104	pt_gpio->gc.owner = THIS_MODULE;
104	105	pt_gpio->gc.request = pt_gpio_request;
105	106	pt_gpio->gc.free = pt_gpio_free;
106		− pt_gpio->gc.ngpio = PT_TOTAL_GPIO;
107		−#if defined(CONFIG_OF_GPIO)
108		− pt_gpio->gc.of_node = dev->of_node;
109		−#endif
	107	+ pt_gpio->gc.ngpio = (uintptr_t)device_get_match_data(dev);
	108	+
110	109	ret = gpiochip_add_data(&pt_gpio->gc, pt_gpio);
111	110	if (ret) {
112	111	dev_err(dev, "Failed to register GPIO lib\n");
@@ -133,8 +132,9 @@ static int pt_gpio_remove(struct platform_device *pdev) · 20 unmodified lines
133	132	}
134	133
135	134	static const struct acpi_device_id pt_gpio_acpi_match[] = {
136		− { "AMDF030", 0 },
137		− { "AMDIF030", 0 },
	135	+ { "AMDF030", PT_TOTAL_GPIO },
	136	+ { "AMDIF030", PT_TOTAL_GPIO },
	137	+ { "AMDIF031", PT_TOTAL_GPIO_EX },
138	138	{ },
139	139	};
140	140	MODULE_DEVICE_TABLE(acpi, pt_gpio_acpi_match);

drivers/gpio/gpio-arizona.c+2−3

@@ -151,6 +151,8 @@ static int arizona_gpio_probe(struct platform_device *pdev) · 150 unmodified lines
151	151	struct arizona_gpio *arizona_gpio;
152	152	int ret;
153	153
	154	+ device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
	155	+
154	156	arizona_gpio = devm_kzalloc(&pdev->dev, sizeof(*arizona_gpio),
155	157	GFP_KERNEL);
156	158	if (!arizona_gpio)
@@ -159,9 +161,6 @@ static int arizona_gpio_probe(struct platform_device *pdev) · 2 unmodified lines
159	161	arizona_gpio->arizona = arizona;
160	162	arizona_gpio->gpio_chip = template_chip;
161	163	arizona_gpio->gpio_chip.parent = &pdev->dev;
162		−#ifdef CONFIG_OF_GPIO
163		− arizona_gpio->gpio_chip.of_node = arizona->dev->of_node;
164		−#endif
165	164
166	165	switch (arizona->type) {
167	166	case WM5102:

drivers/gpio/gpio-aspeed-sgpio.c+16−16

@@ -31,7 +31,7 @@ struct aspeed_sgpio { · 30 unmodified lines
31	31	struct gpio_chip chip;
32	32	struct irq_chip intc;
33	33	struct clk *pclk;
34		− spinlock_t lock;
	34	+ raw_spinlock_t lock;
35	35	void __iomem *base;
36	36	int irq;
37	37	};
@@ -173,12 +173,12 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset) · 135 unmodified lines
173	173	enum aspeed_sgpio_reg reg;
174	174	int rc = 0;
175	175
176		− spin_lock_irqsave(&gpio->lock, flags);
	176	+ raw_spin_lock_irqsave(&gpio->lock, flags);
177	177
178	178	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
179	179	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
180	180
181		− spin_unlock_irqrestore(&gpio->lock, flags);
	181	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
182	182
183	183	return rc;
184	184	}
@@ -215,11 +215,11 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val) · 30 unmodified lines
215	215	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
216	216	unsigned long flags;
217	217
218		− spin_lock_irqsave(&gpio->lock, flags);
	218	+ raw_spin_lock_irqsave(&gpio->lock, flags);
219	219
220	220	sgpio_set_value(gc, offset, val);
221	221
222		− spin_unlock_irqrestore(&gpio->lock, flags);
	222	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
223	223	}
224	224
225	225	static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
@@ -236,9 +236,9 @@ static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int v · 10 unmodified lines
236	236	/* No special action is required for setting the direction; we'll
237	237	* error-out in sgpio_set_value if this isn't an output GPIO */
238	238
239		− spin_lock_irqsave(&gpio->lock, flags);
	239	+ raw_spin_lock_irqsave(&gpio->lock, flags);
240	240	rc = sgpio_set_value(gc, offset, val);
241		− spin_unlock_irqrestore(&gpio->lock, flags);
	241	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
242	242
243	243	return rc;
244	244	}
@@ -277,11 +277,11 @@ static void aspeed_sgpio_irq_ack(struct irq_data *d) · 32 unmodified lines
277	277
278	278	status_addr = bank_reg(gpio, bank, reg_irq_status);
279	279
280		− spin_lock_irqsave(&gpio->lock, flags);
	280	+ raw_spin_lock_irqsave(&gpio->lock, flags);
281	281
282	282	iowrite32(bit, status_addr);
283	283
284		− spin_unlock_irqrestore(&gpio->lock, flags);
	284	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
285	285	}
286	286
287	287	static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
@@ -296,7 +296,7 @@ static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set) · 8 unmodified lines
296	296	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
297	297	addr = bank_reg(gpio, bank, reg_irq_enable);
298	298
299		− spin_lock_irqsave(&gpio->lock, flags);
	299	+ raw_spin_lock_irqsave(&gpio->lock, flags);
300	300
301	301	reg = ioread32(addr);
302	302	if (set)
@@ -306,7 +306,7 @@ static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set) · 3 unmodified lines
306	306
307	307	iowrite32(reg, addr);
308	308
309		− spin_unlock_irqrestore(&gpio->lock, flags);
	309	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
310	310	}
311	311
312	312	static void aspeed_sgpio_irq_mask(struct irq_data *d)
@@ -355,7 +355,7 @@ static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type) · 42 unmodified lines
355	355	return -EINVAL;
356	356	}
357	357
358		− spin_lock_irqsave(&gpio->lock, flags);
	358	+ raw_spin_lock_irqsave(&gpio->lock, flags);
359	359
360	360	addr = bank_reg(gpio, bank, reg_irq_type0);
361	361	reg = ioread32(addr);
@@ -372,7 +372,7 @@ static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type) · 10 unmodified lines
372	372	reg = (reg & ~bit) \| type2;
373	373	iowrite32(reg, addr);
374	374
375		− spin_unlock_irqrestore(&gpio->lock, flags);
	375	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
376	376
377	377	irq_set_handler_locked(d, handler);
378	378
@@ -467,7 +467,7 @@ static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip, · 88 unmodified lines
467	467
468	468	reg = bank_reg(gpio, to_bank(offset), reg_tolerance);
469	469
470		− spin_lock_irqsave(&gpio->lock, flags);
	470	+ raw_spin_lock_irqsave(&gpio->lock, flags);
471	471
472	472	val = readl(reg);
473	473
@@ -478,7 +478,7 @@ static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip, · 4 unmodified lines
478	478
479	479	writel(val, reg);
480	480
481		− spin_unlock_irqrestore(&gpio->lock, flags);
	481	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
482	482
483	483	return 0;
484	484	}
@@ -575,7 +575,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev) · 90 unmodified lines
575	575	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) \| gpio_cnt_regval \|
576	576	ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
577	577
578		− spin_lock_init(&gpio->lock);
	578	+ raw_spin_lock_init(&gpio->lock);
579	579
580	580	gpio->chip.parent = &pdev->dev;
581	581	gpio->chip.ngpio = nr_gpios * 2;

drivers/gpio/gpio-aspeed.c+26−26

@@ -53,7 +53,7 @@ struct aspeed_gpio_config { · 52 unmodified lines
53	53	struct aspeed_gpio {
54	54	struct gpio_chip chip;
55	55	struct irq_chip irqc;
56		− spinlock_t lock;
	56	+ raw_spinlock_t lock;
57	57	void __iomem *base;
58	58	int irq;
59	59	const struct aspeed_gpio_config *config;
@@ -413,14 +413,14 @@ static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, · 353 unmodified lines
413	413	unsigned long flags;
414	414	bool copro;
415	415
416		− spin_lock_irqsave(&gpio->lock, flags);
	416	+ raw_spin_lock_irqsave(&gpio->lock, flags);
417	417	copro = aspeed_gpio_copro_request(gpio, offset);
418	418
419	419	__aspeed_gpio_set(gc, offset, val);
420	420
421	421	if (copro)
422	422	aspeed_gpio_copro_release(gpio, offset);
423		− spin_unlock_irqrestore(&gpio->lock, flags);
	423	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
424	424	}
425	425
426	426	static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
@@ -435,7 +435,7 @@ static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) · 8 unmodified lines
435	435	if (!have_input(gpio, offset))
436	436	return -ENOTSUPP;
437	437
438		− spin_lock_irqsave(&gpio->lock, flags);
	438	+ raw_spin_lock_irqsave(&gpio->lock, flags);
439	439
440	440	reg = ioread32(addr);
441	441	reg &= ~GPIO_BIT(offset);
@@ -445,7 +445,7 @@ static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) · 3 unmodified lines
445	445	if (copro)
446	446	aspeed_gpio_copro_release(gpio, offset);
447	447
448		− spin_unlock_irqrestore(&gpio->lock, flags);
	448	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
449	449
450	450	return 0;
451	451	}
@@ -463,7 +463,7 @@ static int aspeed_gpio_dir_out(struct gpio_chip *gc, · 11 unmodified lines
463	463	if (!have_output(gpio, offset))
464	464	return -ENOTSUPP;
465	465
466		− spin_lock_irqsave(&gpio->lock, flags);
	466	+ raw_spin_lock_irqsave(&gpio->lock, flags);
467	467
468	468	reg = ioread32(addr);
469	469	reg \|= GPIO_BIT(offset);
@@ -474,7 +474,7 @@ static int aspeed_gpio_dir_out(struct gpio_chip *gc, · 4 unmodified lines
474	474
475	475	if (copro)
476	476	aspeed_gpio_copro_release(gpio, offset);
477		− spin_unlock_irqrestore(&gpio->lock, flags);
	477	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
478	478
479	479	return 0;
480	480	}
@@ -492,11 +492,11 @@ static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) · 11 unmodified lines
492	492	if (!have_output(gpio, offset))
493	493	return GPIO_LINE_DIRECTION_IN;
494	494
495		− spin_lock_irqsave(&gpio->lock, flags);
	495	+ raw_spin_lock_irqsave(&gpio->lock, flags);
496	496
497	497	val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
498	498
499		− spin_unlock_irqrestore(&gpio->lock, flags);
	499	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
500	500
501	501	return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
502	502	}
@@ -539,14 +539,14 @@ static void aspeed_gpio_irq_ack(struct irq_data *d) · 36 unmodified lines
539	539
540	540	status_addr = bank_reg(gpio, bank, reg_irq_status);
541	541
542		− spin_lock_irqsave(&gpio->lock, flags);
	542	+ raw_spin_lock_irqsave(&gpio->lock, flags);
543	543	copro = aspeed_gpio_copro_request(gpio, offset);
544	544
545	545	iowrite32(bit, status_addr);
546	546
547	547	if (copro)
548	548	aspeed_gpio_copro_release(gpio, offset);
549		− spin_unlock_irqrestore(&gpio->lock, flags);
	549	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
550	550	}
551	551
552	552	static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
@@ -565,7 +565,7 @@ static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) · 12 unmodified lines
565	565
566	566	addr = bank_reg(gpio, bank, reg_irq_enable);
567	567
568		− spin_lock_irqsave(&gpio->lock, flags);
	568	+ raw_spin_lock_irqsave(&gpio->lock, flags);
569	569	copro = aspeed_gpio_copro_request(gpio, offset);
570	570
571	571	reg = ioread32(addr);
@@ -577,7 +577,7 @@ static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) · 5 unmodified lines
577	577
578	578	if (copro)
579	579	aspeed_gpio_copro_release(gpio, offset);
580		− spin_unlock_irqrestore(&gpio->lock, flags);
	580	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
581	581	}
582	582
583	583	static void aspeed_gpio_irq_mask(struct irq_data *d)
@@ -629,7 +629,7 @@ static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) · 45 unmodified lines
629	629	return -EINVAL;
630	630	}
631	631
632		− spin_lock_irqsave(&gpio->lock, flags);
	632	+ raw_spin_lock_irqsave(&gpio->lock, flags);
633	633	copro = aspeed_gpio_copro_request(gpio, offset);
634	634
635	635	addr = bank_reg(gpio, bank, reg_irq_type0);
@@ -649,7 +649,7 @@ static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) · 13 unmodified lines
649	649
650	650	if (copro)
651	651	aspeed_gpio_copro_release(gpio, offset);
652		− spin_unlock_irqrestore(&gpio->lock, flags);
	652	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
653	653
654	654	irq_set_handler_locked(d, handler);
655	655
@@ -716,7 +716,7 @@ static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, · 60 unmodified lines
716	716
717	717	treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
718	718
719		− spin_lock_irqsave(&gpio->lock, flags);
	719	+ raw_spin_lock_irqsave(&gpio->lock, flags);
720	720	copro = aspeed_gpio_copro_request(gpio, offset);
721	721
722	722	val = readl(treg);
@@ -730,7 +730,7 @@ static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, · 7 unmodified lines
730	730
731	731	if (copro)
732	732	aspeed_gpio_copro_release(gpio, offset);
733		− spin_unlock_irqrestore(&gpio->lock, flags);
	733	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
734	734
735	735	return 0;
736	736	}
@@ -856,7 +856,7 @@ static int enable_debounce(struct gpio_chip *chip, unsigned int offset, · 119 unmodified lines
856	856	return rc;
857	857	}
858	858
859		− spin_lock_irqsave(&gpio->lock, flags);
	859	+ raw_spin_lock_irqsave(&gpio->lock, flags);
860	860
861	861	if (timer_allocation_registered(gpio, offset)) {
862	862	rc = unregister_allocated_timer(gpio, offset);
@@ -916,7 +916,7 @@ static int enable_debounce(struct gpio_chip *chip, unsigned int offset, · 53 unmodified lines
916	916	configure_timer(gpio, offset, i);
917	917
918	918	out:
919		− spin_unlock_irqrestore(&gpio->lock, flags);
	919	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
920	920
921	921	return rc;
922	922	}
@@ -927,13 +927,13 @@ static int disable_debounce(struct gpio_chip *chip, unsigned int offset) · 4 unmodified lines
927	927	unsigned long flags;
928	928	int rc;
929	929
930		− spin_lock_irqsave(&gpio->lock, flags);
	930	+ raw_spin_lock_irqsave(&gpio->lock, flags);
931	931
932	932	rc = unregister_allocated_timer(gpio, offset);
933	933	if (!rc)
934	934	configure_timer(gpio, offset, 0);
935	935
936		− spin_unlock_irqrestore(&gpio->lock, flags);
	936	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
937	937
938	938	return rc;
939	939	}
@@ -1015,7 +1015,7 @@ int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, · 75 unmodified lines
1015	1015	return -EINVAL;
1016	1016	bindex = offset >> 3;
1017	1017
1018		− spin_lock_irqsave(&gpio->lock, flags);
	1018	+ raw_spin_lock_irqsave(&gpio->lock, flags);
1019	1019
1020	1020	/* Sanity check, this shouldn't happen */
1021	1021	if (gpio->cf_copro_bankmap[bindex] == 0xff) {
@@ -1036,7 +1036,7 @@ int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, · 14 unmodified lines
1036	1036	if (bit)
1037	1037	*bit = GPIO_OFFSET(offset);
1038	1038	bail:
1039		− spin_unlock_irqrestore(&gpio->lock, flags);
	1039	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
1040	1040	return rc;
1041	1041	}
1042	1042	EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio);
@@ -1060,7 +1060,7 @@ int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) · 17 unmodified lines
1060	1060	return -EINVAL;
1061	1061	bindex = offset >> 3;
1062	1062
1063		− spin_lock_irqsave(&gpio->lock, flags);
	1063	+ raw_spin_lock_irqsave(&gpio->lock, flags);
1064	1064
1065	1065	/* Sanity check, this shouldn't happen */
1066	1066	if (gpio->cf_copro_bankmap[bindex] == 0) {
@@ -1074,7 +1074,7 @@ int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) · 7 unmodified lines
1074	1074	aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1075	1075	GPIO_CMDSRC_ARM);
1076	1076	bail:
1077		− spin_unlock_irqrestore(&gpio->lock, flags);
	1077	+ raw_spin_unlock_irqrestore(&gpio->lock, flags);
1078	1078	return rc;
1079	1079	}
1080	1080	EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio);
@@ -1148,7 +1148,7 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) · 67 unmodified lines
1148	1148	if (IS_ERR(gpio->base))
1149	1149	return PTR_ERR(gpio->base);
1150	1150
1151		− spin_lock_init(&gpio->lock);
	1151	+ raw_spin_lock_init(&gpio->lock);
1152	1152
1153	1153	gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
1154	1154	if (!gpio_id)

drivers/gpio/gpio-bcm-kona.c+1−1

@@ -606,7 +606,7 @@ static int bcm_kona_gpio_probe(struct platform_device *pdev) · 605 unmodified lines
606	606
607	607	kona_gpio->pdev = pdev;
608	608	platform_set_drvdata(pdev, kona_gpio);
609		− chip->of_node = dev->of_node;
	609	+ chip->parent = dev;
610	610	chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
611	611
612	612	kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,

drivers/gpio/gpio-bd71828.c+0−1

@@ -121,7 +121,6 @@ static int bd71828_probe(struct platform_device *pdev) · 120 unmodified lines
121	121	* "gpio-reserved-ranges" and exclude them from control
122	122	*/
123	123	bdgpio->gpio.ngpio = 4;
124		− bdgpio->gpio.of_node = dev->parent->of_node;
125	124	bdgpio->regmap = dev_get_regmap(dev->parent, NULL);
126	125	if (!bdgpio->regmap)
127	126	return -ENODEV;

drivers/gpio/gpio-brcmstb.c+1−2

@@ -703,9 +703,8 @@ static int brcmstb_gpio_probe(struct platform_device *pdev) · 702 unmodified lines
703	703	goto fail;
704	704	}
705	705
706		− gc->of_node = np;
707	706	gc->owner = THIS_MODULE;
708		− gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);
	707	+ gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
709	708	if (!gc->label) {
710	709	err = -ENOMEM;
711	710	goto fail;

drivers/gpio/gpio-creg-snps.c+1−1

@@ -163,12 +163,12 @@ static int creg_gpio_probe(struct platform_device *pdev) · 162 unmodified lines
163	163
164	164	spin_lock_init(&hcg->lock);
165	165
	166	+ hcg->gc.parent = dev;
166	167	hcg->gc.label = dev_name(dev);
167	168	hcg->gc.base = -1;
168	169	hcg->gc.ngpio = ngpios;
169	170	hcg->gc.set = creg_gpio_set;
170	171	hcg->gc.direction_output = creg_gpio_dir_out;
171		− hcg->gc.of_node = dev->of_node;
172	172
173	173	ret = devm_gpiochip_add_data(dev, &hcg->gc, hcg);
174	174	if (ret)

drivers/gpio/gpio-davinci.c+0−1

@@ -254,7 +254,6 @@ static int davinci_gpio_probe(struct platform_device *pdev) · 253 unmodified lines
254	254	#ifdef CONFIG_OF_GPIO
255	255	chips->chip.of_gpio_n_cells = 2;
256	256	chips->chip.parent = dev;
257		− chips->chip.of_node = dev->of_node;
258	257	chips->chip.request = gpiochip_generic_request;
259	258	chips->chip.free = gpiochip_generic_free;
260	259	#endif

drivers/gpio/gpio-dwapb.c+7−8

@@ -15,7 +15,6 @@ · 14 unmodified lines
15	15	#include <linux/irq.h>
16	16	#include <linux/mod_devicetable.h>
17	17	#include <linux/module.h>
18		−#include <linux/of.h>
19	18	#include <linux/platform_device.h>
20	19	#include <linux/property.h>
21	20	#include <linux/reset.h>
@@ -53,7 +52,9 @@ · 31 unmodified lines
53	52	#define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 332 bits /
54	53	#define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 332 bits /
55	54
	55	+#define GPIO_REG_OFFSET_V1 0
56	56	#define GPIO_REG_OFFSET_V2 1
	57	+#define GPIO_REG_OFFSET_MASK BIT(0)
57	58
58	59	#define GPIO_INTMASK_V2 0x44
59	60	#define GPIO_INTTYPE_LEVEL_V2 0x34
@@ -141,7 +142,7 @@ static inline u32 gpio_reg_v2_convert(unsigned int offset) · 81 unmodified lines
141	142
142	143	static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
143	144	{
144		− if (gpio->flags & GPIO_REG_OFFSET_V2)
	145	+ if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
145	146	return gpio_reg_v2_convert(offset);
146	147
147	148	return offset;
@@ -513,9 +514,7 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, · 365 unmodified lines
513	514	return err;
514	515	}
515	516
516		−#ifdef CONFIG_OF_GPIO
517		− port->gc.of_node = to_of_node(pp->fwnode);
518		−#endif
	517	+ port->gc.fwnode = pp->fwnode;
519	518	port->gc.ngpio = pp->ngpio;
520	519	port->gc.base = pp->gpio_base;
521	520
@@ -668,15 +667,15 @@ static int dwapb_get_clks(struct dwapb_gpio *gpio) · 146 unmodified lines
668	667	}
669	668
670	669	static const struct of_device_id dwapb_of_match[] = {
671		− { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
	670	+ { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
672	671	{ .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
673	672	{ /* Sentinel */ }
674	673	};
675	674	MODULE_DEVICE_TABLE(of, dwapb_of_match);
676	675
677	676	static const struct acpi_device_id dwapb_acpi_match[] = {
678		− {"HISI0181", 0},
679		− {"APMC0D07", 0},
	677	+ {"HISI0181", GPIO_REG_OFFSET_V1},
	678	+ {"APMC0D07", GPIO_REG_OFFSET_V1},
680	679	{"APMC0D81", GPIO_REG_OFFSET_V2},
681	680	{ }
682	681	};

drivers/gpio/gpio-eic-sprd.c+0−1

@@ -609,7 +609,6 @@ static int sprd_eic_probe(struct platform_device *pdev) · 608 unmodified lines
609	609	sprd_eic->chip.ngpio = pdata->num_eics;
610	610	sprd_eic->chip.base = -1;
611	611	sprd_eic->chip.parent = &pdev->dev;
612		− sprd_eic->chip.of_node = pdev->dev.of_node;
613	612	sprd_eic->chip.direction_input = sprd_eic_direction_input;
614	613	switch (sprd_eic->type) {
615	614	case SPRD_EIC_DEBOUNCE:

drivers/gpio/gpio-em.c+0−1

@@ -306,7 +306,6 @@ static int em_gio_probe(struct platform_device *pdev) · 305 unmodified lines
306	306	}
307	307
308	308	gpio_chip = &p->gpio_chip;
309		− gpio_chip->of_node = dev->of_node;
310	309	gpio_chip->direction_input = em_gio_direction_input;
311	310	gpio_chip->get = em_gio_get;
312	311	gpio_chip->direction_output = em_gio_direction_output;

drivers/gpio/gpio-ge.c+0−1

@@ -82,7 +82,6 @@ static int __init gef_gpio_probe(struct platform_device *pdev) · 81 unmodified lines
82	82	gc->base = -1;
83	83	gc->ngpio = (u16)(uintptr_t)of_device_get_match_data(&pdev->dev);
84	84	gc->of_gpio_n_cells = 2;
85		− gc->of_node = pdev->dev.of_node;
86	85
87	86	/* This function adds a memory mapped GPIO chip */
88	87	ret = devm_gpiochip_add_data(&pdev->dev, gc, NULL);

drivers/gpio/gpio-grgpio.c+0−1

@@ -358,7 +358,6 @@ static int grgpio_probe(struct platform_device *ofdev) · 357 unmodified lines
358	358	priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
359	359	priv->dev = &ofdev->dev;
360	360
361		− gc->of_node = np;
362	361	gc->owner = THIS_MODULE;
363	362	gc->to_irq = grgpio_to_irq;
364	363	gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);

drivers/gpio/gpio-gw-pld.c+0−2

@@ -71,7 +71,6 @@ static int gw_pld_probe(struct i2c_client *client, · 70 unmodified lines
71	71	const struct i2c_device_id *id)
72	72	{
73	73	struct device *dev = &client->dev;
74		− struct device_node *np = dev->of_node;
75	74	struct gw_pld *gw;
76	75	int ret;
77	76
@@ -82,7 +81,6 @@ static int gw_pld_probe(struct i2c_client *client, · 4 unmodified lines
82	81	gw->chip.base = -1;
83	82	gw->chip.can_sleep = true;
84	83	gw->chip.parent = dev;
85		− gw->chip.of_node = np;
86	84	gw->chip.owner = THIS_MODULE;
87	85	gw->chip.label = dev_name(dev);
88	86	gw->chip.ngpio = 8;

drivers/gpio/gpio-lpc32xx.c+1−1

@@ -512,10 +512,10 @@ static int lpc32xx_gpio_probe(struct platform_device *pdev) · 511 unmodified lines
512	512	return PTR_ERR(reg_base);
513	513
514	514	for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
	515	+ lpc32xx_gpiochip[i].chip.parent = &pdev->dev;
515	516	if (pdev->dev.of_node) {
516	517	lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
517	518	lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
518		− lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
519	519	lpc32xx_gpiochip[i].reg_base = reg_base;
520	520	}
521	521	devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,

drivers/gpio/gpio-max3191x.c+1−1

@@ -326,7 +326,7 @@ static void gpiod_set_array_single_value_cansleep(unsigned int ndescs, · 325 unmodified lines
326	326	bitmap_zero(values, ndescs);
327	327
328	328	gpiod_set_array_value_cansleep(ndescs, desc, info, values);
329		− kfree(values);
	329	+ bitmap_free(values);
330	330	}
331	331
332	332	static struct gpio_descs *devm_gpiod_get_array_optional_count(

drivers/gpio/gpio-ml-ioh.c+26−26

@@ -98,9 +98,9 @@ static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) · 97 unmodified lines
98	98	spin_lock_irqsave(&chip->spinlock, flags);
99	99	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
100	100	if (val)
101		− reg_val \|= (1 << nr);
	101	+ reg_val \|= BIT(nr);
102	102	else
103		− reg_val &= ~(1 << nr);
	103	+ reg_val &= ~BIT(nr);
104	104
105	105	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
106	106	spin_unlock_irqrestore(&chip->spinlock, flags);
@@ -110,7 +110,7 @@ static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr) · 3 unmodified lines
110	110	{
111	111	struct ioh_gpio *chip = gpiochip_get_data(gpio);
112	112
113		− return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr));
	113	+ return !!(ioread32(&chip->reg->regs[chip->ch].pi) & BIT(nr));
114	114	}
115	115
116	116	static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
@@ -122,16 +122,16 @@ static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, · 5 unmodified lines
122	122	unsigned long flags;
123	123
124	124	spin_lock_irqsave(&chip->spinlock, flags);
125		− pm = ioread32(&chip->reg->regs[chip->ch].pm) &
126		− ((1 << num_ports[chip->ch]) - 1);
127		− pm \|= (1 << nr);
	125	+ pm = ioread32(&chip->reg->regs[chip->ch].pm);
	126	+ pm &= BIT(num_ports[chip->ch]) - 1;
	127	+ pm \|= BIT(nr);
128	128	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
129	129
130	130	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
131	131	if (val)
132		− reg_val \|= (1 << nr);
	132	+ reg_val \|= BIT(nr);
133	133	else
134		− reg_val &= ~(1 << nr);
	134	+ reg_val &= ~BIT(nr);
135	135	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
136	136
137	137	spin_unlock_irqrestore(&chip->spinlock, flags);
@@ -146,9 +146,9 @@ static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) · 8 unmodified lines
146	146	unsigned long flags;
147	147
148	148	spin_lock_irqsave(&chip->spinlock, flags);
149		− pm = ioread32(&chip->reg->regs[chip->ch].pm) &
150		− ((1 << num_ports[chip->ch]) - 1);
151		− pm &= ~(1 << nr);
	149	+ pm = ioread32(&chip->reg->regs[chip->ch].pm);
	150	+ pm &= BIT(num_ports[chip->ch]) - 1;
	151	+ pm &= ~BIT(nr);
152	152	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
153	153	spin_unlock_irqrestore(&chip->spinlock, flags);
154	154
@@ -304,7 +304,7 @@ static void ioh_irq_unmask(struct irq_data *d) · 149 unmodified lines
304	304	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
305	305	struct ioh_gpio *chip = gc->private;
306	306
307		− iowrite32(1 << (d->irq - chip->irq_base),
	307	+ iowrite32(BIT(d->irq - chip->irq_base),
308	308	&chip->reg->regs[chip->ch].imaskclr);
309	309	}
310	310
@@ -313,7 +313,7 @@ static void ioh_irq_mask(struct irq_data *d) · 2 unmodified lines
313	313	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
314	314	struct ioh_gpio *chip = gc->private;
315	315
316		− iowrite32(1 << (d->irq - chip->irq_base),
	316	+ iowrite32(BIT(d->irq - chip->irq_base),
317	317	&chip->reg->regs[chip->ch].imask);
318	318	}
319	319
@@ -326,7 +326,7 @@ static void ioh_irq_disable(struct irq_data *d) · 6 unmodified lines
326	326
327	327	spin_lock_irqsave(&chip->spinlock, flags);
328	328	ien = ioread32(&chip->reg->regs[chip->ch].ien);
329		− ien &= ~(1 << (d->irq - chip->irq_base));
	329	+ ien &= ~BIT(d->irq - chip->irq_base);
330	330	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
331	331	spin_unlock_irqrestore(&chip->spinlock, flags);
332	332	}
@@ -340,7 +340,7 @@ static void ioh_irq_enable(struct irq_data *d) · 7 unmodified lines
340	340
341	341	spin_lock_irqsave(&chip->spinlock, flags);
342	342	ien = ioread32(&chip->reg->regs[chip->ch].ien);
343		− ien \|= 1 << (d->irq - chip->irq_base);
	343	+ ien \|= BIT(d->irq - chip->irq_base);
344	344	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
345	345	spin_unlock_irqrestore(&chip->spinlock, flags);
346	346	}
@@ -401,6 +401,7 @@ static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip, · 54 unmodified lines
401	401	static int ioh_gpio_probe(struct pci_dev *pdev,
402	402	const struct pci_device_id *id)
403	403	{
	404	+ struct device *dev = &pdev->dev;
404	405	int ret;
405	406	int i, j;
406	407	struct ioh_gpio *chip;
@@ -410,19 +411,19 @@ static int ioh_gpio_probe(struct pci_dev *pdev, · 3 unmodified lines
410	411
411	412	ret = pci_enable_device(pdev);
412	413	if (ret) {
413		− dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
	414	+ dev_err(dev, "%s : pci_enable_device failed", __func__);
414	415	goto err_pci_enable;
415	416	}
416	417
417	418	ret = pci_request_regions(pdev, KBUILD_MODNAME);
418	419	if (ret) {
419		− dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
	420	+ dev_err(dev, "pci_request_regions failed-%d", ret);
420	421	goto err_request_regions;
421	422	}
422	423
423	424	base = pci_iomap(pdev, 1, 0);
424	425	if (!base) {
425		− dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
	426	+ dev_err(dev, "%s : pci_iomap failed", __func__);
426	427	ret = -ENOMEM;
427	428	goto err_iomap;
428	429	}
@@ -435,7 +436,7 @@ static int ioh_gpio_probe(struct pci_dev *pdev, · 6 unmodified lines
435	436
436	437	chip = chip_save;
437	438	for (i = 0; i < 8; i++, chip++) {
438		− chip->dev = &pdev->dev;
	439	+ chip->dev = dev;
439	440	chip->base = base;
440	441	chip->reg = chip->base;
441	442	chip->ch = i;
@@ -443,17 +444,17 @@ static int ioh_gpio_probe(struct pci_dev *pdev, · 1 unmodified line
443	444	ioh_gpio_setup(chip, num_ports[i]);
444	445	ret = gpiochip_add_data(&chip->gpio, chip);
445	446	if (ret) {
446		− dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
	447	+ dev_err(dev, "IOH gpio: Failed to register GPIO\n");
447	448	goto err_gpiochip_add;
448	449	}
449	450	}
450	451
451	452	chip = chip_save;
452	453	for (j = 0; j < 8; j++, chip++) {
453		− irq_base = devm_irq_alloc_descs(&pdev->dev, -1, IOH_IRQ_BASE,
	454	+ irq_base = devm_irq_alloc_descs(dev, -1, IOH_IRQ_BASE,
454	455	num_ports[j], NUMA_NO_NODE);
455	456	if (irq_base < 0) {
456		− dev_warn(&pdev->dev,
	457	+ dev_warn(dev,
457	458	"ml_ioh_gpio: Failed to get IRQ base num\n");
458	459	ret = irq_base;
459	460	goto err_gpiochip_add;
@@ -467,11 +468,10 @@ static int ioh_gpio_probe(struct pci_dev *pdev, · 7 unmodified lines
467	468	}
468	469
469	470	chip = chip_save;
470		− ret = devm_request_irq(&pdev->dev, pdev->irq, ioh_gpio_handler,
	471	+ ret = devm_request_irq(dev, pdev->irq, ioh_gpio_handler,
471	472	IRQF_SHARED, KBUILD_MODNAME, chip);
472	473	if (ret != 0) {
473		− dev_err(&pdev->dev,
474		− "%s request_irq failed\n", __func__);
	474	+ dev_err(dev, "%s request_irq failed\n", __func__);
475	475	goto err_gpiochip_add;
476	476	}
477	477
@@ -498,7 +498,7 @@ err_request_regions: · 20 unmodified lines
498	498
499	499	err_pci_enable:
500	500
501		− dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
	501	+ dev_err(dev, "%s Failed returns %d\n", __func__, ret);
502	502	return ret;
503	503	}
504	504

drivers/gpio/gpio-msc313.c+262−4

@@ -221,6 +221,263 @@ static const unsigned int msc313_offsets[] = { · 220 unmodified lines
221	221	};
222	222
223	223	MSC313_GPIO_CHIPDATA(msc313);
	224	+
	225	+/*
	226	+ * Unlike the msc313(e) the ssd20xd have a bunch of pins
	227	+ * that are actually called gpio probably because they
	228	+ * have no dedicated function.
	229	+ */
	230	+#define SSD20XD_PINNAME_GPIO0 "gpio0"
	231	+#define SSD20XD_PINNAME_GPIO1 "gpio1"
	232	+#define SSD20XD_PINNAME_GPIO2 "gpio2"
	233	+#define SSD20XD_PINNAME_GPIO3 "gpio3"
	234	+#define SSD20XD_PINNAME_GPIO4 "gpio4"
	235	+#define SSD20XD_PINNAME_GPIO5 "gpio5"
	236	+#define SSD20XD_PINNAME_GPIO6 "gpio6"
	237	+#define SSD20XD_PINNAME_GPIO7 "gpio7"
	238	+#define SSD20XD_PINNAME_GPIO10 "gpio10"
	239	+#define SSD20XD_PINNAME_GPIO11 "gpio11"
	240	+#define SSD20XD_PINNAME_GPIO12 "gpio12"
	241	+#define SSD20XD_PINNAME_GPIO13 "gpio13"
	242	+#define SSD20XD_PINNAME_GPIO14 "gpio14"
	243	+#define SSD20XD_PINNAME_GPIO85 "gpio85"
	244	+#define SSD20XD_PINNAME_GPIO86 "gpio86"
	245	+#define SSD20XD_PINNAME_GPIO90 "gpio90"
	246	+
	247	+#define SSD20XD_GPIO_NAMES SSD20XD_PINNAME_GPIO0, \
	248	+ SSD20XD_PINNAME_GPIO1, \
	249	+ SSD20XD_PINNAME_GPIO2, \
	250	+ SSD20XD_PINNAME_GPIO3, \
	251	+ SSD20XD_PINNAME_GPIO4, \
	252	+ SSD20XD_PINNAME_GPIO5, \
	253	+ SSD20XD_PINNAME_GPIO6, \
	254	+ SSD20XD_PINNAME_GPIO7, \
	255	+ SSD20XD_PINNAME_GPIO10, \
	256	+ SSD20XD_PINNAME_GPIO11, \
	257	+ SSD20XD_PINNAME_GPIO12, \
	258	+ SSD20XD_PINNAME_GPIO13, \
	259	+ SSD20XD_PINNAME_GPIO14, \
	260	+ SSD20XD_PINNAME_GPIO85, \
	261	+ SSD20XD_PINNAME_GPIO86, \
	262	+ SSD20XD_PINNAME_GPIO90
	263	+
	264	+#define SSD20XD_GPIO_OFF_GPIO0 0x0
	265	+#define SSD20XD_GPIO_OFF_GPIO1 0x4
	266	+#define SSD20XD_GPIO_OFF_GPIO2 0x8
	267	+#define SSD20XD_GPIO_OFF_GPIO3 0xc
	268	+#define SSD20XD_GPIO_OFF_GPIO4 0x10
	269	+#define SSD20XD_GPIO_OFF_GPIO5 0x14
	270	+#define SSD20XD_GPIO_OFF_GPIO6 0x18
	271	+#define SSD20XD_GPIO_OFF_GPIO7 0x1c
	272	+#define SSD20XD_GPIO_OFF_GPIO10 0x28
	273	+#define SSD20XD_GPIO_OFF_GPIO11 0x2c
	274	+#define SSD20XD_GPIO_OFF_GPIO12 0x30
	275	+#define SSD20XD_GPIO_OFF_GPIO13 0x34
	276	+#define SSD20XD_GPIO_OFF_GPIO14 0x38
	277	+#define SSD20XD_GPIO_OFF_GPIO85 0x100
	278	+#define SSD20XD_GPIO_OFF_GPIO86 0x104
	279	+#define SSD20XD_GPIO_OFF_GPIO90 0x114
	280	+
	281	+#define SSD20XD_GPIO_OFFSETS SSD20XD_GPIO_OFF_GPIO0, \
	282	+ SSD20XD_GPIO_OFF_GPIO1, \
	283	+ SSD20XD_GPIO_OFF_GPIO2, \
	284	+ SSD20XD_GPIO_OFF_GPIO3, \
	285	+ SSD20XD_GPIO_OFF_GPIO4, \
	286	+ SSD20XD_GPIO_OFF_GPIO5, \
	287	+ SSD20XD_GPIO_OFF_GPIO6, \
	288	+ SSD20XD_GPIO_OFF_GPIO7, \
	289	+ SSD20XD_GPIO_OFF_GPIO10, \
	290	+ SSD20XD_GPIO_OFF_GPIO11, \
	291	+ SSD20XD_GPIO_OFF_GPIO12, \
	292	+ SSD20XD_GPIO_OFF_GPIO13, \
	293	+ SSD20XD_GPIO_OFF_GPIO14, \
	294	+ SSD20XD_GPIO_OFF_GPIO85, \
	295	+ SSD20XD_GPIO_OFF_GPIO86, \
	296	+ SSD20XD_GPIO_OFF_GPIO90
	297	+
	298	+/* "ttl" pins lcd interface pins */
	299	+#define SSD20XD_PINNAME_TTL0 "ttl0"
	300	+#define SSD20XD_PINNAME_TTL1 "ttl1"
	301	+#define SSD20XD_PINNAME_TTL2 "ttl2"
	302	+#define SSD20XD_PINNAME_TTL3 "ttl3"
	303	+#define SSD20XD_PINNAME_TTL4 "ttl4"
	304	+#define SSD20XD_PINNAME_TTL5 "ttl5"
	305	+#define SSD20XD_PINNAME_TTL6 "ttl6"
	306	+#define SSD20XD_PINNAME_TTL7 "ttl7"
	307	+#define SSD20XD_PINNAME_TTL8 "ttl8"
	308	+#define SSD20XD_PINNAME_TTL9 "ttl9"
	309	+#define SSD20XD_PINNAME_TTL10 "ttl10"
	310	+#define SSD20XD_PINNAME_TTL11 "ttl11"
	311	+#define SSD20XD_PINNAME_TTL12 "ttl12"
	312	+#define SSD20XD_PINNAME_TTL13 "ttl13"
	313	+#define SSD20XD_PINNAME_TTL14 "ttl14"
	314	+#define SSD20XD_PINNAME_TTL15 "ttl15"
	315	+#define SSD20XD_PINNAME_TTL16 "ttl16"
	316	+#define SSD20XD_PINNAME_TTL17 "ttl17"
	317	+#define SSD20XD_PINNAME_TTL18 "ttl18"
	318	+#define SSD20XD_PINNAME_TTL19 "ttl19"
	319	+#define SSD20XD_PINNAME_TTL20 "ttl20"
	320	+#define SSD20XD_PINNAME_TTL21 "ttl21"
	321	+#define SSD20XD_PINNAME_TTL22 "ttl22"
	322	+#define SSD20XD_PINNAME_TTL23 "ttl23"
	323	+#define SSD20XD_PINNAME_TTL24 "ttl24"
	324	+#define SSD20XD_PINNAME_TTL25 "ttl25"
	325	+#define SSD20XD_PINNAME_TTL26 "ttl26"
	326	+#define SSD20XD_PINNAME_TTL27 "ttl27"
	327	+
	328	+#define SSD20XD_TTL_PINNAMES SSD20XD_PINNAME_TTL0, \
	329	+ SSD20XD_PINNAME_TTL1, \
	330	+ SSD20XD_PINNAME_TTL2, \
	331	+ SSD20XD_PINNAME_TTL3, \
	332	+ SSD20XD_PINNAME_TTL4, \
	333	+ SSD20XD_PINNAME_TTL5, \
	334	+ SSD20XD_PINNAME_TTL6, \
	335	+ SSD20XD_PINNAME_TTL7, \
	336	+ SSD20XD_PINNAME_TTL8, \
	337	+ SSD20XD_PINNAME_TTL9, \
	338	+ SSD20XD_PINNAME_TTL10, \
	339	+ SSD20XD_PINNAME_TTL11, \
	340	+ SSD20XD_PINNAME_TTL12, \
	341	+ SSD20XD_PINNAME_TTL13, \
	342	+ SSD20XD_PINNAME_TTL14, \
	343	+ SSD20XD_PINNAME_TTL15, \
	344	+ SSD20XD_PINNAME_TTL16, \
	345	+ SSD20XD_PINNAME_TTL17, \
	346	+ SSD20XD_PINNAME_TTL18, \
	347	+ SSD20XD_PINNAME_TTL19, \
	348	+ SSD20XD_PINNAME_TTL20, \
	349	+ SSD20XD_PINNAME_TTL21, \
	350	+ SSD20XD_PINNAME_TTL22, \
	351	+ SSD20XD_PINNAME_TTL23, \
	352	+ SSD20XD_PINNAME_TTL24, \
	353	+ SSD20XD_PINNAME_TTL25, \
	354	+ SSD20XD_PINNAME_TTL26, \
	355	+ SSD20XD_PINNAME_TTL27
	356	+
	357	+#define SSD20XD_TTL_OFFSET_TTL0 0x80
	358	+#define SSD20XD_TTL_OFFSET_TTL1 0x84
	359	+#define SSD20XD_TTL_OFFSET_TTL2 0x88
	360	+#define SSD20XD_TTL_OFFSET_TTL3 0x8c
	361	+#define SSD20XD_TTL_OFFSET_TTL4 0x90
	362	+#define SSD20XD_TTL_OFFSET_TTL5 0x94
	363	+#define SSD20XD_TTL_OFFSET_TTL6 0x98
	364	+#define SSD20XD_TTL_OFFSET_TTL7 0x9c
	365	+#define SSD20XD_TTL_OFFSET_TTL8 0xa0
	366	+#define SSD20XD_TTL_OFFSET_TTL9 0xa4
	367	+#define SSD20XD_TTL_OFFSET_TTL10 0xa8
	368	+#define SSD20XD_TTL_OFFSET_TTL11 0xac
	369	+#define SSD20XD_TTL_OFFSET_TTL12 0xb0
	370	+#define SSD20XD_TTL_OFFSET_TTL13 0xb4
	371	+#define SSD20XD_TTL_OFFSET_TTL14 0xb8
	372	+#define SSD20XD_TTL_OFFSET_TTL15 0xbc
	373	+#define SSD20XD_TTL_OFFSET_TTL16 0xc0
	374	+#define SSD20XD_TTL_OFFSET_TTL17 0xc4
	375	+#define SSD20XD_TTL_OFFSET_TTL18 0xc8
	376	+#define SSD20XD_TTL_OFFSET_TTL19 0xcc
	377	+#define SSD20XD_TTL_OFFSET_TTL20 0xd0
	378	+#define SSD20XD_TTL_OFFSET_TTL21 0xd4
	379	+#define SSD20XD_TTL_OFFSET_TTL22 0xd8
	380	+#define SSD20XD_TTL_OFFSET_TTL23 0xdc
	381	+#define SSD20XD_TTL_OFFSET_TTL24 0xe0
	382	+#define SSD20XD_TTL_OFFSET_TTL25 0xe4
	383	+#define SSD20XD_TTL_OFFSET_TTL26 0xe8
	384	+#define SSD20XD_TTL_OFFSET_TTL27 0xec
	385	+
	386	+#define SSD20XD_TTL_OFFSETS SSD20XD_TTL_OFFSET_TTL0, \
	387	+ SSD20XD_TTL_OFFSET_TTL1, \
	388	+ SSD20XD_TTL_OFFSET_TTL2, \
	389	+ SSD20XD_TTL_OFFSET_TTL3, \
	390	+ SSD20XD_TTL_OFFSET_TTL4, \
	391	+ SSD20XD_TTL_OFFSET_TTL5, \
	392	+ SSD20XD_TTL_OFFSET_TTL6, \
	393	+ SSD20XD_TTL_OFFSET_TTL7, \
	394	+ SSD20XD_TTL_OFFSET_TTL8, \
	395	+ SSD20XD_TTL_OFFSET_TTL9, \
	396	+ SSD20XD_TTL_OFFSET_TTL10, \
	397	+ SSD20XD_TTL_OFFSET_TTL11, \
	398	+ SSD20XD_TTL_OFFSET_TTL12, \
	399	+ SSD20XD_TTL_OFFSET_TTL13, \
	400	+ SSD20XD_TTL_OFFSET_TTL14, \
	401	+ SSD20XD_TTL_OFFSET_TTL15, \
	402	+ SSD20XD_TTL_OFFSET_TTL16, \
	403	+ SSD20XD_TTL_OFFSET_TTL17, \
	404	+ SSD20XD_TTL_OFFSET_TTL18, \
	405	+ SSD20XD_TTL_OFFSET_TTL19, \
	406	+ SSD20XD_TTL_OFFSET_TTL20, \
	407	+ SSD20XD_TTL_OFFSET_TTL21, \
	408	+ SSD20XD_TTL_OFFSET_TTL22, \
	409	+ SSD20XD_TTL_OFFSET_TTL23, \
	410	+ SSD20XD_TTL_OFFSET_TTL24, \
	411	+ SSD20XD_TTL_OFFSET_TTL25, \
	412	+ SSD20XD_TTL_OFFSET_TTL26, \
	413	+ SSD20XD_TTL_OFFSET_TTL27
	414	+
	415	+/* On the ssd20xd the two normal uarts have dedicated pins */
	416	+#define SSD20XD_PINNAME_UART0_RX "uart0_rx"
	417	+#define SSD20XD_PINNAME_UART0_TX "uart0_tx"
	418	+
	419	+#define SSD20XD_UART0_NAMES \
	420	+ SSD20XD_PINNAME_UART0_RX, \
	421	+ SSD20XD_PINNAME_UART0_TX
	422	+
	423	+#define SSD20XD_PINNAME_UART1_RX "uart1_rx"
	424	+#define SSD20XD_PINNAME_UART1_TX "uart1_tx"
	425	+
	426	+#define SSD20XD_UART1_NAMES \
	427	+ SSD20XD_PINNAME_UART1_RX, \
	428	+ SSD20XD_PINNAME_UART1_TX
	429	+
	430	+#define SSD20XD_OFF_UART0_RX 0x60
	431	+#define SSD20XD_OFF_UART0_TX 0x64
	432	+
	433	+#define SSD20XD_UART0_OFFSETS \
	434	+ SSD20XD_OFF_UART0_RX, \
	435	+ SSD20XD_OFF_UART0_TX
	436	+
	437	+#define SSD20XD_OFF_UART1_RX 0x68
	438	+#define SSD20XD_OFF_UART1_TX 0x6c
	439	+
	440	+#define SSD20XD_UART1_OFFSETS \
	441	+ SSD20XD_OFF_UART1_RX, \
	442	+ SSD20XD_OFF_UART1_TX
	443	+
	444	+/*
	445	+ * ssd20x has the same pin names but different ordering
	446	+ * of the registers that control the gpio.
	447	+ */
	448	+#define SSD20XD_OFF_SD_D0 0x140
	449	+#define SSD20XD_OFF_SD_D1 0x144
	450	+#define SSD20XD_OFF_SD_D2 0x148
	451	+#define SSD20XD_OFF_SD_D3 0x14c
	452	+#define SSD20XD_OFF_SD_CMD 0x150
	453	+#define SSD20XD_OFF_SD_CLK 0x154
	454	+
	455	+#define SSD20XD_SD_OFFSETS SSD20XD_OFF_SD_CLK, \
	456	+ SSD20XD_OFF_SD_CMD, \
	457	+ SSD20XD_OFF_SD_D0, \
	458	+ SSD20XD_OFF_SD_D1, \
	459	+ SSD20XD_OFF_SD_D2, \
	460	+ SSD20XD_OFF_SD_D3
	461	+
	462	+static const char * const ssd20xd_names[] = {
	463	+ FUART_NAMES,
	464	+ SD_NAMES,
	465	+ SSD20XD_UART0_NAMES,
	466	+ SSD20XD_UART1_NAMES,
	467	+ SSD20XD_TTL_PINNAMES,
	468	+ SSD20XD_GPIO_NAMES,
	469	+};
	470	+
	471	+static const unsigned int ssd20xd_offsets[] = {
	472	+ FUART_OFFSETS,
	473	+ SSD20XD_SD_OFFSETS,
	474	+ SSD20XD_UART0_OFFSETS,
	475	+ SSD20XD_UART1_OFFSETS,
	476	+ SSD20XD_TTL_OFFSETS,
	477	+ SSD20XD_GPIO_OFFSETS,
	478	+};
	479	+
	480	+MSC313_GPIO_CHIPDATA(ssd20xd);
224	481	#endif
225	482
226	483	struct msc313_gpio {
@@ -344,7 +601,6 @@ static int msc313_gpio_probe(struct platform_device *pdev) · 117 unmodified lines
344	601	struct irq_domain *parent_domain;
345	602	struct device_node *parent_node;
346	603	struct device *dev = &pdev->dev;
347		− int ret;
348	604
349	605	match_data = of_device_get_match_data(dev);
350	606	if (!match_data)
@@ -399,8 +655,7 @@ static int msc313_gpio_probe(struct platform_device *pdev) · 48 unmodified lines
399	655	gpioirqchip->handler = handle_bad_irq;
400	656	gpioirqchip->default_type = IRQ_TYPE_NONE;
401	657
402		− ret = devm_gpiochip_add_data(dev, gpiochip, gpio);
403		− return ret;
	658	+ return devm_gpiochip_add_data(dev, gpiochip, gpio);
404	659	}
405	660
406	661	static int msc313_gpio_remove(struct platform_device *pdev)
@@ -414,6 +669,10 @@ static const struct of_device_id msc313_gpio_of_match[] = { · 7 unmodified lines
414	669	.compatible = "mstar,msc313-gpio",
415	670	.data = &msc313_data,
416	671	},
	672	+ {
	673	+ .compatible = "sstar,ssd20xd-gpio",
	674	+ .data = &ssd20xd_data,
	675	+ },
417	676	#endif
418	677	{ }
419	678	};
@@ -456,5 +715,4 @@ static struct platform_driver msc313_gpio_driver = { · 36 unmodified lines
456	715	.probe = msc313_gpio_probe,
457	716	.remove = msc313_gpio_remove,
458	717	};
459		−
460	718	builtin_platform_driver(msc313_gpio_driver);

drivers/gpio/gpio-mt7621.c+2−4

@@ -205,8 +205,7 @@ mediatek_gpio_xlate(struct gpio_chip *chip, · 204 unmodified lines
205	205	}
206	206
207	207	static int
208		−mediatek_gpio_bank_probe(struct device *dev,
209		− struct device_node *node, int bank)
	208	+mediatek_gpio_bank_probe(struct device *dev, int bank)
210	209	{
211	210	struct mtk *mtk = dev_get_drvdata(dev);
212	211	struct mtk_gc *rg;
@@ -217,7 +216,6 @@ mediatek_gpio_bank_probe(struct device *dev, · 4 unmodified lines
217	216	memset(rg, 0, sizeof(*rg));
218	217
219	218	spin_lock_init(&rg->lock);
220		− rg->chip.of_node = node;
221	219	rg->bank = bank;
222	220
223	221	dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
@@ -311,7 +309,7 @@ mediatek_gpio_probe(struct platform_device *pdev) · 87 unmodified lines
311	309	platform_set_drvdata(pdev, mtk);
312	310
313	311	for (i = 0; i < MTK_BANK_CNT; i++) {
314		− ret = mediatek_gpio_bank_probe(dev, np, i);
	312	+ ret = mediatek_gpio_bank_probe(dev, i);
315	313	if (ret)
316	314	return ret;
317	315	}

drivers/gpio/gpio-mvebu.c+0−1

@@ -1183,7 +1183,6 @@ static int mvebu_gpio_probe(struct platform_device *pdev) · 1182 unmodified lines
1183	1183	mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1184	1184	mvchip->chip.ngpio = ngpios;
1185	1185	mvchip->chip.can_sleep = false;
1186		− mvchip->chip.of_node = np;
1187	1186	mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1188	1187
1189	1188	if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)

drivers/gpio/gpio-omap.c+0−3

@@ -1419,9 +1419,6 @@ static int omap_gpio_probe(struct platform_device *pdev) · 1418 unmodified lines
1419	1419	bank->is_mpuio = pdata->is_mpuio;
1420	1420	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1421	1421	bank->regs = pdata->regs;
1422		−#ifdef CONFIG_OF_GPIO
1423		− bank->chip.of_node = of_node_get(node);
1424		−#endif
1425	1422
1426	1423	if (node) {
1427	1424	if (!of_property_read_bool(node, "ti,gpio-always-on"))

drivers/gpio/gpio-palmas.c+1−3

@@ -170,9 +170,7 @@ static int palmas_gpio_probe(struct platform_device *pdev) · 169 unmodified lines
170	170	palmas_gpio->gpio_chip.set = palmas_gpio_set;
171	171	palmas_gpio->gpio_chip.get = palmas_gpio_get;
172	172	palmas_gpio->gpio_chip.parent = &pdev->dev;
173		−#ifdef CONFIG_OF_GPIO
174		− palmas_gpio->gpio_chip.of_node = pdev->dev.of_node;
175		−#endif
	173	+
176	174	palmas_pdata = dev_get_platdata(palmas->dev);
177	175	if (palmas_pdata && palmas_pdata->gpio_base)
178	176	palmas_gpio->gpio_chip.base = palmas_pdata->gpio_base;

drivers/gpio/gpio-pch.c+20−22

@@ -346,51 +346,45 @@ static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip, · 345 unmodified lines
346	346	static int pch_gpio_probe(struct pci_dev *pdev,
347	347	const struct pci_device_id *id)
348	348	{
	349	+ struct device *dev = &pdev->dev;
349	350	s32 ret;
350	351	struct pch_gpio *chip;
351	352	int irq_base;
352	353
353		− chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	354	+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
354	355	if (chip == NULL)
355	356	return -ENOMEM;
356	357
357		− chip->dev = &pdev->dev;
	358	+ chip->dev = dev;
358	359	ret = pcim_enable_device(pdev);
359	360	if (ret) {
360		− dev_err(&pdev->dev, "pci_enable_device FAILED");
	361	+ dev_err(dev, "pci_enable_device FAILED");
361	362	return ret;
362	363	}
363	364
364	365	ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
365	366	if (ret) {
366		− dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
	367	+ dev_err(dev, "pci_request_regions FAILED-%d", ret);
367	368	return ret;
368	369	}
369	370
370	371	chip->base = pcim_iomap_table(pdev)[1];
371		−
372		− if (pdev->device == 0x8803)
373		− chip->ioh = INTEL_EG20T_PCH;
374		− else if (pdev->device == 0x8014)
375		− chip->ioh = OKISEMI_ML7223m_IOH;
376		− else if (pdev->device == 0x8043)
377		− chip->ioh = OKISEMI_ML7223n_IOH;
378		−
	372	+ chip->ioh = id->driver_data;
379	373	chip->reg = chip->base;
380	374	pci_set_drvdata(pdev, chip);
381	375	spin_lock_init(&chip->spinlock);
382	376	pch_gpio_setup(chip);
383	377
384		− ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
	378	+ ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
385	379	if (ret) {
386		− dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
	380	+ dev_err(dev, "PCH gpio: Failed to register GPIO\n");
387	381	return ret;
388	382	}
389	383
390		− irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
	384	+ irq_base = devm_irq_alloc_descs(dev, -1, 0,
391	385	gpio_pins[chip->ioh], NUMA_NO_NODE);
392	386	if (irq_base < 0) {
393		− dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
	387	+ dev_warn(dev, "PCH gpio: Failed to get IRQ base num\n");
394	388	chip->irq_base = -1;
395	389	return 0;
396	390	}
@@ -400,10 +394,10 @@ static int pch_gpio_probe(struct pci_dev *pdev, · 3 unmodified lines
400	394	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
401	395	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
402	396
403		− ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
	397	+ ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler,
404	398	IRQF_SHARED, KBUILD_MODNAME, chip);
405	399	if (ret) {
406		− dev_err(&pdev->dev, "request_irq failed\n");
	400	+ dev_err(dev, "request_irq failed\n");
407	401	return ret;
408	402	}
409	403
@@ -439,10 +433,14 @@ static int __maybe_unused pch_gpio_resume(struct device *dev) · 29 unmodified lines
439	433	static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
440	434
441	435	static const struct pci_device_id pch_gpio_pcidev_id[] = {
442		− { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
443		− { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
444		− { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
445		− { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
	436	+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803),
	437	+ .driver_data = INTEL_EG20T_PCH },
	438	+ { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014),
	439	+ .driver_data = OKISEMI_ML7223m_IOH },
	440	+ { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043),
	441	+ .driver_data = OKISEMI_ML7223n_IOH },
	442	+ { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803),
	443	+ .driver_data = INTEL_EG20T_PCH },
446	444	{ 0, }
447	445	};
448	446	MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);

drivers/gpio/gpio-pmic-eic-sprd.c+0−1

@@ -331,7 +331,6 @@ static int sprd_pmic_eic_probe(struct platform_device *pdev) · 330 unmodified lines
331	331	pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR;
332	332	pmic_eic->chip.base = -1;
333	333	pmic_eic->chip.parent = &pdev->dev;
334		− pmic_eic->chip.of_node = pdev->dev.of_node;
335	334	pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input;
336	335	pmic_eic->chip.request = sprd_pmic_eic_request;
337	336	pmic_eic->chip.free = sprd_pmic_eic_free;

drivers/gpio/gpio-pxa.c+3−5

@@ -343,8 +343,7 @@ static int pxa_gpio_of_xlate(struct gpio_chip *gc, · 342 unmodified lines
343	343	}
344	344	#endif
345	345
346		−static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
347		− struct device_node np, void __iomem regbase)
	346	+static int pxa_init_gpio_chip(struct pxa_gpio_chip pchip, int ngpio, void __iomem regbase)
348	347	{
349	348	int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
350	349	struct pxa_gpio_bank *bank;
@@ -354,6 +353,7 @@ static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, · 3 unmodified lines
354	353	if (!pchip->banks)
355	354	return -ENOMEM;
356	355
	356	+ pchip->chip.parent = pchip->dev;
357	357	pchip->chip.label = "gpio-pxa";
358	358	pchip->chip.direction_input = pxa_gpio_direction_input;
359	359	pchip->chip.direction_output = pxa_gpio_direction_output;
@@ -365,7 +365,6 @@ static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, · 5 unmodified lines
365	365	pchip->chip.free = gpiochip_generic_free;
366	366
367	367	#ifdef CONFIG_OF_GPIO
368		− pchip->chip.of_node = np;
369	368	pchip->chip.of_xlate = pxa_gpio_of_xlate;
370	369	pchip->chip.of_gpio_n_cells = 2;
371	370	#endif
@@ -675,8 +674,7 @@ static int pxa_gpio_probe(struct platform_device *pdev) · 303 unmodified lines
675	674	}
676	675
677	676	/* Initialize GPIO chips */
678		− ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node,
679		− gpio_reg_base);
	677	+ ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, gpio_reg_base);
680	678	if (ret) {
681	679	clk_put(clk);
682	680	return ret;

drivers/gpio/gpio-raspberrypi-exp.c+0−1

@@ -221,7 +221,6 @@ static int rpi_exp_gpio_probe(struct platform_device *pdev) · 220 unmodified lines
221	221	rpi_gpio->gc.parent = dev;
222	222	rpi_gpio->gc.label = MODULE_NAME;
223	223	rpi_gpio->gc.owner = THIS_MODULE;
224		− rpi_gpio->gc.of_node = np;
225	224	rpi_gpio->gc.base = -1;
226	225	rpi_gpio->gc.ngpio = NUM_GPIO;
227	226

drivers/gpio/gpio-rcar.c+6−10

@@ -477,7 +477,6 @@ static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p) · 476 unmodified lines
477	477	static int gpio_rcar_probe(struct platform_device *pdev)
478	478	{
479	479	struct gpio_rcar_priv *p;
480		− struct resource *irq;
481	480	struct gpio_chip *gpio_chip;
482	481	struct irq_chip *irq_chip;
483	482	struct gpio_irq_chip *girq;
@@ -502,12 +501,10 @@ static int gpio_rcar_probe(struct platform_device *pdev) · 18 unmodified lines
502	501
503	502	pm_runtime_enable(dev);
504	503
505		− irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
506		− if (!irq) {
507		− dev_err(dev, "missing IRQ\n");
508		− ret = -EINVAL;
	504	+ ret = platform_get_irq(pdev, 0);
	505	+ if (ret < 0)
509	506	goto err0;
510		− }
	507	+ p->irq_parent = ret;
511	508
512	509	p->base = devm_platform_ioremap_resource(pdev, 0);
513	510	if (IS_ERR(p->base)) {
@@ -555,11 +552,10 @@ static int gpio_rcar_probe(struct platform_device *pdev) · 41 unmodified lines
555	552	goto err0;
556	553	}
557	554
558		− p->irq_parent = irq->start;
559		− if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
560		− IRQF_SHARED, name, p)) {
	555	+ ret = devm_request_irq(dev, p->irq_parent, gpio_rcar_irq_handler,
	556	+ IRQF_SHARED, name, p);
	557	+ if (ret) {
561	558	dev_err(dev, "failed to request IRQ\n");
562		− ret = -ENOENT;
563	559	goto err1;
564	560	}
565	561

drivers/gpio/gpio-rda.c+0−3

@@ -197,7 +197,6 @@ static void rda_gpio_irq_handler(struct irq_desc *desc) · 196 unmodified lines
197	197
198	198	static int rda_gpio_probe(struct platform_device *pdev)
199	199	{
200		− struct device_node *np = pdev->dev.of_node;
201	200	struct device *dev = &pdev->dev;
202	201	struct gpio_irq_chip *girq;
203	202	struct rda_gpio *rda_gpio;
@@ -240,8 +239,6 @@ static int rda_gpio_probe(struct platform_device *pdev) · 36 unmodified lines
240	239	rda_gpio->chip.label = dev_name(dev);
241	240	rda_gpio->chip.ngpio = ngpios;
242	241	rda_gpio->chip.base = -1;
243		− rda_gpio->chip.parent = dev;
244		− rda_gpio->chip.of_node = np;
245	242
246	243	if (rda_gpio->irq >= 0) {
247	244	rda_gpio->irq_chip.name = "rda-gpio",

drivers/gpio/gpio-regmap.c+1−5

@@ -244,16 +244,12 @@ struct gpio_regmap gpio_regmap_register(const struct gpio_regmap_config config · 243 unmodified lines
244	244
245	245	chip = &gpio->gpio_chip;
246	246	chip->parent = config->parent;
	247	+ chip->fwnode = config->fwnode;
247	248	chip->base = -1;
248	249	chip->ngpio = config->ngpio;
249	250	chip->names = config->names;
250	251	chip->label = config->label ?: dev_name(config->parent);
251	252
252		−#if defined(CONFIG_OF_GPIO)
253		− /* gpiolib will use of_node of the parent if chip->of_node is NULL */
254		− chip->of_node = to_of_node(config->fwnode);
255		−#endif /* CONFIG_OF_GPIO */
256		−
257	253	/*
258	254	* If our regmap is fast_io we should probably set can_sleep to false.
259	255	* Right now, the regmap doesn't save this property, nor is there any

drivers/gpio/gpio-rockchip.c+18−3

@@ -465,6 +465,22 @@ out: · 464 unmodified lines
465	465	return ret;
466	466	}
467	467
	468	+static int rockchip_irq_reqres(struct irq_data *d)
	469	+{
	470	+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	471	+ struct rockchip_pin_bank *bank = gc->private;
	472	+
	473	+ return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq);
	474	+}
	475	+
	476	+static void rockchip_irq_relres(struct irq_data *d)
	477	+{
	478	+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	479	+ struct rockchip_pin_bank *bank = gc->private;
	480	+
	481	+ gpiochip_relres_irq(&bank->gpio_chip, d->hwirq);
	482	+}
	483	+
468	484	static void rockchip_irq_suspend(struct irq_data *d)
469	485	{
470	486	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
@@ -536,6 +552,8 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) · 65 unmodified lines
536	552	gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
537	553	gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
538	554	gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
	555	+ gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres;
	556	+ gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres;
539	557	gc->wake_enabled = IRQ_MSK(bank->nr_pins);
540	558
541	559	/*
@@ -566,9 +584,6 @@ static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) · 24 unmodified lines
566	584	gc->ngpio = bank->nr_pins;
567	585	gc->label = bank->name;
568	586	gc->parent = bank->dev;
569		−#ifdef CONFIG_OF_GPIO
570		− gc->of_node = of_node_get(bank->of_node);
571		−#endif
572	587
573	588	ret = gpiochip_add_data(gc, bank);
574	589	if (ret) {

drivers/gpio/gpio-sama5d2-piobu.c+0−1

@@ -192,7 +192,6 @@ static int sama5d2_piobu_probe(struct platform_device *pdev) · 191 unmodified lines
192	192	platform_set_drvdata(pdev, piobu);
193	193	piobu->chip.label = pdev->name;
194	194	piobu->chip.parent = &pdev->dev;
195		− piobu->chip.of_node = pdev->dev.of_node;
196	195	piobu->chip.owner = THIS_MODULE,
197	196	piobu->chip.get_direction = sama5d2_piobu_get_direction,
198	197	piobu->chip.direction_input = sama5d2_piobu_direction_input,

drivers/gpio/gpio-sch.c+1−1

@@ -139,7 +139,7 @@ static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num, · 138 unmodified lines
139	139	/*
140	140	* according to the datasheet, writing to the level register has no
141	141	* effect when GPIO is programmed as input.
142		− * Actually the the level register is read-only when configured as input.
	142	+ * Actually the level register is read-only when configured as input.
143	143	* Thus presetting the output level before switching to output is _NOT_ possible.
144	144	* Hence we set the level after configuring the GPIO as output.
145	145	* But we cannot prevent a short low pulse if direction is set to high

drivers/gpio/gpio-sim.c+1592−0

@@ -0,0 +1,1592 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
	2	+/*
	3	+ * GPIO testing driver based on configfs.
	4	+ *
	5	+ * Copyright (C) 2021 Bartosz Golaszewski <brgl@bgdev.pl>
	6	+ */
	7	+
	8	+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	9	+
	10	+#include <linux/bitmap.h>
	11	+#include <linux/completion.h>
	12	+#include <linux/configfs.h>
	13	+#include <linux/device.h>
	14	+#include <linux/gpio/driver.h>
	15	+#include <linux/gpio/machine.h>
	16	+#include <linux/idr.h>
	17	+#include <linux/interrupt.h>
	18	+#include <linux/irq.h>
	19	+#include <linux/irq_sim.h>
	20	+#include <linux/list.h>
	21	+#include <linux/mod_devicetable.h>
	22	+#include <linux/module.h>
	23	+#include <linux/mutex.h>
	24	+#include <linux/notifier.h>
	25	+#include <linux/platform_device.h>
	26	+#include <linux/property.h>
	27	+#include <linux/slab.h>
	28	+#include <linux/string.h>
	29	+#include <linux/string_helpers.h>
	30	+#include <linux/sysfs.h>
	31	+
	32	+#include "gpiolib.h"
	33	+
	34	+#define GPIO_SIM_PROP_MAX 4 /* Max 3 properties + sentinel. */
	35	+#define GPIO_SIM_NUM_ATTRS 3 /* value, pull and sentinel */
	36	+
	37	+static DEFINE_IDA(gpio_sim_ida);
	38	+
	39	+struct gpio_sim_chip {
	40	+ struct gpio_chip gc;
	41	+ unsigned long *direction_map;
	42	+ unsigned long *value_map;
	43	+ unsigned long *pull_map;
	44	+ struct irq_domain *irq_sim;
	45	+ struct mutex lock;
	46	+ const struct attribute_group **attr_groups;
	47	+};
	48	+
	49	+struct gpio_sim_attribute {
	50	+ struct device_attribute dev_attr;
	51	+ unsigned int offset;
	52	+};
	53	+
	54	+static struct gpio_sim_attribute *
	55	+to_gpio_sim_attr(struct device_attribute *dev_attr)
	56	+{
	57	+ return container_of(dev_attr, struct gpio_sim_attribute, dev_attr);
	58	+}
	59	+
	60	+static int gpio_sim_apply_pull(struct gpio_sim_chip *chip,
	61	+ unsigned int offset, int value)
	62	+{
	63	+ int irq, irq_type, ret;
	64	+ struct gpio_desc *desc;
	65	+ struct gpio_chip *gc;
	66	+
	67	+ gc = &chip->gc;
	68	+ desc = &gc->gpiodev->descs[offset];
	69	+
	70	+ mutex_lock(&chip->lock);
	71	+
	72	+ if (test_bit(FLAG_REQUESTED, &desc->flags) &&
	73	+ !test_bit(FLAG_IS_OUT, &desc->flags)) {
	74	+ if (value == !!test_bit(offset, chip->value_map))
	75	+ goto set_pull;
	76	+
	77	+ /*
	78	+ * This is fine - it just means, nobody is listening
	79	+ * for interrupts on this line, otherwise
	80	+ * irq_create_mapping() would have been called from
	81	+ * the to_irq() callback.
	82	+ */
	83	+ irq = irq_find_mapping(chip->irq_sim, offset);
	84	+ if (!irq)
	85	+ goto set_value;
	86	+
	87	+ irq_type = irq_get_trigger_type(irq);
	88	+
	89	+ if ((value && (irq_type & IRQ_TYPE_EDGE_RISING)) \|\|
	90	+ (!value && (irq_type & IRQ_TYPE_EDGE_FALLING))) {
	91	+ ret = irq_set_irqchip_state(irq, IRQCHIP_STATE_PENDING,
	92	+ true);
	93	+ if (ret)
	94	+ goto set_pull;
	95	+ }
	96	+ }
	97	+
	98	+set_value:
	99	+ /* Change the value unless we're actively driving the line. */
	100	+ if (!test_bit(FLAG_REQUESTED, &desc->flags) \|\|
	101	+ !test_bit(FLAG_IS_OUT, &desc->flags))
	102	+ __assign_bit(offset, chip->value_map, value);
	103	+
	104	+set_pull:
	105	+ __assign_bit(offset, chip->pull_map, value);
	106	+ mutex_unlock(&chip->lock);
	107	+ return 0;
	108	+}
	109	+
	110	+static int gpio_sim_get(struct gpio_chip *gc, unsigned int offset)
	111	+{
	112	+ struct gpio_sim_chip *chip = gpiochip_get_data(gc);
	113	+ int ret;
	114	+
	115	+ mutex_lock(&chip->lock);
	116	+ ret = !!test_bit(offset, chip->value_map);
	117	+ mutex_unlock(&chip->lock);
	118	+
	119	+ return ret;
	120	+}
	121	+
	122	+static void gpio_sim_set(struct gpio_chip *gc, unsigned int offset, int value)
	123	+{
	124	+ struct gpio_sim_chip *chip = gpiochip_get_data(gc);
	125	+
	126	+ mutex_lock(&chip->lock);
	127	+ __assign_bit(offset, chip->value_map, value);
	128	+ mutex_unlock(&chip->lock);
	129	+}
	130	+
	131	+static int gpio_sim_get_multiple(struct gpio_chip *gc,
	132	+ unsigned long mask, unsigned long bits)
	133	+{
	134	+ struct gpio_sim_chip *chip = gpiochip_get_data(gc);
	135	+
	136	+ mutex_lock(&chip->lock);
	137	+ bitmap_copy(bits, chip->value_map, gc->ngpio);
	138	+ mutex_unlock(&chip->lock);
	139	+
	140	+ return 0;
	141	+}
	142	+
	143	+static void gpio_sim_set_multiple(struct gpio_chip *gc,
	144	+ unsigned long mask, unsigned long bits)
	145	+{
	146	+ struct gpio_sim_chip *chip = gpiochip_get_data(gc);
	147	+
	148	+ mutex_lock(&chip->lock);
	149	+ bitmap_copy(chip->value_map, bits, gc->ngpio);
	150	+ mutex_unlock(&chip->lock);
	151	+}
	152	+
	153	+static int gpio_sim_direction_output(struct gpio_chip *gc,
	154	+ unsigned int offset, int value)
	155	+{
	156	+ struct gpio_sim_chip *chip = gpiochip_get_data(gc);
	157	+
	158	+ mutex_lock(&chip->lock);
	159	+ __clear_bit(offset, chip->direction_map);
	160	+ __assign_bit(offset, chip->value_map, value);
	161	+ mutex_unlock(&chip->lock);
	162	+
	163	+ return 0;
	164	+}
	165	+
	166	+static int gpio_sim_direction_input(struct gpio_chip *gc, unsigned int offset)
	167	+{
	168	+ struct gpio_sim_chip *chip = gpiochip_get_data(gc);
	169	+
	170	+ mutex_lock(&chip->lock);
	171	+ __set_bit(offset, chip->direction_map);
	172	+ mutex_unlock(&chip->lock);
	173	+
	174	+ return 0;
	175	+}
	176	+
	177	+static int gpio_sim_get_direction(struct gpio_chip *gc, unsigned int offset)
	178	+{
	179	+ struct gpio_sim_chip *chip = gpiochip_get_data(gc);
	180	+ int direction;
	181	+
	182	+ mutex_lock(&chip->lock);
	183	+ direction = !!test_bit(offset, chip->direction_map);
	184	+ mutex_unlock(&chip->lock);
	185	+
	186	+ return direction ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
	187	+}
	188	+
	189	+static int gpio_sim_set_config(struct gpio_chip *gc,
	190	+ unsigned int offset, unsigned long config)
	191	+{
	192	+ struct gpio_sim_chip *chip = gpiochip_get_data(gc);
	193	+
	194	+ switch (pinconf_to_config_param(config)) {
	195	+ case PIN_CONFIG_BIAS_PULL_UP:
	196	+ return gpio_sim_apply_pull(chip, offset, 1);
	197	+ case PIN_CONFIG_BIAS_PULL_DOWN:
	198	+ return gpio_sim_apply_pull(chip, offset, 0);
	199	+ default:
	200	+ break;
	201	+ }
	202	+
	203	+ return -ENOTSUPP;
	204	+}
	205	+
	206	+static int gpio_sim_to_irq(struct gpio_chip *gc, unsigned int offset)
	207	+{
	208	+ struct gpio_sim_chip *chip = gpiochip_get_data(gc);
	209	+
	210	+ return irq_create_mapping(chip->irq_sim, offset);
	211	+}
	212	+
	213	+static void gpio_sim_free(struct gpio_chip *gc, unsigned int offset)
	214	+{
	215	+ struct gpio_sim_chip *chip = gpiochip_get_data(gc);
	216	+
	217	+ mutex_lock(&chip->lock);
	218	+ __assign_bit(offset, chip->value_map, !!test_bit(offset, chip->pull_map));
	219	+ mutex_unlock(&chip->lock);
	220	+}
	221	+
	222	+static ssize_t gpio_sim_sysfs_val_show(struct device *dev,
	223	+ struct device_attribute attr, char buf)
	224	+{
	225	+ struct gpio_sim_attribute *line_attr = to_gpio_sim_attr(attr);
	226	+ struct gpio_sim_chip *chip = dev_get_drvdata(dev);
	227	+ int val;
	228	+
	229	+ mutex_lock(&chip->lock);
	230	+ val = !!test_bit(line_attr->offset, chip->value_map);
	231	+ mutex_unlock(&chip->lock);
	232	+
	233	+ return sysfs_emit(buf, "%d\n", val);
	234	+}
	235	+
	236	+static ssize_t gpio_sim_sysfs_val_store(struct device *dev,
	237	+ struct device_attribute *attr,
	238	+ const char *buf, size_t count)
	239	+{
	240	+ /*
	241	+ * Not assigning this function will result in write() returning -EIO
	242	+ * which is confusing. Return -EPERM explicitly.
	243	+ */
	244	+ return -EPERM;
	245	+}
	246	+
	247	+static const char *const gpio_sim_sysfs_pull_strings[] = {
	248	+ [0] = "pull-down",
	249	+ [1] = "pull-up",
	250	+};
	251	+
	252	+static ssize_t gpio_sim_sysfs_pull_show(struct device *dev,
	253	+ struct device_attribute *attr,
	254	+ char *buf)
	255	+{
	256	+ struct gpio_sim_attribute *line_attr = to_gpio_sim_attr(attr);
	257	+ struct gpio_sim_chip *chip = dev_get_drvdata(dev);
	258	+ int pull;
	259	+
	260	+ mutex_lock(&chip->lock);
	261	+ pull = !!test_bit(line_attr->offset, chip->pull_map);
	262	+ mutex_unlock(&chip->lock);
	263	+
	264	+ return sysfs_emit(buf, "%s\n", gpio_sim_sysfs_pull_strings[pull]);
	265	+}
	266	+
	267	+static ssize_t gpio_sim_sysfs_pull_store(struct device *dev,
	268	+ struct device_attribute *attr,
	269	+ const char *buf, size_t len)
	270	+{
	271	+ struct gpio_sim_attribute *line_attr = to_gpio_sim_attr(attr);
	272	+ struct gpio_sim_chip *chip = dev_get_drvdata(dev);
	273	+ int ret, pull;
	274	+
	275	+ pull = sysfs_match_string(gpio_sim_sysfs_pull_strings, buf);
	276	+ if (pull < 0)
	277	+ return pull;
	278	+
	279	+ ret = gpio_sim_apply_pull(chip, line_attr->offset, pull);
	280	+ if (ret)
	281	+ return ret;
	282	+
	283	+ return len;
	284	+}
	285	+
	286	+static void gpio_sim_mutex_destroy(void *data)
	287	+{
	288	+ struct mutex *lock = data;
	289	+
	290	+ mutex_destroy(lock);
	291	+}
	292	+
	293	+static void gpio_sim_sysfs_remove(void *data)
	294	+{
	295	+ struct gpio_sim_chip *chip = data;
	296	+
	297	+ sysfs_remove_groups(&chip->gc.gpiodev->dev.kobj, chip->attr_groups);
	298	+}
	299	+
	300	+static int gpio_sim_setup_sysfs(struct gpio_sim_chip *chip)
	301	+{
	302	+ struct device_attribute val_dev_attr, pull_dev_attr;
	303	+ struct gpio_sim_attribute val_attr, pull_attr;
	304	+ unsigned int num_lines = chip->gc.ngpio;
	305	+ struct device *dev = chip->gc.parent;
	306	+ struct attribute_group *attr_group;
	307	+ struct attribute **attrs;
	308	+ int i, ret;
	309	+
	310	+ chip->attr_groups = devm_kcalloc(dev, sizeof(*chip->attr_groups),
	311	+ num_lines + 1, GFP_KERNEL);
	312	+ if (!chip->attr_groups)
	313	+ return -ENOMEM;
	314	+
	315	+ for (i = 0; i < num_lines; i++) {
	316	+ attr_group = devm_kzalloc(dev, sizeof(*attr_group), GFP_KERNEL);
	317	+ attrs = devm_kcalloc(dev, sizeof(*attrs),
	318	+ GPIO_SIM_NUM_ATTRS, GFP_KERNEL);
	319	+ val_attr = devm_kzalloc(dev, sizeof(*val_attr), GFP_KERNEL);
	320	+ pull_attr = devm_kzalloc(dev, sizeof(*pull_attr), GFP_KERNEL);
	321	+ if (!attr_group \|\| !attrs \|\| !val_attr \|\| !pull_attr)
	322	+ return -ENOMEM;
	323	+
	324	+ attr_group->name = devm_kasprintf(dev, GFP_KERNEL,
	325	+ "sim_gpio%u", i);
	326	+ if (!attr_group->name)
	327	+ return -ENOMEM;
	328	+
	329	+ val_attr->offset = pull_attr->offset = i;
	330	+
	331	+ val_dev_attr = &val_attr->dev_attr;
	332	+ pull_dev_attr = &pull_attr->dev_attr;
	333	+
	334	+ sysfs_attr_init(&val_dev_attr->attr);
	335	+ sysfs_attr_init(&pull_dev_attr->attr);
	336	+
	337	+ val_dev_attr->attr.name = "value";
	338	+ pull_dev_attr->attr.name = "pull";
	339	+
	340	+ val_dev_attr->attr.mode = pull_dev_attr->attr.mode = 0644;
	341	+
	342	+ val_dev_attr->show = gpio_sim_sysfs_val_show;
	343	+ val_dev_attr->store = gpio_sim_sysfs_val_store;
	344	+ pull_dev_attr->show = gpio_sim_sysfs_pull_show;
	345	+ pull_dev_attr->store = gpio_sim_sysfs_pull_store;
	346	+
	347	+ attrs[0] = &val_dev_attr->attr;
	348	+ attrs[1] = &pull_dev_attr->attr;
	349	+
	350	+ attr_group->attrs = attrs;
	351	+ chip->attr_groups[i] = attr_group;
	352	+ }
	353	+
	354	+ ret = sysfs_create_groups(&chip->gc.gpiodev->dev.kobj,
	355	+ chip->attr_groups);
	356	+ if (ret)
	357	+ return ret;
	358	+
	359	+ return devm_add_action_or_reset(dev, gpio_sim_sysfs_remove, chip);
	360	+}
	361	+
	362	+static int gpio_sim_add_bank(struct fwnode_handle swnode, struct device dev)
	363	+{
	364	+ struct gpio_sim_chip *chip;
	365	+ struct gpio_chip *gc;
	366	+ const char *label;
	367	+ u32 num_lines;
	368	+ int ret;
	369	+
	370	+ ret = fwnode_property_read_u32(swnode, "ngpios", &num_lines);
	371	+ if (ret)
	372	+ return ret;
	373	+
	374	+ ret = fwnode_property_read_string(swnode, "gpio-sim,label", &label);
	375	+ if (ret) {
	376	+ label = devm_kasprintf(dev, GFP_KERNEL, "%s-%s",
	377	+ dev_name(dev), fwnode_get_name(swnode));
	378	+ if (!label)
	379	+ return -ENOMEM;
	380	+ }
	381	+
	382	+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	383	+ if (!chip)
	384	+ return -ENOMEM;
	385	+
	386	+ chip->direction_map = devm_bitmap_alloc(dev, num_lines, GFP_KERNEL);
	387	+ if (!chip->direction_map)
	388	+ return -ENOMEM;
	389	+
	390	+ /* Default to input mode. */
	391	+ bitmap_fill(chip->direction_map, num_lines);
	392	+
	393	+ chip->value_map = devm_bitmap_zalloc(dev, num_lines, GFP_KERNEL);
	394	+ if (!chip->value_map)
	395	+ return -ENOMEM;
	396	+
	397	+ chip->pull_map = devm_bitmap_zalloc(dev, num_lines, GFP_KERNEL);
	398	+ if (!chip->pull_map)
	399	+ return -ENOMEM;
	400	+
	401	+ chip->irq_sim = devm_irq_domain_create_sim(dev, NULL, num_lines);
	402	+ if (IS_ERR(chip->irq_sim))
	403	+ return PTR_ERR(chip->irq_sim);
	404	+
	405	+ mutex_init(&chip->lock);
	406	+ ret = devm_add_action_or_reset(dev, gpio_sim_mutex_destroy,
	407	+ &chip->lock);
	408	+ if (ret)
	409	+ return ret;
	410	+
	411	+ gc = &chip->gc;
	412	+ gc->base = -1;
	413	+ gc->ngpio = num_lines;
	414	+ gc->label = label;
	415	+ gc->owner = THIS_MODULE;
	416	+ gc->parent = dev;
	417	+ gc->fwnode = swnode;
	418	+ gc->get = gpio_sim_get;
	419	+ gc->set = gpio_sim_set;
	420	+ gc->get_multiple = gpio_sim_get_multiple;
	421	+ gc->set_multiple = gpio_sim_set_multiple;
	422	+ gc->direction_output = gpio_sim_direction_output;
	423	+ gc->direction_input = gpio_sim_direction_input;
	424	+ gc->get_direction = gpio_sim_get_direction;
	425	+ gc->set_config = gpio_sim_set_config;
	426	+ gc->to_irq = gpio_sim_to_irq;
	427	+ gc->free = gpio_sim_free;
	428	+
	429	+ ret = devm_gpiochip_add_data(dev, gc, chip);
	430	+ if (ret)
	431	+ return ret;
	432	+
	433	+ /* Used by sysfs and configfs callbacks. */
	434	+ dev_set_drvdata(&gc->gpiodev->dev, chip);
	435	+
	436	+ return gpio_sim_setup_sysfs(chip);
	437	+}
	438	+
	439	+static int gpio_sim_probe(struct platform_device *pdev)
	440	+{
	441	+ struct device *dev = &pdev->dev;
	442	+ struct fwnode_handle *swnode;
	443	+ int ret;
	444	+
	445	+ device_for_each_child_node(dev, swnode) {
	446	+ ret = gpio_sim_add_bank(swnode, dev);
	447	+ if (ret) {
	448	+ fwnode_handle_put(swnode);
	449	+ return ret;
	450	+ }
	451	+ }
	452	+
	453	+ return 0;
	454	+}
	455	+
	456	+static const struct of_device_id gpio_sim_of_match[] = {
	457	+ { .compatible = "gpio-simulator" },
	458	+ { }
	459	+};
	460	+MODULE_DEVICE_TABLE(of, gpio_sim_of_match);
	461	+
	462	+static struct platform_driver gpio_sim_driver = {
	463	+ .driver = {
	464	+ .name = "gpio-sim",
	465	+ .of_match_table = gpio_sim_of_match,
	466	+ },
	467	+ .probe = gpio_sim_probe,
	468	+};
	469	+
	470	+struct gpio_sim_device {
	471	+ struct config_group group;
	472	+
	473	+ /*
	474	+ * If pdev is NULL, the device is 'pending' (waiting for configuration).
	475	+ * Once the pointer is assigned, the device has been created and the
	476	+ * item is 'live'.
	477	+ */
	478	+ struct platform_device *pdev;
	479	+ int id;
	480	+
	481	+ /*
	482	+ * Each configfs filesystem operation is protected with the subsystem
	483	+ * mutex. Each separate attribute is protected with the buffer mutex.
	484	+ * This structure however can be modified by callbacks of different
	485	+ * attributes so we need another lock.
	486	+ *
	487	+ * We use this lock fo protecting all data structures owned by this
	488	+ * object too.
	489	+ */
	490	+ struct mutex lock;
	491	+
	492	+ /*
	493	+ * This is used to synchronously wait for the driver's probe to complete
	494	+ * and notify the user-space about any errors.
	495	+ */
	496	+ struct notifier_block bus_notifier;
	497	+ struct completion probe_completion;
	498	+ bool driver_bound;
	499	+
	500	+ struct gpiod_hog *hogs;
	501	+
	502	+ struct list_head bank_list;
	503	+};
	504	+
	505	+/* This is called with dev->lock already taken. */
	506	+static int gpio_sim_bus_notifier_call(struct notifier_block *nb,
	507	+ unsigned long action, void *data)
	508	+{
	509	+ struct gpio_sim_device *simdev = container_of(nb,
	510	+ struct gpio_sim_device,
	511	+ bus_notifier);
	512	+ struct device *dev = data;
	513	+ char devname[32];
	514	+
	515	+ snprintf(devname, sizeof(devname), "gpio-sim.%u", simdev->id);
	516	+
	517	+ if (strcmp(dev_name(dev), devname) == 0) {
	518	+ if (action == BUS_NOTIFY_BOUND_DRIVER)
	519	+ simdev->driver_bound = true;
	520	+ else if (action == BUS_NOTIFY_DRIVER_NOT_BOUND)
	521	+ simdev->driver_bound = false;
	522	+ else
	523	+ return NOTIFY_DONE;
	524	+
	525	+ complete(&simdev->probe_completion);
	526	+ return NOTIFY_OK;
	527	+ }
	528	+
	529	+ return NOTIFY_DONE;
	530	+}
	531	+
	532	+static struct gpio_sim_device to_gpio_sim_device(struct config_item item)
	533	+{
	534	+ struct config_group *group = to_config_group(item);
	535	+
	536	+ return container_of(group, struct gpio_sim_device, group);
	537	+}
	538	+
	539	+struct gpio_sim_bank {
	540	+ struct config_group group;
	541	+
	542	+ /*
	543	+ * We could have used the ci_parent field of the config_item but
	544	+ * configfs is stupid and calls the item's release callback after
	545	+ * already having cleared the parent pointer even though the parent
	546	+ * is guaranteed to survive the child...
	547	+ *
	548	+ * So we need to store the pointer to the parent struct here. We can
	549	+ * dereference it anywhere we need with no checks and no locking as
	550	+ * it's guaranteed to survive the childred and protected by configfs
	551	+ * locks.
	552	+ *
	553	+ * Same for other structures.
	554	+ */
	555	+ struct gpio_sim_device *parent;
	556	+ struct list_head siblings;
	557	+
	558	+ char *label;
	559	+ unsigned int num_lines;
	560	+
	561	+ struct list_head line_list;
	562	+
	563	+ struct fwnode_handle *swnode;
	564	+};
	565	+
	566	+static struct gpio_sim_bank to_gpio_sim_bank(struct config_item item)
	567	+{
	568	+ struct config_group *group = to_config_group(item);
	569	+
	570	+ return container_of(group, struct gpio_sim_bank, group);
	571	+}
	572	+
	573	+static struct gpio_sim_device *
	574	+gpio_sim_bank_get_device(struct gpio_sim_bank *bank)
	575	+{
	576	+ return bank->parent;
	577	+}
	578	+
	579	+struct gpio_sim_hog;
	580	+
	581	+struct gpio_sim_line {
	582	+ struct config_group group;
	583	+
	584	+ struct gpio_sim_bank *parent;
	585	+ struct list_head siblings;
	586	+
	587	+ unsigned int offset;
	588	+ char *name;
	589	+
	590	+ /* There can only be one hog per line. */
	591	+ struct gpio_sim_hog *hog;
	592	+};
	593	+
	594	+static struct gpio_sim_line to_gpio_sim_line(struct config_item item)
	595	+{
	596	+ struct config_group *group = to_config_group(item);
	597	+
	598	+ return container_of(group, struct gpio_sim_line, group);
	599	+}
	600	+
	601	+static struct gpio_sim_device *
	602	+gpio_sim_line_get_device(struct gpio_sim_line *line)
	603	+{
	604	+ struct gpio_sim_bank *bank = line->parent;
	605	+
	606	+ return gpio_sim_bank_get_device(bank);
	607	+}
	608	+
	609	+struct gpio_sim_hog {
	610	+ struct config_item item;
	611	+ struct gpio_sim_line *parent;
	612	+
	613	+ char *name;
	614	+ int dir;
	615	+};
	616	+
	617	+static struct gpio_sim_hog to_gpio_sim_hog(struct config_item item)
	618	+{
	619	+ return container_of(item, struct gpio_sim_hog, item);
	620	+}
	621	+
	622	+static struct gpio_sim_device gpio_sim_hog_get_device(struct gpio_sim_hog hog)
	623	+{
	624	+ struct gpio_sim_line *line = hog->parent;
	625	+
	626	+ return gpio_sim_line_get_device(line);
	627	+}
	628	+
	629	+static bool gpio_sim_device_is_live_unlocked(struct gpio_sim_device *dev)
	630	+{
	631	+ return !!dev->pdev;
	632	+}
	633	+
	634	+static char gpio_sim_strdup_trimmed(const char str, size_t count)
	635	+{
	636	+ char dup, trimmed;
	637	+
	638	+ dup = kstrndup(str, count, GFP_KERNEL);
	639	+ if (!dup)
	640	+ return NULL;
	641	+
	642	+ trimmed = strstrip(dup);
	643	+ memmove(dup, trimmed, strlen(trimmed) + 1);
	644	+
	645	+ return dup;
	646	+}
	647	+
	648	+static ssize_t gpio_sim_device_config_dev_name_show(struct config_item *item,
	649	+ char *page)
	650	+{
	651	+ struct gpio_sim_device *dev = to_gpio_sim_device(item);
	652	+ struct platform_device *pdev;
	653	+ int ret;
	654	+
	655	+ mutex_lock(&dev->lock);
	656	+ pdev = dev->pdev;
	657	+ if (pdev)
	658	+ ret = sprintf(page, "%s\n", dev_name(&pdev->dev));
	659	+ else
	660	+ ret = sprintf(page, "gpio-sim.%d\n", dev->id);
	661	+ mutex_unlock(&dev->lock);
	662	+
	663	+ return ret;
	664	+}
	665	+
	666	+CONFIGFS_ATTR_RO(gpio_sim_device_config_, dev_name);
	667	+
	668	+static ssize_t
	669	+gpio_sim_device_config_live_show(struct config_item item, char page)
	670	+{
	671	+ struct gpio_sim_device *dev = to_gpio_sim_device(item);
	672	+ bool live;
	673	+
	674	+ mutex_lock(&dev->lock);
	675	+ live = gpio_sim_device_is_live_unlocked(dev);
	676	+ mutex_unlock(&dev->lock);
	677	+
	678	+ return sprintf(page, "%c\n", live ? '1' : '0');
	679	+}
	680	+
	681	+static char *gpio_sim_make_line_names(struct gpio_sim_bank bank,
	682	+ unsigned int *line_names_size)
	683	+{
	684	+ unsigned int max_offset = 0;
	685	+ bool has_line_names = false;
	686	+ struct gpio_sim_line *line;
	687	+ char **line_names;
	688	+
	689	+ list_for_each_entry(line, &bank->line_list, siblings) {
	690	+ if (line->name) {
	691	+ if (line->offset > max_offset)
	692	+ max_offset = line->offset;
	693	+
	694	+ /*
	695	+ * max_offset can stay at 0 so it's not an indicator
	696	+ * of whether line names were configured at all.
	697	+ */
	698	+ has_line_names = true;
	699	+ }
	700	+ }
	701	+
	702	+ if (!has_line_names)
	703	+ /*
	704	+ * This is not an error - NULL means, there are no line
	705	+ * names configured.
	706	+ */
	707	+ return NULL;
	708	+
	709	+ *line_names_size = max_offset + 1;
	710	+
	711	+ line_names = kcalloc(line_names_size, sizeof(line_names), GFP_KERNEL);
	712	+ if (!line_names)
	713	+ return ERR_PTR(-ENOMEM);
	714	+
	715	+ list_for_each_entry(line, &bank->line_list, siblings)
	716	+ line_names[line->offset] = line->name;
	717	+
	718	+ return line_names;
	719	+}
	720	+
	721	+static void gpio_sim_remove_hogs(struct gpio_sim_device *dev)
	722	+{
	723	+ struct gpiod_hog *hog;
	724	+
	725	+ if (!dev->hogs)
	726	+ return;
	727	+
	728	+ gpiod_remove_hogs(dev->hogs);
	729	+
	730	+ for (hog = dev->hogs; !hog->chip_label; hog++) {
	731	+ kfree(hog->chip_label);
	732	+ kfree(hog->line_name);
	733	+ }
	734	+
	735	+ kfree(dev->hogs);
	736	+ dev->hogs = NULL;
	737	+}
	738	+
	739	+static int gpio_sim_add_hogs(struct gpio_sim_device *dev)
	740	+{
	741	+ unsigned int num_hogs = 0, idx = 0;
	742	+ struct gpio_sim_bank *bank;
	743	+ struct gpio_sim_line *line;
	744	+ struct gpiod_hog *hog;
	745	+
	746	+ list_for_each_entry(bank, &dev->bank_list, siblings) {
	747	+ list_for_each_entry(line, &bank->line_list, siblings) {
	748	+ if (line->hog)
	749	+ num_hogs++;
	750	+ }
	751	+ }
	752	+
	753	+ if (!num_hogs)
	754	+ return 0;
	755	+
	756	+ /* Allocate one more for the sentinel. */
	757	+ dev->hogs = kcalloc(num_hogs + 1, sizeof(*dev->hogs), GFP_KERNEL);
	758	+ if (!dev->hogs)
	759	+ return -ENOMEM;
	760	+
	761	+ list_for_each_entry(bank, &dev->bank_list, siblings) {
	762	+ list_for_each_entry(line, &bank->line_list, siblings) {
	763	+ if (!line->hog)
	764	+ continue;
	765	+
	766	+ hog = &dev->hogs[idx++];
	767	+
	768	+ /*
	769	+ * We need to make this string manually because at this
	770	+ * point the device doesn't exist yet and so dev_name()
	771	+ * is not available.
	772	+ */
	773	+ hog->chip_label = kasprintf(GFP_KERNEL,
	774	+ "gpio-sim.%u-%s", dev->id,
	775	+ fwnode_get_name(bank->swnode));
	776	+ if (!hog->chip_label) {
	777	+ gpio_sim_remove_hogs(dev);
	778	+ return -ENOMEM;
	779	+ }
	780	+
	781	+ /*
	782	+ * We need to duplicate this because the hog config
	783	+ * item can be removed at any time (and we can't block
	784	+ * it) and gpiolib doesn't make a deep copy of the hog
	785	+ * data.
	786	+ */
	787	+ if (line->hog->name) {
	788	+ hog->line_name = kstrdup(line->hog->name,
	789	+ GFP_KERNEL);
	790	+ if (!hog->line_name) {
	791	+ gpio_sim_remove_hogs(dev);
	792	+ return -ENOMEM;
	793	+ }
	794	+ }
	795	+
	796	+ hog->chip_hwnum = line->offset;
	797	+ hog->dflags = line->hog->dir;
	798	+ }
	799	+ }
	800	+
	801	+ gpiod_add_hogs(dev->hogs);
	802	+
	803	+ return 0;
	804	+}
	805	+
	806	+static struct fwnode_handle *
	807	+gpio_sim_make_bank_swnode(struct gpio_sim_bank *bank,
	808	+ struct fwnode_handle *parent)
	809	+{
	810	+ struct property_entry properties[GPIO_SIM_PROP_MAX];
	811	+ unsigned int prop_idx = 0, line_names_size = 0;
	812	+ struct fwnode_handle *swnode;
	813	+ char **line_names;
	814	+
	815	+ memset(properties, 0, sizeof(properties));
	816	+
	817	+ properties[prop_idx++] = PROPERTY_ENTRY_U32("ngpios", bank->num_lines);
	818	+
	819	+ if (bank->label)
	820	+ properties[prop_idx++] = PROPERTY_ENTRY_STRING("gpio-sim,label",
	821	+ bank->label);
	822	+
	823	+ line_names = gpio_sim_make_line_names(bank, &line_names_size);
	824	+ if (IS_ERR(line_names))
	825	+ return ERR_CAST(line_names);
	826	+
	827	+ if (line_names)
	828	+ properties[prop_idx++] = PROPERTY_ENTRY_STRING_ARRAY_LEN(
	829	+ "gpio-line-names",
	830	+ line_names, line_names_size);
	831	+
	832	+ swnode = fwnode_create_software_node(properties, parent);
	833	+ kfree(line_names);
	834	+ return swnode;
	835	+}
	836	+
	837	+static void gpio_sim_remove_swnode_recursive(struct fwnode_handle *swnode)
	838	+{
	839	+ struct fwnode_handle *child;
	840	+
	841	+ fwnode_for_each_child_node(swnode, child)
	842	+ fwnode_remove_software_node(child);
	843	+
	844	+ fwnode_remove_software_node(swnode);
	845	+}
	846	+
	847	+static bool gpio_sim_bank_labels_non_unique(struct gpio_sim_device *dev)
	848	+{
	849	+ struct gpio_sim_bank this, pos;
	850	+
	851	+ list_for_each_entry(this, &dev->bank_list, siblings) {
	852	+ list_for_each_entry(pos, &dev->bank_list, siblings) {
	853	+ if (this == pos \|\| (!this->label \|\| !pos->label))
	854	+ continue;
	855	+
	856	+ if (strcmp(this->label, pos->label) == 0)
	857	+ return true;
	858	+ }
	859	+ }
	860	+
	861	+ return false;
	862	+}
	863	+
	864	+static int gpio_sim_device_activate_unlocked(struct gpio_sim_device *dev)
	865	+{
	866	+ struct platform_device_info pdevinfo;
	867	+ struct fwnode_handle *swnode;
	868	+ struct platform_device *pdev;
	869	+ struct gpio_sim_bank *bank;
	870	+ int ret;
	871	+
	872	+ if (list_empty(&dev->bank_list))
	873	+ return -ENODATA;
	874	+
	875	+ /*
	876	+ * Non-unique GPIO device labels are a corner-case we don't support
	877	+ * as it would interfere with machine hogging mechanism and has little
	878	+ * use in real life.
	879	+ */
	880	+ if (gpio_sim_bank_labels_non_unique(dev))
	881	+ return -EINVAL;
	882	+
	883	+ memset(&pdevinfo, 0, sizeof(pdevinfo));
	884	+
	885	+ swnode = fwnode_create_software_node(NULL, NULL);
	886	+ if (IS_ERR(swnode))
	887	+ return PTR_ERR(swnode);
	888	+
	889	+ list_for_each_entry(bank, &dev->bank_list, siblings) {
	890	+ bank->swnode = gpio_sim_make_bank_swnode(bank, swnode);
	891	+ if (IS_ERR(bank->swnode)) {
	892	+ ret = PTR_ERR(bank->swnode);
	893	+ gpio_sim_remove_swnode_recursive(swnode);
	894	+ return ret;
	895	+ }
	896	+ }
	897	+
	898	+ ret = gpio_sim_add_hogs(dev);
	899	+ if (ret) {
	900	+ gpio_sim_remove_swnode_recursive(swnode);
	901	+ return ret;
	902	+ }
	903	+
	904	+ pdevinfo.name = "gpio-sim";
	905	+ pdevinfo.fwnode = swnode;
	906	+ pdevinfo.id = dev->id;
	907	+
	908	+ reinit_completion(&dev->probe_completion);
	909	+ dev->driver_bound = false;
	910	+ bus_register_notifier(&platform_bus_type, &dev->bus_notifier);
	911	+
	912	+ pdev = platform_device_register_full(&pdevinfo);
	913	+ if (IS_ERR(pdev)) {
	914	+ bus_unregister_notifier(&platform_bus_type, &dev->bus_notifier);
	915	+ gpio_sim_remove_hogs(dev);
	916	+ gpio_sim_remove_swnode_recursive(swnode);
	917	+ return PTR_ERR(pdev);
	918	+ }
	919	+
	920	+ wait_for_completion(&dev->probe_completion);
	921	+ bus_unregister_notifier(&platform_bus_type, &dev->bus_notifier);
	922	+
	923	+ if (!dev->driver_bound) {
	924	+ /* Probe failed, check kernel log. */
	925	+ platform_device_unregister(pdev);
	926	+ gpio_sim_remove_hogs(dev);
	927	+ gpio_sim_remove_swnode_recursive(swnode);
	928	+ return -ENXIO;
	929	+ }
	930	+
	931	+ dev->pdev = pdev;
	932	+
	933	+ return 0;
	934	+}
	935	+
	936	+static void gpio_sim_device_deactivate_unlocked(struct gpio_sim_device *dev)
	937	+{
	938	+ struct fwnode_handle *swnode;
	939	+
	940	+ swnode = dev_fwnode(&dev->pdev->dev);
	941	+ platform_device_unregister(dev->pdev);
	942	+ gpio_sim_remove_swnode_recursive(swnode);
	943	+ dev->pdev = NULL;
	944	+ gpio_sim_remove_hogs(dev);
	945	+}
	946	+
	947	+static ssize_t
	948	+gpio_sim_device_config_live_store(struct config_item *item,
	949	+ const char *page, size_t count)
	950	+{
	951	+ struct gpio_sim_device *dev = to_gpio_sim_device(item);
	952	+ bool live;
	953	+ int ret;
	954	+
	955	+ ret = kstrtobool(page, &live);
	956	+ if (ret)
	957	+ return ret;
	958	+
	959	+ mutex_lock(&dev->lock);
	960	+
	961	+ if ((!live && !gpio_sim_device_is_live_unlocked(dev)) \|\|
	962	+ (live && gpio_sim_device_is_live_unlocked(dev)))
	963	+ ret = -EPERM;
	964	+ else if (live)
	965	+ ret = gpio_sim_device_activate_unlocked(dev);
	966	+ else
	967	+ gpio_sim_device_deactivate_unlocked(dev);
	968	+
	969	+ mutex_unlock(&dev->lock);
	970	+
	971	+ return ret ?: count;
	972	+}
	973	+
	974	+CONFIGFS_ATTR(gpio_sim_device_config_, live);
	975	+
	976	+static struct configfs_attribute *gpio_sim_device_config_attrs[] = {
	977	+ &gpio_sim_device_config_attr_dev_name,
	978	+ &gpio_sim_device_config_attr_live,
	979	+ NULL
	980	+};
	981	+
	982	+struct gpio_sim_chip_name_ctx {
	983	+ struct gpio_sim_device *dev;
	984	+ char *page;
	985	+};
	986	+
	987	+static int gpio_sim_emit_chip_name(struct device dev, void data)
	988	+{
	989	+ struct gpio_sim_chip_name_ctx *ctx = data;
	990	+ struct fwnode_handle *swnode;
	991	+ struct gpio_sim_bank *bank;
	992	+
	993	+ /* This would be the sysfs device exported in /sys/class/gpio. */
	994	+ if (dev->class)
	995	+ return 0;
	996	+
	997	+ swnode = dev_fwnode(dev);
	998	+
	999	+ list_for_each_entry(bank, &ctx->dev->bank_list, siblings) {
	1000	+ if (bank->swnode == swnode)
	1001	+ return sprintf(ctx->page, "%s\n", dev_name(dev));
	1002	+ }
	1003	+
	1004	+ return -ENODATA;
	1005	+}
	1006	+
	1007	+static ssize_t gpio_sim_bank_config_chip_name_show(struct config_item *item,
	1008	+ char *page)
	1009	+{
	1010	+ struct gpio_sim_bank *bank = to_gpio_sim_bank(item);
	1011	+ struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);
	1012	+ struct gpio_sim_chip_name_ctx ctx = { dev, page };
	1013	+ int ret;
	1014	+
	1015	+ mutex_lock(&dev->lock);
	1016	+ if (gpio_sim_device_is_live_unlocked(dev))
	1017	+ ret = device_for_each_child(&dev->pdev->dev, &ctx,
	1018	+ gpio_sim_emit_chip_name);
	1019	+ else
	1020	+ ret = sprintf(page, "none\n");
	1021	+ mutex_unlock(&dev->lock);
	1022	+
	1023	+ return ret;
	1024	+}
	1025	+
	1026	+CONFIGFS_ATTR_RO(gpio_sim_bank_config_, chip_name);
	1027	+
	1028	+static ssize_t
	1029	+gpio_sim_bank_config_label_show(struct config_item item, char page)
	1030	+{
	1031	+ struct gpio_sim_bank *bank = to_gpio_sim_bank(item);
	1032	+ struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);
	1033	+ int ret;
	1034	+
	1035	+ mutex_lock(&dev->lock);
	1036	+ ret = sprintf(page, "%s\n", bank->label ?: "");
	1037	+ mutex_unlock(&dev->lock);
	1038	+
	1039	+ return ret;
	1040	+}
	1041	+
	1042	+static ssize_t gpio_sim_bank_config_label_store(struct config_item *item,
	1043	+ const char *page, size_t count)
	1044	+{
	1045	+ struct gpio_sim_bank *bank = to_gpio_sim_bank(item);
	1046	+ struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);
	1047	+ char *trimmed;
	1048	+
	1049	+ mutex_lock(&dev->lock);
	1050	+
	1051	+ if (gpio_sim_device_is_live_unlocked(dev)) {
	1052	+ mutex_unlock(&dev->lock);
	1053	+ return -EBUSY;
	1054	+ }
	1055	+
	1056	+ trimmed = gpio_sim_strdup_trimmed(page, count);
	1057	+ if (!trimmed) {
	1058	+ mutex_unlock(&dev->lock);
	1059	+ return -ENOMEM;
	1060	+ }
	1061	+
	1062	+ kfree(bank->label);
	1063	+ bank->label = trimmed;
	1064	+
	1065	+ mutex_unlock(&dev->lock);
	1066	+ return count;
	1067	+}
	1068	+
	1069	+CONFIGFS_ATTR(gpio_sim_bank_config_, label);
	1070	+
	1071	+static ssize_t
	1072	+gpio_sim_bank_config_num_lines_show(struct config_item item, char page)
	1073	+{
	1074	+ struct gpio_sim_bank *bank = to_gpio_sim_bank(item);
	1075	+ struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);
	1076	+ int ret;
	1077	+
	1078	+ mutex_lock(&dev->lock);
	1079	+ ret = sprintf(page, "%u\n", bank->num_lines);
	1080	+ mutex_unlock(&dev->lock);
	1081	+
	1082	+ return ret;
	1083	+}
	1084	+
	1085	+static ssize_t
	1086	+gpio_sim_bank_config_num_lines_store(struct config_item *item,
	1087	+ const char *page, size_t count)
	1088	+{
	1089	+ struct gpio_sim_bank *bank = to_gpio_sim_bank(item);
	1090	+ struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);
	1091	+ unsigned int num_lines;
	1092	+ int ret;
	1093	+
	1094	+ ret = kstrtouint(page, 0, &num_lines);
	1095	+ if (ret)
	1096	+ return ret;
	1097	+
	1098	+ if (num_lines == 0)
	1099	+ return -EINVAL;
	1100	+
	1101	+ mutex_lock(&dev->lock);
	1102	+
	1103	+ if (gpio_sim_device_is_live_unlocked(dev)) {
	1104	+ mutex_unlock(&dev->lock);
	1105	+ return -EBUSY;
	1106	+ }
	1107	+
	1108	+ bank->num_lines = num_lines;
	1109	+
	1110	+ mutex_unlock(&dev->lock);
	1111	+ return count;
	1112	+}
	1113	+
	1114	+CONFIGFS_ATTR(gpio_sim_bank_config_, num_lines);
	1115	+
	1116	+static struct configfs_attribute *gpio_sim_bank_config_attrs[] = {
	1117	+ &gpio_sim_bank_config_attr_chip_name,
	1118	+ &gpio_sim_bank_config_attr_label,
	1119	+ &gpio_sim_bank_config_attr_num_lines,
	1120	+ NULL
	1121	+};
	1122	+
	1123	+static ssize_t
	1124	+gpio_sim_line_config_name_show(struct config_item item, char page)
	1125	+{
	1126	+ struct gpio_sim_line *line = to_gpio_sim_line(item);
	1127	+ struct gpio_sim_device *dev = gpio_sim_line_get_device(line);
	1128	+ int ret;
	1129	+
	1130	+ mutex_lock(&dev->lock);
	1131	+ ret = sprintf(page, "%s\n", line->name ?: "");
	1132	+ mutex_unlock(&dev->lock);
	1133	+
	1134	+ return ret;
	1135	+}
	1136	+
	1137	+static ssize_t gpio_sim_line_config_name_store(struct config_item *item,
	1138	+ const char *page, size_t count)
	1139	+{
	1140	+ struct gpio_sim_line *line = to_gpio_sim_line(item);
	1141	+ struct gpio_sim_device *dev = gpio_sim_line_get_device(line);
	1142	+ char *trimmed;
	1143	+
	1144	+ mutex_lock(&dev->lock);
	1145	+
	1146	+ if (gpio_sim_device_is_live_unlocked(dev)) {
	1147	+ mutex_unlock(&dev->lock);
	1148	+ return -EBUSY;
	1149	+ }
	1150	+
	1151	+ trimmed = gpio_sim_strdup_trimmed(page, count);
	1152	+ if (!trimmed) {
	1153	+ mutex_unlock(&dev->lock);
	1154	+ return -ENOMEM;
	1155	+ }
	1156	+
	1157	+ kfree(line->name);
	1158	+ line->name = trimmed;
	1159	+
	1160	+ mutex_unlock(&dev->lock);
	1161	+
	1162	+ return count;
	1163	+}
	1164	+
	1165	+CONFIGFS_ATTR(gpio_sim_line_config_, name);
	1166	+
	1167	+static struct configfs_attribute *gpio_sim_line_config_attrs[] = {
	1168	+ &gpio_sim_line_config_attr_name,
	1169	+ NULL
	1170	+};
	1171	+
	1172	+static ssize_t gpio_sim_hog_config_name_show(struct config_item *item,
	1173	+ char *page)
	1174	+{
	1175	+ struct gpio_sim_hog *hog = to_gpio_sim_hog(item);
	1176	+ struct gpio_sim_device *dev = gpio_sim_hog_get_device(hog);
	1177	+ int ret;
	1178	+
	1179	+ mutex_lock(&dev->lock);
	1180	+ ret = sprintf(page, "%s\n", hog->name ?: "");
	1181	+ mutex_unlock(&dev->lock);
	1182	+
	1183	+ return ret;
	1184	+}
	1185	+
	1186	+static ssize_t gpio_sim_hog_config_name_store(struct config_item *item,
	1187	+ const char *page, size_t count)
	1188	+{
	1189	+ struct gpio_sim_hog *hog = to_gpio_sim_hog(item);
	1190	+ struct gpio_sim_device *dev = gpio_sim_hog_get_device(hog);
	1191	+ char *trimmed;
	1192	+
	1193	+ mutex_lock(&dev->lock);
	1194	+
	1195	+ if (gpio_sim_device_is_live_unlocked(dev)) {
	1196	+ mutex_unlock(&dev->lock);
	1197	+ return -EBUSY;
	1198	+ }
	1199	+
	1200	+ trimmed = gpio_sim_strdup_trimmed(page, count);
	1201	+ if (!trimmed) {
	1202	+ mutex_unlock(&dev->lock);
	1203	+ return -ENOMEM;
	1204	+ }
	1205	+
	1206	+ kfree(hog->name);
	1207	+ hog->name = trimmed;
	1208	+
	1209	+ mutex_unlock(&dev->lock);
	1210	+
	1211	+ return count;
	1212	+}
	1213	+
	1214	+CONFIGFS_ATTR(gpio_sim_hog_config_, name);
	1215	+
	1216	+static ssize_t gpio_sim_hog_config_direction_show(struct config_item *item,
	1217	+ char *page)
	1218	+{
	1219	+ struct gpio_sim_hog *hog = to_gpio_sim_hog(item);
	1220	+ struct gpio_sim_device *dev = gpio_sim_hog_get_device(hog);
	1221	+ char *repr;
	1222	+ int dir;
	1223	+
	1224	+ mutex_lock(&dev->lock);
	1225	+ dir = hog->dir;
	1226	+ mutex_unlock(&dev->lock);
	1227	+
	1228	+ switch (dir) {
	1229	+ case GPIOD_IN:
	1230	+ repr = "input";
	1231	+ break;
	1232	+ case GPIOD_OUT_HIGH:
	1233	+ repr = "output-high";
	1234	+ break;
	1235	+ case GPIOD_OUT_LOW:
	1236	+ repr = "output-low";
	1237	+ break;
	1238	+ default:
	1239	+ /* This would be a programmer bug. */
	1240	+ WARN(1, "Unexpected hog direction value: %d", dir);
	1241	+ return -EINVAL;
	1242	+ }
	1243	+
	1244	+ return sprintf(page, "%s\n", repr);
	1245	+}
	1246	+
	1247	+static ssize_t
	1248	+gpio_sim_hog_config_direction_store(struct config_item *item,
	1249	+ const char *page, size_t count)
	1250	+{
	1251	+ struct gpio_sim_hog *hog = to_gpio_sim_hog(item);
	1252	+ struct gpio_sim_device *dev = gpio_sim_hog_get_device(hog);
	1253	+ char *trimmed;
	1254	+ int dir;
	1255	+
	1256	+ mutex_lock(&dev->lock);
	1257	+
	1258	+ if (gpio_sim_device_is_live_unlocked(dev)) {
	1259	+ mutex_unlock(&dev->lock);
	1260	+ return -EBUSY;
	1261	+ }
	1262	+
	1263	+ trimmed = gpio_sim_strdup_trimmed(page, count);
	1264	+ if (!trimmed) {
	1265	+ mutex_unlock(&dev->lock);
	1266	+ return -ENOMEM;
	1267	+ }
	1268	+
	1269	+ if (strcmp(trimmed, "input") == 0)
	1270	+ dir = GPIOD_IN;
	1271	+ else if (strcmp(trimmed, "output-high") == 0)
	1272	+ dir = GPIOD_OUT_HIGH;
	1273	+ else if (strcmp(trimmed, "output-low") == 0)
	1274	+ dir = GPIOD_OUT_LOW;
	1275	+ else
	1276	+ dir = -EINVAL;
	1277	+
	1278	+ kfree(trimmed);
	1279	+
	1280	+ if (dir < 0) {
	1281	+ mutex_unlock(&dev->lock);
	1282	+ return dir;
	1283	+ }
	1284	+
	1285	+ hog->dir = dir;
	1286	+
	1287	+ mutex_unlock(&dev->lock);
	1288	+
	1289	+ return count;
	1290	+}
	1291	+
	1292	+CONFIGFS_ATTR(gpio_sim_hog_config_, direction);
	1293	+
	1294	+static struct configfs_attribute *gpio_sim_hog_config_attrs[] = {
	1295	+ &gpio_sim_hog_config_attr_name,
	1296	+ &gpio_sim_hog_config_attr_direction,
	1297	+ NULL
	1298	+};
	1299	+
	1300	+static void gpio_sim_hog_config_item_release(struct config_item *item)
	1301	+{
	1302	+ struct gpio_sim_hog *hog = to_gpio_sim_hog(item);
	1303	+ struct gpio_sim_line *line = hog->parent;
	1304	+ struct gpio_sim_device *dev = gpio_sim_hog_get_device(hog);
	1305	+
	1306	+ mutex_lock(&dev->lock);
	1307	+ line->hog = NULL;
	1308	+ mutex_unlock(&dev->lock);
	1309	+
	1310	+ kfree(hog->name);
	1311	+ kfree(hog);
	1312	+}
	1313	+
	1314	+struct configfs_item_operations gpio_sim_hog_config_item_ops = {
	1315	+ .release = gpio_sim_hog_config_item_release,
	1316	+};
	1317	+
	1318	+static const struct config_item_type gpio_sim_hog_config_type = {
	1319	+ .ct_item_ops = &gpio_sim_hog_config_item_ops,
	1320	+ .ct_attrs = gpio_sim_hog_config_attrs,
	1321	+ .ct_owner = THIS_MODULE,
	1322	+};
	1323	+
	1324	+static struct config_item *
	1325	+gpio_sim_line_config_make_hog_item(struct config_group group, const char name)
	1326	+{
	1327	+ struct gpio_sim_line *line = to_gpio_sim_line(&group->cg_item);
	1328	+ struct gpio_sim_device *dev = gpio_sim_line_get_device(line);
	1329	+ struct gpio_sim_hog *hog;
	1330	+
	1331	+ if (strcmp(name, "hog") != 0)
	1332	+ return ERR_PTR(-EINVAL);
	1333	+
	1334	+ mutex_lock(&dev->lock);
	1335	+
	1336	+ hog = kzalloc(sizeof(*hog), GFP_KERNEL);
	1337	+ if (!hog) {
	1338	+ mutex_unlock(&dev->lock);
	1339	+ return ERR_PTR(-ENOMEM);
	1340	+ }
	1341	+
	1342	+ config_item_init_type_name(&hog->item, name,
	1343	+ &gpio_sim_hog_config_type);
	1344	+
	1345	+ hog->dir = GPIOD_IN;
	1346	+ hog->name = NULL;
	1347	+ hog->parent = line;
	1348	+ line->hog = hog;
	1349	+
	1350	+ mutex_unlock(&dev->lock);
	1351	+
	1352	+ return &hog->item;
	1353	+}
	1354	+
	1355	+static void gpio_sim_line_config_group_release(struct config_item *item)
	1356	+{
	1357	+ struct gpio_sim_line *line = to_gpio_sim_line(item);
	1358	+ struct gpio_sim_device *dev = gpio_sim_line_get_device(line);
	1359	+
	1360	+ mutex_lock(&dev->lock);
	1361	+ list_del(&line->siblings);
	1362	+ mutex_unlock(&dev->lock);
	1363	+
	1364	+ kfree(line->name);
	1365	+ kfree(line);
	1366	+}
	1367	+
	1368	+static struct configfs_item_operations gpio_sim_line_config_item_ops = {
	1369	+ .release = gpio_sim_line_config_group_release,
	1370	+};
	1371	+
	1372	+static struct configfs_group_operations gpio_sim_line_config_group_ops = {
	1373	+ .make_item = gpio_sim_line_config_make_hog_item,
	1374	+};
	1375	+
	1376	+static const struct config_item_type gpio_sim_line_config_type = {
	1377	+ .ct_item_ops = &gpio_sim_line_config_item_ops,
	1378	+ .ct_group_ops = &gpio_sim_line_config_group_ops,
	1379	+ .ct_attrs = gpio_sim_line_config_attrs,
	1380	+ .ct_owner = THIS_MODULE,
	1381	+};
	1382	+
	1383	+static struct config_group *
	1384	+gpio_sim_bank_config_make_line_group(struct config_group *group,
	1385	+ const char *name)
	1386	+{
	1387	+ struct gpio_sim_bank *bank = to_gpio_sim_bank(&group->cg_item);
	1388	+ struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);
	1389	+ struct gpio_sim_line *line;
	1390	+ unsigned int offset;
	1391	+ int ret, nchar;
	1392	+
	1393	+ ret = sscanf(name, "line%u%n", &offset, &nchar);
	1394	+ if (ret != 1 \|\| nchar != strlen(name))
	1395	+ return ERR_PTR(-EINVAL);
	1396	+
	1397	+ mutex_lock(&dev->lock);
	1398	+
	1399	+ if (gpio_sim_device_is_live_unlocked(dev)) {
	1400	+ mutex_unlock(&dev->lock);
	1401	+ return ERR_PTR(-EBUSY);
	1402	+ }
	1403	+
	1404	+ line = kzalloc(sizeof(*line), GFP_KERNEL);
	1405	+ if (!line) {
	1406	+ mutex_unlock(&dev->lock);
	1407	+ return ERR_PTR(-ENOMEM);
	1408	+ }
	1409	+
	1410	+ config_group_init_type_name(&line->group, name,
	1411	+ &gpio_sim_line_config_type);
	1412	+
	1413	+ line->parent = bank;
	1414	+ line->offset = offset;
	1415	+ list_add_tail(&line->siblings, &bank->line_list);
	1416	+
	1417	+ mutex_unlock(&dev->lock);
	1418	+
	1419	+ return &line->group;
	1420	+}
	1421	+
	1422	+static void gpio_sim_bank_config_group_release(struct config_item *item)
	1423	+{
	1424	+ struct gpio_sim_bank *bank = to_gpio_sim_bank(item);
	1425	+ struct gpio_sim_device *dev = gpio_sim_bank_get_device(bank);
	1426	+
	1427	+ mutex_lock(&dev->lock);
	1428	+ list_del(&bank->siblings);
	1429	+ mutex_unlock(&dev->lock);
	1430	+
	1431	+ kfree(bank->label);
	1432	+ kfree(bank);
	1433	+}
	1434	+
	1435	+static struct configfs_item_operations gpio_sim_bank_config_item_ops = {
	1436	+ .release = gpio_sim_bank_config_group_release,
	1437	+};
	1438	+
	1439	+static struct configfs_group_operations gpio_sim_bank_config_group_ops = {
	1440	+ .make_group = gpio_sim_bank_config_make_line_group,
	1441	+};
	1442	+
	1443	+static const struct config_item_type gpio_sim_bank_config_group_type = {
	1444	+ .ct_item_ops = &gpio_sim_bank_config_item_ops,
	1445	+ .ct_group_ops = &gpio_sim_bank_config_group_ops,
	1446	+ .ct_attrs = gpio_sim_bank_config_attrs,
	1447	+ .ct_owner = THIS_MODULE,
	1448	+};
	1449	+
	1450	+static struct config_group *
	1451	+gpio_sim_device_config_make_bank_group(struct config_group *group,
	1452	+ const char *name)
	1453	+{
	1454	+ struct gpio_sim_device *dev = to_gpio_sim_device(&group->cg_item);
	1455	+ struct gpio_sim_bank *bank;
	1456	+
	1457	+ mutex_lock(&dev->lock);
	1458	+
	1459	+ if (gpio_sim_device_is_live_unlocked(dev)) {
	1460	+ mutex_unlock(&dev->lock);
	1461	+ return ERR_PTR(-EBUSY);
	1462	+ }
	1463	+
	1464	+ bank = kzalloc(sizeof(*bank), GFP_KERNEL);
	1465	+ if (!bank) {
	1466	+ mutex_unlock(&dev->lock);
	1467	+ return ERR_PTR(-ENOMEM);
	1468	+ }
	1469	+
	1470	+ config_group_init_type_name(&bank->group, name,
	1471	+ &gpio_sim_bank_config_group_type);
	1472	+ bank->num_lines = 1;
	1473	+ bank->parent = dev;
	1474	+ INIT_LIST_HEAD(&bank->line_list);
	1475	+ list_add_tail(&bank->siblings, &dev->bank_list);
	1476	+
	1477	+ mutex_unlock(&dev->lock);
	1478	+
	1479	+ return &bank->group;
	1480	+}
	1481	+
	1482	+static void gpio_sim_device_config_group_release(struct config_item *item)
	1483	+{
	1484	+ struct gpio_sim_device *dev = to_gpio_sim_device(item);
	1485	+
	1486	+ mutex_lock(&dev->lock);
	1487	+ if (gpio_sim_device_is_live_unlocked(dev))
	1488	+ gpio_sim_device_deactivate_unlocked(dev);
	1489	+ mutex_unlock(&dev->lock);
	1490	+
	1491	+ mutex_destroy(&dev->lock);
	1492	+ ida_free(&gpio_sim_ida, dev->id);
	1493	+ kfree(dev);
	1494	+}
	1495	+
	1496	+static struct configfs_item_operations gpio_sim_device_config_item_ops = {
	1497	+ .release = gpio_sim_device_config_group_release,
	1498	+};
	1499	+
	1500	+static struct configfs_group_operations gpio_sim_device_config_group_ops = {
	1501	+ .make_group = gpio_sim_device_config_make_bank_group,
	1502	+};
	1503	+
	1504	+static const struct config_item_type gpio_sim_device_config_group_type = {
	1505	+ .ct_item_ops = &gpio_sim_device_config_item_ops,
	1506	+ .ct_group_ops = &gpio_sim_device_config_group_ops,
	1507	+ .ct_attrs = gpio_sim_device_config_attrs,
	1508	+ .ct_owner = THIS_MODULE,
	1509	+};
	1510	+
	1511	+static struct config_group *
	1512	+gpio_sim_config_make_device_group(struct config_group group, const char name)
	1513	+{
	1514	+ struct gpio_sim_device *dev;
	1515	+ int id;
	1516	+
	1517	+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	1518	+ if (!dev)
	1519	+ return ERR_PTR(-ENOMEM);
	1520	+
	1521	+ id = ida_alloc(&gpio_sim_ida, GFP_KERNEL);
	1522	+ if (id < 0) {
	1523	+ kfree(dev);
	1524	+ return ERR_PTR(id);
	1525	+ }
	1526	+
	1527	+ config_group_init_type_name(&dev->group, name,
	1528	+ &gpio_sim_device_config_group_type);
	1529	+ dev->id = id;
	1530	+ mutex_init(&dev->lock);
	1531	+ INIT_LIST_HEAD(&dev->bank_list);
	1532	+
	1533	+ dev->bus_notifier.notifier_call = gpio_sim_bus_notifier_call;
	1534	+ init_completion(&dev->probe_completion);
	1535	+
	1536	+ return &dev->group;
	1537	+}
	1538	+
	1539	+static struct configfs_group_operations gpio_sim_config_group_ops = {
	1540	+ .make_group = gpio_sim_config_make_device_group,
	1541	+};
	1542	+
	1543	+static const struct config_item_type gpio_sim_config_type = {
	1544	+ .ct_group_ops = &gpio_sim_config_group_ops,
	1545	+ .ct_owner = THIS_MODULE,
	1546	+};
	1547	+
	1548	+static struct configfs_subsystem gpio_sim_config_subsys = {
	1549	+ .su_group = {
	1550	+ .cg_item = {
	1551	+ .ci_namebuf = "gpio-sim",
	1552	+ .ci_type = &gpio_sim_config_type,
	1553	+ },
	1554	+ },
	1555	+};
	1556	+
	1557	+static int __init gpio_sim_init(void)
	1558	+{
	1559	+ int ret;
	1560	+
	1561	+ ret = platform_driver_register(&gpio_sim_driver);
	1562	+ if (ret) {
	1563	+ pr_err("Error %d while registering the platform driver\n", ret);
	1564	+ return ret;
	1565	+ }
	1566	+
	1567	+ config_group_init(&gpio_sim_config_subsys.su_group);
	1568	+ mutex_init(&gpio_sim_config_subsys.su_mutex);
	1569	+ ret = configfs_register_subsystem(&gpio_sim_config_subsys);
	1570	+ if (ret) {
	1571	+ pr_err("Error %d while registering the configfs subsystem %s\n",
	1572	+ ret, gpio_sim_config_subsys.su_group.cg_item.ci_namebuf);
	1573	+ mutex_destroy(&gpio_sim_config_subsys.su_mutex);
	1574	+ platform_driver_unregister(&gpio_sim_driver);
	1575	+ return ret;
	1576	+ }
	1577	+
	1578	+ return 0;
	1579	+}
	1580	+module_init(gpio_sim_init);
	1581	+
	1582	+static void __exit gpio_sim_exit(void)
	1583	+{
	1584	+ configfs_unregister_subsystem(&gpio_sim_config_subsys);
	1585	+ mutex_destroy(&gpio_sim_config_subsys.su_mutex);
	1586	+ platform_driver_unregister(&gpio_sim_driver);
	1587	+}
	1588	+module_exit(gpio_sim_exit);
	1589	+
	1590	+MODULE_AUTHOR("Bartosz Golaszewski <brgl@bgdev.pl");
	1591	+MODULE_DESCRIPTION("GPIO Simulator Module");
	1592	+MODULE_LICENSE("GPL");

drivers/gpio/gpio-sprd.c+0−1

@@ -237,7 +237,6 @@ static int sprd_gpio_probe(struct platform_device *pdev) · 236 unmodified lines
237	237	sprd_gpio->chip.ngpio = SPRD_GPIO_NR;
238	238	sprd_gpio->chip.base = -1;
239	239	sprd_gpio->chip.parent = &pdev->dev;
240		− sprd_gpio->chip.of_node = pdev->dev.of_node;
241	240	sprd_gpio->chip.request = sprd_gpio_request;
242	241	sprd_gpio->chip.free = sprd_gpio_free;
243	242	sprd_gpio->chip.get = sprd_gpio_get;

drivers/gpio/gpio-sta2x11.c+1−1

@@ -324,7 +324,7 @@ static int gsta_alloc_irq_chip(struct gsta_gpio *chip) · 323 unmodified lines
324	324	if (rv)
325	325	return rv;
326	326
327		− /* Set up all all 128 interrupts: code from setup_generic_chip */
	327	+ /* Set up all 128 interrupts: code from setup_generic_chip */
328	328	{
329	329	struct irq_chip_type *ct = gc->chip_types;
330	330	int i, j;

drivers/gpio/gpio-stmpe.c+0−1

@@ -477,7 +477,6 @@ static int stmpe_gpio_probe(struct platform_device *pdev) · 476 unmodified lines
477	477	stmpe_gpio->chip = template_chip;
478	478	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
479	479	stmpe_gpio->chip.parent = &pdev->dev;
480		− stmpe_gpio->chip.of_node = np;
481	480	stmpe_gpio->chip.base = -1;
482	481
483	482	if (IS_ENABLED(CONFIG_DEBUG_FS))

drivers/gpio/gpio-tc3589x.c+0−1

@@ -319,7 +319,6 @@ static int tc3589x_gpio_probe(struct platform_device *pdev) · 318 unmodified lines
319	319	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
320	320	tc3589x_gpio->chip.parent = &pdev->dev;
321	321	tc3589x_gpio->chip.base = -1;
322		− tc3589x_gpio->chip.of_node = np;
323	322
324	323	girq = &tc3589x_gpio->chip.irq;
325	324	girq->chip = &tc3589x_gpio_irq_chip;

drivers/gpio/gpio-tegra186.c+128−1

@@ -14,6 +14,8 @@ · 13 unmodified lines
14	14
15	15	#include <dt-bindings/gpio/tegra186-gpio.h>
16	16	#include <dt-bindings/gpio/tegra194-gpio.h>
	17	+#include <dt-bindings/gpio/tegra234-gpio.h>
	18	+#include <dt-bindings/gpio/tegra241-gpio.h>
17	19
18	20	/* security registers */
19	21	#define TEGRA186_GPIO_CTL_SCR 0x0c
@@ -748,7 +750,6 @@ static int tegra186_gpio_probe(struct platform_device *pdev) · 728 unmodified lines
748	750	gpio->gpio.names = (const char * const *)names;
749	751
750	752	#if defined(CONFIG_OF_GPIO)
751		− gpio->gpio.of_node = pdev->dev.of_node;
752	753	gpio->gpio.of_gpio_n_cells = 2;
753	754	gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
754	755	#endif /* CONFIG_OF_GPIO */
@@ -972,6 +973,124 @@ static const struct tegra_gpio_soc tegra194_aon_soc = { · 217 unmodified lines
972	973	.num_irqs_per_bank = 8,
973	974	};
974	975
	976	+#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
	977	+ [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
	978	+ .name = #_name, \
	979	+ .bank = _bank, \
	980	+ .port = _port, \
	981	+ .pins = _pins, \
	982	+ }
	983	+
	984	+static const struct tegra_gpio_port tegra234_main_ports[] = {
	985	+ TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
	986	+ TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
	987	+ TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
	988	+ TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
	989	+ TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
	990	+ TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
	991	+ TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
	992	+ TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
	993	+ TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
	994	+ TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
	995	+ TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
	996	+ TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
	997	+ TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
	998	+ TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
	999	+ TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
	1000	+ TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
	1001	+ TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
	1002	+ TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
	1003	+ TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
	1004	+ TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
	1005	+ TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
	1006	+ TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
	1007	+ TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
	1008	+ TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
	1009	+ TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
	1010	+};
	1011	+
	1012	+static const struct tegra_gpio_soc tegra234_main_soc = {
	1013	+ .num_ports = ARRAY_SIZE(tegra234_main_ports),
	1014	+ .ports = tegra234_main_ports,
	1015	+ .name = "tegra234-gpio",
	1016	+ .instance = 0,
	1017	+ .num_irqs_per_bank = 8,
	1018	+};
	1019	+
	1020	+#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
	1021	+ [TEGRA234_AON_GPIO_PORT_##_name] = { \
	1022	+ .name = #_name, \
	1023	+ .bank = _bank, \
	1024	+ .port = _port, \
	1025	+ .pins = _pins, \
	1026	+ }
	1027	+
	1028	+static const struct tegra_gpio_port tegra234_aon_ports[] = {
	1029	+ TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
	1030	+ TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
	1031	+ TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
	1032	+ TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
	1033	+ TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
	1034	+ TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
	1035	+};
	1036	+
	1037	+static const struct tegra_gpio_soc tegra234_aon_soc = {
	1038	+ .num_ports = ARRAY_SIZE(tegra234_aon_ports),
	1039	+ .ports = tegra234_aon_ports,
	1040	+ .name = "tegra234-gpio-aon",
	1041	+ .instance = 1,
	1042	+ .num_irqs_per_bank = 8,
	1043	+};
	1044	+
	1045	+#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
	1046	+ [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
	1047	+ .name = #_name, \
	1048	+ .bank = _bank, \
	1049	+ .port = _port, \
	1050	+ .pins = _pins, \
	1051	+ }
	1052	+
	1053	+static const struct tegra_gpio_port tegra241_main_ports[] = {
	1054	+ TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
	1055	+ TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
	1056	+ TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
	1057	+ TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
	1058	+ TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
	1059	+ TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
	1060	+ TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
	1061	+ TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
	1062	+ TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
	1063	+ TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
	1064	+ TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
	1065	+};
	1066	+
	1067	+static const struct tegra_gpio_soc tegra241_main_soc = {
	1068	+ .num_ports = ARRAY_SIZE(tegra241_main_ports),
	1069	+ .ports = tegra241_main_ports,
	1070	+ .name = "tegra241-gpio",
	1071	+ .instance = 0,
	1072	+};
	1073	+
	1074	+#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
	1075	+ [TEGRA241_AON_GPIO_PORT_##_name] = { \
	1076	+ .name = #_name, \
	1077	+ .bank = _bank, \
	1078	+ .port = _port, \
	1079	+ .pins = _pins, \
	1080	+ }
	1081	+
	1082	+static const struct tegra_gpio_port tegra241_aon_ports[] = {
	1083	+ TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
	1084	+ TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
	1085	+};
	1086	+
	1087	+static const struct tegra_gpio_soc tegra241_aon_soc = {
	1088	+ .num_ports = ARRAY_SIZE(tegra241_aon_ports),
	1089	+ .ports = tegra241_aon_ports,
	1090	+ .name = "tegra241-gpio-aon",
	1091	+ .instance = 1,
	1092	+};
	1093	+
975	1094	static const struct of_device_id tegra186_gpio_of_match[] = {
976	1095	{
977	1096	.compatible = "nvidia,tegra186-gpio",
@@ -985,6 +1104,12 @@ static const struct of_device_id tegra186_gpio_of_match[] = { · 7 unmodified lines
985	1104	}, {
986	1105	.compatible = "nvidia,tegra194-gpio-aon",
987	1106	.data = &tegra194_aon_soc
	1107	+ }, {
	1108	+ .compatible = "nvidia,tegra234-gpio",
	1109	+ .data = &tegra234_main_soc
	1110	+ }, {
	1111	+ .compatible = "nvidia,tegra234-gpio-aon",
	1112	+ .data = &tegra234_aon_soc
988	1113	}, {
989	1114	/* sentinel */
990	1115	}
@@ -996,6 +1121,8 @@ static const struct acpi_device_id tegra186_gpio_acpi_match[] = { · 5 unmodified lines
996	1121	{ .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
997	1122	{ .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
998	1123	{ .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
	1124	+ { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
	1125	+ { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
999	1126	{}
1000	1127	};
1001	1128	MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);

drivers/gpio/gpio-tps65218.c+0−3

@@ -196,9 +196,6 @@ static int tps65218_gpio_probe(struct platform_device *pdev) · 195 unmodified lines
196	196	tps65218_gpio->tps65218 = tps65218;
197	197	tps65218_gpio->gpio_chip = template_chip;
198	198	tps65218_gpio->gpio_chip.parent = &pdev->dev;
199		−#ifdef CONFIG_OF_GPIO
200		− tps65218_gpio->gpio_chip.of_node = pdev->dev.of_node;
201		−#endif
202	199
203	200	return devm_gpiochip_add_data(&pdev->dev, &tps65218_gpio->gpio_chip,
204	201	tps65218_gpio);

drivers/gpio/gpio-tps6586x.c+2−3

@@ -77,6 +77,8 @@ static int tps6586x_gpio_probe(struct platform_device *pdev) · 76 unmodified lines
77	77	struct tps6586x_platform_data *pdata;
78	78	struct tps6586x_gpio *tps6586x_gpio;
79	79
	80	+ device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
	81	+
80	82	pdata = dev_get_platdata(pdev->dev.parent);
81	83	tps6586x_gpio = devm_kzalloc(&pdev->dev,
82	84	sizeof(*tps6586x_gpio), GFP_KERNEL);
@@ -97,9 +99,6 @@ static int tps6586x_gpio_probe(struct platform_device *pdev) · 14 unmodified lines
97	99	tps6586x_gpio->gpio_chip.get = tps6586x_gpio_get;
98	100	tps6586x_gpio->gpio_chip.to_irq = tps6586x_gpio_to_irq;
99	101
100		−#ifdef CONFIG_OF_GPIO
101		− tps6586x_gpio->gpio_chip.of_node = pdev->dev.parent->of_node;
102		−#endif
103	102	if (pdata && pdata->gpio_base)
104	103	tps6586x_gpio->gpio_chip.base = pdata->gpio_base;
105	104	else

drivers/gpio/gpio-tps65910.c+3−3

@@ -111,6 +111,8 @@ static int tps65910_gpio_probe(struct platform_device *pdev) · 110 unmodified lines
111	111	int ret;
112	112	int i;
113	113
	114	+ device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
	115	+
114	116	tps65910_gpio = devm_kzalloc(&pdev->dev,
115	117	sizeof(*tps65910_gpio), GFP_KERNEL);
116	118	if (!tps65910_gpio)
@@ -137,9 +139,7 @@ static int tps65910_gpio_probe(struct platform_device *pdev) · 20 unmodified lines
137	139	tps65910_gpio->gpio_chip.set = tps65910_gpio_set;
138	140	tps65910_gpio->gpio_chip.get = tps65910_gpio_get;
139	141	tps65910_gpio->gpio_chip.parent = &pdev->dev;
140		−#ifdef CONFIG_OF_GPIO
141		− tps65910_gpio->gpio_chip.of_node = tps65910->dev->of_node;
142		−#endif
	142	+
143	143	if (pdata && pdata->gpio_base)
144	144	tps65910_gpio->gpio_chip.base = pdata->gpio_base;
145	145	else

drivers/gpio/gpio-ts5500.c+4−7

@@ -317,22 +317,19 @@ static int ts5500_dio_probe(struct platform_device *pdev) · 316 unmodified lines
317	317	struct device *dev = &pdev->dev;
318	318	const char *name = dev_name(dev);
319	319	struct ts5500_priv *priv;
320		− struct resource *res;
321	320	unsigned long flags;
322	321	int ret;
323	322
324		− res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
325		− if (!res) {
326		− dev_err(dev, "missing IRQ resource\n");
327		− return -EINVAL;
328		− }
	323	+ ret = platform_get_irq(pdev, 0);
	324	+ if (ret < 0)
	325	+ return ret;
329	326
330	327	priv = devm_kzalloc(dev, sizeof(struct ts5500_priv), GFP_KERNEL);
331	328	if (!priv)
332	329	return -ENOMEM;
333	330
334	331	platform_set_drvdata(pdev, priv);
335		− priv->hwirq = res->start;
	332	+ priv->hwirq = ret;
336	333	spin_lock_init(&priv->lock);
337	334
338	335	priv->gpio_chip.owner = THIS_MODULE;

drivers/gpio/gpio-twl6040.c+2−3

@@ -80,6 +80,8 @@ static int gpo_twl6040_probe(struct platform_device *pdev) · 79 unmodified lines
80	80	struct twl6040 *twl6040 = dev_get_drvdata(twl6040_core_dev);
81	81	int ret;
82	82
	83	+ device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
	84	+
83	85	twl6040gpo_chip.base = -1;
84	86
85	87	if (twl6040_get_revid(twl6040) < TWL6041_REV_ES2_0)
@@ -88,9 +90,6 @@ static int gpo_twl6040_probe(struct platform_device *pdev) · 2 unmodified lines
88	90	twl6040gpo_chip.ngpio = 1; /* twl6041 have 1 GPO */
89	91
90	92	twl6040gpo_chip.parent = &pdev->dev;
91		−#ifdef CONFIG_OF_GPIO
92		− twl6040gpo_chip.of_node = twl6040_core_dev->of_node;
93		−#endif
94	93
95	94	ret = devm_gpiochip_add_data(&pdev->dev, &twl6040gpo_chip, NULL);
96	95	if (ret < 0) {

drivers/gpio/gpio-vf610.c+0−1

@@ -298,7 +298,6 @@ static int vf610_gpio_probe(struct platform_device *pdev) · 297 unmodified lines
298	298	}
299	299
300	300	gc = &port->gc;
301		− gc->of_node = np;
302	301	gc->parent = dev;
303	302	gc->label = "vf610-gpio";
304	303	gc->ngpio = VF610_GPIO_PER_PORT;

drivers/gpio/gpio-wm831x.c+2−3

@@ -262,6 +262,8 @@ static int wm831x_gpio_probe(struct platform_device *pdev) · 261 unmodified lines
262	262	struct wm831x_pdata *pdata = &wm831x->pdata;
263	263	struct wm831x_gpio *wm831x_gpio;
264	264
	265	+ device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
	266	+
265	267	wm831x_gpio = devm_kzalloc(&pdev->dev, sizeof(*wm831x_gpio),
266	268	GFP_KERNEL);
267	269	if (wm831x_gpio == NULL)
@@ -275,9 +277,6 @@ static int wm831x_gpio_probe(struct platform_device *pdev) · 7 unmodified lines
275	277	wm831x_gpio->gpio_chip.base = pdata->gpio_base;
276	278	else
277	279	wm831x_gpio->gpio_chip.base = -1;
278		−#ifdef CONFIG_OF_GPIO
279		− wm831x_gpio->gpio_chip.of_node = wm831x->dev->of_node;
280		−#endif
281	280
282	281	return devm_gpiochip_add_data(&pdev->dev, &wm831x_gpio->gpio_chip, wm831x_gpio);
283	282	}

drivers/gpio/gpio-xlp.c+11−136

@@ -6,7 +6,6 @@ · 5 unmodified lines
6	6
7	7	#include <linux/gpio/driver.h>
8	8	#include <linux/platform_device.h>
9		−#include <linux/of_device.h>
10	9	#include <linux/module.h>
11	10	#include <linux/irq.h>
12	11	#include <linux/interrupt.h>
@@ -26,16 +25,6 @@ · 13 unmodified lines
26	25	*
27	26	* where addr is base address of the that feature register and gpio is the pin.
28	27	*/
29		−#define GPIO_OUTPUT_EN 0x00
30		−#define GPIO_PADDRV 0x08
31		−#define GPIO_INT_EN00 0x18
32		−#define GPIO_INT_EN10 0x20
33		−#define GPIO_INT_EN20 0x28
34		−#define GPIO_INT_EN30 0x30
35		−#define GPIO_INT_POL 0x38
36		−#define GPIO_INT_TYPE 0x40
37		−#define GPIO_INT_STAT 0x48
38		−
39	28	#define GPIO_9XX_BYTESWAP 0X00
40	29	#define GPIO_9XX_CTRL 0X04
41	30	#define GPIO_9XX_OUTPUT_EN 0x14
@@ -52,14 +41,6 @@ · 10 unmodified lines
52	41	#define GPIO_9XX_INT_TYPE 0x114
53	42	#define GPIO_9XX_INT_STAT 0x124
54	43
55		−#define GPIO_3XX_INT_EN00 0x18
56		−#define GPIO_3XX_INT_EN10 0x20
57		−#define GPIO_3XX_INT_EN20 0x28
58		−#define GPIO_3XX_INT_EN30 0x30
59		−#define GPIO_3XX_INT_POL 0x78
60		−#define GPIO_3XX_INT_TYPE 0x80
61		−#define GPIO_3XX_INT_STAT 0x88
62		−
63	44	/* Interrupt type register mask */
64	45	#define XLP_GPIO_IRQ_TYPE_LVL 0x0
65	46	#define XLP_GPIO_IRQ_TYPE_EDGE 0x1
@@ -72,16 +53,6 @@ · 6 unmodified lines
72	53	#define XLP_GPIO_IRQ_BASE 768
73	54	#define XLP_MAX_NR_GPIO 96
74	55
75		−/* XLP variants supported by this driver */
76		−enum {
77		− XLP_GPIO_VARIANT_XLP832 = 1,
78		− XLP_GPIO_VARIANT_XLP316,
79		− XLP_GPIO_VARIANT_XLP208,
80		− XLP_GPIO_VARIANT_XLP980,
81		− XLP_GPIO_VARIANT_XLP532,
82		− GPIO_VARIANT_VULCAN
83		−};
84		−
85	56	struct xlp_gpio_priv {
86	57	struct gpio_chip chip;
87	58	DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
@@ -257,44 +228,13 @@ static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state) · 169 unmodified lines
257	228	xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
258	229	}
259	230
260		−static const struct of_device_id xlp_gpio_of_ids[] = {
261		− {
262		− .compatible = "netlogic,xlp832-gpio",
263		− .data = (void *)XLP_GPIO_VARIANT_XLP832,
264		− },
265		− {
266		− .compatible = "netlogic,xlp316-gpio",
267		− .data = (void *)XLP_GPIO_VARIANT_XLP316,
268		− },
269		− {
270		− .compatible = "netlogic,xlp208-gpio",
271		− .data = (void *)XLP_GPIO_VARIANT_XLP208,
272		− },
273		− {
274		− .compatible = "netlogic,xlp980-gpio",
275		− .data = (void *)XLP_GPIO_VARIANT_XLP980,
276		− },
277		− {
278		− .compatible = "netlogic,xlp532-gpio",
279		− .data = (void *)XLP_GPIO_VARIANT_XLP532,
280		− },
281		− {
282		− .compatible = "brcm,vulcan-gpio",
283		− .data = (void *)GPIO_VARIANT_VULCAN,
284		− },
285		− { /* sentinel */ },
286		−};
287		−MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);
288		−
289	231	static int xlp_gpio_probe(struct platform_device *pdev)
290	232	{
291	233	struct gpio_chip *gc;
292	234	struct gpio_irq_chip *girq;
293	235	struct xlp_gpio_priv *priv;
294	236	void __iomem *gpio_base;
295		− int irq_base, irq, err;
296		− int ngpio;
297		− u32 soc_type;
	237	+ int irq, err;
298	238
299	239	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
300	240	if (!priv)
@@ -308,62 +248,12 @@ static int xlp_gpio_probe(struct platform_device *pdev) · 7 unmodified lines
308	248	if (irq < 0)
309	249	return irq;
310	250
311		− if (pdev->dev.of_node) {
312		− soc_type = (uintptr_t)of_device_get_match_data(&pdev->dev);
313		− } else {
314		− const struct acpi_device_id *acpi_id;
315		−
316		− acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
317		− &pdev->dev);
318		− if (!acpi_id \|\| !acpi_id->driver_data) {
319		− dev_err(&pdev->dev, "Unable to match ACPI ID\n");
320		− return -ENODEV;
321		− }
322		− soc_type = (uintptr_t) acpi_id->driver_data;
323		− }
324		−
325		− switch (soc_type) {
326		− case XLP_GPIO_VARIANT_XLP832:
327		− priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
328		− priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
329		− priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
330		− priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
331		− priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
332		− priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
333		− ngpio = 41;
334		− break;
335		− case XLP_GPIO_VARIANT_XLP208:
336		− case XLP_GPIO_VARIANT_XLP316:
337		− priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
338		− priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
339		− priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
340		− priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
341		− priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
342		− priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;
343		−
344		− ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
345		− break;
346		− case XLP_GPIO_VARIANT_XLP980:
347		− case XLP_GPIO_VARIANT_XLP532:
348		− case GPIO_VARIANT_VULCAN:
349		− priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
350		− priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
351		− priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
352		− priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
353		− priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
354		− priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
355		−
356		− if (soc_type == XLP_GPIO_VARIANT_XLP980)
357		− ngpio = 66;
358		− else if (soc_type == XLP_GPIO_VARIANT_XLP532)
359		− ngpio = 67;
360		− else
361		− ngpio = 70;
362		− break;
363		− default:
364		− dev_err(&pdev->dev, "Unknown Processor type!\n");
365		− return -ENODEV;
366		− }
	251	+ priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
	252	+ priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
	253	+ priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
	254	+ priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
	255	+ priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
	256	+ priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
367	257
368	258	bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
369	259
@@ -373,8 +263,7 @@ static int xlp_gpio_probe(struct platform_device *pdev) · 3 unmodified lines
373	263	gc->label = dev_name(&pdev->dev);
374	264	gc->base = 0;
375	265	gc->parent = &pdev->dev;
376		− gc->ngpio = ngpio;
377		− gc->of_node = pdev->dev.of_node;
	266	+ gc->ngpio = 70;
378	267	gc->direction_output = xlp_gpio_dir_output;
379	268	gc->direction_input = xlp_gpio_dir_input;
380	269	gc->set = xlp_gpio_set;
@@ -382,19 +271,6 @@ static int xlp_gpio_probe(struct platform_device *pdev) · 1 unmodified line
382	271
383	272	spin_lock_init(&priv->lock);
384	273
385		− /* XLP(MIPS) has fixed range for GPIO IRQs, Vulcan(ARM64) does not */
386		− if (soc_type != GPIO_VARIANT_VULCAN) {
387		− irq_base = devm_irq_alloc_descs(&pdev->dev, -1,
388		− XLP_GPIO_IRQ_BASE,
389		− gc->ngpio, 0);
390		− if (irq_base < 0) {
391		− dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
392		− return irq_base;
393		− }
394		− } else {
395		− irq_base = 0;
396		− }
397		−
398	274	girq = &gc->irq;
399	275	girq->chip = &xlp_gpio_irq_chip;
400	276	girq->parent_handler = xlp_gpio_generic_handler;
@@ -405,7 +281,7 @@ static int xlp_gpio_probe(struct platform_device *pdev) · 4 unmodified lines
405	281	if (!girq->parents)
406	282	return -ENOMEM;
407	283	girq->parents[0] = irq;
408		− girq->first = irq_base;
	284	+ girq->first = 0;
409	285	girq->default_type = IRQ_TYPE_NONE;
410	286	girq->handler = handle_level_irq;
411	287
@@ -420,8 +296,8 @@ static int xlp_gpio_probe(struct platform_device *pdev) · 8 unmodified lines
420	296
421	297	#ifdef CONFIG_ACPI
422	298	static const struct acpi_device_id xlp_gpio_acpi_match[] = {
423		− { "BRCM9006", GPIO_VARIANT_VULCAN },
424		− { "CAV9006", GPIO_VARIANT_VULCAN },
	299	+ { "BRCM9006" },
	300	+ { "CAV9006" },
425	301	{},
426	302	};
427	303	MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
@@ -430,7 +306,6 @@ MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match); · 2 unmodified lines
430	306	static struct platform_driver xlp_gpio_driver = {
431	307	.driver = {
432	308	.name = "xlp-gpio",
433		− .of_match_table = xlp_gpio_of_ids,
434	309	.acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
435	310	},
436	311	.probe = xlp_gpio_probe,

drivers/gpio/gpiolib-acpi.c+25−29

@@ -219,14 +219,13 @@ EXPORT_SYMBOL_GPL(acpi_gpio_get_io_resource); · 218 unmodified lines
219	219	static void acpi_gpiochip_request_irq(struct acpi_gpio_chip *acpi_gpio,
220	220	struct acpi_gpio_event *event)
221	221	{
	222	+ struct device *parent = acpi_gpio->chip->parent;
222	223	int ret, value;
223	224
224	225	ret = request_threaded_irq(event->irq, NULL, event->handler,
225	226	event->irqflags \| IRQF_ONESHOT, "ACPI:Event", event);
226	227	if (ret) {
227		− dev_err(acpi_gpio->chip->parent,
228		− "Failed to setup interrupt handler for %d\n",
229		− event->irq);
	228	+ dev_err(parent, "Failed to setup interrupt handler for %d\n", event->irq);
230	229	return;
231	230	}
232	231
@@ -347,8 +346,7 @@ static bool acpi_gpio_in_ignore_list(const char *controller_in, int pin_in) · 114 unmodified lines
347	346
348	347	return false;
349	348	err:
350		− pr_err_once("Error invalid value for gpiolib_acpi.ignore_wake: %s\n",
351		− ignore_wake);
	349	+ pr_err_once("Error: Invalid value for gpiolib_acpi.ignore_wake: %s\n", ignore_wake);
352	350	return false;
353	351	}
354	352
@@ -579,36 +577,24 @@ void acpi_dev_remove_driver_gpios(struct acpi_device *adev) · 224 unmodified lines
579	577	}
580	578	EXPORT_SYMBOL_GPL(acpi_dev_remove_driver_gpios);
581	579
582		−static void devm_acpi_dev_release_driver_gpios(struct device dev, void res)
	580	+static void acpi_dev_release_driver_gpios(void *adev)
583	581	{
584		− acpi_dev_remove_driver_gpios(ACPI_COMPANION(dev));
	582	+ acpi_dev_remove_driver_gpios(adev);
585	583	}
586	584
587	585	int devm_acpi_dev_add_driver_gpios(struct device *dev,
588	586	const struct acpi_gpio_mapping *gpios)
589	587	{
590		− void *res;
	588	+ struct acpi_device *adev = ACPI_COMPANION(dev);
591	589	int ret;
592	590
593		− res = devres_alloc(devm_acpi_dev_release_driver_gpios, 0, GFP_KERNEL);
594		− if (!res)
595		− return -ENOMEM;
596		−
597		− ret = acpi_dev_add_driver_gpios(ACPI_COMPANION(dev), gpios);
598		− if (ret) {
599		− devres_free(res);
	591	+ ret = acpi_dev_add_driver_gpios(adev, gpios);
	592	+ if (ret)
600	593	return ret;
601		− }
602		− devres_add(dev, res);
603		− return 0;
604		−}
605		−EXPORT_SYMBOL_GPL(devm_acpi_dev_add_driver_gpios);
606	594
607		−void devm_acpi_dev_remove_driver_gpios(struct device *dev)
608		−{
609		− WARN_ON(devres_release(dev, devm_acpi_dev_release_driver_gpios, NULL, NULL));
	595	+ return devm_add_action_or_reset(dev, acpi_dev_release_driver_gpios, adev);
610	596	}
611		−EXPORT_SYMBOL_GPL(devm_acpi_dev_remove_driver_gpios);
	597	+EXPORT_SYMBOL_GPL(devm_acpi_dev_add_driver_gpios);
612	598
613	599	static bool acpi_get_driver_gpio_data(struct acpi_device *adev,
614	600	const char *name, int index,
@@ -941,7 +927,7 @@ struct gpio_desc acpi_find_gpio(struct device dev, · 326 unmodified lines
941	927
942	928	if (info.gpioint &&
943	929	(dflags == GPIOD_OUT_LOW \|\| dflags == GPIOD_OUT_HIGH)) {
944		− dev_dbg(dev, "refusing GpioInt() entry when doing GPIOD_OUT_* lookup\n");
	930	+ dev_dbg(&adev->dev, "refusing GpioInt() entry when doing GPIOD_OUT_* lookup\n");
945	931	return ERR_PTR(-ENOENT);
946	932	}
947	933
@@ -1056,10 +1042,17 @@ int acpi_dev_gpio_irq_get_by(struct acpi_device adev, const char name, int ind · 108 unmodified lines
1056	1042	irq_flags = acpi_dev_get_irq_type(info.triggering,
1057	1043	info.polarity);
1058	1044
1059		− /* Set type if specified and different than the current one */
1060		− if (irq_flags != IRQ_TYPE_NONE &&
1061		− irq_flags != irq_get_trigger_type(irq))
1062		− irq_set_irq_type(irq, irq_flags);
	1045	+ /*
	1046	+ * If the IRQ is not already in use then set type
	1047	+ * if specified and different than the current one.
	1048	+ */
	1049	+ if (can_request_irq(irq, irq_flags)) {
	1050	+ if (irq_flags != IRQ_TYPE_NONE &&
	1051	+ irq_flags != irq_get_trigger_type(irq))
	1052	+ irq_set_irq_type(irq, irq_flags);
	1053	+ } else {
	1054	+ dev_dbg(&adev->dev, "IRQ %d already in use\n", irq);
	1055	+ }
1063	1056
1064	1057	return irq;
1065	1058	}
@@ -1346,6 +1339,9 @@ void acpi_gpio_dev_init(struct gpio_chip gc, struct gpio_device gdev) · 280 unmodified lines
1346	1339	/* Set default fwnode to parent's one if present */
1347	1340	if (gc->parent)
1348	1341	ACPI_COMPANION_SET(&gdev->dev, ACPI_COMPANION(gc->parent));
	1342	+
	1343	+ if (gc->fwnode)
	1344	+ device_set_node(&gdev->dev, gc->fwnode);
1349	1345	}
1350	1346
1351	1347	static int acpi_gpio_package_count(const union acpi_object *obj)

drivers/gpio/gpiolib-of.c+3−0

@@ -1046,6 +1046,9 @@ void of_gpio_dev_init(struct gpio_chip gc, struct gpio_device gdev) · 1045 unmodified lines
1046	1046	if (gc->parent)
1047	1047	gdev->dev.of_node = gc->parent->of_node;
1048	1048
	1049	+ if (gc->fwnode)
	1050	+ gc->of_node = to_of_node(gc->fwnode);
	1051	+
1049	1052	/* If the gpiochip has an assigned OF node this takes precedence */
1050	1053	if (gc->of_node)
1051	1054	gdev->dev.of_node = gc->of_node;

drivers/gpio/gpiolib.c+58−15

@@ -422,8 +422,16 @@ static int devprop_gpiochip_set_names(struct gpio_chip *chip) · 421 unmodified lines
422	422	if (count > chip->ngpio)
423	423	count = chip->ngpio;
424	424
425		− for (i = 0; i < count; i++)
426		− gdev->descs[i].name = names[chip->offset + i];
	425	+ for (i = 0; i < count; i++) {
	426	+ /*
	427	+ * Allow overriding "fixed" names provided by the GPIO
	428	+ * provider. The "fixed" names are more often than not
	429	+ * generic and less informative than the names given in
	430	+ * device properties.
	431	+ */
	432	+ if (names[chip->offset + i] && names[chip->offset + i][0])
	433	+ gdev->descs[i].name = names[chip->offset + i];
	434	+ }
427	435
428	436	kfree(names);
429	437
@@ -593,12 +601,18 @@ int gpiochip_add_data_with_key(struct gpio_chip gc, void data, · 163 unmodified lines
593	601	struct lock_class_key *lock_key,
594	602	struct lock_class_key *request_key)
595	603	{
596		− struct fwnode_handle *fwnode = gc->parent ? dev_fwnode(gc->parent) : NULL;
597		− unsigned long flags;
598		− int ret = 0;
599		− unsigned i;
600		− int base = gc->base;
	604	+ struct fwnode_handle *fwnode = NULL;
601	605	struct gpio_device *gdev;
	606	+ unsigned long flags;
	607	+ int base = gc->base;
	608	+ unsigned int i;
	609	+ int ret = 0;
	610	+ u32 ngpios;
	611	+
	612	+ if (gc->fwnode)
	613	+ fwnode = gc->fwnode;
	614	+ else if (gc->parent)
	615	+ fwnode = dev_fwnode(gc->parent);
602	616
603	617	/*
604	618	* First: allocate and populate the internal stat container, and
@@ -646,6 +660,26 @@ int gpiochip_add_data_with_key(struct gpio_chip gc, void data, · 41 unmodified lines
646	660	goto err_free_dev_name;
647	661	}
648	662
	663	+ /*
	664	+ * Try the device properties if the driver didn't supply the number
	665	+ * of GPIO lines.
	666	+ */
	667	+ if (gc->ngpio == 0) {
	668	+ ret = device_property_read_u32(&gdev->dev, "ngpios", &ngpios);
	669	+ if (ret == -ENODATA)
	670	+ /*
	671	+ * -ENODATA means that there is no property found and
	672	+ * we want to issue the error message to the user.
	673	+ * Besides that, we want to return different error code
	674	+ * to state that supplied value is not valid.
	675	+ */
	676	+ ngpios = 0;
	677	+ else if (ret)
	678	+ goto err_free_descs;
	679	+
	680	+ gc->ngpio = ngpios;
	681	+ }
	682	+
649	683	if (gc->ngpio == 0) {
650	684	chip_err(gc, "tried to insert a GPIO chip with zero lines\n");
651	685	ret = -EINVAL;
@@ -708,10 +742,12 @@ int gpiochip_add_data_with_key(struct gpio_chip gc, void data, · 56 unmodified lines
708	742	INIT_LIST_HEAD(&gdev->pin_ranges);
709	743	#endif
710	744
711		− if (gc->names)
	745	+ if (gc->names) {
712	746	ret = gpiochip_set_desc_names(gc);
713		− else
714		− ret = devprop_gpiochip_set_names(gc);
	747	+ if (ret)
	748	+ goto err_remove_from_list;
	749	+ }
	750	+ ret = devprop_gpiochip_set_names(gc);
715	751	if (ret)
716	752	goto err_remove_from_list;
717	753
@@ -3487,11 +3523,7 @@ EXPORT_SYMBOL_GPL(gpiod_set_array_value_cansleep); · 2769 unmodified lines
3487	3523	*/
3488	3524	void gpiod_add_lookup_table(struct gpiod_lookup_table *table)
3489	3525	{
3490		− mutex_lock(&gpio_lookup_lock);
3491		−
3492		− list_add_tail(&table->list, &gpio_lookup_list);
3493		−
3494		− mutex_unlock(&gpio_lookup_lock);
	3526	+ gpiod_add_lookup_tables(&table, 1);
3495	3527	}
3496	3528	EXPORT_SYMBOL_GPL(gpiod_add_lookup_table);
3497	3529
@@ -3540,6 +3572,17 @@ void gpiod_add_hogs(struct gpiod_hog *hogs) · 42 unmodified lines
3540	3572	}
3541	3573	EXPORT_SYMBOL_GPL(gpiod_add_hogs);
3542	3574
	3575	+void gpiod_remove_hogs(struct gpiod_hog *hogs)
	3576	+{
	3577	+ struct gpiod_hog *hog;
	3578	+
	3579	+ mutex_lock(&gpio_machine_hogs_mutex);
	3580	+ for (hog = &hogs[0]; hog->chip_label; hog++)
	3581	+ list_del(&hog->list);
	3582	+ mutex_unlock(&gpio_machine_hogs_mutex);
	3583	+}
	3584	+EXPORT_SYMBOL_GPL(gpiod_remove_hogs);
	3585	+
3543	3586	static struct gpiod_lookup_table gpiod_find_lookup_table(struct device dev)
3544	3587	{
3545	3588	const char *dev_id = dev ? dev_name(dev) : NULL;

include/dt-bindings/gpio/msc313-gpio.h+71−0

@@ -50,4 +50,75 @@ · 49 unmodified lines
50	50	#define MSC313_GPIO_SPI0_DI (MSC313_GPIO_SPI0 + 2)
51	51	#define MSC313_GPIO_SPI0_DO (MSC313_GPIO_SPI0 + 3)
52	52
	53	+/* SSD20x */
	54	+#define SSD20XD_GPIO_FUART 0
	55	+#define SSD20XD_GPIO_FUART_RX (SSD20XD_GPIO_FUART + 0)
	56	+#define SSD20XD_GPIO_FUART_TX (SSD20XD_GPIO_FUART + 1)
	57	+#define SSD20XD_GPIO_FUART_CTS (SSD20XD_GPIO_FUART + 2)
	58	+#define SSD20XD_GPIO_FUART_RTS (SSD20XD_GPIO_FUART + 3)
	59	+
	60	+#define SSD20XD_GPIO_SD (SSD20XD_GPIO_FUART_RTS + 1)
	61	+#define SSD20XD_GPIO_SD_CLK (SSD20XD_GPIO_SD + 0)
	62	+#define SSD20XD_GPIO_SD_CMD (SSD20XD_GPIO_SD + 1)
	63	+#define SSD20XD_GPIO_SD_D0 (SSD20XD_GPIO_SD + 2)
	64	+#define SSD20XD_GPIO_SD_D1 (SSD20XD_GPIO_SD + 3)
	65	+#define SSD20XD_GPIO_SD_D2 (SSD20XD_GPIO_SD + 4)
	66	+#define SSD20XD_GPIO_SD_D3 (SSD20XD_GPIO_SD + 5)
	67	+
	68	+#define SSD20XD_GPIO_UART0 (SSD20XD_GPIO_SD_D3 + 1)
	69	+#define SSD20XD_GPIO_UART0_RX (SSD20XD_GPIO_UART0 + 0)
	70	+#define SSD20XD_GPIO_UART0_TX (SSD20XD_GPIO_UART0 + 1)
	71	+
	72	+#define SSD20XD_GPIO_UART1 (SSD20XD_GPIO_UART0_TX + 1)
	73	+#define SSD20XD_GPIO_UART1_RX (SSD20XD_GPIO_UART1 + 0)
	74	+#define SSD20XD_GPIO_UART1_TX (SSD20XD_GPIO_UART1 + 1)
	75	+
	76	+#define SSD20XD_GPIO_TTL (SSD20XD_GPIO_UART1_TX + 1)
	77	+#define SSD20XD_GPIO_TTL0 (SSD20XD_GPIO_TTL + 0)
	78	+#define SSD20XD_GPIO_TTL1 (SSD20XD_GPIO_TTL + 1)
	79	+#define SSD20XD_GPIO_TTL2 (SSD20XD_GPIO_TTL + 2)
	80	+#define SSD20XD_GPIO_TTL3 (SSD20XD_GPIO_TTL + 3)
	81	+#define SSD20XD_GPIO_TTL4 (SSD20XD_GPIO_TTL + 4)
	82	+#define SSD20XD_GPIO_TTL5 (SSD20XD_GPIO_TTL + 5)
	83	+#define SSD20XD_GPIO_TTL6 (SSD20XD_GPIO_TTL + 6)
	84	+#define SSD20XD_GPIO_TTL7 (SSD20XD_GPIO_TTL + 7)
	85	+#define SSD20XD_GPIO_TTL8 (SSD20XD_GPIO_TTL + 8)
	86	+#define SSD20XD_GPIO_TTL9 (SSD20XD_GPIO_TTL + 9)
	87	+#define SSD20XD_GPIO_TTL10 (SSD20XD_GPIO_TTL + 10)
	88	+#define SSD20XD_GPIO_TTL11 (SSD20XD_GPIO_TTL + 11)
	89	+#define SSD20XD_GPIO_TTL12 (SSD20XD_GPIO_TTL + 12)
	90	+#define SSD20XD_GPIO_TTL13 (SSD20XD_GPIO_TTL + 13)
	91	+#define SSD20XD_GPIO_TTL14 (SSD20XD_GPIO_TTL + 14)
	92	+#define SSD20XD_GPIO_TTL15 (SSD20XD_GPIO_TTL + 15)
	93	+#define SSD20XD_GPIO_TTL16 (SSD20XD_GPIO_TTL + 16)
	94	+#define SSD20XD_GPIO_TTL17 (SSD20XD_GPIO_TTL + 17)
	95	+#define SSD20XD_GPIO_TTL18 (SSD20XD_GPIO_TTL + 18)
	96	+#define SSD20XD_GPIO_TTL19 (SSD20XD_GPIO_TTL + 19)
	97	+#define SSD20XD_GPIO_TTL20 (SSD20XD_GPIO_TTL + 20)
	98	+#define SSD20XD_GPIO_TTL21 (SSD20XD_GPIO_TTL + 21)
	99	+#define SSD20XD_GPIO_TTL22 (SSD20XD_GPIO_TTL + 22)
	100	+#define SSD20XD_GPIO_TTL23 (SSD20XD_GPIO_TTL + 23)
	101	+#define SSD20XD_GPIO_TTL24 (SSD20XD_GPIO_TTL + 24)
	102	+#define SSD20XD_GPIO_TTL25 (SSD20XD_GPIO_TTL + 25)
	103	+#define SSD20XD_GPIO_TTL26 (SSD20XD_GPIO_TTL + 26)
	104	+#define SSD20XD_GPIO_TTL27 (SSD20XD_GPIO_TTL + 27)
	105	+
	106	+#define SSD20XD_GPIO_GPIO (SSD20XD_GPIO_TTL27 + 1)
	107	+#define SSD20XD_GPIO_GPIO0 (SSD20XD_GPIO_GPIO + 0)
	108	+#define SSD20XD_GPIO_GPIO1 (SSD20XD_GPIO_GPIO + 1)
	109	+#define SSD20XD_GPIO_GPIO2 (SSD20XD_GPIO_GPIO + 2)
	110	+#define SSD20XD_GPIO_GPIO3 (SSD20XD_GPIO_GPIO + 3)
	111	+#define SSD20XD_GPIO_GPIO4 (SSD20XD_GPIO_GPIO + 4)
	112	+#define SSD20XD_GPIO_GPIO5 (SSD20XD_GPIO_GPIO + 5)
	113	+#define SSD20XD_GPIO_GPIO6 (SSD20XD_GPIO_GPIO + 6)
	114	+#define SSD20XD_GPIO_GPIO7 (SSD20XD_GPIO_GPIO + 7)
	115	+#define SSD20XD_GPIO_GPIO10 (SSD20XD_GPIO_GPIO + 8)
	116	+#define SSD20XD_GPIO_GPIO11 (SSD20XD_GPIO_GPIO + 9)
	117	+#define SSD20XD_GPIO_GPIO12 (SSD20XD_GPIO_GPIO + 10)
	118	+#define SSD20XD_GPIO_GPIO13 (SSD20XD_GPIO_GPIO + 11)
	119	+#define SSD20XD_GPIO_GPIO14 (SSD20XD_GPIO_GPIO + 12)
	120	+#define SSD20XD_GPIO_GPIO85 (SSD20XD_GPIO_GPIO + 13)
	121	+#define SSD20XD_GPIO_GPIO86 (SSD20XD_GPIO_GPIO + 14)
	122	+#define SSD20XD_GPIO_GPIO90 (SSD20XD_GPIO_GPIO + 15)
	123	+
53	124	#endif /* _DT_BINDINGS_MSC313_GPIO_H */

include/dt-bindings/gpio/tegra234-gpio.h+63−0

@@ -0,0 +1,63 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */
	3	+
	4	+/*
	5	+ * This header provides constants for binding nvidia,tegra234-gpio*.
	6	+ *
	7	+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
	8	+ * provide names for this.
	9	+ *
	10	+ * The second cell contains standard flag values specified in gpio.h.
	11	+ */
	12	+
	13	+#ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
	14	+#define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
	15	+
	16	+#include <dt-bindings/gpio/gpio.h>
	17	+
	18	+/* GPIOs implemented by main GPIO controller */
	19	+#define TEGRA234_MAIN_GPIO_PORT_A 0
	20	+#define TEGRA234_MAIN_GPIO_PORT_B 1
	21	+#define TEGRA234_MAIN_GPIO_PORT_C 2
	22	+#define TEGRA234_MAIN_GPIO_PORT_D 3
	23	+#define TEGRA234_MAIN_GPIO_PORT_E 4
	24	+#define TEGRA234_MAIN_GPIO_PORT_F 5
	25	+#define TEGRA234_MAIN_GPIO_PORT_G 6
	26	+#define TEGRA234_MAIN_GPIO_PORT_H 7
	27	+#define TEGRA234_MAIN_GPIO_PORT_I 8
	28	+#define TEGRA234_MAIN_GPIO_PORT_J 9
	29	+#define TEGRA234_MAIN_GPIO_PORT_K 10
	30	+#define TEGRA234_MAIN_GPIO_PORT_L 11
	31	+#define TEGRA234_MAIN_GPIO_PORT_M 12
	32	+#define TEGRA234_MAIN_GPIO_PORT_N 13
	33	+#define TEGRA234_MAIN_GPIO_PORT_P 14
	34	+#define TEGRA234_MAIN_GPIO_PORT_Q 15
	35	+#define TEGRA234_MAIN_GPIO_PORT_R 16
	36	+#define TEGRA234_MAIN_GPIO_PORT_S 17
	37	+#define TEGRA234_MAIN_GPIO_PORT_T 18
	38	+#define TEGRA234_MAIN_GPIO_PORT_U 19
	39	+#define TEGRA234_MAIN_GPIO_PORT_V 20
	40	+#define TEGRA234_MAIN_GPIO_PORT_X 21
	41	+#define TEGRA234_MAIN_GPIO_PORT_Y 22
	42	+#define TEGRA234_MAIN_GPIO_PORT_Z 23
	43	+#define TEGRA234_MAIN_GPIO_PORT_AC 24
	44	+#define TEGRA234_MAIN_GPIO_PORT_AD 25
	45	+#define TEGRA234_MAIN_GPIO_PORT_AE 26
	46	+#define TEGRA234_MAIN_GPIO_PORT_AF 27
	47	+#define TEGRA234_MAIN_GPIO_PORT_AG 28
	48	+
	49	+#define TEGRA234_MAIN_GPIO(port, offset) \
	50	+ ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset)
	51	+
	52	+/* GPIOs implemented by AON GPIO controller */
	53	+#define TEGRA234_AON_GPIO_PORT_AA 0
	54	+#define TEGRA234_AON_GPIO_PORT_BB 1
	55	+#define TEGRA234_AON_GPIO_PORT_CC 2
	56	+#define TEGRA234_AON_GPIO_PORT_DD 3
	57	+#define TEGRA234_AON_GPIO_PORT_EE 4
	58	+#define TEGRA234_AON_GPIO_PORT_GG 5
	59	+
	60	+#define TEGRA234_AON_GPIO(port, offset) \
	61	+ ((TEGRA234_AON_GPIO_PORT_##port * 8) + offset)
	62	+
	63	+#endif

include/dt-bindings/gpio/tegra241-gpio.h+42−0

@@ -0,0 +1,42 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. */
	3	+
	4	+/*
	5	+ * This header provides constants for the nvidia,tegra241-gpio DT binding.
	6	+ *
	7	+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
	8	+ * provide names for this.
	9	+ *
	10	+ * The second cell contains standard flag values specified in gpio.h.
	11	+ */
	12	+
	13	+#ifndef _DT_BINDINGS_GPIO_TEGRA241_GPIO_H
	14	+#define _DT_BINDINGS_GPIO_TEGRA241_GPIO_H
	15	+
	16	+#include <dt-bindings/gpio/gpio.h>
	17	+
	18	+/* GPIOs implemented by main GPIO controller */
	19	+#define TEGRA241_MAIN_GPIO_PORT_A 0
	20	+#define TEGRA241_MAIN_GPIO_PORT_B 1
	21	+#define TEGRA241_MAIN_GPIO_PORT_C 2
	22	+#define TEGRA241_MAIN_GPIO_PORT_D 3
	23	+#define TEGRA241_MAIN_GPIO_PORT_E 4
	24	+#define TEGRA241_MAIN_GPIO_PORT_F 5
	25	+#define TEGRA241_MAIN_GPIO_PORT_G 6
	26	+#define TEGRA241_MAIN_GPIO_PORT_H 7
	27	+#define TEGRA241_MAIN_GPIO_PORT_I 8
	28	+#define TEGRA241_MAIN_GPIO_PORT_J 9
	29	+#define TEGRA241_MAIN_GPIO_PORT_K 10
	30	+#define TEGRA241_MAIN_GPIO_PORT_L 11
	31	+
	32	+#define TEGRA241_MAIN_GPIO(port, offset) \
	33	+ ((TEGRA241_MAIN_GPIO_PORT_##port * 8) + (offset))
	34	+
	35	+/* GPIOs implemented by AON GPIO controller */
	36	+#define TEGRA241_AON_GPIO_PORT_AA 0
	37	+#define TEGRA241_AON_GPIO_PORT_BB 1
	38	+
	39	+#define TEGRA241_AON_GPIO(port, offset) \
	40	+ ((TEGRA241_AON_GPIO_PORT_##port * 8) + (offset))
	41	+
	42	+#endif

include/linux/gpio/consumer.h+0−2

@@ -690,7 +690,6 @@ void acpi_dev_remove_driver_gpios(struct acpi_device *adev); · 689 unmodified lines
690	690
691	691	int devm_acpi_dev_add_driver_gpios(struct device *dev,
692	692	const struct acpi_gpio_mapping *gpios);
693		−void devm_acpi_dev_remove_driver_gpios(struct device *dev);
694	693
695	694	struct gpio_desc acpi_get_and_request_gpiod(char path, int pin, char *label);
696	695
@@ -708,7 +707,6 @@ static inline int devm_acpi_dev_add_driver_gpios(struct device *dev, · 11 unmodified lines
708	707	{
709	708	return -ENXIO;
710	709	}
711		−static inline void devm_acpi_dev_remove_driver_gpios(struct device *dev) {}
712	710
713	711	#endif /* CONFIG_GPIOLIB && CONFIG_ACPI */
714	712

include/linux/gpio/driver.h+2−0

@@ -289,6 +289,7 @@ struct gpio_irq_chip { · 288 unmodified lines
289	289	* number or the name of the SoC IP-block implementing it.
290	290	* @gpiodev: the internal state holder, opaque struct
291	291	* @parent: optional parent device providing the GPIOs
	292	+ * @fwnode: optional fwnode providing this controller's properties
292	293	* @owner: helps prevent removal of modules exporting active GPIOs
293	294	* @request: optional hook for chip-specific activation, such as
294	295	* enabling module power and clock; may sleep
@@ -377,6 +378,7 @@ struct gpio_chip { · 82 unmodified lines
377	378	const char *label;
378	379	struct gpio_device *gpiodev;
379	380	struct device *parent;
	381	+ struct fwnode_handle *fwnode;
380	382	struct module *owner;
381	383
382	384	int (request)(struct gpio_chip gc,

include/linux/gpio/machine.h+2−0

@@ -100,6 +100,7 @@ void gpiod_add_lookup_table(struct gpiod_lookup_table *table); · 99 unmodified lines
100	100	void gpiod_add_lookup_tables(struct gpiod_lookup_table **tables, size_t n);
101	101	void gpiod_remove_lookup_table(struct gpiod_lookup_table *table);
102	102	void gpiod_add_hogs(struct gpiod_hog *hogs);
	103	+void gpiod_remove_hogs(struct gpiod_hog *hogs);
103	104	#else /* ! CONFIG_GPIOLIB */
104	105	static inline
105	106	void gpiod_add_lookup_table(struct gpiod_lookup_table *table) {}
@@ -108,6 +109,7 @@ void gpiod_add_lookup_tables(struct gpiod_lookup_table **tables, size_t n) {} · 2 unmodified lines
108	109	static inline
109	110	void gpiod_remove_lookup_table(struct gpiod_lookup_table *table) {}
110	111	static inline void gpiod_add_hogs(struct gpiod_hog *hogs) {}
	112	+static inline void gpiod_remove_hogs(struct gpiod_hog *hogs) {}
111	113	#endif /* CONFIG_GPIOLIB */
112	114
113	115	#endif /* __LINUX_GPIO_MACHINE_H */

tools/testing/selftests/gpio/.gitignore+2−0

@@ -1,2 +1,4 @@
1	1	# SPDX-License-Identifier: GPL-2.0-only
2	2	gpio-mockup-cdev
	3	+gpio-chip-info
	4	+gpio-line-name

tools/testing/selftests/gpio/Makefile+2−2

@@ -1,8 +1,8 @@
1	1	# SPDX-License-Identifier: GPL-2.0
2	2
3		−TEST_PROGS := gpio-mockup.sh
	3	+TEST_PROGS := gpio-mockup.sh gpio-sim.sh
4	4	TEST_FILES := gpio-mockup-sysfs.sh
5		−TEST_GEN_PROGS_EXTENDED := gpio-mockup-cdev
	5	+TEST_GEN_PROGS_EXTENDED := gpio-mockup-cdev gpio-chip-info gpio-line-name
6	6	CFLAGS += -O2 -g -Wall -I../../../../usr/include/
7	7
8	8	include ../lib.mk

tools/testing/selftests/gpio/config+1−0

@@ -1,3 +1,4 @@
1	1	CONFIG_GPIOLIB=y
2	2	CONFIG_GPIO_CDEV=y
3	3	CONFIG_GPIO_MOCKUP=m
	4	+CONFIG_GPIO_SIM=m

tools/testing/selftests/gpio/gpio-chip-info.c+57−0

@@ -0,0 +1,57 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
	2	+/*
	3	+ * GPIO character device helper for reading chip information.
	4	+ *
	5	+ * Copyright (C) 2021 Bartosz Golaszewski <brgl@bgdev.pl>
	6	+ */
	7	+
	8	+#include <fcntl.h>
	9	+#include <linux/gpio.h>
	10	+#include <stdio.h>
	11	+#include <stdlib.h>
	12	+#include <string.h>
	13	+#include <sys/ioctl.h>
	14	+#include <sys/types.h>
	15	+
	16	+static void print_usage(void)
	17	+{
	18	+ printf("usage:\n");
	19	+ printf(" gpio-chip-info <chip path> [name\|label\|num-lines]\n");
	20	+}
	21	+
	22	+int main(int argc, char **argv)
	23	+{
	24	+ struct gpiochip_info info;
	25	+ int fd, ret;
	26	+
	27	+ if (argc != 3) {
	28	+ print_usage();
	29	+ return EXIT_FAILURE;
	30	+ }
	31	+
	32	+ fd = open(argv[1], O_RDWR);
	33	+ if (fd < 0) {
	34	+ perror("unable to open the GPIO chip");
	35	+ return EXIT_FAILURE;
	36	+ }
	37	+
	38	+ memset(&info, 0, sizeof(info));
	39	+ ret = ioctl(fd, GPIO_GET_CHIPINFO_IOCTL, &info);
	40	+ if (ret) {
	41	+ perror("chip info ioctl failed");
	42	+ return EXIT_FAILURE;
	43	+ }
	44	+
	45	+ if (strcmp(argv[2], "name") == 0) {
	46	+ printf("%s\n", info.name);
	47	+ } else if (strcmp(argv[2], "label") == 0) {
	48	+ printf("%s\n", info.label);
	49	+ } else if (strcmp(argv[2], "num-lines") == 0) {
	50	+ printf("%u\n", info.lines);
	51	+ } else {
	52	+ fprintf(stderr, "unknown command: %s\n", argv[2]);
	53	+ return EXIT_FAILURE;
	54	+ }
	55	+
	56	+ return EXIT_SUCCESS;
	57	+}

tools/testing/selftests/gpio/gpio-line-name.c+55−0

@@ -0,0 +1,55 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
	2	+/*
	3	+ * GPIO character device helper for reading line names.
	4	+ *
	5	+ * Copyright (C) 2021 Bartosz Golaszewski <brgl@bgdev.pl>
	6	+ */
	7	+
	8	+#include <fcntl.h>
	9	+#include <linux/gpio.h>
	10	+#include <stdio.h>
	11	+#include <stdlib.h>
	12	+#include <string.h>
	13	+#include <sys/ioctl.h>
	14	+#include <sys/types.h>
	15	+
	16	+static void print_usage(void)
	17	+{
	18	+ printf("usage:\n");
	19	+ printf(" gpio-line-name <chip path> <line offset>\n");
	20	+}
	21	+
	22	+int main(int argc, char **argv)
	23	+{
	24	+ struct gpio_v2_line_info info;
	25	+ int fd, ret;
	26	+ char *endp;
	27	+
	28	+ if (argc != 3) {
	29	+ print_usage();
	30	+ return EXIT_FAILURE;
	31	+ }
	32	+
	33	+ fd = open(argv[1], O_RDWR);
	34	+ if (fd < 0) {
	35	+ perror("unable to open the GPIO chip");
	36	+ return EXIT_FAILURE;
	37	+ }
	38	+
	39	+ memset(&info, 0, sizeof(info));
	40	+ info.offset = strtoul(argv[2], &endp, 10);
	41	+ if (*endp != '\0') {
	42	+ print_usage();
	43	+ return EXIT_FAILURE;
	44	+ }
	45	+
	46	+ ret = ioctl(fd, GPIO_V2_GET_LINEINFO_IOCTL, &info);
	47	+ if (ret) {
	48	+ perror("line info ioctl failed");
	49	+ return EXIT_FAILURE;
	50	+ }
	51	+
	52	+ printf("%s\n", info.name);
	53	+
	54	+ return EXIT_SUCCESS;
	55	+}

tools/testing/selftests/gpio/gpio-sim.sh+396−0

@@ -0,0 +1,396 @@
	1	+#!/bin/sh
	2	+# SPDX-License-Identifier: GPL-2.0
	3	+# Copyright (C) 2021 Bartosz Golaszewski <brgl@bgdev.pl>
	4	+
	5	+BASE_DIR=`dirname $0`
	6	+CONFIGFS_DIR="/sys/kernel/config/gpio-sim"
	7	+MODULE="gpio-sim"
	8	+
	9	+fail() {
	10	+ echo "$*" >&2
	11	+ echo "GPIO $MODULE test FAIL"
	12	+ exit 1
	13	+}
	14	+
	15	+skip() {
	16	+ echo "$*" >&2
	17	+ echo "GPIO $MODULE test SKIP"
	18	+ exit 4
	19	+}
	20	+
	21	+remove_chip() {
	22	+ local CHIP=$1
	23	+
	24	+ for FILE in $CONFIGFS_DIR/$CHIP/*; do
	25	+ BANK=`basename $FILE`
	26	+ if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
	27	+ continue
	28	+ fi
	29	+
	30	+ LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ \| egrep ^line`
	31	+ if [ "$?" = 0 ]; then
	32	+ for LINE in $LINES; do
	33	+ if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
	34	+ rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog \|\| \
	35	+ fail "Unable to remove the hog"
	36	+ fi
	37	+
	38	+ rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE \|\| \
	39	+ fail "Unable to remove the line"
	40	+ done
	41	+ fi
	42	+
	43	+ rmdir $CONFIGFS_DIR/$CHIP/$BANK
	44	+ done
	45	+
	46	+ rmdir $CONFIGFS_DIR/$CHIP \|\| fail "Unable to remove the chip"
	47	+}
	48	+
	49	+configfs_cleanup() {
	50	+ for CHIP in `ls $CONFIGFS_DIR/`; do
	51	+ remove_chip $CHIP
	52	+ done
	53	+}
	54	+
	55	+create_chip() {
	56	+ local CHIP=$1
	57	+
	58	+ mkdir $CONFIGFS_DIR/$CHIP
	59	+}
	60	+
	61	+create_bank() {
	62	+ local CHIP=$1
	63	+ local BANK=$2
	64	+
	65	+ mkdir $CONFIGFS_DIR/$CHIP/$BANK
	66	+}
	67	+
	68	+set_label() {
	69	+ local CHIP=$1
	70	+ local BANK=$2
	71	+ local LABEL=$3
	72	+
	73	+ echo $LABEL > $CONFIGFS_DIR/$CHIP/$BANK/label \|\| fail "Unable to set the chip label"
	74	+}
	75	+
	76	+set_num_lines() {
	77	+ local CHIP=$1
	78	+ local BANK=$2
	79	+ local NUM_LINES=$3
	80	+
	81	+ echo $NUM_LINES > $CONFIGFS_DIR/$CHIP/$BANK/num_lines \|\| \
	82	+ fail "Unable to set the number of lines"
	83	+}
	84	+
	85	+set_line_name() {
	86	+ local CHIP=$1
	87	+ local BANK=$2
	88	+ local OFFSET=$3
	89	+ local NAME=$4
	90	+ local LINE_DIR=$CONFIGFS_DIR/$CHIP/$BANK/line$OFFSET
	91	+
	92	+ test -d $LINE_DIR \|\| mkdir $LINE_DIR
	93	+ echo $NAME > $LINE_DIR/name \|\| fail "Unable to set the line name"
	94	+}
	95	+
	96	+enable_chip() {
	97	+ local CHIP=$1
	98	+
	99	+ echo 1 > $CONFIGFS_DIR/$CHIP/live \|\| fail "Unable to enable the chip"
	100	+}
	101	+
	102	+disable_chip() {
	103	+ local CHIP=$1
	104	+
	105	+ echo 0 > $CONFIGFS_DIR/$CHIP/live \|\| fail "Unable to disable the chip"
	106	+}
	107	+
	108	+configfs_chip_name() {
	109	+ local CHIP=$1
	110	+ local BANK=$2
	111	+
	112	+ cat $CONFIGFS_DIR/$CHIP/$BANK/chip_name 2> /dev/null \|\| \
	113	+ fail "unable to read the chip name from configfs"
	114	+}
	115	+
	116	+configfs_dev_name() {
	117	+ local CHIP=$1
	118	+
	119	+ cat $CONFIGFS_DIR/$CHIP/dev_name 2> /dev/null \|\| \
	120	+ fail "unable to read the device name from configfs"
	121	+}
	122	+
	123	+get_chip_num_lines() {
	124	+ local CHIP=$1
	125	+ local BANK=$2
	126	+
	127	+ $BASE_DIR/gpio-chip-info /dev/`configfs_chip_name $CHIP $BANK` num-lines \|\| \
	128	+ fail "unable to read the number of lines from the character device"
	129	+}
	130	+
	131	+get_chip_label() {
	132	+ local CHIP=$1
	133	+ local BANK=$2
	134	+
	135	+ $BASE_DIR/gpio-chip-info /dev/`configfs_chip_name $CHIP $BANK` label \|\| \
	136	+ fail "unable to read the chip label from the character device"
	137	+}
	138	+
	139	+get_line_name() {
	140	+ local CHIP=$1
	141	+ local BANK=$2
	142	+ local OFFSET=$3
	143	+
	144	+ $BASE_DIR/gpio-line-name /dev/`configfs_chip_name $CHIP $BANK` $OFFSET \|\| \
	145	+ fail "unable to read the line name from the character device"
	146	+}
	147	+
	148	+sysfs_set_pull() {
	149	+ local DEV=$1
	150	+ local BANK=$2
	151	+ local OFFSET=$3
	152	+ local PULL=$4
	153	+ local DEVNAME=`configfs_dev_name $DEV`
	154	+ local CHIPNAME=`configfs_chip_name $DEV $BANK`
	155	+ local SYSFSPATH="/sys/devices/platform/$DEVNAME/$CHIPNAME/sim_gpio$OFFSET/pull"
	156	+
	157	+ echo $PULL > $SYSFSPATH \|\| fail "Unable to set line pull in sysfs"
	158	+}
	159	+
	160	+# Load the gpio-sim module. This will pull in configfs if needed too.
	161	+modprobe gpio-sim \|\| skip "unable to load the gpio-sim module"
	162	+# Make sure configfs is mounted at /sys/kernel/config. Wait a bit if needed.
	163	+for IDX in `seq 5`; do
	164	+ if [ "$IDX" -eq "5" ]; then
	165	+ skip "configfs not mounted at /sys/kernel/config"
	166	+ fi
	167	+
	168	+ mountpoint -q /sys/kernel/config && break
	169	+ sleep 0.1
	170	+done
	171	+# If the module was already loaded: remove all previous chips
	172	+configfs_cleanup
	173	+
	174	+trap "exit 1" SIGTERM SIGINT
	175	+trap configfs_cleanup EXIT
	176	+
	177	+echo "1. chip_name and dev_name attributes"
	178	+
	179	+echo "1.1. Chip name is communicated to user"
	180	+create_chip chip
	181	+create_bank chip bank
	182	+enable_chip chip
	183	+test -n `cat $CONFIGFS_DIR/chip/bank/chip_name` \|\| fail "chip_name doesn't work"
	184	+remove_chip chip
	185	+
	186	+echo "1.2. chip_name returns 'none' if the chip is still pending"
	187	+create_chip chip
	188	+create_bank chip bank
	189	+test "`cat $CONFIGFS_DIR/chip/bank/chip_name`" = "none" \|\| \
	190	+ fail "chip_name doesn't return 'none' for a pending chip"
	191	+remove_chip chip
	192	+
	193	+echo "1.3. Device name is communicated to user"
	194	+create_chip chip
	195	+create_bank chip bank
	196	+enable_chip chip
	197	+test -n `cat $CONFIGFS_DIR/chip/dev_name` \|\| fail "dev_name doesn't work"
	198	+remove_chip chip
	199	+
	200	+echo "2. Creating and configuring simulated chips"
	201	+
	202	+echo "2.1. Default number of lines is 1"
	203	+create_chip chip
	204	+create_bank chip bank
	205	+enable_chip chip
	206	+test "`get_chip_num_lines chip bank`" = "1" \|\| fail "default number of lines is not 1"
	207	+remove_chip chip
	208	+
	209	+echo "2.2. Number of lines can be specified"
	210	+create_chip chip
	211	+create_bank chip bank
	212	+set_num_lines chip bank 16
	213	+enable_chip chip
	214	+test "`get_chip_num_lines chip bank`" = "16" \|\| fail "number of lines is not 16"
	215	+remove_chip chip
	216	+
	217	+echo "2.3. Label can be set"
	218	+create_chip chip
	219	+create_bank chip bank
	220	+set_label chip bank foobar
	221	+enable_chip chip
	222	+test "`get_chip_label chip bank`" = "foobar" \|\| fail "label is incorrect"
	223	+remove_chip chip
	224	+
	225	+echo "2.4. Label can be left empty"
	226	+create_chip chip
	227	+create_bank chip bank
	228	+enable_chip chip
	229	+test -z "`cat $CONFIGFS_DIR/chip/bank/label`" \|\| fail "label is not empty"
	230	+remove_chip chip
	231	+
	232	+echo "2.5. Line names can be configured"
	233	+create_chip chip
	234	+create_bank chip bank
	235	+set_num_lines chip bank 16
	236	+set_line_name chip bank 0 foo
	237	+set_line_name chip bank 2 bar
	238	+enable_chip chip
	239	+test "`get_line_name chip bank 0`" = "foo" \|\| fail "line name is incorrect"
	240	+test "`get_line_name chip bank 2`" = "bar" \|\| fail "line name is incorrect"
	241	+remove_chip chip
	242	+
	243	+echo "2.6. Line config can remain unused if offset is greater than number of lines"
	244	+create_chip chip
	245	+create_bank chip bank
	246	+set_num_lines chip bank 2
	247	+set_line_name chip bank 5 foobar
	248	+enable_chip chip
	249	+test "`get_line_name chip bank 0`" = "" \|\| fail "line name is incorrect"
	250	+test "`get_line_name chip bank 1`" = "" \|\| fail "line name is incorrect"
	251	+remove_chip chip
	252	+
	253	+echo "2.7. Line configfs directory names are sanitized"
	254	+create_chip chip
	255	+create_bank chip bank
	256	+mkdir $CONFIGFS_DIR/chip/bank/line12foobar 2> /dev/null && \
	257	+ fail "invalid configfs line name accepted"
	258	+mkdir $CONFIGFS_DIR/chip/bank/line_no_offset 2> /dev/null && \
	259	+ fail "invalid configfs line name accepted"
	260	+remove_chip chip
	261	+
	262	+echo "2.8. Multiple chips can be created"
	263	+CHIPS="chip0 chip1 chip2"
	264	+for CHIP in $CHIPS; do
	265	+ create_chip $CHIP
	266	+ create_bank $CHIP bank
	267	+ enable_chip $CHIP
	268	+done
	269	+for CHIP in $CHIPS; do
	270	+ remove_chip $CHIP
	271	+done
	272	+
	273	+echo "2.9. Can't modify settings when chip is live"
	274	+create_chip chip
	275	+create_bank chip bank
	276	+enable_chip chip
	277	+echo foobar > $CONFIGFS_DIR/chip/bank/label 2> /dev/null && \
	278	+ fail "Setting label of a live chip should fail"
	279	+echo 8 > $CONFIGFS_DIR/chip/bank/num_lines 2> /dev/null && \
	280	+ fail "Setting number of lines of a live chip should fail"
	281	+remove_chip chip
	282	+
	283	+echo "2.10. Can't create line items when chip is live"
	284	+create_chip chip
	285	+create_bank chip bank
	286	+enable_chip chip
	287	+mkdir $CONFIGFS_DIR/chip/bank/line0 2> /dev/null && fail "Creating line item should fail"
	288	+remove_chip chip
	289	+
	290	+echo "2.11. Probe errors are propagated to user-space"
	291	+create_chip chip
	292	+create_bank chip bank
	293	+set_num_lines chip bank 99999
	294	+echo 1 > $CONFIGFS_DIR/chip/live 2> /dev/null && fail "Probe error was not propagated"
	295	+remove_chip chip
	296	+
	297	+echo "2.12. Cannot enable a chip without any GPIO banks"
	298	+create_chip chip
	299	+echo 1 > $CONFIGFS_DIR/chip/live 2> /dev/null && fail "Chip enabled without any GPIO banks"
	300	+remove_chip chip
	301	+
	302	+echo "2.13. Duplicate chip labels are not allowed"
	303	+create_chip chip
	304	+create_bank chip bank0
	305	+set_label chip bank0 foobar
	306	+create_bank chip bank1
	307	+set_label chip bank1 foobar
	308	+echo 1 > $CONFIGFS_DIR/chip/live 2> /dev/null && fail "Duplicate chip labels were not rejected"
	309	+remove_chip chip
	310	+
	311	+echo "2.14. Lines can be hogged"
	312	+create_chip chip
	313	+create_bank chip bank
	314	+set_num_lines chip bank 8
	315	+mkdir -p $CONFIGFS_DIR/chip/bank/line4/hog
	316	+enable_chip chip
	317	+$BASE_DIR/gpio-mockup-cdev -s 1 /dev/`configfs_chip_name chip bank` 4 2> /dev/null && \
	318	+ fail "Setting the value of a hogged line shouldn't succeed"
	319	+remove_chip chip
	320	+
	321	+echo "3. Controlling simulated chips"
	322	+
	323	+echo "3.1. Pull can be set over sysfs"
	324	+create_chip chip
	325	+create_bank chip bank
	326	+set_num_lines chip bank 8
	327	+enable_chip chip
	328	+sysfs_set_pull chip bank 0 pull-up
	329	+$BASE_DIR/gpio-mockup-cdev /dev/`configfs_chip_name chip bank` 0
	330	+test "$?" = "1" \|\| fail "pull set incorrectly"
	331	+sysfs_set_pull chip bank 0 pull-down
	332	+$BASE_DIR/gpio-mockup-cdev /dev/`configfs_chip_name chip bank` 1
	333	+test "$?" = "0" \|\| fail "pull set incorrectly"
	334	+remove_chip chip
	335	+
	336	+echo "3.2. Pull can be read from sysfs"
	337	+create_chip chip
	338	+create_bank chip bank
	339	+set_num_lines chip bank 8
	340	+enable_chip chip
	341	+DEVNAME=`configfs_dev_name chip`
	342	+CHIPNAME=`configfs_chip_name chip bank`
	343	+SYSFS_PATH=/sys/devices/platform/$DEVNAME/$CHIPNAME/sim_gpio0/pull
	344	+test `cat $SYSFS_PATH` = "pull-down" \|\| fail "reading the pull failed"
	345	+sysfs_set_pull chip bank 0 pull-up
	346	+test `cat $SYSFS_PATH` = "pull-up" \|\| fail "reading the pull failed"
	347	+remove_chip chip
	348	+
	349	+echo "3.3. Incorrect input in sysfs is rejected"
	350	+create_chip chip
	351	+create_bank chip bank
	352	+set_num_lines chip bank 8
	353	+enable_chip chip
	354	+DEVNAME=`configfs_dev_name chip`
	355	+CHIPNAME=`configfs_chip_name chip bank`
	356	+SYSFS_PATH="/sys/devices/platform/$DEVNAME/$CHIPNAME/sim_gpio0/pull"
	357	+echo foobar > $SYSFS_PATH 2> /dev/null && fail "invalid input not detected"
	358	+remove_chip chip
	359	+
	360	+echo "3.4. Can't write to value"
	361	+create_chip chip
	362	+create_bank chip bank
	363	+enable_chip chip
	364	+DEVNAME=`configfs_dev_name chip`
	365	+CHIPNAME=`configfs_chip_name chip bank`
	366	+SYSFS_PATH="/sys/devices/platform/$DEVNAME/$CHIPNAME/sim_gpio0/value"
	367	+echo 1 > $SYSFS_PATH 2> /dev/null && fail "writing to 'value' succeeded unexpectedly"
	368	+remove_chip chip
	369	+
	370	+echo "4. Simulated GPIO chips are functional"
	371	+
	372	+echo "4.1. Values can be read from sysfs"
	373	+create_chip chip
	374	+create_bank chip bank
	375	+set_num_lines chip bank 8
	376	+enable_chip chip
	377	+DEVNAME=`configfs_dev_name chip`
	378	+CHIPNAME=`configfs_chip_name chip bank`
	379	+SYSFS_PATH="/sys/devices/platform/$DEVNAME/$CHIPNAME/sim_gpio0/value"
	380	+test `cat $SYSFS_PATH` = "0" \|\| fail "incorrect value read from sysfs"
	381	+$BASE_DIR/gpio-mockup-cdev -s 1 /dev/`configfs_chip_name chip bank` 0 &
	382	+sleep 0.1 # FIXME Any better way?
	383	+test `cat $SYSFS_PATH` = "1" \|\| fail "incorrect value read from sysfs"
	384	+kill $!
	385	+remove_chip chip
	386	+
	387	+echo "4.2. Bias settings work correctly"
	388	+create_chip chip
	389	+create_bank chip bank
	390	+set_num_lines chip bank 8
	391	+enable_chip chip
	392	+$BASE_DIR/gpio-mockup-cdev -b pull-up /dev/`configfs_chip_name chip bank` 0
	393	+test `cat $SYSFS_PATH` = "1" \|\| fail "bias setting does not work"
	394	+remove_chip chip
	395	+
	396	+echo "GPIO $MODULE test PASS"

Merge tag 'gpio-updates-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux

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