Pull linus#master to merge PER_CPU_DEF_ATTRIBUTES and alpha build fix changes. As alpha in percpu tree uses 'weak' attribute instead of inline assembly, there's no need for __used attribute.
Unified · Split
| @@ -122,3 +122,10 @@ Description: · 121 unmodified lines | |||
| 122 | This symbolic link appears when a device is a Virtual Function. | 122 | This symbolic link appears when a device is a Virtual Function. |
| 123 | The symbolic link points to the PCI device sysfs entry of the | 123 | The symbolic link points to the PCI device sysfs entry of the |
| 124 | Physical Function this device associates with. | 124 | Physical Function this device associates with. |
| 125 | |||
| 126 | What: /sys/bus/pci/slots/.../module | ||
| 127 | Date: June 2009 | ||
| 128 | Contact: linux-pci@vger.kernel.org | ||
| 129 | Description: | ||
| 130 | This symbolic link points to the PCI hotplug controller driver | ||
| 131 | module that manages the hotplug slot. | ||
| @@ -0,0 +1,125 @@ | |||
| 1 | What: /sys/class/mtd/ | ||
| 2 | Date: April 2009 | ||
| 3 | KernelVersion: 2.6.29 | ||
| 4 | Contact: linux-mtd@lists.infradead.org | ||
| 5 | Description: | ||
| 6 | The mtd/ class subdirectory belongs to the MTD subsystem | ||
| 7 | (MTD core). | ||
| 8 | |||
| 9 | What: /sys/class/mtd/mtdX/ | ||
| 10 | Date: April 2009 | ||
| 11 | KernelVersion: 2.6.29 | ||
| 12 | Contact: linux-mtd@lists.infradead.org | ||
| 13 | Description: | ||
| 14 | The /sys/class/mtd/mtd{0,1,2,3,...} directories correspond | ||
| 15 | to each /dev/mtdX character device. These may represent | ||
| 16 | physical/simulated flash devices, partitions on a flash | ||
| 17 | device, or concatenated flash devices. They exist regardless | ||
| 18 | of whether CONFIG_MTD_CHAR is actually enabled. | ||
| 19 | |||
| 20 | What: /sys/class/mtd/mtdXro/ | ||
| 21 | Date: April 2009 | ||
| 22 | KernelVersion: 2.6.29 | ||
| 23 | Contact: linux-mtd@lists.infradead.org | ||
| 24 | Description: | ||
| 25 | These directories provide the corresponding read-only device | ||
| 26 | nodes for /sys/class/mtd/mtdX/ . They are only created | ||
| 27 | (for the benefit of udev) if CONFIG_MTD_CHAR is enabled. | ||
| 28 | |||
| 29 | What: /sys/class/mtd/mtdX/dev | ||
| 30 | Date: April 2009 | ||
| 31 | KernelVersion: 2.6.29 | ||
| 32 | Contact: linux-mtd@lists.infradead.org | ||
| 33 | Description: | ||
| 34 | Major and minor numbers of the character device corresponding | ||
| 35 | to this MTD device (in <major>:<minor> format). This is the | ||
| 36 | read-write device so <minor> will be even. | ||
| 37 | |||
| 38 | What: /sys/class/mtd/mtdXro/dev | ||
| 39 | Date: April 2009 | ||
| 40 | KernelVersion: 2.6.29 | ||
| 41 | Contact: linux-mtd@lists.infradead.org | ||
| 42 | Description: | ||
| 43 | Major and minor numbers of the character device corresponding | ||
| 44 | to the read-only variant of thie MTD device (in | ||
| 45 | <major>:<minor> format). In this case <minor> will be odd. | ||
| 46 | |||
| 47 | What: /sys/class/mtd/mtdX/erasesize | ||
| 48 | Date: April 2009 | ||
| 49 | KernelVersion: 2.6.29 | ||
| 50 | Contact: linux-mtd@lists.infradead.org | ||
| 51 | Description: | ||
| 52 | "Major" erase size for the device. If numeraseregions is | ||
| 53 | zero, this is the eraseblock size for the entire device. | ||
| 54 | Otherwise, the MEMGETREGIONCOUNT/MEMGETREGIONINFO ioctls | ||
| 55 | can be used to determine the actual eraseblock layout. | ||
| 56 | |||
| 57 | What: /sys/class/mtd/mtdX/flags | ||
| 58 | Date: April 2009 | ||
| 59 | KernelVersion: 2.6.29 | ||
| 60 | Contact: linux-mtd@lists.infradead.org | ||
| 61 | Description: | ||
| 62 | A hexadecimal value representing the device flags, ORed | ||
| 63 | together: | ||
| 64 | |||
| 65 | 0x0400: MTD_WRITEABLE - device is writable | ||
| 66 | 0x0800: MTD_BIT_WRITEABLE - single bits can be flipped | ||
| 67 | 0x1000: MTD_NO_ERASE - no erase necessary | ||
| 68 | 0x2000: MTD_POWERUP_LOCK - always locked after reset | ||
| 69 | |||
| 70 | What: /sys/class/mtd/mtdX/name | ||
| 71 | Date: April 2009 | ||
| 72 | KernelVersion: 2.6.29 | ||
| 73 | Contact: linux-mtd@lists.infradead.org | ||
| 74 | Description: | ||
| 75 | A human-readable ASCII name for the device or partition. | ||
| 76 | This will match the name in /proc/mtd . | ||
| 77 | |||
| 78 | What: /sys/class/mtd/mtdX/numeraseregions | ||
| 79 | Date: April 2009 | ||
| 80 | KernelVersion: 2.6.29 | ||
| 81 | Contact: linux-mtd@lists.infradead.org | ||
| 82 | Description: | ||
| 83 | For devices that have variable eraseblock sizes, this | ||
| 84 | provides the total number of erase regions. Otherwise, | ||
| 85 | it will read back as zero. | ||
| 86 | |||
| 87 | What: /sys/class/mtd/mtdX/oobsize | ||
| 88 | Date: April 2009 | ||
| 89 | KernelVersion: 2.6.29 | ||
| 90 | Contact: linux-mtd@lists.infradead.org | ||
| 91 | Description: | ||
| 92 | Number of OOB bytes per page. | ||
| 93 | |||
| 94 | What: /sys/class/mtd/mtdX/size | ||
| 95 | Date: April 2009 | ||
| 96 | KernelVersion: 2.6.29 | ||
| 97 | Contact: linux-mtd@lists.infradead.org | ||
| 98 | Description: | ||
| 99 | Total size of the device/partition, in bytes. | ||
| 100 | |||
| 101 | What: /sys/class/mtd/mtdX/type | ||
| 102 | Date: April 2009 | ||
| 103 | KernelVersion: 2.6.29 | ||
| 104 | Contact: linux-mtd@lists.infradead.org | ||
| 105 | Description: | ||
| 106 | One of the following ASCII strings, representing the device | ||
| 107 | type: | ||
| 108 | |||
| 109 | absent, ram, rom, nor, nand, dataflash, ubi, unknown | ||
| 110 | |||
| 111 | What: /sys/class/mtd/mtdX/writesize | ||
| 112 | Date: April 2009 | ||
| 113 | KernelVersion: 2.6.29 | ||
| 114 | Contact: linux-mtd@lists.infradead.org | ||
| 115 | Description: | ||
| 116 | Minimal writable flash unit size. This will always be | ||
| 117 | a positive integer. | ||
| 118 | |||
| 119 | In the case of NOR flash it is 1 (even though individual | ||
| 120 | bits can be cleared). | ||
| 121 | |||
| 122 | In the case of NAND flash it is one NAND page (or a | ||
| 123 | half page, or a quarter page). | ||
| 124 | |||
| 125 | In the case of ECC NOR, it is the ECC block size. | ||
| @@ -61,6 +61,10 @@ be initiated although firmwares have no _OSC support. To enable the · 60 unmodified lines | |||
| 61 | walkaround, pls. add aerdriver.forceload=y to kernel boot parameter line | 61 | walkaround, pls. add aerdriver.forceload=y to kernel boot parameter line |
| 62 | when booting kernel. Note that forceload=n by default. | 62 | when booting kernel. Note that forceload=n by default. |
| 63 | 63 | ||
| 64 | nosourceid, another parameter of type bool, can be used when broken | ||
| 65 | hardware (mostly chipsets) has root ports that cannot obtain the reporting | ||
| 66 | source ID. nosourceid=n by default. | ||
| 67 | |||
| 64 | 2.3 AER error output | 68 | 2.3 AER error output |
| 65 | When a PCI-E AER error is captured, an error message will be outputed to | 69 | When a PCI-E AER error is captured, an error message will be outputed to |
| 66 | console. If it's a correctable error, it is outputed as a warning. | 70 | console. If it's a correctable error, it is outputed as a warning. |
| @@ -246,3 +250,24 @@ with the PCI Express AER Root driver? · 179 unmodified lines | |||
| 246 | A: It could call the helper functions to enable AER in devices and | 250 | A: It could call the helper functions to enable AER in devices and |
| 247 | cleanup uncorrectable status register. Pls. refer to section 3.3. | 251 | cleanup uncorrectable status register. Pls. refer to section 3.3. |
| 248 | 252 | ||
| 253 | |||
| 254 | 4. Software error injection | ||
| 255 | |||
| 256 | Debugging PCIE AER error recovery code is quite difficult because it | ||
| 257 | is hard to trigger real hardware errors. Software based error | ||
| 258 | injection can be used to fake various kinds of PCIE errors. | ||
| 259 | |||
| 260 | First you should enable PCIE AER software error injection in kernel | ||
| 261 | configuration, that is, following item should be in your .config. | ||
| 262 | |||
| 263 | CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m | ||
| 264 | |||
| 265 | After reboot with new kernel or insert the module, a device file named | ||
| 266 | /dev/aer_inject should be created. | ||
| 267 | |||
| 268 | Then, you need a user space tool named aer-inject, which can be gotten | ||
| 269 | from: | ||
| 270 | http://www.kernel.org/pub/linux/utils/pci/aer-inject/ | ||
| 271 | |||
| 272 | More information about aer-inject can be found in the document comes | ||
| 273 | with its source code. | ||
| @@ -50,7 +50,7 @@ encouraged them to allow separation of the data and integrity metadata · 49 unmodified lines | |||
| 50 | scatter-gather lists. | 50 | scatter-gather lists. |
| 51 | 51 | ||
| 52 | The controller will interleave the buffers on write and split them on | 52 | The controller will interleave the buffers on write and split them on |
| 53 | read. This means that the Linux can DMA the data buffers to and from | 53 | read. This means that Linux can DMA the data buffers to and from |
| 54 | host memory without changes to the page cache. | 54 | host memory without changes to the page cache. |
| 55 | 55 | ||
| 56 | Also, the 16-bit CRC checksum mandated by both the SCSI and SATA specs | 56 | Also, the 16-bit CRC checksum mandated by both the SCSI and SATA specs |
| @@ -66,7 +66,7 @@ software RAID5). · 9 unmodified lines | |||
| 66 | 66 | ||
| 67 | The IP checksum is weaker than the CRC in terms of detecting bit | 67 | The IP checksum is weaker than the CRC in terms of detecting bit |
| 68 | errors. However, the strength is really in the separation of the data | 68 | errors. However, the strength is really in the separation of the data |
| 69 | buffers and the integrity metadata. These two distinct buffers much | 69 | buffers and the integrity metadata. These two distinct buffers must |
| 70 | match up for an I/O to complete. | 70 | match up for an I/O to complete. |
| 71 | 71 | ||
| 72 | The separation of the data and integrity metadata buffers as well as | 72 | The separation of the data and integrity metadata buffers as well as |
| @@ -777,6 +777,18 @@ in cpuset directories: · 776 unmodified lines | |||
| 777 | # /bin/echo 1-4 > cpus -> set cpus list to cpus 1,2,3,4 | 777 | # /bin/echo 1-4 > cpus -> set cpus list to cpus 1,2,3,4 |
| 778 | # /bin/echo 1,2,3,4 > cpus -> set cpus list to cpus 1,2,3,4 | 778 | # /bin/echo 1,2,3,4 > cpus -> set cpus list to cpus 1,2,3,4 |
| 779 | 779 | ||
| 780 | To add a CPU to a cpuset, write the new list of CPUs including the | ||
| 781 | CPU to be added. To add 6 to the above cpuset: | ||
| 782 | |||
| 783 | # /bin/echo 1-4,6 > cpus -> set cpus list to cpus 1,2,3,4,6 | ||
| 784 | |||
| 785 | Similarly to remove a CPU from a cpuset, write the new list of CPUs | ||
| 786 | without the CPU to be removed. | ||
| 787 | |||
| 788 | To remove all the CPUs: | ||
| 789 | |||
| 790 | # /bin/echo "" > cpus -> clear cpus list | ||
| 791 | |||
| 780 | 2.3 Setting flags | 792 | 2.3 Setting flags |
| 781 | ----------------- | 793 | ----------------- |
| 782 | 794 | ||
| @@ -0,0 +1,54 @@ | |||
| 1 | Device-Mapper Logging | ||
| 2 | ===================== | ||
| 3 | The device-mapper logging code is used by some of the device-mapper | ||
| 4 | RAID targets to track regions of the disk that are not consistent. | ||
| 5 | A region (or portion of the address space) of the disk may be | ||
| 6 | inconsistent because a RAID stripe is currently being operated on or | ||
| 7 | a machine died while the region was being altered. In the case of | ||
| 8 | mirrors, a region would be considered dirty/inconsistent while you | ||
| 9 | are writing to it because the writes need to be replicated for all | ||
| 10 | the legs of the mirror and may not reach the legs at the same time. | ||
| 11 | Once all writes are complete, the region is considered clean again. | ||
| 12 | |||
| 13 | There is a generic logging interface that the device-mapper RAID | ||
| 14 | implementations use to perform logging operations (see | ||
| 15 | dm_dirty_log_type in include/linux/dm-dirty-log.h). Various different | ||
| 16 | logging implementations are available and provide different | ||
| 17 | capabilities. The list includes: | ||
| 18 | |||
| 19 | Type Files | ||
| 20 | ==== ===== | ||
| 21 | disk drivers/md/dm-log.c | ||
| 22 | core drivers/md/dm-log.c | ||
| 23 | userspace drivers/md/dm-log-userspace* include/linux/dm-log-userspace.h | ||
| 24 | |||
| 25 | The "disk" log type | ||
| 26 | ------------------- | ||
| 27 | This log implementation commits the log state to disk. This way, the | ||
| 28 | logging state survives reboots/crashes. | ||
| 29 | |||
| 30 | The "core" log type | ||
| 31 | ------------------- | ||
| 32 | This log implementation keeps the log state in memory. The log state | ||
| 33 | will not survive a reboot or crash, but there may be a small boost in | ||
| 34 | performance. This method can also be used if no storage device is | ||
| 35 | available for storing log state. | ||
| 36 | |||
| 37 | The "userspace" log type | ||
| 38 | ------------------------ | ||
| 39 | This log type simply provides a way to export the log API to userspace, | ||
| 40 | so log implementations can be done there. This is done by forwarding most | ||
| 41 | logging requests to userspace, where a daemon receives and processes the | ||
| 42 | request. | ||
| 43 | |||
| 44 | The structure used for communication between kernel and userspace are | ||
| 45 | located in include/linux/dm-log-userspace.h. Due to the frequency, | ||
| 46 | diversity, and 2-way communication nature of the exchanges between | ||
| 47 | kernel and userspace, 'connector' is used as the interface for | ||
| 48 | communication. | ||
| 49 | |||
| 50 | There are currently two userspace log implementations that leverage this | ||
| 51 | framework - "clustered_disk" and "clustered_core". These implementations | ||
| 52 | provide a cluster-coherent log for shared-storage. Device-mapper mirroring | ||
| 53 | can be used in a shared-storage environment when the cluster log implementations | ||
| 54 | are employed. | ||
| @@ -0,0 +1,39 @@ | |||
| 1 | dm-queue-length | ||
| 2 | =============== | ||
| 3 | |||
| 4 | dm-queue-length is a path selector module for device-mapper targets, | ||
| 5 | which selects a path with the least number of in-flight I/Os. | ||
| 6 | The path selector name is 'queue-length'. | ||
| 7 | |||
| 8 | Table parameters for each path: [<repeat_count>] | ||
| 9 | <repeat_count>: The number of I/Os to dispatch using the selected | ||
| 10 | path before switching to the next path. | ||
| 11 | If not given, internal default is used. To check | ||
| 12 | the default value, see the activated table. | ||
| 13 | |||
| 14 | Status for each path: <status> <fail-count> <in-flight> | ||
| 15 | <status>: 'A' if the path is active, 'F' if the path is failed. | ||
| 16 | <fail-count>: The number of path failures. | ||
| 17 | <in-flight>: The number of in-flight I/Os on the path. | ||
| 18 | |||
| 19 | |||
| 20 | Algorithm | ||
| 21 | ========= | ||
| 22 | |||
| 23 | dm-queue-length increments/decrements 'in-flight' when an I/O is | ||
| 24 | dispatched/completed respectively. | ||
| 25 | dm-queue-length selects a path with the minimum 'in-flight'. | ||
| 26 | |||
| 27 | |||
| 28 | Examples | ||
| 29 | ======== | ||
| 30 | In case that 2 paths (sda and sdb) are used with repeat_count == 128. | ||
| 31 | |||
| 32 | # echo "0 10 multipath 0 0 1 1 queue-length 0 2 1 8:0 128 8:16 128" \ | ||
| 33 | dmsetup create test | ||
| 34 | # | ||
| 35 | # dmsetup table | ||
| 36 | test: 0 10 multipath 0 0 1 1 queue-length 0 2 1 8:0 128 8:16 128 | ||
| 37 | # | ||
| 38 | # dmsetup status | ||
| 39 | test: 0 10 multipath 2 0 0 0 1 1 E 0 2 1 8:0 A 0 0 8:16 A 0 0 | ||
| @@ -0,0 +1,91 @@ | |||
| 1 | dm-service-time | ||
| 2 | =============== | ||
| 3 | |||
| 4 | dm-service-time is a path selector module for device-mapper targets, | ||
| 5 | which selects a path with the shortest estimated service time for | ||
| 6 | the incoming I/O. | ||
| 7 | |||
| 8 | The service time for each path is estimated by dividing the total size | ||
| 9 | of in-flight I/Os on a path with the performance value of the path. | ||
| 10 | The performance value is a relative throughput value among all paths | ||
| 11 | in a path-group, and it can be specified as a table argument. | ||
| 12 | |||
| 13 | The path selector name is 'service-time'. | ||
| 14 | |||
| 15 | Table parameters for each path: [<repeat_count> [<relative_throughput>]] | ||
| 16 | <repeat_count>: The number of I/Os to dispatch using the selected | ||
| 17 | path before switching to the next path. | ||
| 18 | If not given, internal default is used. To check | ||
| 19 | the default value, see the activated table. | ||
| 20 | <relative_throughput>: The relative throughput value of the path | ||
| 21 | among all paths in the path-group. | ||
| 22 | The valid range is 0-100. | ||
| 23 | If not given, minimum value '1' is used. | ||
| 24 | If '0' is given, the path isn't selected while | ||
| 25 | other paths having a positive value are available. | ||
| 26 | |||
| 27 | Status for each path: <status> <fail-count> <in-flight-size> \ | ||
| 28 | <relative_throughput> | ||
| 29 | <status>: 'A' if the path is active, 'F' if the path is failed. | ||
| 30 | <fail-count>: The number of path failures. | ||
| 31 | <in-flight-size>: The size of in-flight I/Os on the path. | ||
| 32 | <relative_throughput>: The relative throughput value of the path | ||
| 33 | among all paths in the path-group. | ||
| 34 | |||
| 35 | |||
| 36 | Algorithm | ||
| 37 | ========= | ||
| 38 | |||
| 39 | dm-service-time adds the I/O size to 'in-flight-size' when the I/O is | ||
| 40 | dispatched and substracts when completed. | ||
| 41 | Basically, dm-service-time selects a path having minimum service time | ||
| 42 | which is calculated by: | ||
| 43 | |||
| 44 | ('in-flight-size' + 'size-of-incoming-io') / 'relative_throughput' | ||
| 45 | |||
| 46 | However, some optimizations below are used to reduce the calculation | ||
| 47 | as much as possible. | ||
| 48 | |||
| 49 | 1. If the paths have the same 'relative_throughput', skip | ||
| 50 | the division and just compare the 'in-flight-size'. | ||
| 51 | |||
| 52 | 2. If the paths have the same 'in-flight-size', skip the division | ||
| 53 | and just compare the 'relative_throughput'. | ||
| 54 | |||
| 55 | 3. If some paths have non-zero 'relative_throughput' and others | ||
| 56 | have zero 'relative_throughput', ignore those paths with zero | ||
| 57 | 'relative_throughput'. | ||
| 58 | |||
| 59 | If such optimizations can't be applied, calculate service time, and | ||
| 60 | compare service time. | ||
| 61 | If calculated service time is equal, the path having maximum | ||
| 62 | 'relative_throughput' may be better. So compare 'relative_throughput' | ||
| 63 | then. | ||
| 64 | |||
| 65 | |||
| 66 | Examples | ||
| 67 | ======== | ||
| 68 | In case that 2 paths (sda and sdb) are used with repeat_count == 128 | ||
| 69 | and sda has an average throughput 1GB/s and sdb has 4GB/s, | ||
| 70 | 'relative_throughput' value may be '1' for sda and '4' for sdb. | ||
| 71 | |||
| 72 | # echo "0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 1 8:16 128 4" \ | ||
| 73 | dmsetup create test | ||
| 74 | # | ||
| 75 | # dmsetup table | ||
| 76 | test: 0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 1 8:16 128 4 | ||
| 77 | # | ||
| 78 | # dmsetup status | ||
| 79 | test: 0 10 multipath 2 0 0 0 1 1 E 0 2 2 8:0 A 0 0 1 8:16 A 0 0 4 | ||
| 80 | |||
| 81 | |||
| 82 | Or '2' for sda and '8' for sdb would be also true. | ||
| 83 | |||
| 84 | # echo "0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 2 8:16 128 8" \ | ||
| 85 | dmsetup create test | ||
| 86 | # | ||
| 87 | # dmsetup table | ||
| 88 | test: 0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 2 8:16 128 8 | ||
| 89 | # | ||
| 90 | # dmsetup status | ||
| 91 | test: 0 10 multipath 2 0 0 0 1 1 E 0 2 2 8:0 A 0 0 2 8:16 A 0 0 8 | ||
| @@ -66,6 +66,10 @@ mandatory-locking.txt · 65 unmodified lines | |||
| 66 | - info on the Linux implementation of Sys V mandatory file locking. | 66 | - info on the Linux implementation of Sys V mandatory file locking. |
| 67 | ncpfs.txt | 67 | ncpfs.txt |
| 68 | - info on Novell Netware(tm) filesystem using NCP protocol. | 68 | - info on Novell Netware(tm) filesystem using NCP protocol. |
| 69 | nfs41-server.txt | ||
| 70 | - info on the Linux server implementation of NFSv4 minor version 1. | ||
| 71 | nfs-rdma.txt | ||
| 72 | - how to install and setup the Linux NFS/RDMA client and server software. | ||
| 69 | nfsroot.txt | 73 | nfsroot.txt |
| 70 | - short guide on setting up a diskless box with NFS root filesystem. | 74 | - short guide on setting up a diskless box with NFS root filesystem. |
| 71 | nilfs2.txt | 75 | nilfs2.txt |
| @@ -109,27 +109,28 @@ prototypes: · 108 unmodified lines | |||
| 109 | 109 | ||
| 110 | locking rules: | 110 | locking rules: |
| 111 | All may block. | 111 | All may block. |
| 112 | BKL s_lock s_umount | 112 | None have BKL |
| 113 | alloc_inode: no no no | 113 | s_umount |
| 114 | destroy_inode: no | 114 | alloc_inode: |
| 115 | dirty_inode: no (must not sleep) | 115 | destroy_inode: |
| 116 | write_inode: no | 116 | dirty_inode: (must not sleep) |
| 117 | drop_inode: no !!!inode_lock!!! | 117 | write_inode: |
| 118 | delete_inode: no | 118 | drop_inode: !!!inode_lock!!! |
| 119 | put_super: yes yes no | 119 | delete_inode: |
| 120 | write_super: no yes read | 120 | put_super: write |
| 121 | sync_fs: no no read | 121 | write_super: read |
| 122 | freeze_fs: ? | 122 | sync_fs: read |
| 123 | unfreeze_fs: ? | 123 | freeze_fs: read |
| 124 | statfs: no no no | 124 | unfreeze_fs: read |
| 125 | remount_fs: yes yes maybe (see below) | 125 | statfs: no |
| 126 | clear_inode: no | 126 | remount_fs: maybe (see below) |
| 127 | umount_begin: yes no no | 127 | clear_inode: |
| 128 | show_options: no (vfsmount->sem) | 128 | umount_begin: no |
| 129 | quota_read: no no no (see below) | 129 | show_options: no (namespace_sem) |
| 130 | quota_write: no no no (see below) | 130 | quota_read: no (see below) |
| 131 | 131 | quota_write: no (see below) | |
| 132 | ->remount_fs() will have the s_umount lock if it's already mounted. | 132 | |
| 133 | ->remount_fs() will have the s_umount exclusive lock if it's already mounted. | ||
| 133 | When called from get_sb_single, it does NOT have the s_umount lock. | 134 | When called from get_sb_single, it does NOT have the s_umount lock. |
| 134 | ->quota_read() and ->quota_write() functions are both guaranteed to | 135 | ->quota_read() and ->quota_write() functions are both guaranteed to |
| 135 | be the only ones operating on the quota file by the quota code (via | 136 | be the only ones operating on the quota file by the quota code (via |
| @@ -188,13 +188,18 @@ Solution: Exclude affected source files from profiling by specifying · 187 unmodified lines | |||
| 188 | GCOV_PROFILE := n or GCOV_PROFILE_basename.o := n in the | 188 | GCOV_PROFILE := n or GCOV_PROFILE_basename.o := n in the |
| 189 | corresponding Makefile. | 189 | corresponding Makefile. |
| 190 | 190 | ||
| 191 | Problem: Files copied from sysfs appear empty or incomplete. | ||
| 192 | Cause: Due to the way seq_file works, some tools such as cp or tar | ||
| 193 | may not correctly copy files from sysfs. | ||
| 194 | Solution: Use 'cat' to read .gcda files and 'cp -d' to copy links. | ||
| 195 | Alternatively use the mechanism shown in Appendix B. | ||
| 196 | |||
| 191 | 197 | ||
| 192 | Appendix A: gather_on_build.sh | 198 | Appendix A: gather_on_build.sh |
| 193 | ============================== | 199 | ============================== |
| 194 | 200 | ||
| 195 | Sample script to gather coverage meta files on the build machine | 201 | Sample script to gather coverage meta files on the build machine |
| 196 | (see 6a): | 202 | (see 6a): |
| 197 | |||
| 198 | #!/bin/bash | 203 | #!/bin/bash |
| 199 | 204 | ||
| 200 | KSRC=$1 | 205 | KSRC=$1 |
| @@ -226,7 +231,7 @@ Appendix B: gather_on_test.sh · 25 unmodified lines | |||
| 226 | Sample script to gather coverage data files on the test machine | 231 | Sample script to gather coverage data files on the test machine |
| 227 | (see 6b): | 232 | (see 6b): |
| 228 | 233 | ||
| 229 | #!/bin/bash | 234 | #!/bin/bash -e |
| 230 | 235 | ||
| 231 | DEST=$1 | 236 | DEST=$1 |
| 232 | GCDA=/sys/kernel/debug/gcov | 237 | GCDA=/sys/kernel/debug/gcov |
| @@ -236,11 +241,13 @@ if [ -z "$DEST" ] ; then · 3 unmodified lines | |||
| 236 | exit 1 | 241 | exit 1 |
| 237 | fi | 242 | fi |
| 238 | 243 | ||
| 239 | find $GCDA -name '*.gcno' -o -name '*.gcda' | tar cfz $DEST -T - | 244 | TEMPDIR=$(mktemp -d) |
| 245 | echo Collecting data.. | ||
| 246 | find $GCDA -type d -exec mkdir -p $TEMPDIR/\{\} \; | ||
| 247 | find $GCDA -name '*.gcda' -exec sh -c 'cat < $0 > '$TEMPDIR'/$0' {} \; | ||
| 248 | find $GCDA -name '*.gcno' -exec sh -c 'cp -d $0 '$TEMPDIR'/$0' {} \; | ||
| 249 | tar czf $DEST -C $TEMPDIR sys | ||
| 250 | rm -rf $TEMPDIR | ||
| 240 | 251 | ||
| 241 | if [ $? -eq 0 ] ; then | 252 | echo "$DEST successfully created, copy to build system and unpack with:" |
| 242 | echo "$DEST successfully created, copy to build system and unpack with:" | 253 | echo " tar xfz $DEST" |
| 243 | echo " tar xfz $DEST" | ||
| 244 | else | ||
| 245 | echo "Could not create file $DEST" | ||
| 246 | fi | ||
| @@ -14,25 +14,14 @@ README · 13 unmodified lines | |||
| 14 | - general info on what you need and what to do for Linux ISDN. | 14 | - general info on what you need and what to do for Linux ISDN. |
| 15 | README.FAQ | 15 | README.FAQ |
| 16 | - general info for FAQ. | 16 | - general info for FAQ. |
| 17 | README.audio | ||
| 18 | - info for running audio over ISDN. | ||
| 19 | README.fax | ||
| 20 | - info for using Fax over ISDN. | ||
| 21 | README.gigaset | ||
| 22 | - info on the drivers for Siemens Gigaset ISDN adapters. | ||
| 23 | README.icn | ||
| 24 | - info on the ICN-ISDN-card and its driver. | ||
| 25 | >>>>>>> 93af7aca44f0e82e67bda10a0fb73d383edcc8bd:Documentation/isdn/00-INDEX | ||
| 26 | README.HiSax | 17 | README.HiSax |
| 27 | - info on the HiSax driver which replaces the old teles. | 18 | - info on the HiSax driver which replaces the old teles. |
| 19 | README.act2000 | ||
| 20 | - info on driver for IBM ACT-2000 card. | ||
| 28 | README.audio | 21 | README.audio |
| 29 | - info for running audio over ISDN. | 22 | - info for running audio over ISDN. |
| 30 | README.avmb1 | 23 | README.avmb1 |
| 31 | - info on driver for AVM-B1 ISDN card. | 24 | - info on driver for AVM-B1 ISDN card. |
| 32 | README.act2000 | ||
| 33 | - info on driver for IBM ACT-2000 card. | ||
| 34 | README.eicon | ||
| 35 | - info on driver for Eicon active cards. | ||
| 36 | README.concap | 25 | README.concap |
| 37 | - info on "CONCAP" encapsulation protocol interface used for X.25. | 26 | - info on "CONCAP" encapsulation protocol interface used for X.25. |
| 38 | README.diversion | 27 | README.diversion |
| @@ -59,7 +48,3 @@ README.x25 · 20 unmodified lines | |||
| 59 | - info for running X.25 over ISDN. | 48 | - info for running X.25 over ISDN. |
| 60 | syncPPP.FAQ | 49 | syncPPP.FAQ |
| 61 | - frequently asked questions about running PPP over ISDN. | 50 | - frequently asked questions about running PPP over ISDN. |
| 62 | README.hysdn | ||
| 63 | - info on driver for Hypercope active HYSDN cards | ||
| 64 | README.mISDN | ||
| 65 | - info on the Modular ISDN subsystem (mISDN). | ||
| @@ -229,14 +229,6 @@ and is between 256 and 4096 characters. It is defined in the file · 228 unmodified lines | |||
| 229 | to assume that this machine's pmtimer latches its value | 229 | to assume that this machine's pmtimer latches its value |
| 230 | and always returns good values. | 230 | and always returns good values. |
| 231 | 231 | ||
| 232 | acpi.power_nocheck= [HW,ACPI] | ||
| 233 | Format: 1/0 enable/disable the check of power state. | ||
| 234 | On some bogus BIOS the _PSC object/_STA object of | ||
| 235 | power resource can't return the correct device power | ||
| 236 | state. In such case it is unneccessary to check its | ||
| 237 | power state again in power transition. | ||
| 238 | 1 : disable the power state check | ||
| 239 | |||
| 240 | acpi_sci= [HW,ACPI] ACPI System Control Interrupt trigger mode | 232 | acpi_sci= [HW,ACPI] ACPI System Control Interrupt trigger mode |
| 241 | Format: { level | edge | high | low } | 233 | Format: { level | edge | high | low } |
| 242 | 234 | ||
| @@ -1006,6 +998,7 @@ and is between 256 and 4096 characters. It is defined in the file · 763 unmodified lines | |||
| 1006 | nomerge | 998 | nomerge |
| 1007 | forcesac | 999 | forcesac |
| 1008 | soft | 1000 | soft |
| 1001 | pt [x86, IA64] | ||
| 1009 | 1002 | ||
| 1010 | io7= [HW] IO7 for Marvel based alpha systems | 1003 | io7= [HW] IO7 for Marvel based alpha systems |
| 1011 | See comment before marvel_specify_io7 in | 1004 | See comment before marvel_specify_io7 in |
| @@ -1369,6 +1362,27 @@ and is between 256 and 4096 characters. It is defined in the file · 357 unmodified lines | |||
| 1369 | min_addr=nn[KMG] [KNL,BOOT,ia64] All physical memory below this | 1362 | min_addr=nn[KMG] [KNL,BOOT,ia64] All physical memory below this |
| 1370 | physical address is ignored. | 1363 | physical address is ignored. |
| 1371 | 1364 | ||
| 1365 | mini2440= [ARM,HW,KNL] | ||
| 1366 | Format:[0..2][b][c][t] | ||
| 1367 | Default: "0tb" | ||
| 1368 | MINI2440 configuration specification: | ||
| 1369 | 0 - The attached screen is the 3.5" TFT | ||
| 1370 | 1 - The attached screen is the 7" TFT | ||
| 1371 | 2 - The VGA Shield is attached (1024x768) | ||
| 1372 | Leaving out the screen size parameter will not load | ||
| 1373 | the TFT driver, and the framebuffer will be left | ||
| 1374 | unconfigured. | ||
| 1375 | b - Enable backlight. The TFT backlight pin will be | ||
| 1376 | linked to the kernel VESA blanking code and a GPIO | ||
| 1377 | LED. This parameter is not necessary when using the | ||
| 1378 | VGA shield. | ||
| 1379 | c - Enable the s3c camera interface. | ||
| 1380 | t - Reserved for enabling touchscreen support. The | ||
| 1381 | touchscreen support is not enabled in the mainstream | ||
| 1382 | kernel as of 2.6.30, a preliminary port can be found | ||
| 1383 | in the "bleeding edge" mini2440 support kernel at | ||
| 1384 | http://repo.or.cz/w/linux-2.6/mini2440.git | ||
| 1385 | |||
| 1372 | mminit_loglevel= | 1386 | mminit_loglevel= |
| 1373 | [KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this | 1387 | [KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this |
| 1374 | parameter allows control of the logging verbosity for | 1388 | parameter allows control of the logging verbosity for |
| @@ -1410,6 +1424,16 @@ and is between 256 and 4096 characters. It is defined in the file · 35 unmodified lines | |||
| 1410 | mtdparts= [MTD] | 1424 | mtdparts= [MTD] |
| 1411 | See drivers/mtd/cmdlinepart.c. | 1425 | See drivers/mtd/cmdlinepart.c. |
| 1412 | 1426 | ||
| 1427 | onenand.bdry= [HW,MTD] Flex-OneNAND Boundary Configuration | ||
| 1428 | |||
| 1429 | Format: [die0_boundary][,die0_lock][,die1_boundary][,die1_lock] | ||
| 1430 | |||
| 1431 | boundary - index of last SLC block on Flex-OneNAND. | ||
| 1432 | The remaining blocks are configured as MLC blocks. | ||
| 1433 | lock - Configure if Flex-OneNAND boundary should be locked. | ||
| 1434 | Once locked, the boundary cannot be changed. | ||
| 1435 | 1 indicates lock status, 0 indicates unlock status. | ||
| 1436 | |||
| 1413 | mtdset= [ARM] | 1437 | mtdset= [ARM] |
| 1414 | ARM/S3C2412 JIVE boot control | 1438 | ARM/S3C2412 JIVE boot control |
| 1415 | 1439 | ||
| @@ -1776,6 +1800,9 @@ and is between 256 and 4096 characters. It is defined in the file · 360 unmodified lines | |||
| 1776 | root domains (aka PCI segments, in ACPI-speak). | 1800 | root domains (aka PCI segments, in ACPI-speak). |
| 1777 | nommconf [X86] Disable use of MMCONFIG for PCI | 1801 | nommconf [X86] Disable use of MMCONFIG for PCI |
| 1778 | Configuration | 1802 | Configuration |
| 1803 | check_enable_amd_mmconf [X86] check for and enable | ||
| 1804 | properly configured MMIO access to PCI | ||
| 1805 | config space on AMD family 10h CPU | ||
| 1779 | nomsi [MSI] If the PCI_MSI kernel config parameter is | 1806 | nomsi [MSI] If the PCI_MSI kernel config parameter is |
| 1780 | enabled, this kernel boot option can be used to | 1807 | enabled, this kernel boot option can be used to |
| 1781 | disable the use of MSI interrupts system-wide. | 1808 | disable the use of MSI interrupts system-wide. |
| @@ -1865,6 +1892,12 @@ and is between 256 and 4096 characters. It is defined in the file · 83 unmodified lines | |||
| 1865 | PAGE_SIZE is used as alignment. | 1892 | PAGE_SIZE is used as alignment. |
| 1866 | PCI-PCI bridge can be specified, if resource | 1893 | PCI-PCI bridge can be specified, if resource |
| 1867 | windows need to be expanded. | 1894 | windows need to be expanded. |
| 1895 | ecrc= Enable/disable PCIe ECRC (transaction layer | ||
| 1896 | end-to-end CRC checking). | ||
| 1897 | bios: Use BIOS/firmware settings. This is the | ||
| 1898 | the default. | ||
| 1899 | off: Turn ECRC off | ||
| 1900 | on: Turn ECRC on. | ||
| 1868 | 1901 | ||
| 1869 | pcie_aspm= [PCIE] Forcibly enable or disable PCIe Active State Power | 1902 | pcie_aspm= [PCIE] Forcibly enable or disable PCIe Active State Power |
| 1870 | Management. | 1903 | Management. |
| @@ -2440,7 +2473,8 @@ and is between 256 and 4096 characters. It is defined in the file · 569 unmodified lines | |||
| 2440 | 2473 | ||
| 2441 | tp720= [HW,PS2] | 2474 | tp720= [HW,PS2] |
| 2442 | 2475 | ||
| 2443 | trace_buf_size=nn[KMG] [ftrace] will set tracing buffer size. | 2476 | trace_buf_size=nn[KMG] |
| 2477 | [FTRACE] will set tracing buffer size. | ||
| 2444 | 2478 | ||
| 2445 | trix= [HW,OSS] MediaTrix AudioTrix Pro | 2479 | trix= [HW,OSS] MediaTrix AudioTrix Pro |
| 2446 | Format: | 2480 | Format: |
| @@ -16,13 +16,17 @@ Usage · 15 unmodified lines | |||
| 16 | ----- | 16 | ----- |
| 17 | 17 | ||
| 18 | CONFIG_DEBUG_KMEMLEAK in "Kernel hacking" has to be enabled. A kernel | 18 | CONFIG_DEBUG_KMEMLEAK in "Kernel hacking" has to be enabled. A kernel |
| 19 | thread scans the memory every 10 minutes (by default) and prints any new | 19 | thread scans the memory every 10 minutes (by default) and prints the |
| 20 | unreferenced objects found. To trigger an intermediate scan and display | 20 | number of new unreferenced objects found. To display the details of all |
| 21 | all the possible memory leaks: | 21 | the possible memory leaks: |
| 22 | 22 | ||
| 23 | # mount -t debugfs nodev /sys/kernel/debug/ | 23 | # mount -t debugfs nodev /sys/kernel/debug/ |
| 24 | # cat /sys/kernel/debug/kmemleak | 24 | # cat /sys/kernel/debug/kmemleak |
| 25 | 25 | ||
| 26 | To trigger an intermediate memory scan: | ||
| 27 | |||
| 28 | # echo scan > /sys/kernel/debug/kmemleak | ||
| 29 | |||
| 26 | Note that the orphan objects are listed in the order they were allocated | 30 | Note that the orphan objects are listed in the order they were allocated |
| 27 | and one object at the beginning of the list may cause other subsequent | 31 | and one object at the beginning of the list may cause other subsequent |
| 28 | objects to be reported as orphan. | 32 | objects to be reported as orphan. |
| @@ -31,16 +35,21 @@ Memory scanning parameters can be modified at run-time by writing to the · 2 unmodified lines | |||
| 31 | /sys/kernel/debug/kmemleak file. The following parameters are supported: | 35 | /sys/kernel/debug/kmemleak file. The following parameters are supported: |
| 32 | 36 | ||
| 33 | off - disable kmemleak (irreversible) | 37 | off - disable kmemleak (irreversible) |
| 34 | stack=on - enable the task stacks scanning | 38 | stack=on - enable the task stacks scanning (default) |
| 35 | stack=off - disable the tasks stacks scanning | 39 | stack=off - disable the tasks stacks scanning |
| 36 | scan=on - start the automatic memory scanning thread | 40 | scan=on - start the automatic memory scanning thread (default) |
| 37 | scan=off - stop the automatic memory scanning thread | 41 | scan=off - stop the automatic memory scanning thread |
| 38 | scan=<secs> - set the automatic memory scanning period in seconds (0 | 42 | scan=<secs> - set the automatic memory scanning period in seconds |
| 39 | to disable it) | 43 | (default 600, 0 to stop the automatic scanning) |
| 44 | scan - trigger a memory scan | ||
| 40 | 45 | ||
| 41 | Kmemleak can also be disabled at boot-time by passing "kmemleak=off" on | 46 | Kmemleak can also be disabled at boot-time by passing "kmemleak=off" on |
| 42 | the kernel command line. | 47 | the kernel command line. |
| 43 | 48 | ||
| 49 | Memory may be allocated or freed before kmemleak is initialised and | ||
| 50 | these actions are stored in an early log buffer. The size of this buffer | ||
| 51 | is configured via the CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE option. | ||
| 52 | |||
| 44 | Basic Algorithm | 53 | Basic Algorithm |
| 45 | --------------- | 54 | --------------- |
| 46 | 55 | ||
| @@ -920,7 +920,7 @@ The available commands are: · 919 unmodified lines | |||
| 920 | echo '<LED number> off' >/proc/acpi/ibm/led | 920 | echo '<LED number> off' >/proc/acpi/ibm/led |
| 921 | echo '<LED number> blink' >/proc/acpi/ibm/led | 921 | echo '<LED number> blink' >/proc/acpi/ibm/led |
| 922 | 922 | ||
| 923 | The <LED number> range is 0 to 7. The set of LEDs that can be | 923 | The <LED number> range is 0 to 15. The set of LEDs that can be |
| 924 | controlled varies from model to model. Here is the common ThinkPad | 924 | controlled varies from model to model. Here is the common ThinkPad |
| 925 | mapping: | 925 | mapping: |
| 926 | 926 | ||
| @@ -932,6 +932,11 @@ mapping: · 5 unmodified lines | |||
| 932 | 5 - UltraBase battery slot | 932 | 5 - UltraBase battery slot |
| 933 | 6 - (unknown) | 933 | 6 - (unknown) |
| 934 | 7 - standby | 934 | 7 - standby |
| 935 | 8 - dock status 1 | ||
| 936 | 9 - dock status 2 | ||
| 937 | 10, 11 - (unknown) | ||
| 938 | 12 - thinkvantage | ||
| 939 | 13, 14, 15 - (unknown) | ||
| 935 | 940 | ||
| 936 | All of the above can be turned on and off and can be made to blink. | 941 | All of the above can be turned on and off and can be made to blink. |
| 937 | 942 | ||
| @@ -940,10 +945,12 @@ sysfs notes: · 2 unmodified lines | |||
| 940 | The ThinkPad LED sysfs interface is described in detail by the LED class | 945 | The ThinkPad LED sysfs interface is described in detail by the LED class |
| 941 | documentation, in Documentation/leds-class.txt. | 946 | documentation, in Documentation/leds-class.txt. |
| 942 | 947 | ||
| 943 | The leds are named (in LED ID order, from 0 to 7): | 948 | The LEDs are named (in LED ID order, from 0 to 12): |
| 944 | "tpacpi::power", "tpacpi:orange:batt", "tpacpi:green:batt", | 949 | "tpacpi::power", "tpacpi:orange:batt", "tpacpi:green:batt", |
| 945 | "tpacpi::dock_active", "tpacpi::bay_active", "tpacpi::dock_batt", | 950 | "tpacpi::dock_active", "tpacpi::bay_active", "tpacpi::dock_batt", |
| 946 | "tpacpi::unknown_led", "tpacpi::standby". | 951 | "tpacpi::unknown_led", "tpacpi::standby", "tpacpi::dock_status1", |
| 952 | "tpacpi::dock_status2", "tpacpi::unknown_led2", "tpacpi::unknown_led3", | ||
| 953 | "tpacpi::thinkvantage". | ||
| 947 | 954 | ||
| 948 | Due to limitations in the sysfs LED class, if the status of the LED | 955 | Due to limitations in the sysfs LED class, if the status of the LED |
| 949 | indicators cannot be read due to an error, thinkpad-acpi will report it as | 956 | indicators cannot be read due to an error, thinkpad-acpi will report it as |
| @@ -958,6 +965,12 @@ ThinkPad indicator LED should blink in hardware accelerated mode, use the · 8 unmodified lines | |||
| 958 | "timer" trigger, and leave the delay_on and delay_off parameters set to | 965 | "timer" trigger, and leave the delay_on and delay_off parameters set to |
| 959 | zero (to request hardware acceleration autodetection). | 966 | zero (to request hardware acceleration autodetection). |
| 960 | 967 | ||
| 968 | LEDs that are known not to exist in a given ThinkPad model are not | ||
| 969 | made available through the sysfs interface. If you have a dock and you | ||
| 970 | notice there are LEDs listed for your ThinkPad that do not exist (and | ||
| 971 | are not in the dock), or if you notice that there are missing LEDs, | ||
| 972 | a report to ibm-acpi-devel@lists.sourceforge.net is appreciated. | ||
| 973 | |||
| 961 | 974 | ||
| 962 | ACPI sounds -- /proc/acpi/ibm/beep | 975 | ACPI sounds -- /proc/acpi/ibm/beep |
| 963 | ---------------------------------- | 976 | ---------------------------------- |
| @@ -1156,17 +1169,19 @@ may not be distinct. Later Lenovo models that implement the ACPI · 192 unmodified lines | |||
| 1156 | display backlight brightness control methods have 16 levels, ranging | 1169 | display backlight brightness control methods have 16 levels, ranging |
| 1157 | from 0 to 15. | 1170 | from 0 to 15. |
| 1158 | 1171 | ||
| 1159 | There are two interfaces to the firmware for direct brightness control, | 1172 | For IBM ThinkPads, there are two interfaces to the firmware for direct |
| 1160 | EC and UCMS (or CMOS). To select which one should be used, use the | 1173 | brightness control, EC and UCMS (or CMOS). To select which one should be |
| 1161 | brightness_mode module parameter: brightness_mode=1 selects EC mode, | 1174 | used, use the brightness_mode module parameter: brightness_mode=1 selects |
| 1162 | brightness_mode=2 selects UCMS mode, brightness_mode=3 selects EC | 1175 | EC mode, brightness_mode=2 selects UCMS mode, brightness_mode=3 selects EC |
| 1163 | mode with NVRAM backing (so that brightness changes are remembered | 1176 | mode with NVRAM backing (so that brightness changes are remembered across |
| 1164 | across shutdown/reboot). | 1177 | shutdown/reboot). |
| 1165 | 1178 | ||
| 1166 | The driver tries to select which interface to use from a table of | 1179 | The driver tries to select which interface to use from a table of |
| 1167 | defaults for each ThinkPad model. If it makes a wrong choice, please | 1180 | defaults for each ThinkPad model. If it makes a wrong choice, please |
| 1168 | report this as a bug, so that we can fix it. | 1181 | report this as a bug, so that we can fix it. |
| 1169 | 1182 | ||
| 1183 | Lenovo ThinkPads only support brightness_mode=2 (UCMS). | ||
| 1184 | |||
| 1170 | When display backlight brightness controls are available through the | 1185 | When display backlight brightness controls are available through the |
| 1171 | standard ACPI interface, it is best to use it instead of this direct | 1186 | standard ACPI interface, it is best to use it instead of this direct |
| 1172 | ThinkPad-specific interface. The driver will disable its native | 1187 | ThinkPad-specific interface. The driver will disable its native |
| @@ -1254,7 +1269,7 @@ Fan control and monitoring: fan speed, fan enable/disable · 81 unmodified lines | |||
| 1254 | 1269 | ||
| 1255 | procfs: /proc/acpi/ibm/fan | 1270 | procfs: /proc/acpi/ibm/fan |
| 1256 | sysfs device attributes: (hwmon "thinkpad") fan1_input, pwm1, | 1271 | sysfs device attributes: (hwmon "thinkpad") fan1_input, pwm1, |
| 1257 | pwm1_enable | 1272 | pwm1_enable, fan2_input |
| 1258 | sysfs hwmon driver attributes: fan_watchdog | 1273 | sysfs hwmon driver attributes: fan_watchdog |
| 1259 | 1274 | ||
| 1260 | NOTE NOTE NOTE: fan control operations are disabled by default for | 1275 | NOTE NOTE NOTE: fan control operations are disabled by default for |
| @@ -1267,6 +1282,9 @@ from the hardware registers of the embedded controller. This is known · 6 unmodified lines | |||
| 1267 | to work on later R, T, X and Z series ThinkPads but may show a bogus | 1282 | to work on later R, T, X and Z series ThinkPads but may show a bogus |
| 1268 | value on other models. | 1283 | value on other models. |
| 1269 | 1284 | ||
| 1285 | Some Lenovo ThinkPads support a secondary fan. This fan cannot be | ||
| 1286 | controlled separately, it shares the main fan control. | ||
| 1287 | |||
| 1270 | Fan levels: | 1288 | Fan levels: |
| 1271 | 1289 | ||
| 1272 | Most ThinkPad fans work in "levels" at the firmware interface. Level 0 | 1290 | Most ThinkPad fans work in "levels" at the firmware interface. Level 0 |
| @@ -1397,6 +1415,11 @@ hwmon device attribute fan1_input: · 124 unmodified lines | |||
| 1397 | which can take up to two minutes. May return rubbish on older | 1415 | which can take up to two minutes. May return rubbish on older |
| 1398 | ThinkPads. | 1416 | ThinkPads. |
| 1399 | 1417 | ||
| 1418 | hwmon device attribute fan2_input: | ||
| 1419 | Fan tachometer reading, in RPM, for the secondary fan. | ||
| 1420 | Available only on some ThinkPads. If the secondary fan is | ||
| 1421 | not installed, will always read 0. | ||
| 1422 | |||
| 1400 | hwmon driver attribute fan_watchdog: | 1423 | hwmon driver attribute fan_watchdog: |
| 1401 | Fan safety watchdog timer interval, in seconds. Minimum is | 1424 | Fan safety watchdog timer interval, in seconds. Minimum is |
| 1402 | 1 second, maximum is 120 seconds. 0 disables the watchdog. | 1425 | 1 second, maximum is 120 seconds. 0 disables the watchdog. |
| @@ -1555,3 +1578,7 @@ Sysfs interface changelog: · 152 unmodified lines | |||
| 1555 | 0x020300: hotkey enable/disable support removed, attributes | 1578 | 0x020300: hotkey enable/disable support removed, attributes |
| 1556 | hotkey_bios_enabled and hotkey_enable deprecated and | 1579 | hotkey_bios_enabled and hotkey_enable deprecated and |
| 1557 | marked for removal. | 1580 | marked for removal. |
| 1581 | |||
| 1582 | 0x020400: Marker for 16 LEDs support. Also, LEDs that are known | ||
| 1583 | to not exist in a given model are not registered with | ||
| 1584 | the LED sysfs class anymore. | ||
| @@ -0,0 +1,50 @@ | |||
| 1 | Kernel driver lp3944 | ||
| 2 | ==================== | ||
| 3 | |||
| 4 | * National Semiconductor LP3944 Fun-light Chip | ||
| 5 | Prefix: 'lp3944' | ||
| 6 | Addresses scanned: None (see the Notes section below) | ||
| 7 | Datasheet: Publicly available at the National Semiconductor website | ||
| 8 | http://www.national.com/pf/LP/LP3944.html | ||
| 9 | |||
| 10 | Authors: | ||
| 11 | Antonio Ospite <ospite@studenti.unina.it> | ||
| 12 | |||
| 13 | |||
| 14 | Description | ||
| 15 | ----------- | ||
| 16 | The LP3944 is a helper chip that can drive up to 8 leds, with two programmable | ||
| 17 | DIM modes; it could even be used as a gpio expander but this driver assumes it | ||
| 18 | is used as a led controller. | ||
| 19 | |||
| 20 | The DIM modes are used to set _blink_ patterns for leds, the pattern is | ||
| 21 | specified supplying two parameters: | ||
| 22 | - period: from 0s to 1.6s | ||
| 23 | - duty cycle: percentage of the period the led is on, from 0 to 100 | ||
| 24 | |||
| 25 | Setting a led in DIM0 or DIM1 mode makes it blink according to the pattern. | ||
| 26 | See the datasheet for details. | ||
| 27 | |||
| 28 | LP3944 can be found on Motorola A910 smartphone, where it drives the rgb | ||
| 29 | leds, the camera flash light and the lcds power. | ||
| 30 | |||
| 31 | |||
| 32 | Notes | ||
| 33 | ----- | ||
| 34 | The chip is used mainly in embedded contexts, so this driver expects it is | ||
| 35 | registered using the i2c_board_info mechanism. | ||
| 36 | |||
| 37 | To register the chip at address 0x60 on adapter 0, set the platform data | ||
| 38 | according to include/linux/leds-lp3944.h, set the i2c board info: | ||
| 39 | |||
| 40 | static struct i2c_board_info __initdata a910_i2c_board_info[] = { | ||
| 41 | { | ||
| 42 | I2C_BOARD_INFO("lp3944", 0x60), | ||
| 43 | .platform_data = &a910_lp3944_leds, | ||
| 44 | }, | ||
| 45 | }; | ||
| 46 | |||
| 47 | and register it in the platform init function | ||
| 48 | |||
| 49 | i2c_register_board_info(0, a910_i2c_board_info, | ||
| 50 | ARRAY_SIZE(a910_i2c_board_info)); | ||
| @@ -1238,1122 +1238,7 @@ descriptions for the SOC devices for which new nodes have been · 1237 unmodified lines | |||
| 1238 | defined; this list will expand as more and more SOC-containing | 1238 | defined; this list will expand as more and more SOC-containing |
| 1239 | platforms are moved over to use the flattened-device-tree model. | 1239 | platforms are moved over to use the flattened-device-tree model. |
| 1240 | 1240 | ||
| 1241 | a) PHY nodes | 1241 | VII - Specifying interrupt information for devices |
| 1242 | |||
| 1243 | Required properties: | ||
| 1244 | |||
| 1245 | - device_type : Should be "ethernet-phy" | ||
| 1246 | - interrupts : <a b> where a is the interrupt number and b is a | ||
| 1247 | field that represents an encoding of the sense and level | ||
| 1248 | information for the interrupt. This should be encoded based on | ||
| 1249 | the information in section 2) depending on the type of interrupt | ||
| 1250 | controller you have. | ||
| 1251 | - interrupt-parent : the phandle for the interrupt controller that | ||
| 1252 | services interrupts for this device. | ||
| 1253 | - reg : The ID number for the phy, usually a small integer | ||
| 1254 | - linux,phandle : phandle for this node; likely referenced by an | ||
| 1255 | ethernet controller node. | ||
| 1256 | |||
| 1257 | |||
| 1258 | Example: | ||
| 1259 | |||
| 1260 | ethernet-phy@0 { | ||
| 1261 | linux,phandle = <2452000> | ||
| 1262 | interrupt-parent = <40000>; | ||
| 1263 | interrupts = <35 1>; | ||
| 1264 | reg = <0>; | ||
| 1265 | device_type = "ethernet-phy"; | ||
| 1266 | }; | ||
| 1267 | |||
| 1268 | |||
| 1269 | b) Interrupt controllers | ||
| 1270 | |||
| 1271 | Some SOC devices contain interrupt controllers that are different | ||
| 1272 | from the standard Open PIC specification. The SOC device nodes for | ||
| 1273 | these types of controllers should be specified just like a standard | ||
| 1274 | OpenPIC controller. Sense and level information should be encoded | ||
| 1275 | as specified in section 2) of this chapter for each device that | ||
| 1276 | specifies an interrupt. | ||
| 1277 | |||
| 1278 | Example : | ||
| 1279 | |||
| 1280 | pic@40000 { | ||
| 1281 | linux,phandle = <40000>; | ||
| 1282 | interrupt-controller; | ||
| 1283 | #address-cells = <0>; | ||
| 1284 | reg = <40000 40000>; | ||
| 1285 | compatible = "chrp,open-pic"; | ||
| 1286 | device_type = "open-pic"; | ||
| 1287 | }; | ||
| 1288 | |||
| 1289 | c) 4xx/Axon EMAC ethernet nodes | ||
| 1290 | |||
| 1291 | The EMAC ethernet controller in IBM and AMCC 4xx chips, and also | ||
| 1292 | the Axon bridge. To operate this needs to interact with a ths | ||
| 1293 | special McMAL DMA controller, and sometimes an RGMII or ZMII | ||
| 1294 | interface. In addition to the nodes and properties described | ||
| 1295 | below, the node for the OPB bus on which the EMAC sits must have a | ||
| 1296 | correct clock-frequency property. | ||
| 1297 | |||
| 1298 | i) The EMAC node itself | ||
| 1299 | |||
| 1300 | Required properties: | ||
| 1301 | - device_type : "network" | ||
| 1302 | |||
| 1303 | - compatible : compatible list, contains 2 entries, first is | ||
| 1304 | "ibm,emac-CHIP" where CHIP is the host ASIC (440gx, | ||
| 1305 | 405gp, Axon) and second is either "ibm,emac" or | ||
| 1306 | "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", | ||
| 1307 | "ibm,emac4" | ||
| 1308 | - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ> | ||
| 1309 | - interrupt-parent : optional, if needed for interrupt mapping | ||
| 1310 | - reg : <registers mapping> | ||
| 1311 | - local-mac-address : 6 bytes, MAC address | ||
| 1312 | - mal-device : phandle of the associated McMAL node | ||
| 1313 | - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated | ||
| 1314 | with this EMAC | ||
| 1315 | - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated | ||
| 1316 | with this EMAC | ||
| 1317 | - cell-index : 1 cell, hardware index of the EMAC cell on a given | ||
| 1318 | ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on | ||
| 1319 | each Axon chip) | ||
| 1320 | - max-frame-size : 1 cell, maximum frame size supported in bytes | ||
| 1321 | - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec | ||
| 1322 | operations. | ||
| 1323 | For Axon, 2048 | ||
| 1324 | - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec | ||
| 1325 | operations. | ||
| 1326 | For Axon, 2048. | ||
| 1327 | - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate | ||
| 1328 | thresholds). | ||
| 1329 | For Axon, 0x00000010 | ||
| 1330 | - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds) | ||
| 1331 | in bytes. | ||
| 1332 | For Axon, 0x00000100 (I think ...) | ||
| 1333 | - phy-mode : string, mode of operations of the PHY interface. | ||
| 1334 | Supported values are: "mii", "rmii", "smii", "rgmii", | ||
| 1335 | "tbi", "gmii", rtbi", "sgmii". | ||
| 1336 | For Axon on CAB, it is "rgmii" | ||
| 1337 | - mdio-device : 1 cell, required iff using shared MDIO registers | ||
| 1338 | (440EP). phandle of the EMAC to use to drive the | ||
| 1339 | MDIO lines for the PHY used by this EMAC. | ||
| 1340 | - zmii-device : 1 cell, required iff connected to a ZMII. phandle of | ||
| 1341 | the ZMII device node | ||
| 1342 | - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII | ||
| 1343 | channel or 0xffffffff if ZMII is only used for MDIO. | ||
| 1344 | - rgmii-device : 1 cell, required iff connected to an RGMII. phandle | ||
| 1345 | of the RGMII device node. | ||
| 1346 | For Axon: phandle of plb5/plb4/opb/rgmii | ||
| 1347 | - rgmii-channel : 1 cell, required iff connected to an RGMII. Which | ||
| 1348 | RGMII channel is used by this EMAC. | ||
| 1349 | Fox Axon: present, whatever value is appropriate for each | ||
| 1350 | EMAC, that is the content of the current (bogus) "phy-port" | ||
| 1351 | property. | ||
| 1352 | |||
| 1353 | Optional properties: | ||
| 1354 | - phy-address : 1 cell, optional, MDIO address of the PHY. If absent, | ||
| 1355 | a search is performed. | ||
| 1356 | - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY | ||
| 1357 | for, used if phy-address is absent. bit 0x00000001 is | ||
| 1358 | MDIO address 0. | ||
| 1359 | For Axon it can be absent, though my current driver | ||
| 1360 | doesn't handle phy-address yet so for now, keep | ||
| 1361 | 0x00ffffff in it. | ||
| 1362 | - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec | ||
| 1363 | operations (if absent the value is the same as | ||
| 1364 | rx-fifo-size). For Axon, either absent or 2048. | ||
| 1365 | - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec | ||
| 1366 | operations (if absent the value is the same as | ||
| 1367 | tx-fifo-size). For Axon, either absent or 2048. | ||
| 1368 | - tah-device : 1 cell, optional. If connected to a TAH engine for | ||
| 1369 | offload, phandle of the TAH device node. | ||
| 1370 | - tah-channel : 1 cell, optional. If appropriate, channel used on the | ||
| 1371 | TAH engine. | ||
| 1372 | |||
| 1373 | Example: | ||
| 1374 | |||
| 1375 | EMAC0: ethernet@40000800 { | ||
| 1376 | device_type = "network"; | ||
| 1377 | compatible = "ibm,emac-440gp", "ibm,emac"; | ||
| 1378 | interrupt-parent = <&UIC1>; | ||
| 1379 | interrupts = <1c 4 1d 4>; | ||
| 1380 | reg = <40000800 70>; | ||
| 1381 | local-mac-address = [00 04 AC E3 1B 1E]; | ||
| 1382 | mal-device = <&MAL0>; | ||
| 1383 | mal-tx-channel = <0 1>; | ||
| 1384 | mal-rx-channel = <0>; | ||
| 1385 | cell-index = <0>; | ||
| 1386 | max-frame-size = <5dc>; | ||
| 1387 | rx-fifo-size = <1000>; | ||
| 1388 | tx-fifo-size = <800>; | ||
| 1389 | phy-mode = "rmii"; | ||
| 1390 | phy-map = <00000001>; | ||
| 1391 | zmii-device = <&ZMII0>; | ||
| 1392 | zmii-channel = <0>; | ||
| 1393 | }; | ||
| 1394 | |||
| 1395 | ii) McMAL node | ||
| 1396 | |||
| 1397 | Required properties: | ||
| 1398 | - device_type : "dma-controller" | ||
| 1399 | - compatible : compatible list, containing 2 entries, first is | ||
| 1400 | "ibm,mcmal-CHIP" where CHIP is the host ASIC (like | ||
| 1401 | emac) and the second is either "ibm,mcmal" or | ||
| 1402 | "ibm,mcmal2". | ||
| 1403 | For Axon, "ibm,mcmal-axon","ibm,mcmal2" | ||
| 1404 | - interrupts : <interrupt mapping for the MAL interrupts sources: | ||
| 1405 | 5 sources: tx_eob, rx_eob, serr, txde, rxde>. | ||
| 1406 | For Axon: This is _different_ from the current | ||
| 1407 | firmware. We use the "delayed" interrupts for txeob | ||
| 1408 | and rxeob. Thus we end up with mapping those 5 MPIC | ||
| 1409 | interrupts, all level positive sensitive: 10, 11, 32, | ||
| 1410 | 33, 34 (in decimal) | ||
| 1411 | - dcr-reg : < DCR registers range > | ||
| 1412 | - dcr-parent : if needed for dcr-reg | ||
| 1413 | - num-tx-chans : 1 cell, number of Tx channels | ||
| 1414 | - num-rx-chans : 1 cell, number of Rx channels | ||
| 1415 | |||
| 1416 | iii) ZMII node | ||
| 1417 | |||
| 1418 | Required properties: | ||
| 1419 | - compatible : compatible list, containing 2 entries, first is | ||
| 1420 | "ibm,zmii-CHIP" where CHIP is the host ASIC (like | ||
| 1421 | EMAC) and the second is "ibm,zmii". | ||
| 1422 | For Axon, there is no ZMII node. | ||
| 1423 | - reg : <registers mapping> | ||
| 1424 | |||
| 1425 | iv) RGMII node | ||
| 1426 | |||
| 1427 | Required properties: | ||
| 1428 | - compatible : compatible list, containing 2 entries, first is | ||
| 1429 | "ibm,rgmii-CHIP" where CHIP is the host ASIC (like | ||
| 1430 | EMAC) and the second is "ibm,rgmii". | ||
| 1431 | For Axon, "ibm,rgmii-axon","ibm,rgmii" | ||
| 1432 | - reg : <registers mapping> | ||
| 1433 | - revision : as provided by the RGMII new version register if | ||
| 1434 | available. | ||
| 1435 | For Axon: 0x0000012a | ||
| 1436 | |||
| 1437 | d) Xilinx IP cores | ||
| 1438 | |||
| 1439 | The Xilinx EDK toolchain ships with a set of IP cores (devices) for use | ||
| 1440 | in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range | ||
| 1441 | of standard device types (network, serial, etc.) and miscellaneous | ||
| 1442 | devices (gpio, LCD, spi, etc). Also, since these devices are | ||
| 1443 | implemented within the fpga fabric every instance of the device can be | ||
| 1444 | synthesised with different options that change the behaviour. | ||
| 1445 | |||
| 1446 | Each IP-core has a set of parameters which the FPGA designer can use to | ||
| 1447 | control how the core is synthesized. Historically, the EDK tool would | ||
| 1448 | extract the device parameters relevant to device drivers and copy them | ||
| 1449 | into an 'xparameters.h' in the form of #define symbols. This tells the | ||
| 1450 | device drivers how the IP cores are configured, but it requres the kernel | ||
| 1451 | to be recompiled every time the FPGA bitstream is resynthesized. | ||
| 1452 | |||
| 1453 | The new approach is to export the parameters into the device tree and | ||
| 1454 | generate a new device tree each time the FPGA bitstream changes. The | ||
| 1455 | parameters which used to be exported as #defines will now become | ||
| 1456 | properties of the device node. In general, device nodes for IP-cores | ||
| 1457 | will take the following form: | ||
| 1458 | |||
| 1459 | (name): (generic-name)@(base-address) { | ||
| 1460 | compatible = "xlnx,(ip-core-name)-(HW_VER)" | ||
| 1461 | [, (list of compatible devices), ...]; | ||
| 1462 | reg = <(baseaddr) (size)>; | ||
| 1463 | interrupt-parent = <&interrupt-controller-phandle>; | ||
| 1464 | interrupts = < ... >; | ||
| 1465 | xlnx,(parameter1) = "(string-value)"; | ||
| 1466 | xlnx,(parameter2) = <(int-value)>; | ||
| 1467 | }; | ||
| 1468 | |||
| 1469 | (generic-name): an open firmware-style name that describes the | ||
| 1470 | generic class of device. Preferably, this is one word, such | ||
| 1471 | as 'serial' or 'ethernet'. | ||
| 1472 | (ip-core-name): the name of the ip block (given after the BEGIN | ||
| 1473 | directive in system.mhs). Should be in lowercase | ||
| 1474 | and all underscores '_' converted to dashes '-'. | ||
| 1475 | (name): is derived from the "PARAMETER INSTANCE" value. | ||
| 1476 | (parameter#): C_* parameters from system.mhs. The C_ prefix is | ||
| 1477 | dropped from the parameter name, the name is converted | ||
| 1478 | to lowercase and all underscore '_' characters are | ||
| 1479 | converted to dashes '-'. | ||
| 1480 | (baseaddr): the baseaddr parameter value (often named C_BASEADDR). | ||
| 1481 | (HW_VER): from the HW_VER parameter. | ||
| 1482 | (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1). | ||
| 1483 | |||
| 1484 | Typically, the compatible list will include the exact IP core version | ||
| 1485 | followed by an older IP core version which implements the same | ||
| 1486 | interface or any other device with the same interface. | ||
| 1487 | |||
| 1488 | 'reg', 'interrupt-parent' and 'interrupts' are all optional properties. | ||
| 1489 | |||
| 1490 | For example, the following block from system.mhs: | ||
| 1491 | |||
| 1492 | BEGIN opb_uartlite | ||
| 1493 | PARAMETER INSTANCE = opb_uartlite_0 | ||
| 1494 | PARAMETER HW_VER = 1.00.b | ||
| 1495 | PARAMETER C_BAUDRATE = 115200 | ||
| 1496 | PARAMETER C_DATA_BITS = 8 | ||
| 1497 | PARAMETER C_ODD_PARITY = 0 | ||
| 1498 | PARAMETER C_USE_PARITY = 0 | ||
| 1499 | PARAMETER C_CLK_FREQ = 50000000 | ||
| 1500 | PARAMETER C_BASEADDR = 0xEC100000 | ||
| 1501 | PARAMETER C_HIGHADDR = 0xEC10FFFF | ||
| 1502 | BUS_INTERFACE SOPB = opb_7 | ||
| 1503 | PORT OPB_Clk = CLK_50MHz | ||
| 1504 | PORT Interrupt = opb_uartlite_0_Interrupt | ||
| 1505 | PORT RX = opb_uartlite_0_RX | ||
| 1506 | PORT TX = opb_uartlite_0_TX | ||
| 1507 | PORT OPB_Rst = sys_bus_reset_0 | ||
| 1508 | END | ||
| 1509 | |||
| 1510 | becomes the following device tree node: | ||
| 1511 | |||
| 1512 | opb_uartlite_0: serial@ec100000 { | ||
| 1513 | device_type = "serial"; | ||
| 1514 | compatible = "xlnx,opb-uartlite-1.00.b"; | ||
| 1515 | reg = <ec100000 10000>; | ||
| 1516 | interrupt-parent = <&opb_intc_0>; | ||
| 1517 | interrupts = <1 0>; // got this from the opb_intc parameters | ||
| 1518 | current-speed = <d#115200>; // standard serial device prop | ||
| 1519 | clock-frequency = <d#50000000>; // standard serial device prop | ||
| 1520 | xlnx,data-bits = <8>; | ||
| 1521 | xlnx,odd-parity = <0>; | ||
| 1522 | xlnx,use-parity = <0>; | ||
| 1523 | }; | ||
| 1524 | |||
| 1525 | Some IP cores actually implement 2 or more logical devices. In | ||
| 1526 | this case, the device should still describe the whole IP core with | ||
| 1527 | a single node and add a child node for each logical device. The | ||
| 1528 | ranges property can be used to translate from parent IP-core to the | ||
| 1529 | registers of each device. In addition, the parent node should be | ||
| 1530 | compatible with the bus type 'xlnx,compound', and should contain | ||
| 1531 | #address-cells and #size-cells, as with any other bus. (Note: this | ||
| 1532 | makes the assumption that both logical devices have the same bus | ||
| 1533 | binding. If this is not true, then separate nodes should be used | ||
| 1534 | for each logical device). The 'cell-index' property can be used to | ||
| 1535 | enumerate logical devices within an IP core. For example, the | ||
| 1536 | following is the system.mhs entry for the dual ps2 controller found | ||
| 1537 | on the ml403 reference design. | ||
| 1538 | |||
| 1539 | BEGIN opb_ps2_dual_ref | ||
| 1540 | PARAMETER INSTANCE = opb_ps2_dual_ref_0 | ||
| 1541 | PARAMETER HW_VER = 1.00.a | ||
| 1542 | PARAMETER C_BASEADDR = 0xA9000000 | ||
| 1543 | PARAMETER C_HIGHADDR = 0xA9001FFF | ||
| 1544 | BUS_INTERFACE SOPB = opb_v20_0 | ||
| 1545 | PORT Sys_Intr1 = ps2_1_intr | ||
| 1546 | PORT Sys_Intr2 = ps2_2_intr | ||
| 1547 | PORT Clkin1 = ps2_clk_rx_1 | ||
| 1548 | PORT Clkin2 = ps2_clk_rx_2 | ||
| 1549 | PORT Clkpd1 = ps2_clk_tx_1 | ||
| 1550 | PORT Clkpd2 = ps2_clk_tx_2 | ||
| 1551 | PORT Rx1 = ps2_d_rx_1 | ||
| 1552 | PORT Rx2 = ps2_d_rx_2 | ||
| 1553 | PORT Txpd1 = ps2_d_tx_1 | ||
| 1554 | PORT Txpd2 = ps2_d_tx_2 | ||
| 1555 | END | ||
| 1556 | |||
| 1557 | It would result in the following device tree nodes: | ||
| 1558 | |||
| 1559 | opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 { | ||
| 1560 | #address-cells = <1>; | ||
| 1561 | #size-cells = <1>; | ||
| 1562 | compatible = "xlnx,compound"; | ||
| 1563 | ranges = <0 a9000000 2000>; | ||
| 1564 | // If this device had extra parameters, then they would | ||
| 1565 | // go here. | ||
| 1566 | ps2@0 { | ||
| 1567 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | ||
| 1568 | reg = <0 40>; | ||
| 1569 | interrupt-parent = <&opb_intc_0>; | ||
| 1570 | interrupts = <3 0>; | ||
| 1571 | cell-index = <0>; | ||
| 1572 | }; | ||
| 1573 | ps2@1000 { | ||
| 1574 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | ||
| 1575 | reg = <1000 40>; | ||
| 1576 | interrupt-parent = <&opb_intc_0>; | ||
| 1577 | interrupts = <3 0>; | ||
| 1578 | cell-index = <0>; | ||
| 1579 | }; | ||
| 1580 | }; | ||
| 1581 | |||
| 1582 | Also, the system.mhs file defines bus attachments from the processor | ||
| 1583 | to the devices. The device tree structure should reflect the bus | ||
| 1584 | attachments. Again an example; this system.mhs fragment: | ||
| 1585 | |||
| 1586 | BEGIN ppc405_virtex4 | ||
| 1587 | PARAMETER INSTANCE = ppc405_0 | ||
| 1588 | PARAMETER HW_VER = 1.01.a | ||
| 1589 | BUS_INTERFACE DPLB = plb_v34_0 | ||
| 1590 | BUS_INTERFACE IPLB = plb_v34_0 | ||
| 1591 | END | ||
| 1592 | |||
| 1593 | BEGIN opb_intc | ||
| 1594 | PARAMETER INSTANCE = opb_intc_0 | ||
| 1595 | PARAMETER HW_VER = 1.00.c | ||
| 1596 | PARAMETER C_BASEADDR = 0xD1000FC0 | ||
| 1597 | PARAMETER C_HIGHADDR = 0xD1000FDF | ||
| 1598 | BUS_INTERFACE SOPB = opb_v20_0 | ||
| 1599 | END | ||
| 1600 | |||
| 1601 | BEGIN opb_uart16550 | ||
| 1602 | PARAMETER INSTANCE = opb_uart16550_0 | ||
| 1603 | PARAMETER HW_VER = 1.00.d | ||
| 1604 | PARAMETER C_BASEADDR = 0xa0000000 | ||
| 1605 | PARAMETER C_HIGHADDR = 0xa0001FFF | ||
| 1606 | BUS_INTERFACE SOPB = opb_v20_0 | ||
| 1607 | END | ||
| 1608 | |||
| 1609 | BEGIN plb_v34 | ||
| 1610 | PARAMETER INSTANCE = plb_v34_0 | ||
| 1611 | PARAMETER HW_VER = 1.02.a | ||
| 1612 | END | ||
| 1613 | |||
| 1614 | BEGIN plb_bram_if_cntlr | ||
| 1615 | PARAMETER INSTANCE = plb_bram_if_cntlr_0 | ||
| 1616 | PARAMETER HW_VER = 1.00.b | ||
| 1617 | PARAMETER C_BASEADDR = 0xFFFF0000 | ||
| 1618 | PARAMETER C_HIGHADDR = 0xFFFFFFFF | ||
| 1619 | BUS_INTERFACE SPLB = plb_v34_0 | ||
| 1620 | END | ||
| 1621 | |||
| 1622 | BEGIN plb2opb_bridge | ||
| 1623 | PARAMETER INSTANCE = plb2opb_bridge_0 | ||
| 1624 | PARAMETER HW_VER = 1.01.a | ||
| 1625 | PARAMETER C_RNG0_BASEADDR = 0x20000000 | ||
| 1626 | PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF | ||
| 1627 | PARAMETER C_RNG1_BASEADDR = 0x60000000 | ||
| 1628 | PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF | ||
| 1629 | PARAMETER C_RNG2_BASEADDR = 0x80000000 | ||
| 1630 | PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF | ||
| 1631 | PARAMETER C_RNG3_BASEADDR = 0xC0000000 | ||
| 1632 | PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF | ||
| 1633 | BUS_INTERFACE SPLB = plb_v34_0 | ||
| 1634 | BUS_INTERFACE MOPB = opb_v20_0 | ||
| 1635 | END | ||
| 1636 | |||
| 1637 | Gives this device tree (some properties removed for clarity): | ||
| 1638 | |||
| 1639 | plb@0 { | ||
| 1640 | #address-cells = <1>; | ||
| 1641 | #size-cells = <1>; | ||
| 1642 | compatible = "xlnx,plb-v34-1.02.a"; | ||
| 1643 | device_type = "ibm,plb"; | ||
| 1644 | ranges; // 1:1 translation | ||
| 1645 | |||
| 1646 | plb_bram_if_cntrl_0: bram@ffff0000 { | ||
| 1647 | reg = <ffff0000 10000>; | ||
| 1648 | } | ||
| 1649 | |||
| 1650 | opb@20000000 { | ||
| 1651 | #address-cells = <1>; | ||
| 1652 | #size-cells = <1>; | ||
| 1653 | ranges = <20000000 20000000 20000000 | ||
| 1654 | 60000000 60000000 20000000 | ||
| 1655 | 80000000 80000000 40000000 | ||
| 1656 | c0000000 c0000000 20000000>; | ||
| 1657 | |||
| 1658 | opb_uart16550_0: serial@a0000000 { | ||
| 1659 | reg = <a00000000 2000>; | ||
| 1660 | }; | ||
| 1661 | |||
| 1662 | opb_intc_0: interrupt-controller@d1000fc0 { | ||
| 1663 | reg = <d1000fc0 20>; | ||
| 1664 | }; | ||
| 1665 | }; | ||
| 1666 | }; | ||
| 1667 | |||
| 1668 | That covers the general approach to binding xilinx IP cores into the | ||
| 1669 | device tree. The following are bindings for specific devices: | ||
| 1670 | |||
| 1671 | i) Xilinx ML300 Framebuffer | ||
| 1672 | |||
| 1673 | Simple framebuffer device from the ML300 reference design (also on the | ||
| 1674 | ML403 reference design as well as others). | ||
| 1675 | |||
| 1676 | Optional properties: | ||
| 1677 | - resolution = <xres yres> : pixel resolution of framebuffer. Some | ||
| 1678 | implementations use a different resolution. | ||
| 1679 | Default is <d#640 d#480> | ||
| 1680 | - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory. | ||
| 1681 | Default is <d#1024 d#480>. | ||
| 1682 | - rotate-display (empty) : rotate display 180 degrees. | ||
| 1683 | |||
| 1684 | ii) Xilinx SystemACE | ||
| 1685 | |||
| 1686 | The Xilinx SystemACE device is used to program FPGAs from an FPGA | ||
| 1687 | bitstream stored on a CF card. It can also be used as a generic CF | ||
| 1688 | interface device. | ||
| 1689 | |||
| 1690 | Optional properties: | ||
| 1691 | - 8-bit (empty) : Set this property for SystemACE in 8 bit mode | ||
| 1692 | |||
| 1693 | iii) Xilinx EMAC and Xilinx TEMAC | ||
| 1694 | |||
| 1695 | Xilinx Ethernet devices. In addition to general xilinx properties | ||
| 1696 | listed above, nodes for these devices should include a phy-handle | ||
| 1697 | property, and may include other common network device properties | ||
| 1698 | like local-mac-address. | ||
| 1699 | |||
| 1700 | iv) Xilinx Uartlite | ||
| 1701 | |||
| 1702 | Xilinx uartlite devices are simple fixed speed serial ports. | ||
| 1703 | |||
| 1704 | Required properties: | ||
| 1705 | - current-speed : Baud rate of uartlite | ||
| 1706 | |||
| 1707 | v) Xilinx hwicap | ||
| 1708 | |||
| 1709 | Xilinx hwicap devices provide access to the configuration logic | ||
| 1710 | of the FPGA through the Internal Configuration Access Port | ||
| 1711 | (ICAP). The ICAP enables partial reconfiguration of the FPGA, | ||
| 1712 | readback of the configuration information, and some control over | ||
| 1713 | 'warm boots' of the FPGA fabric. | ||
| 1714 | |||
| 1715 | Required properties: | ||
| 1716 | - xlnx,family : The family of the FPGA, necessary since the | ||
| 1717 | capabilities of the underlying ICAP hardware | ||
| 1718 | differ between different families. May be | ||
| 1719 | 'virtex2p', 'virtex4', or 'virtex5'. | ||
| 1720 | |||
| 1721 | vi) Xilinx Uart 16550 | ||
| 1722 | |||
| 1723 | Xilinx UART 16550 devices are very similar to the NS16550 but with | ||
| 1724 | different register spacing and an offset from the base address. | ||
| 1725 | |||
| 1726 | Required properties: | ||
| 1727 | - clock-frequency : Frequency of the clock input | ||
| 1728 | - reg-offset : A value of 3 is required | ||
| 1729 | - reg-shift : A value of 2 is required | ||
| 1730 | |||
| 1731 | e) USB EHCI controllers | ||
| 1732 | |||
| 1733 | Required properties: | ||
| 1734 | - compatible : should be "usb-ehci". | ||
| 1735 | - reg : should contain at least address and length of the standard EHCI | ||
| 1736 | register set for the device. Optional platform-dependent registers | ||
| 1737 | (debug-port or other) can be also specified here, but only after | ||
| 1738 | definition of standard EHCI registers. | ||
| 1739 | - interrupts : one EHCI interrupt should be described here. | ||
| 1740 | If device registers are implemented in big endian mode, the device | ||
| 1741 | node should have "big-endian-regs" property. | ||
| 1742 | If controller implementation operates with big endian descriptors, | ||
| 1743 | "big-endian-desc" property should be specified. | ||
| 1744 | If both big endian registers and descriptors are used by the controller | ||
| 1745 | implementation, "big-endian" property can be specified instead of having | ||
| 1746 | both "big-endian-regs" and "big-endian-desc". | ||
| 1747 | |||
| 1748 | Example (Sequoia 440EPx): | ||
| 1749 | ehci@e0000300 { | ||
| 1750 | compatible = "ibm,usb-ehci-440epx", "usb-ehci"; | ||
| 1751 | interrupt-parent = <&UIC0>; | ||
| 1752 | interrupts = <1a 4>; | ||
| 1753 | reg = <0 e0000300 90 0 e0000390 70>; | ||
| 1754 | big-endian; | ||
| 1755 | }; | ||
| 1756 | |||
| 1757 | f) MDIO on GPIOs | ||
| 1758 | |||
| 1759 | Currently defined compatibles: | ||
| 1760 | - virtual,gpio-mdio | ||
| 1761 | |||
| 1762 | MDC and MDIO lines connected to GPIO controllers are listed in the | ||
| 1763 | gpios property as described in section VIII.1 in the following order: | ||
| 1764 | |||
| 1765 | MDC, MDIO. | ||
| 1766 | |||
| 1767 | Example: | ||
| 1768 | |||
| 1769 | mdio { | ||
| 1770 | compatible = "virtual,mdio-gpio"; | ||
| 1771 | #address-cells = <1>; | ||
| 1772 | #size-cells = <0>; | ||
| 1773 | gpios = <&qe_pio_a 11 | ||
| 1774 | &qe_pio_c 6>; | ||
| 1775 | }; | ||
| 1776 | |||
| 1777 | g) SPI (Serial Peripheral Interface) busses | ||
| 1778 | |||
| 1779 | SPI busses can be described with a node for the SPI master device | ||
| 1780 | and a set of child nodes for each SPI slave on the bus. For this | ||
| 1781 | discussion, it is assumed that the system's SPI controller is in | ||
| 1782 | SPI master mode. This binding does not describe SPI controllers | ||
| 1783 | in slave mode. | ||
| 1784 | |||
| 1785 | The SPI master node requires the following properties: | ||
| 1786 | - #address-cells - number of cells required to define a chip select | ||
| 1787 | address on the SPI bus. | ||
| 1788 | - #size-cells - should be zero. | ||
| 1789 | - compatible - name of SPI bus controller following generic names | ||
| 1790 | recommended practice. | ||
| 1791 | No other properties are required in the SPI bus node. It is assumed | ||
| 1792 | that a driver for an SPI bus device will understand that it is an SPI bus. | ||
| 1793 | However, the binding does not attempt to define the specific method for | ||
| 1794 | assigning chip select numbers. Since SPI chip select configuration is | ||
| 1795 | flexible and non-standardized, it is left out of this binding with the | ||
| 1796 | assumption that board specific platform code will be used to manage | ||
| 1797 | chip selects. Individual drivers can define additional properties to | ||
| 1798 | support describing the chip select layout. | ||
| 1799 | |||
| 1800 | SPI slave nodes must be children of the SPI master node and can | ||
| 1801 | contain the following properties. | ||
| 1802 | - reg - (required) chip select address of device. | ||
| 1803 | - compatible - (required) name of SPI device following generic names | ||
| 1804 | recommended practice | ||
| 1805 | - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz | ||
| 1806 | - spi-cpol - (optional) Empty property indicating device requires | ||
| 1807 | inverse clock polarity (CPOL) mode | ||
| 1808 | - spi-cpha - (optional) Empty property indicating device requires | ||
| 1809 | shifted clock phase (CPHA) mode | ||
| 1810 | - spi-cs-high - (optional) Empty property indicating device requires | ||
| 1811 | chip select active high | ||
| 1812 | |||
| 1813 | SPI example for an MPC5200 SPI bus: | ||
| 1814 | spi@f00 { | ||
| 1815 | #address-cells = <1>; | ||
| 1816 | #size-cells = <0>; | ||
| 1817 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; | ||
| 1818 | reg = <0xf00 0x20>; | ||
| 1819 | interrupts = <2 13 0 2 14 0>; | ||
| 1820 | interrupt-parent = <&mpc5200_pic>; | ||
| 1821 | |||
| 1822 | ethernet-switch@0 { | ||
| 1823 | compatible = "micrel,ks8995m"; | ||
| 1824 | spi-max-frequency = <1000000>; | ||
| 1825 | reg = <0>; | ||
| 1826 | }; | ||
| 1827 | |||
| 1828 | codec@1 { | ||
| 1829 | compatible = "ti,tlv320aic26"; | ||
| 1830 | spi-max-frequency = <100000>; | ||
| 1831 | reg = <1>; | ||
| 1832 | }; | ||
| 1833 | }; | ||
| 1834 | |||
| 1835 | VII - Marvell Discovery mv64[345]6x System Controller chips | ||
| 1836 | =========================================================== | ||
| 1837 | |||
| 1838 | The Marvell mv64[345]60 series of system controller chips contain | ||
| 1839 | many of the peripherals needed to implement a complete computer | ||
| 1840 | system. In this section, we define device tree nodes to describe | ||
| 1841 | the system controller chip itself and each of the peripherals | ||
| 1842 | which it contains. Compatible string values for each node are | ||
| 1843 | prefixed with the string "marvell,", for Marvell Technology Group Ltd. | ||
| 1844 | |||
| 1845 | 1) The /system-controller node | ||
| 1846 | |||
| 1847 | This node is used to represent the system-controller and must be | ||
| 1848 | present when the system uses a system controller chip. The top-level | ||
| 1849 | system-controller node contains information that is global to all | ||
| 1850 | devices within the system controller chip. The node name begins | ||
| 1851 | with "system-controller" followed by the unit address, which is | ||
| 1852 | the base address of the memory-mapped register set for the system | ||
| 1853 | controller chip. | ||
| 1854 | |||
| 1855 | Required properties: | ||
| 1856 | |||
| 1857 | - ranges : Describes the translation of system controller addresses | ||
| 1858 | for memory mapped registers. | ||
| 1859 | - clock-frequency: Contains the main clock frequency for the system | ||
| 1860 | controller chip. | ||
| 1861 | - reg : This property defines the address and size of the | ||
| 1862 | memory-mapped registers contained within the system controller | ||
| 1863 | chip. The address specified in the "reg" property should match | ||
| 1864 | the unit address of the system-controller node. | ||
| 1865 | - #address-cells : Address representation for system controller | ||
| 1866 | devices. This field represents the number of cells needed to | ||
| 1867 | represent the address of the memory-mapped registers of devices | ||
| 1868 | within the system controller chip. | ||
| 1869 | - #size-cells : Size representation for for the memory-mapped | ||
| 1870 | registers within the system controller chip. | ||
| 1871 | - #interrupt-cells : Defines the width of cells used to represent | ||
| 1872 | interrupts. | ||
| 1873 | |||
| 1874 | Optional properties: | ||
| 1875 | |||
| 1876 | - model : The specific model of the system controller chip. Such | ||
| 1877 | as, "mv64360", "mv64460", or "mv64560". | ||
| 1878 | - compatible : A string identifying the compatibility identifiers | ||
| 1879 | of the system controller chip. | ||
| 1880 | |||
| 1881 | The system-controller node contains child nodes for each system | ||
| 1882 | controller device that the platform uses. Nodes should not be created | ||
| 1883 | for devices which exist on the system controller chip but are not used | ||
| 1884 | |||
| 1885 | Example Marvell Discovery mv64360 system-controller node: | ||
| 1886 | |||
| 1887 | system-controller@f1000000 { /* Marvell Discovery mv64360 */ | ||
| 1888 | #address-cells = <1>; | ||
| 1889 | #size-cells = <1>; | ||
| 1890 | model = "mv64360"; /* Default */ | ||
| 1891 | compatible = "marvell,mv64360"; | ||
| 1892 | clock-frequency = <133333333>; | ||
| 1893 | reg = <0xf1000000 0x10000>; | ||
| 1894 | virtual-reg = <0xf1000000>; | ||
| 1895 | ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */ | ||
| 1896 | 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */ | ||
| 1897 | 0xa0000000 0xa0000000 0x4000000 /* User FLASH */ | ||
| 1898 | 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */ | ||
| 1899 | 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */ | ||
| 1900 | |||
| 1901 | [ child node definitions... ] | ||
| 1902 | } | ||
| 1903 | |||
| 1904 | 2) Child nodes of /system-controller | ||
| 1905 | |||
| 1906 | a) Marvell Discovery MDIO bus | ||
| 1907 | |||
| 1908 | The MDIO is a bus to which the PHY devices are connected. For each | ||
| 1909 | device that exists on this bus, a child node should be created. See | ||
| 1910 | the definition of the PHY node below for an example of how to define | ||
| 1911 | a PHY. | ||
| 1912 | |||
| 1913 | Required properties: | ||
| 1914 | - #address-cells : Should be <1> | ||
| 1915 | - #size-cells : Should be <0> | ||
| 1916 | - device_type : Should be "mdio" | ||
| 1917 | - compatible : Should be "marvell,mv64360-mdio" | ||
| 1918 | |||
| 1919 | Example: | ||
| 1920 | |||
| 1921 | mdio { | ||
| 1922 | #address-cells = <1>; | ||
| 1923 | #size-cells = <0>; | ||
| 1924 | device_type = "mdio"; | ||
| 1925 | compatible = "marvell,mv64360-mdio"; | ||
| 1926 | |||
| 1927 | ethernet-phy@0 { | ||
| 1928 | ...... | ||
| 1929 | }; | ||
| 1930 | }; | ||
| 1931 | |||
| 1932 | |||
| 1933 | b) Marvell Discovery ethernet controller | ||
| 1934 | |||
| 1935 | The Discover ethernet controller is described with two levels | ||
| 1936 | of nodes. The first level describes an ethernet silicon block | ||
| 1937 | and the second level describes up to 3 ethernet nodes within | ||
| 1938 | that block. The reason for the multiple levels is that the | ||
| 1939 | registers for the node are interleaved within a single set | ||
| 1940 | of registers. The "ethernet-block" level describes the | ||
| 1941 | shared register set, and the "ethernet" nodes describe ethernet | ||
| 1942 | port-specific properties. | ||
| 1943 | |||
| 1944 | Ethernet block node | ||
| 1945 | |||
| 1946 | Required properties: | ||
| 1947 | - #address-cells : <1> | ||
| 1948 | - #size-cells : <0> | ||
| 1949 | - compatible : "marvell,mv64360-eth-block" | ||
| 1950 | - reg : Offset and length of the register set for this block | ||
| 1951 | |||
| 1952 | Example Discovery Ethernet block node: | ||
| 1953 | ethernet-block@2000 { | ||
| 1954 | #address-cells = <1>; | ||
| 1955 | #size-cells = <0>; | ||
| 1956 | compatible = "marvell,mv64360-eth-block"; | ||
| 1957 | reg = <0x2000 0x2000>; | ||
| 1958 | ethernet@0 { | ||
| 1959 | ....... | ||
| 1960 | }; | ||
| 1961 | }; | ||
| 1962 | |||
| 1963 | Ethernet port node | ||
| 1964 | |||
| 1965 | Required properties: | ||
| 1966 | - device_type : Should be "network". | ||
| 1967 | - compatible : Should be "marvell,mv64360-eth". | ||
| 1968 | - reg : Should be <0>, <1>, or <2>, according to which registers | ||
| 1969 | within the silicon block the device uses. | ||
| 1970 | - interrupts : <a> where a is the interrupt number for the port. | ||
| 1971 | - interrupt-parent : the phandle for the interrupt controller | ||
| 1972 | that services interrupts for this device. | ||
| 1973 | - phy : the phandle for the PHY connected to this ethernet | ||
| 1974 | controller. | ||
| 1975 | - local-mac-address : 6 bytes, MAC address | ||
| 1976 | |||
| 1977 | Example Discovery Ethernet port node: | ||
| 1978 | ethernet@0 { | ||
| 1979 | device_type = "network"; | ||
| 1980 | compatible = "marvell,mv64360-eth"; | ||
| 1981 | reg = <0>; | ||
| 1982 | interrupts = <32>; | ||
| 1983 | interrupt-parent = <&PIC>; | ||
| 1984 | phy = <&PHY0>; | ||
| 1985 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 1986 | }; | ||
| 1987 | |||
| 1988 | |||
| 1989 | |||
| 1990 | c) Marvell Discovery PHY nodes | ||
| 1991 | |||
| 1992 | Required properties: | ||
| 1993 | - device_type : Should be "ethernet-phy" | ||
| 1994 | - interrupts : <a> where a is the interrupt number for this phy. | ||
| 1995 | - interrupt-parent : the phandle for the interrupt controller that | ||
| 1996 | services interrupts for this device. | ||
| 1997 | - reg : The ID number for the phy, usually a small integer | ||
| 1998 | |||
| 1999 | Example Discovery PHY node: | ||
| 2000 | ethernet-phy@1 { | ||
| 2001 | device_type = "ethernet-phy"; | ||
| 2002 | compatible = "broadcom,bcm5421"; | ||
| 2003 | interrupts = <76>; /* GPP 12 */ | ||
| 2004 | interrupt-parent = <&PIC>; | ||
| 2005 | reg = <1>; | ||
| 2006 | }; | ||
| 2007 | |||
| 2008 | |||
| 2009 | d) Marvell Discovery SDMA nodes | ||
| 2010 | |||
| 2011 | Represent DMA hardware associated with the MPSC (multiprotocol | ||
| 2012 | serial controllers). | ||
| 2013 | |||
| 2014 | Required properties: | ||
| 2015 | - compatible : "marvell,mv64360-sdma" | ||
| 2016 | - reg : Offset and length of the register set for this device | ||
| 2017 | - interrupts : <a> where a is the interrupt number for the DMA | ||
| 2018 | device. | ||
| 2019 | - interrupt-parent : the phandle for the interrupt controller | ||
| 2020 | that services interrupts for this device. | ||
| 2021 | |||
| 2022 | Example Discovery SDMA node: | ||
| 2023 | sdma@4000 { | ||
| 2024 | compatible = "marvell,mv64360-sdma"; | ||
| 2025 | reg = <0x4000 0xc18>; | ||
| 2026 | virtual-reg = <0xf1004000>; | ||
| 2027 | interrupts = <36>; | ||
| 2028 | interrupt-parent = <&PIC>; | ||
| 2029 | }; | ||
| 2030 | |||
| 2031 | |||
| 2032 | e) Marvell Discovery BRG nodes | ||
| 2033 | |||
| 2034 | Represent baud rate generator hardware associated with the MPSC | ||
| 2035 | (multiprotocol serial controllers). | ||
| 2036 | |||
| 2037 | Required properties: | ||
| 2038 | - compatible : "marvell,mv64360-brg" | ||
| 2039 | - reg : Offset and length of the register set for this device | ||
| 2040 | - clock-src : A value from 0 to 15 which selects the clock | ||
| 2041 | source for the baud rate generator. This value corresponds | ||
| 2042 | to the CLKS value in the BRGx configuration register. See | ||
| 2043 | the mv64x60 User's Manual. | ||
| 2044 | - clock-frequence : The frequency (in Hz) of the baud rate | ||
| 2045 | generator's input clock. | ||
| 2046 | - current-speed : The current speed setting (presumably by | ||
| 2047 | firmware) of the baud rate generator. | ||
| 2048 | |||
| 2049 | Example Discovery BRG node: | ||
| 2050 | brg@b200 { | ||
| 2051 | compatible = "marvell,mv64360-brg"; | ||
| 2052 | reg = <0xb200 0x8>; | ||
| 2053 | clock-src = <8>; | ||
| 2054 | clock-frequency = <133333333>; | ||
| 2055 | current-speed = <9600>; | ||
| 2056 | }; | ||
| 2057 | |||
| 2058 | |||
| 2059 | f) Marvell Discovery CUNIT nodes | ||
| 2060 | |||
| 2061 | Represent the Serial Communications Unit device hardware. | ||
| 2062 | |||
| 2063 | Required properties: | ||
| 2064 | - reg : Offset and length of the register set for this device | ||
| 2065 | |||
| 2066 | Example Discovery CUNIT node: | ||
| 2067 | cunit@f200 { | ||
| 2068 | reg = <0xf200 0x200>; | ||
| 2069 | }; | ||
| 2070 | |||
| 2071 | |||
| 2072 | g) Marvell Discovery MPSCROUTING nodes | ||
| 2073 | |||
| 2074 | Represent the Discovery's MPSC routing hardware | ||
| 2075 | |||
| 2076 | Required properties: | ||
| 2077 | - reg : Offset and length of the register set for this device | ||
| 2078 | |||
| 2079 | Example Discovery CUNIT node: | ||
| 2080 | mpscrouting@b500 { | ||
| 2081 | reg = <0xb400 0xc>; | ||
| 2082 | }; | ||
| 2083 | |||
| 2084 | |||
| 2085 | h) Marvell Discovery MPSCINTR nodes | ||
| 2086 | |||
| 2087 | Represent the Discovery's MPSC DMA interrupt hardware registers | ||
| 2088 | (SDMA cause and mask registers). | ||
| 2089 | |||
| 2090 | Required properties: | ||
| 2091 | - reg : Offset and length of the register set for this device | ||
| 2092 | |||
| 2093 | Example Discovery MPSCINTR node: | ||
| 2094 | mpsintr@b800 { | ||
| 2095 | reg = <0xb800 0x100>; | ||
| 2096 | }; | ||
| 2097 | |||
| 2098 | |||
| 2099 | i) Marvell Discovery MPSC nodes | ||
| 2100 | |||
| 2101 | Represent the Discovery's MPSC (Multiprotocol Serial Controller) | ||
| 2102 | serial port. | ||
| 2103 | |||
| 2104 | Required properties: | ||
| 2105 | - device_type : "serial" | ||
| 2106 | - compatible : "marvell,mv64360-mpsc" | ||
| 2107 | - reg : Offset and length of the register set for this device | ||
| 2108 | - sdma : the phandle for the SDMA node used by this port | ||
| 2109 | - brg : the phandle for the BRG node used by this port | ||
| 2110 | - cunit : the phandle for the CUNIT node used by this port | ||
| 2111 | - mpscrouting : the phandle for the MPSCROUTING node used by this port | ||
| 2112 | - mpscintr : the phandle for the MPSCINTR node used by this port | ||
| 2113 | - cell-index : the hardware index of this cell in the MPSC core | ||
| 2114 | - max_idle : value needed for MPSC CHR3 (Maximum Frame Length) | ||
| 2115 | register | ||
| 2116 | - interrupts : <a> where a is the interrupt number for the MPSC. | ||
| 2117 | - interrupt-parent : the phandle for the interrupt controller | ||
| 2118 | that services interrupts for this device. | ||
| 2119 | |||
| 2120 | Example Discovery MPSCINTR node: | ||
| 2121 | mpsc@8000 { | ||
| 2122 | device_type = "serial"; | ||
| 2123 | compatible = "marvell,mv64360-mpsc"; | ||
| 2124 | reg = <0x8000 0x38>; | ||
| 2125 | virtual-reg = <0xf1008000>; | ||
| 2126 | sdma = <&SDMA0>; | ||
| 2127 | brg = <&BRG0>; | ||
| 2128 | cunit = <&CUNIT>; | ||
| 2129 | mpscrouting = <&MPSCROUTING>; | ||
| 2130 | mpscintr = <&MPSCINTR>; | ||
| 2131 | cell-index = <0>; | ||
| 2132 | max_idle = <40>; | ||
| 2133 | interrupts = <40>; | ||
| 2134 | interrupt-parent = <&PIC>; | ||
| 2135 | }; | ||
| 2136 | |||
| 2137 | |||
| 2138 | j) Marvell Discovery Watch Dog Timer nodes | ||
| 2139 | |||
| 2140 | Represent the Discovery's watchdog timer hardware | ||
| 2141 | |||
| 2142 | Required properties: | ||
| 2143 | - compatible : "marvell,mv64360-wdt" | ||
| 2144 | - reg : Offset and length of the register set for this device | ||
| 2145 | |||
| 2146 | Example Discovery Watch Dog Timer node: | ||
| 2147 | wdt@b410 { | ||
| 2148 | compatible = "marvell,mv64360-wdt"; | ||
| 2149 | reg = <0xb410 0x8>; | ||
| 2150 | }; | ||
| 2151 | |||
| 2152 | |||
| 2153 | k) Marvell Discovery I2C nodes | ||
| 2154 | |||
| 2155 | Represent the Discovery's I2C hardware | ||
| 2156 | |||
| 2157 | Required properties: | ||
| 2158 | - device_type : "i2c" | ||
| 2159 | - compatible : "marvell,mv64360-i2c" | ||
| 2160 | - reg : Offset and length of the register set for this device | ||
| 2161 | - interrupts : <a> where a is the interrupt number for the I2C. | ||
| 2162 | - interrupt-parent : the phandle for the interrupt controller | ||
| 2163 | that services interrupts for this device. | ||
| 2164 | |||
| 2165 | Example Discovery I2C node: | ||
| 2166 | compatible = "marvell,mv64360-i2c"; | ||
| 2167 | reg = <0xc000 0x20>; | ||
| 2168 | virtual-reg = <0xf100c000>; | ||
| 2169 | interrupts = <37>; | ||
| 2170 | interrupt-parent = <&PIC>; | ||
| 2171 | }; | ||
| 2172 | |||
| 2173 | |||
| 2174 | l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes | ||
| 2175 | |||
| 2176 | Represent the Discovery's PIC hardware | ||
| 2177 | |||
| 2178 | Required properties: | ||
| 2179 | - #interrupt-cells : <1> | ||
| 2180 | - #address-cells : <0> | ||
| 2181 | - compatible : "marvell,mv64360-pic" | ||
| 2182 | - reg : Offset and length of the register set for this device | ||
| 2183 | - interrupt-controller | ||
| 2184 | |||
| 2185 | Example Discovery PIC node: | ||
| 2186 | pic { | ||
| 2187 | #interrupt-cells = <1>; | ||
| 2188 | #address-cells = <0>; | ||
| 2189 | compatible = "marvell,mv64360-pic"; | ||
| 2190 | reg = <0x0 0x88>; | ||
| 2191 | interrupt-controller; | ||
| 2192 | }; | ||
| 2193 | |||
| 2194 | |||
| 2195 | m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes | ||
| 2196 | |||
| 2197 | Represent the Discovery's MPP hardware | ||
| 2198 | |||
| 2199 | Required properties: | ||
| 2200 | - compatible : "marvell,mv64360-mpp" | ||
| 2201 | - reg : Offset and length of the register set for this device | ||
| 2202 | |||
| 2203 | Example Discovery MPP node: | ||
| 2204 | mpp@f000 { | ||
| 2205 | compatible = "marvell,mv64360-mpp"; | ||
| 2206 | reg = <0xf000 0x10>; | ||
| 2207 | }; | ||
| 2208 | |||
| 2209 | |||
| 2210 | n) Marvell Discovery GPP (General Purpose Pins) nodes | ||
| 2211 | |||
| 2212 | Represent the Discovery's GPP hardware | ||
| 2213 | |||
| 2214 | Required properties: | ||
| 2215 | - compatible : "marvell,mv64360-gpp" | ||
| 2216 | - reg : Offset and length of the register set for this device | ||
| 2217 | |||
| 2218 | Example Discovery GPP node: | ||
| 2219 | gpp@f000 { | ||
| 2220 | compatible = "marvell,mv64360-gpp"; | ||
| 2221 | reg = <0xf100 0x20>; | ||
| 2222 | }; | ||
| 2223 | |||
| 2224 | |||
| 2225 | o) Marvell Discovery PCI host bridge node | ||
| 2226 | |||
| 2227 | Represents the Discovery's PCI host bridge device. The properties | ||
| 2228 | for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE | ||
| 2229 | 1275-1994. A typical value for the compatible property is | ||
| 2230 | "marvell,mv64360-pci". | ||
| 2231 | |||
| 2232 | Example Discovery PCI host bridge node | ||
| 2233 | pci@80000000 { | ||
| 2234 | #address-cells = <3>; | ||
| 2235 | #size-cells = <2>; | ||
| 2236 | #interrupt-cells = <1>; | ||
| 2237 | device_type = "pci"; | ||
| 2238 | compatible = "marvell,mv64360-pci"; | ||
| 2239 | reg = <0xcf8 0x8>; | ||
| 2240 | ranges = <0x01000000 0x0 0x0 | ||
| 2241 | 0x88000000 0x0 0x01000000 | ||
| 2242 | 0x02000000 0x0 0x80000000 | ||
| 2243 | 0x80000000 0x0 0x08000000>; | ||
| 2244 | bus-range = <0 255>; | ||
| 2245 | clock-frequency = <66000000>; | ||
| 2246 | interrupt-parent = <&PIC>; | ||
| 2247 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 2248 | interrupt-map = < | ||
| 2249 | /* IDSEL 0x0a */ | ||
| 2250 | 0x5000 0 0 1 &PIC 80 | ||
| 2251 | 0x5000 0 0 2 &PIC 81 | ||
| 2252 | 0x5000 0 0 3 &PIC 91 | ||
| 2253 | 0x5000 0 0 4 &PIC 93 | ||
| 2254 | |||
| 2255 | /* IDSEL 0x0b */ | ||
| 2256 | 0x5800 0 0 1 &PIC 91 | ||
| 2257 | 0x5800 0 0 2 &PIC 93 | ||
| 2258 | 0x5800 0 0 3 &PIC 80 | ||
| 2259 | 0x5800 0 0 4 &PIC 81 | ||
| 2260 | |||
| 2261 | /* IDSEL 0x0c */ | ||
| 2262 | 0x6000 0 0 1 &PIC 91 | ||
| 2263 | 0x6000 0 0 2 &PIC 93 | ||
| 2264 | 0x6000 0 0 3 &PIC 80 | ||
| 2265 | 0x6000 0 0 4 &PIC 81 | ||
| 2266 | |||
| 2267 | /* IDSEL 0x0d */ | ||
| 2268 | 0x6800 0 0 1 &PIC 93 | ||
| 2269 | 0x6800 0 0 2 &PIC 80 | ||
| 2270 | 0x6800 0 0 3 &PIC 81 | ||
| 2271 | 0x6800 0 0 4 &PIC 91 | ||
| 2272 | >; | ||
| 2273 | }; | ||
| 2274 | |||
| 2275 | |||
| 2276 | p) Marvell Discovery CPU Error nodes | ||
| 2277 | |||
| 2278 | Represent the Discovery's CPU error handler device. | ||
| 2279 | |||
| 2280 | Required properties: | ||
| 2281 | - compatible : "marvell,mv64360-cpu-error" | ||
| 2282 | - reg : Offset and length of the register set for this device | ||
| 2283 | - interrupts : the interrupt number for this device | ||
| 2284 | - interrupt-parent : the phandle for the interrupt controller | ||
| 2285 | that services interrupts for this device. | ||
| 2286 | |||
| 2287 | Example Discovery CPU Error node: | ||
| 2288 | cpu-error@0070 { | ||
| 2289 | compatible = "marvell,mv64360-cpu-error"; | ||
| 2290 | reg = <0x70 0x10 0x128 0x28>; | ||
| 2291 | interrupts = <3>; | ||
| 2292 | interrupt-parent = <&PIC>; | ||
| 2293 | }; | ||
| 2294 | |||
| 2295 | |||
| 2296 | q) Marvell Discovery SRAM Controller nodes | ||
| 2297 | |||
| 2298 | Represent the Discovery's SRAM controller device. | ||
| 2299 | |||
| 2300 | Required properties: | ||
| 2301 | - compatible : "marvell,mv64360-sram-ctrl" | ||
| 2302 | - reg : Offset and length of the register set for this device | ||
| 2303 | - interrupts : the interrupt number for this device | ||
| 2304 | - interrupt-parent : the phandle for the interrupt controller | ||
| 2305 | that services interrupts for this device. | ||
| 2306 | |||
| 2307 | Example Discovery SRAM Controller node: | ||
| 2308 | sram-ctrl@0380 { | ||
| 2309 | compatible = "marvell,mv64360-sram-ctrl"; | ||
| 2310 | reg = <0x380 0x80>; | ||
| 2311 | interrupts = <13>; | ||
| 2312 | interrupt-parent = <&PIC>; | ||
| 2313 | }; | ||
| 2314 | |||
| 2315 | |||
| 2316 | r) Marvell Discovery PCI Error Handler nodes | ||
| 2317 | |||
| 2318 | Represent the Discovery's PCI error handler device. | ||
| 2319 | |||
| 2320 | Required properties: | ||
| 2321 | - compatible : "marvell,mv64360-pci-error" | ||
| 2322 | - reg : Offset and length of the register set for this device | ||
| 2323 | - interrupts : the interrupt number for this device | ||
| 2324 | - interrupt-parent : the phandle for the interrupt controller | ||
| 2325 | that services interrupts for this device. | ||
| 2326 | |||
| 2327 | Example Discovery PCI Error Handler node: | ||
| 2328 | pci-error@1d40 { | ||
| 2329 | compatible = "marvell,mv64360-pci-error"; | ||
| 2330 | reg = <0x1d40 0x40 0xc28 0x4>; | ||
| 2331 | interrupts = <12>; | ||
| 2332 | interrupt-parent = <&PIC>; | ||
| 2333 | }; | ||
| 2334 | |||
| 2335 | |||
| 2336 | s) Marvell Discovery Memory Controller nodes | ||
| 2337 | |||
| 2338 | Represent the Discovery's memory controller device. | ||
| 2339 | |||
| 2340 | Required properties: | ||
| 2341 | - compatible : "marvell,mv64360-mem-ctrl" | ||
| 2342 | - reg : Offset and length of the register set for this device | ||
| 2343 | - interrupts : the interrupt number for this device | ||
| 2344 | - interrupt-parent : the phandle for the interrupt controller | ||
| 2345 | that services interrupts for this device. | ||
| 2346 | |||
| 2347 | Example Discovery Memory Controller node: | ||
| 2348 | mem-ctrl@1400 { | ||
| 2349 | compatible = "marvell,mv64360-mem-ctrl"; | ||
| 2350 | reg = <0x1400 0x60>; | ||
| 2351 | interrupts = <17>; | ||
| 2352 | interrupt-parent = <&PIC>; | ||
| 2353 | }; | ||
| 2354 | |||
| 2355 | |||
| 2356 | VIII - Specifying interrupt information for devices | ||
| 2357 | =================================================== | 1242 | =================================================== |
| 2358 | 1243 | ||
| 2359 | The device tree represents the busses and devices of a hardware | 1244 | The device tree represents the busses and devices of a hardware |
| @@ -2439,56 +1324,7 @@ encodings listed below: · 79 unmodified lines | |||
| 2439 | 2 = high to low edge sensitive type enabled | 1324 | 2 = high to low edge sensitive type enabled |
| 2440 | 3 = low to high edge sensitive type enabled | 1325 | 3 = low to high edge sensitive type enabled |
| 2441 | 1326 | ||
| 2442 | IX - Specifying GPIO information for devices | 1327 | VIII - Specifying Device Power Management Information (sleep property) |
| 2443 | ============================================ | ||
| 2444 | |||
| 2445 | 1) gpios property | ||
| 2446 | ----------------- | ||
| 2447 | |||
| 2448 | Nodes that makes use of GPIOs should define them using `gpios' property, | ||
| 2449 | format of which is: <&gpio-controller1-phandle gpio1-specifier | ||
| 2450 | &gpio-controller2-phandle gpio2-specifier | ||
| 2451 | 0 /* holes are permitted, means no GPIO 3 */ | ||
| 2452 | &gpio-controller4-phandle gpio4-specifier | ||
| 2453 | ...>; | ||
| 2454 | |||
| 2455 | Note that gpio-specifier length is controller dependent. | ||
| 2456 | |||
| 2457 | gpio-specifier may encode: bank, pin position inside the bank, | ||
| 2458 | whether pin is open-drain and whether pin is logically inverted. | ||
| 2459 | |||
| 2460 | Example of the node using GPIOs: | ||
| 2461 | |||
| 2462 | node { | ||
| 2463 | gpios = <&qe_pio_e 18 0>; | ||
| 2464 | }; | ||
| 2465 | |||
| 2466 | In this example gpio-specifier is "18 0" and encodes GPIO pin number, | ||
| 2467 | and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller. | ||
| 2468 | |||
| 2469 | 2) gpio-controller nodes | ||
| 2470 | ------------------------ | ||
| 2471 | |||
| 2472 | Every GPIO controller node must have #gpio-cells property defined, | ||
| 2473 | this information will be used to translate gpio-specifiers. | ||
| 2474 | |||
| 2475 | Example of two SOC GPIO banks defined as gpio-controller nodes: | ||
| 2476 | |||
| 2477 | qe_pio_a: gpio-controller@1400 { | ||
| 2478 | #gpio-cells = <2>; | ||
| 2479 | compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; | ||
| 2480 | reg = <0x1400 0x18>; | ||
| 2481 | gpio-controller; | ||
| 2482 | }; | ||
| 2483 | |||
| 2484 | qe_pio_e: gpio-controller@1460 { | ||
| 2485 | #gpio-cells = <2>; | ||
| 2486 | compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; | ||
| 2487 | reg = <0x1460 0x18>; | ||
| 2488 | gpio-controller; | ||
| 2489 | }; | ||
| 2490 | |||
| 2491 | X - Specifying Device Power Management Information (sleep property) | ||
| 2492 | =================================================================== | 1328 | =================================================================== |
| 2493 | 1329 | ||
| 2494 | Devices on SOCs often have mechanisms for placing devices into low-power | 1330 | Devices on SOCs often have mechanisms for placing devices into low-power |
| @@ -0,0 +1,148 @@ | |||
| 1 | 4xx/Axon EMAC ethernet nodes | ||
| 2 | |||
| 3 | The EMAC ethernet controller in IBM and AMCC 4xx chips, and also | ||
| 4 | the Axon bridge. To operate this needs to interact with a ths | ||
| 5 | special McMAL DMA controller, and sometimes an RGMII or ZMII | ||
| 6 | interface. In addition to the nodes and properties described | ||
| 7 | below, the node for the OPB bus on which the EMAC sits must have a | ||
| 8 | correct clock-frequency property. | ||
| 9 | |||
| 10 | i) The EMAC node itself | ||
| 11 | |||
| 12 | Required properties: | ||
| 13 | - device_type : "network" | ||
| 14 | |||
| 15 | - compatible : compatible list, contains 2 entries, first is | ||
| 16 | "ibm,emac-CHIP" where CHIP is the host ASIC (440gx, | ||
| 17 | 405gp, Axon) and second is either "ibm,emac" or | ||
| 18 | "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", | ||
| 19 | "ibm,emac4" | ||
| 20 | - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ> | ||
| 21 | - interrupt-parent : optional, if needed for interrupt mapping | ||
| 22 | - reg : <registers mapping> | ||
| 23 | - local-mac-address : 6 bytes, MAC address | ||
| 24 | - mal-device : phandle of the associated McMAL node | ||
| 25 | - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated | ||
| 26 | with this EMAC | ||
| 27 | - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated | ||
| 28 | with this EMAC | ||
| 29 | - cell-index : 1 cell, hardware index of the EMAC cell on a given | ||
| 30 | ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on | ||
| 31 | each Axon chip) | ||
| 32 | - max-frame-size : 1 cell, maximum frame size supported in bytes | ||
| 33 | - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec | ||
| 34 | operations. | ||
| 35 | For Axon, 2048 | ||
| 36 | - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec | ||
| 37 | operations. | ||
| 38 | For Axon, 2048. | ||
| 39 | - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate | ||
| 40 | thresholds). | ||
| 41 | For Axon, 0x00000010 | ||
| 42 | - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds) | ||
| 43 | in bytes. | ||
| 44 | For Axon, 0x00000100 (I think ...) | ||
| 45 | - phy-mode : string, mode of operations of the PHY interface. | ||
| 46 | Supported values are: "mii", "rmii", "smii", "rgmii", | ||
| 47 | "tbi", "gmii", rtbi", "sgmii". | ||
| 48 | For Axon on CAB, it is "rgmii" | ||
| 49 | - mdio-device : 1 cell, required iff using shared MDIO registers | ||
| 50 | (440EP). phandle of the EMAC to use to drive the | ||
| 51 | MDIO lines for the PHY used by this EMAC. | ||
| 52 | - zmii-device : 1 cell, required iff connected to a ZMII. phandle of | ||
| 53 | the ZMII device node | ||
| 54 | - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII | ||
| 55 | channel or 0xffffffff if ZMII is only used for MDIO. | ||
| 56 | - rgmii-device : 1 cell, required iff connected to an RGMII. phandle | ||
| 57 | of the RGMII device node. | ||
| 58 | For Axon: phandle of plb5/plb4/opb/rgmii | ||
| 59 | - rgmii-channel : 1 cell, required iff connected to an RGMII. Which | ||
| 60 | RGMII channel is used by this EMAC. | ||
| 61 | Fox Axon: present, whatever value is appropriate for each | ||
| 62 | EMAC, that is the content of the current (bogus) "phy-port" | ||
| 63 | property. | ||
| 64 | |||
| 65 | Optional properties: | ||
| 66 | - phy-address : 1 cell, optional, MDIO address of the PHY. If absent, | ||
| 67 | a search is performed. | ||
| 68 | - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY | ||
| 69 | for, used if phy-address is absent. bit 0x00000001 is | ||
| 70 | MDIO address 0. | ||
| 71 | For Axon it can be absent, though my current driver | ||
| 72 | doesn't handle phy-address yet so for now, keep | ||
| 73 | 0x00ffffff in it. | ||
| 74 | - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec | ||
| 75 | operations (if absent the value is the same as | ||
| 76 | rx-fifo-size). For Axon, either absent or 2048. | ||
| 77 | - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec | ||
| 78 | operations (if absent the value is the same as | ||
| 79 | tx-fifo-size). For Axon, either absent or 2048. | ||
| 80 | - tah-device : 1 cell, optional. If connected to a TAH engine for | ||
| 81 | offload, phandle of the TAH device node. | ||
| 82 | - tah-channel : 1 cell, optional. If appropriate, channel used on the | ||
| 83 | TAH engine. | ||
| 84 | |||
| 85 | Example: | ||
| 86 | |||
| 87 | EMAC0: ethernet@40000800 { | ||
| 88 | device_type = "network"; | ||
| 89 | compatible = "ibm,emac-440gp", "ibm,emac"; | ||
| 90 | interrupt-parent = <&UIC1>; | ||
| 91 | interrupts = <1c 4 1d 4>; | ||
| 92 | reg = <40000800 70>; | ||
| 93 | local-mac-address = [00 04 AC E3 1B 1E]; | ||
| 94 | mal-device = <&MAL0>; | ||
| 95 | mal-tx-channel = <0 1>; | ||
| 96 | mal-rx-channel = <0>; | ||
| 97 | cell-index = <0>; | ||
| 98 | max-frame-size = <5dc>; | ||
| 99 | rx-fifo-size = <1000>; | ||
| 100 | tx-fifo-size = <800>; | ||
| 101 | phy-mode = "rmii"; | ||
| 102 | phy-map = <00000001>; | ||
| 103 | zmii-device = <&ZMII0>; | ||
| 104 | zmii-channel = <0>; | ||
| 105 | }; | ||
| 106 | |||
| 107 | ii) McMAL node | ||
| 108 | |||
| 109 | Required properties: | ||
| 110 | - device_type : "dma-controller" | ||
| 111 | - compatible : compatible list, containing 2 entries, first is | ||
| 112 | "ibm,mcmal-CHIP" where CHIP is the host ASIC (like | ||
| 113 | emac) and the second is either "ibm,mcmal" or | ||
| 114 | "ibm,mcmal2". | ||
| 115 | For Axon, "ibm,mcmal-axon","ibm,mcmal2" | ||
| 116 | - interrupts : <interrupt mapping for the MAL interrupts sources: | ||
| 117 | 5 sources: tx_eob, rx_eob, serr, txde, rxde>. | ||
| 118 | For Axon: This is _different_ from the current | ||
| 119 | firmware. We use the "delayed" interrupts for txeob | ||
| 120 | and rxeob. Thus we end up with mapping those 5 MPIC | ||
| 121 | interrupts, all level positive sensitive: 10, 11, 32, | ||
| 122 | 33, 34 (in decimal) | ||
| 123 | - dcr-reg : < DCR registers range > | ||
| 124 | - dcr-parent : if needed for dcr-reg | ||
| 125 | - num-tx-chans : 1 cell, number of Tx channels | ||
| 126 | - num-rx-chans : 1 cell, number of Rx channels | ||
| 127 | |||
| 128 | iii) ZMII node | ||
| 129 | |||
| 130 | Required properties: | ||
| 131 | - compatible : compatible list, containing 2 entries, first is | ||
| 132 | "ibm,zmii-CHIP" where CHIP is the host ASIC (like | ||
| 133 | EMAC) and the second is "ibm,zmii". | ||
| 134 | For Axon, there is no ZMII node. | ||
| 135 | - reg : <registers mapping> | ||
| 136 | |||
| 137 | iv) RGMII node | ||
| 138 | |||
| 139 | Required properties: | ||
| 140 | - compatible : compatible list, containing 2 entries, first is | ||
| 141 | "ibm,rgmii-CHIP" where CHIP is the host ASIC (like | ||
| 142 | EMAC) and the second is "ibm,rgmii". | ||
| 143 | For Axon, "ibm,rgmii-axon","ibm,rgmii" | ||
| 144 | - reg : <registers mapping> | ||
| 145 | - revision : as provided by the RGMII new version register if | ||
| 146 | available. | ||
| 147 | For Axon: 0x0000012a | ||
| 148 | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | Specifying GPIO information for devices | ||
| 2 | ============================================ | ||
| 3 | |||
| 4 | 1) gpios property | ||
| 5 | ----------------- | ||
| 6 | |||
| 7 | Nodes that makes use of GPIOs should define them using `gpios' property, | ||
| 8 | format of which is: <&gpio-controller1-phandle gpio1-specifier | ||
| 9 | &gpio-controller2-phandle gpio2-specifier | ||
| 10 | 0 /* holes are permitted, means no GPIO 3 */ | ||
| 11 | &gpio-controller4-phandle gpio4-specifier | ||
| 12 | ...>; | ||
| 13 | |||
| 14 | Note that gpio-specifier length is controller dependent. | ||
| 15 | |||
| 16 | gpio-specifier may encode: bank, pin position inside the bank, | ||
| 17 | whether pin is open-drain and whether pin is logically inverted. | ||
| 18 | |||
| 19 | Example of the node using GPIOs: | ||
| 20 | |||
| 21 | node { | ||
| 22 | gpios = <&qe_pio_e 18 0>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | In this example gpio-specifier is "18 0" and encodes GPIO pin number, | ||
| 26 | and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller. | ||
| 27 | |||
| 28 | 2) gpio-controller nodes | ||
| 29 | ------------------------ | ||
| 30 | |||
| 31 | Every GPIO controller node must have #gpio-cells property defined, | ||
| 32 | this information will be used to translate gpio-specifiers. | ||
| 33 | |||
| 34 | Example of two SOC GPIO banks defined as gpio-controller nodes: | ||
| 35 | |||
| 36 | qe_pio_a: gpio-controller@1400 { | ||
| 37 | #gpio-cells = <2>; | ||
| 38 | compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; | ||
| 39 | reg = <0x1400 0x18>; | ||
| 40 | gpio-controller; | ||
| 41 | }; | ||
| 42 | |||
| 43 | qe_pio_e: gpio-controller@1460 { | ||
| 44 | #gpio-cells = <2>; | ||
| 45 | compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; | ||
| 46 | reg = <0x1460 0x18>; | ||
| 47 | gpio-controller; | ||
| 48 | }; | ||
| 49 | |||
| 50 | |||
| @@ -16,10 +16,17 @@ LED sub-node properties: · 15 unmodified lines | |||
| 16 | string defining the trigger assigned to the LED. Current triggers are: | 16 | string defining the trigger assigned to the LED. Current triggers are: |
| 17 | "backlight" - LED will act as a back-light, controlled by the framebuffer | 17 | "backlight" - LED will act as a back-light, controlled by the framebuffer |
| 18 | system | 18 | system |
| 19 | "default-on" - LED will turn on | 19 | "default-on" - LED will turn on, but see "default-state" below |
| 20 | "heartbeat" - LED "double" flashes at a load average based rate | 20 | "heartbeat" - LED "double" flashes at a load average based rate |
| 21 | "ide-disk" - LED indicates disk activity | 21 | "ide-disk" - LED indicates disk activity |
| 22 | "timer" - LED flashes at a fixed, configurable rate | 22 | "timer" - LED flashes at a fixed, configurable rate |
| 23 | - default-state: (optional) The initial state of the LED. Valid | ||
| 24 | values are "on", "off", and "keep". If the LED is already on or off | ||
| 25 | and the default-state property is set the to same value, then no | ||
| 26 | glitch should be produced where the LED momentarily turns off (or | ||
| 27 | on). The "keep" setting will keep the LED at whatever its current | ||
| 28 | state is, without producing a glitch. The default is off if this | ||
| 29 | property is not present. | ||
| 23 | 30 | ||
| 24 | Examples: | 31 | Examples: |
| 25 | 32 | ||
| @@ -30,14 +37,22 @@ leds { · 4 unmodified lines | |||
| 30 | gpios = <&mcu_pio 0 1>; /* Active low */ | 37 | gpios = <&mcu_pio 0 1>; /* Active low */ |
| 31 | linux,default-trigger = "ide-disk"; | 38 | linux,default-trigger = "ide-disk"; |
| 32 | }; | 39 | }; |
| 40 | |||
| 41 | fault { | ||
| 42 | gpios = <&mcu_pio 1 0>; | ||
| 43 | /* Keep LED on if BIOS detected hardware fault */ | ||
| 44 | default-state = "keep"; | ||
| 45 | }; | ||
| 33 | }; | 46 | }; |
| 34 | 47 | ||
| 35 | run-control { | 48 | run-control { |
| 36 | compatible = "gpio-leds"; | 49 | compatible = "gpio-leds"; |
| 37 | red { | 50 | red { |
| 38 | gpios = <&mpc8572 6 0>; | 51 | gpios = <&mpc8572 6 0>; |
| 52 | default-state = "off"; | ||
| 39 | }; | 53 | }; |
| 40 | green { | 54 | green { |
| 41 | gpios = <&mpc8572 7 0>; | 55 | gpios = <&mpc8572 7 0>; |
| 56 | default-state = "on"; | ||
| 42 | }; | 57 | }; |
| 43 | } | 58 | } |
| @@ -0,0 +1,19 @@ | |||
| 1 | MDIO on GPIOs | ||
| 2 | |||
| 3 | Currently defined compatibles: | ||
| 4 | - virtual,gpio-mdio | ||
| 5 | |||
| 6 | MDC and MDIO lines connected to GPIO controllers are listed in the | ||
| 7 | gpios property as described in section VIII.1 in the following order: | ||
| 8 | |||
| 9 | MDC, MDIO. | ||
| 10 | |||
| 11 | Example: | ||
| 12 | |||
| 13 | mdio { | ||
| 14 | compatible = "virtual,mdio-gpio"; | ||
| 15 | #address-cells = <1>; | ||
| 16 | #size-cells = <0>; | ||
| 17 | gpios = <&qe_pio_a 11 | ||
| 18 | &qe_pio_c 6>; | ||
| 19 | }; | ||
| @@ -0,0 +1,521 @@ | |||
| 1 | Marvell Discovery mv64[345]6x System Controller chips | ||
| 2 | =========================================================== | ||
| 3 | |||
| 4 | The Marvell mv64[345]60 series of system controller chips contain | ||
| 5 | many of the peripherals needed to implement a complete computer | ||
| 6 | system. In this section, we define device tree nodes to describe | ||
| 7 | the system controller chip itself and each of the peripherals | ||
| 8 | which it contains. Compatible string values for each node are | ||
| 9 | prefixed with the string "marvell,", for Marvell Technology Group Ltd. | ||
| 10 | |||
| 11 | 1) The /system-controller node | ||
| 12 | |||
| 13 | This node is used to represent the system-controller and must be | ||
| 14 | present when the system uses a system controller chip. The top-level | ||
| 15 | system-controller node contains information that is global to all | ||
| 16 | devices within the system controller chip. The node name begins | ||
| 17 | with "system-controller" followed by the unit address, which is | ||
| 18 | the base address of the memory-mapped register set for the system | ||
| 19 | controller chip. | ||
| 20 | |||
| 21 | Required properties: | ||
| 22 | |||
| 23 | - ranges : Describes the translation of system controller addresses | ||
| 24 | for memory mapped registers. | ||
| 25 | - clock-frequency: Contains the main clock frequency for the system | ||
| 26 | controller chip. | ||
| 27 | - reg : This property defines the address and size of the | ||
| 28 | memory-mapped registers contained within the system controller | ||
| 29 | chip. The address specified in the "reg" property should match | ||
| 30 | the unit address of the system-controller node. | ||
| 31 | - #address-cells : Address representation for system controller | ||
| 32 | devices. This field represents the number of cells needed to | ||
| 33 | represent the address of the memory-mapped registers of devices | ||
| 34 | within the system controller chip. | ||
| 35 | - #size-cells : Size representation for for the memory-mapped | ||
| 36 | registers within the system controller chip. | ||
| 37 | - #interrupt-cells : Defines the width of cells used to represent | ||
| 38 | interrupts. | ||
| 39 | |||
| 40 | Optional properties: | ||
| 41 | |||
| 42 | - model : The specific model of the system controller chip. Such | ||
| 43 | as, "mv64360", "mv64460", or "mv64560". | ||
| 44 | - compatible : A string identifying the compatibility identifiers | ||
| 45 | of the system controller chip. | ||
| 46 | |||
| 47 | The system-controller node contains child nodes for each system | ||
| 48 | controller device that the platform uses. Nodes should not be created | ||
| 49 | for devices which exist on the system controller chip but are not used | ||
| 50 | |||
| 51 | Example Marvell Discovery mv64360 system-controller node: | ||
| 52 | |||
| 53 | system-controller@f1000000 { /* Marvell Discovery mv64360 */ | ||
| 54 | #address-cells = <1>; | ||
| 55 | #size-cells = <1>; | ||
| 56 | model = "mv64360"; /* Default */ | ||
| 57 | compatible = "marvell,mv64360"; | ||
| 58 | clock-frequency = <133333333>; | ||
| 59 | reg = <0xf1000000 0x10000>; | ||
| 60 | virtual-reg = <0xf1000000>; | ||
| 61 | ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */ | ||
| 62 | 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */ | ||
| 63 | 0xa0000000 0xa0000000 0x4000000 /* User FLASH */ | ||
| 64 | 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */ | ||
| 65 | 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */ | ||
| 66 | |||
| 67 | [ child node definitions... ] | ||
| 68 | } | ||
| 69 | |||
| 70 | 2) Child nodes of /system-controller | ||
| 71 | |||
| 72 | a) Marvell Discovery MDIO bus | ||
| 73 | |||
| 74 | The MDIO is a bus to which the PHY devices are connected. For each | ||
| 75 | device that exists on this bus, a child node should be created. See | ||
| 76 | the definition of the PHY node below for an example of how to define | ||
| 77 | a PHY. | ||
| 78 | |||
| 79 | Required properties: | ||
| 80 | - #address-cells : Should be <1> | ||
| 81 | - #size-cells : Should be <0> | ||
| 82 | - device_type : Should be "mdio" | ||
| 83 | - compatible : Should be "marvell,mv64360-mdio" | ||
| 84 | |||
| 85 | Example: | ||
| 86 | |||
| 87 | mdio { | ||
| 88 | #address-cells = <1>; | ||
| 89 | #size-cells = <0>; | ||
| 90 | device_type = "mdio"; | ||
| 91 | compatible = "marvell,mv64360-mdio"; | ||
| 92 | |||
| 93 | ethernet-phy@0 { | ||
| 94 | ...... | ||
| 95 | }; | ||
| 96 | }; | ||
| 97 | |||
| 98 | |||
| 99 | b) Marvell Discovery ethernet controller | ||
| 100 | |||
| 101 | The Discover ethernet controller is described with two levels | ||
| 102 | of nodes. The first level describes an ethernet silicon block | ||
| 103 | and the second level describes up to 3 ethernet nodes within | ||
| 104 | that block. The reason for the multiple levels is that the | ||
| 105 | registers for the node are interleaved within a single set | ||
| 106 | of registers. The "ethernet-block" level describes the | ||
| 107 | shared register set, and the "ethernet" nodes describe ethernet | ||
| 108 | port-specific properties. | ||
| 109 | |||
| 110 | Ethernet block node | ||
| 111 | |||
| 112 | Required properties: | ||
| 113 | - #address-cells : <1> | ||
| 114 | - #size-cells : <0> | ||
| 115 | - compatible : "marvell,mv64360-eth-block" | ||
| 116 | - reg : Offset and length of the register set for this block | ||
| 117 | |||
| 118 | Example Discovery Ethernet block node: | ||
| 119 | ethernet-block@2000 { | ||
| 120 | #address-cells = <1>; | ||
| 121 | #size-cells = <0>; | ||
| 122 | compatible = "marvell,mv64360-eth-block"; | ||
| 123 | reg = <0x2000 0x2000>; | ||
| 124 | ethernet@0 { | ||
| 125 | ....... | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 | |||
| 129 | Ethernet port node | ||
| 130 | |||
| 131 | Required properties: | ||
| 132 | - device_type : Should be "network". | ||
| 133 | - compatible : Should be "marvell,mv64360-eth". | ||
| 134 | - reg : Should be <0>, <1>, or <2>, according to which registers | ||
| 135 | within the silicon block the device uses. | ||
| 136 | - interrupts : <a> where a is the interrupt number for the port. | ||
| 137 | - interrupt-parent : the phandle for the interrupt controller | ||
| 138 | that services interrupts for this device. | ||
| 139 | - phy : the phandle for the PHY connected to this ethernet | ||
| 140 | controller. | ||
| 141 | - local-mac-address : 6 bytes, MAC address | ||
| 142 | |||
| 143 | Example Discovery Ethernet port node: | ||
| 144 | ethernet@0 { | ||
| 145 | device_type = "network"; | ||
| 146 | compatible = "marvell,mv64360-eth"; | ||
| 147 | reg = <0>; | ||
| 148 | interrupts = <32>; | ||
| 149 | interrupt-parent = <&PIC>; | ||
| 150 | phy = <&PHY0>; | ||
| 151 | local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| 152 | }; | ||
| 153 | |||
| 154 | |||
| 155 | |||
| 156 | c) Marvell Discovery PHY nodes | ||
| 157 | |||
| 158 | Required properties: | ||
| 159 | - device_type : Should be "ethernet-phy" | ||
| 160 | - interrupts : <a> where a is the interrupt number for this phy. | ||
| 161 | - interrupt-parent : the phandle for the interrupt controller that | ||
| 162 | services interrupts for this device. | ||
| 163 | - reg : The ID number for the phy, usually a small integer | ||
| 164 | |||
| 165 | Example Discovery PHY node: | ||
| 166 | ethernet-phy@1 { | ||
| 167 | device_type = "ethernet-phy"; | ||
| 168 | compatible = "broadcom,bcm5421"; | ||
| 169 | interrupts = <76>; /* GPP 12 */ | ||
| 170 | interrupt-parent = <&PIC>; | ||
| 171 | reg = <1>; | ||
| 172 | }; | ||
| 173 | |||
| 174 | |||
| 175 | d) Marvell Discovery SDMA nodes | ||
| 176 | |||
| 177 | Represent DMA hardware associated with the MPSC (multiprotocol | ||
| 178 | serial controllers). | ||
| 179 | |||
| 180 | Required properties: | ||
| 181 | - compatible : "marvell,mv64360-sdma" | ||
| 182 | - reg : Offset and length of the register set for this device | ||
| 183 | - interrupts : <a> where a is the interrupt number for the DMA | ||
| 184 | device. | ||
| 185 | - interrupt-parent : the phandle for the interrupt controller | ||
| 186 | that services interrupts for this device. | ||
| 187 | |||
| 188 | Example Discovery SDMA node: | ||
| 189 | sdma@4000 { | ||
| 190 | compatible = "marvell,mv64360-sdma"; | ||
| 191 | reg = <0x4000 0xc18>; | ||
| 192 | virtual-reg = <0xf1004000>; | ||
| 193 | interrupts = <36>; | ||
| 194 | interrupt-parent = <&PIC>; | ||
| 195 | }; | ||
| 196 | |||
| 197 | |||
| 198 | e) Marvell Discovery BRG nodes | ||
| 199 | |||
| 200 | Represent baud rate generator hardware associated with the MPSC | ||
| 201 | (multiprotocol serial controllers). | ||
| 202 | |||
| 203 | Required properties: | ||
| 204 | - compatible : "marvell,mv64360-brg" | ||
| 205 | - reg : Offset and length of the register set for this device | ||
| 206 | - clock-src : A value from 0 to 15 which selects the clock | ||
| 207 | source for the baud rate generator. This value corresponds | ||
| 208 | to the CLKS value in the BRGx configuration register. See | ||
| 209 | the mv64x60 User's Manual. | ||
| 210 | - clock-frequence : The frequency (in Hz) of the baud rate | ||
| 211 | generator's input clock. | ||
| 212 | - current-speed : The current speed setting (presumably by | ||
| 213 | firmware) of the baud rate generator. | ||
| 214 | |||
| 215 | Example Discovery BRG node: | ||
| 216 | brg@b200 { | ||
| 217 | compatible = "marvell,mv64360-brg"; | ||
| 218 | reg = <0xb200 0x8>; | ||
| 219 | clock-src = <8>; | ||
| 220 | clock-frequency = <133333333>; | ||
| 221 | current-speed = <9600>; | ||
| 222 | }; | ||
| 223 | |||
| 224 | |||
| 225 | f) Marvell Discovery CUNIT nodes | ||
| 226 | |||
| 227 | Represent the Serial Communications Unit device hardware. | ||
| 228 | |||
| 229 | Required properties: | ||
| 230 | - reg : Offset and length of the register set for this device | ||
| 231 | |||
| 232 | Example Discovery CUNIT node: | ||
| 233 | cunit@f200 { | ||
| 234 | reg = <0xf200 0x200>; | ||
| 235 | }; | ||
| 236 | |||
| 237 | |||
| 238 | g) Marvell Discovery MPSCROUTING nodes | ||
| 239 | |||
| 240 | Represent the Discovery's MPSC routing hardware | ||
| 241 | |||
| 242 | Required properties: | ||
| 243 | - reg : Offset and length of the register set for this device | ||
| 244 | |||
| 245 | Example Discovery CUNIT node: | ||
| 246 | mpscrouting@b500 { | ||
| 247 | reg = <0xb400 0xc>; | ||
| 248 | }; | ||
| 249 | |||
| 250 | |||
| 251 | h) Marvell Discovery MPSCINTR nodes | ||
| 252 | |||
| 253 | Represent the Discovery's MPSC DMA interrupt hardware registers | ||
| 254 | (SDMA cause and mask registers). | ||
| 255 | |||
| 256 | Required properties: | ||
| 257 | - reg : Offset and length of the register set for this device | ||
| 258 | |||
| 259 | Example Discovery MPSCINTR node: | ||
| 260 | mpsintr@b800 { | ||
| 261 | reg = <0xb800 0x100>; | ||
| 262 | }; | ||
| 263 | |||
| 264 | |||
| 265 | i) Marvell Discovery MPSC nodes | ||
| 266 | |||
| 267 | Represent the Discovery's MPSC (Multiprotocol Serial Controller) | ||
| 268 | serial port. | ||
| 269 | |||
| 270 | Required properties: | ||
| 271 | - device_type : "serial" | ||
| 272 | - compatible : "marvell,mv64360-mpsc" | ||
| 273 | - reg : Offset and length of the register set for this device | ||
| 274 | - sdma : the phandle for the SDMA node used by this port | ||
| 275 | - brg : the phandle for the BRG node used by this port | ||
| 276 | - cunit : the phandle for the CUNIT node used by this port | ||
| 277 | - mpscrouting : the phandle for the MPSCROUTING node used by this port | ||
| 278 | - mpscintr : the phandle for the MPSCINTR node used by this port | ||
| 279 | - cell-index : the hardware index of this cell in the MPSC core | ||
| 280 | - max_idle : value needed for MPSC CHR3 (Maximum Frame Length) | ||
| 281 | register | ||
| 282 | - interrupts : <a> where a is the interrupt number for the MPSC. | ||
| 283 | - interrupt-parent : the phandle for the interrupt controller | ||
| 284 | that services interrupts for this device. | ||
| 285 | |||
| 286 | Example Discovery MPSCINTR node: | ||
| 287 | mpsc@8000 { | ||
| 288 | device_type = "serial"; | ||
| 289 | compatible = "marvell,mv64360-mpsc"; | ||
| 290 | reg = <0x8000 0x38>; | ||
| 291 | virtual-reg = <0xf1008000>; | ||
| 292 | sdma = <&SDMA0>; | ||
| 293 | brg = <&BRG0>; | ||
| 294 | cunit = <&CUNIT>; | ||
| 295 | mpscrouting = <&MPSCROUTING>; | ||
| 296 | mpscintr = <&MPSCINTR>; | ||
| 297 | cell-index = <0>; | ||
| 298 | max_idle = <40>; | ||
| 299 | interrupts = <40>; | ||
| 300 | interrupt-parent = <&PIC>; | ||
| 301 | }; | ||
| 302 | |||
| 303 | |||
| 304 | j) Marvell Discovery Watch Dog Timer nodes | ||
| 305 | |||
| 306 | Represent the Discovery's watchdog timer hardware | ||
| 307 | |||
| 308 | Required properties: | ||
| 309 | - compatible : "marvell,mv64360-wdt" | ||
| 310 | - reg : Offset and length of the register set for this device | ||
| 311 | |||
| 312 | Example Discovery Watch Dog Timer node: | ||
| 313 | wdt@b410 { | ||
| 314 | compatible = "marvell,mv64360-wdt"; | ||
| 315 | reg = <0xb410 0x8>; | ||
| 316 | }; | ||
| 317 | |||
| 318 | |||
| 319 | k) Marvell Discovery I2C nodes | ||
| 320 | |||
| 321 | Represent the Discovery's I2C hardware | ||
| 322 | |||
| 323 | Required properties: | ||
| 324 | - device_type : "i2c" | ||
| 325 | - compatible : "marvell,mv64360-i2c" | ||
| 326 | - reg : Offset and length of the register set for this device | ||
| 327 | - interrupts : <a> where a is the interrupt number for the I2C. | ||
| 328 | - interrupt-parent : the phandle for the interrupt controller | ||
| 329 | that services interrupts for this device. | ||
| 330 | |||
| 331 | Example Discovery I2C node: | ||
| 332 | compatible = "marvell,mv64360-i2c"; | ||
| 333 | reg = <0xc000 0x20>; | ||
| 334 | virtual-reg = <0xf100c000>; | ||
| 335 | interrupts = <37>; | ||
| 336 | interrupt-parent = <&PIC>; | ||
| 337 | }; | ||
| 338 | |||
| 339 | |||
| 340 | l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes | ||
| 341 | |||
| 342 | Represent the Discovery's PIC hardware | ||
| 343 | |||
| 344 | Required properties: | ||
| 345 | - #interrupt-cells : <1> | ||
| 346 | - #address-cells : <0> | ||
| 347 | - compatible : "marvell,mv64360-pic" | ||
| 348 | - reg : Offset and length of the register set for this device | ||
| 349 | - interrupt-controller | ||
| 350 | |||
| 351 | Example Discovery PIC node: | ||
| 352 | pic { | ||
| 353 | #interrupt-cells = <1>; | ||
| 354 | #address-cells = <0>; | ||
| 355 | compatible = "marvell,mv64360-pic"; | ||
| 356 | reg = <0x0 0x88>; | ||
| 357 | interrupt-controller; | ||
| 358 | }; | ||
| 359 | |||
| 360 | |||
| 361 | m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes | ||
| 362 | |||
| 363 | Represent the Discovery's MPP hardware | ||
| 364 | |||
| 365 | Required properties: | ||
| 366 | - compatible : "marvell,mv64360-mpp" | ||
| 367 | - reg : Offset and length of the register set for this device | ||
| 368 | |||
| 369 | Example Discovery MPP node: | ||
| 370 | mpp@f000 { | ||
| 371 | compatible = "marvell,mv64360-mpp"; | ||
| 372 | reg = <0xf000 0x10>; | ||
| 373 | }; | ||
| 374 | |||
| 375 | |||
| 376 | n) Marvell Discovery GPP (General Purpose Pins) nodes | ||
| 377 | |||
| 378 | Represent the Discovery's GPP hardware | ||
| 379 | |||
| 380 | Required properties: | ||
| 381 | - compatible : "marvell,mv64360-gpp" | ||
| 382 | - reg : Offset and length of the register set for this device | ||
| 383 | |||
| 384 | Example Discovery GPP node: | ||
| 385 | gpp@f000 { | ||
| 386 | compatible = "marvell,mv64360-gpp"; | ||
| 387 | reg = <0xf100 0x20>; | ||
| 388 | }; | ||
| 389 | |||
| 390 | |||
| 391 | o) Marvell Discovery PCI host bridge node | ||
| 392 | |||
| 393 | Represents the Discovery's PCI host bridge device. The properties | ||
| 394 | for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE | ||
| 395 | 1275-1994. A typical value for the compatible property is | ||
| 396 | "marvell,mv64360-pci". | ||
| 397 | |||
| 398 | Example Discovery PCI host bridge node | ||
| 399 | pci@80000000 { | ||
| 400 | #address-cells = <3>; | ||
| 401 | #size-cells = <2>; | ||
| 402 | #interrupt-cells = <1>; | ||
| 403 | device_type = "pci"; | ||
| 404 | compatible = "marvell,mv64360-pci"; | ||
| 405 | reg = <0xcf8 0x8>; | ||
| 406 | ranges = <0x01000000 0x0 0x0 | ||
| 407 | 0x88000000 0x0 0x01000000 | ||
| 408 | 0x02000000 0x0 0x80000000 | ||
| 409 | 0x80000000 0x0 0x08000000>; | ||
| 410 | bus-range = <0 255>; | ||
| 411 | clock-frequency = <66000000>; | ||
| 412 | interrupt-parent = <&PIC>; | ||
| 413 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | ||
| 414 | interrupt-map = < | ||
| 415 | /* IDSEL 0x0a */ | ||
| 416 | 0x5000 0 0 1 &PIC 80 | ||
| 417 | 0x5000 0 0 2 &PIC 81 | ||
| 418 | 0x5000 0 0 3 &PIC 91 | ||
| 419 | 0x5000 0 0 4 &PIC 93 | ||
| 420 | |||
| 421 | /* IDSEL 0x0b */ | ||
| 422 | 0x5800 0 0 1 &PIC 91 | ||
| 423 | 0x5800 0 0 2 &PIC 93 | ||
| 424 | 0x5800 0 0 3 &PIC 80 | ||
| 425 | 0x5800 0 0 4 &PIC 81 | ||
| 426 | |||
| 427 | /* IDSEL 0x0c */ | ||
| 428 | 0x6000 0 0 1 &PIC 91 | ||
| 429 | 0x6000 0 0 2 &PIC 93 | ||
| 430 | 0x6000 0 0 3 &PIC 80 | ||
| 431 | 0x6000 0 0 4 &PIC 81 | ||
| 432 | |||
| 433 | /* IDSEL 0x0d */ | ||
| 434 | 0x6800 0 0 1 &PIC 93 | ||
| 435 | 0x6800 0 0 2 &PIC 80 | ||
| 436 | 0x6800 0 0 3 &PIC 81 | ||
| 437 | 0x6800 0 0 4 &PIC 91 | ||
| 438 | >; | ||
| 439 | }; | ||
| 440 | |||
| 441 | |||
| 442 | p) Marvell Discovery CPU Error nodes | ||
| 443 | |||
| 444 | Represent the Discovery's CPU error handler device. | ||
| 445 | |||
| 446 | Required properties: | ||
| 447 | - compatible : "marvell,mv64360-cpu-error" | ||
| 448 | - reg : Offset and length of the register set for this device | ||
| 449 | - interrupts : the interrupt number for this device | ||
| 450 | - interrupt-parent : the phandle for the interrupt controller | ||
| 451 | that services interrupts for this device. | ||
| 452 | |||
| 453 | Example Discovery CPU Error node: | ||
| 454 | cpu-error@0070 { | ||
| 455 | compatible = "marvell,mv64360-cpu-error"; | ||
| 456 | reg = <0x70 0x10 0x128 0x28>; | ||
| 457 | interrupts = <3>; | ||
| 458 | interrupt-parent = <&PIC>; | ||
| 459 | }; | ||
| 460 | |||
| 461 | |||
| 462 | q) Marvell Discovery SRAM Controller nodes | ||
| 463 | |||
| 464 | Represent the Discovery's SRAM controller device. | ||
| 465 | |||
| 466 | Required properties: | ||
| 467 | - compatible : "marvell,mv64360-sram-ctrl" | ||
| 468 | - reg : Offset and length of the register set for this device | ||
| 469 | - interrupts : the interrupt number for this device | ||
| 470 | - interrupt-parent : the phandle for the interrupt controller | ||
| 471 | that services interrupts for this device. | ||
| 472 | |||
| 473 | Example Discovery SRAM Controller node: | ||
| 474 | sram-ctrl@0380 { | ||
| 475 | compatible = "marvell,mv64360-sram-ctrl"; | ||
| 476 | reg = <0x380 0x80>; | ||
| 477 | interrupts = <13>; | ||
| 478 | interrupt-parent = <&PIC>; | ||
| 479 | }; | ||
| 480 | |||
| 481 | |||
| 482 | r) Marvell Discovery PCI Error Handler nodes | ||
| 483 | |||
| 484 | Represent the Discovery's PCI error handler device. | ||
| 485 | |||
| 486 | Required properties: | ||
| 487 | - compatible : "marvell,mv64360-pci-error" | ||
| 488 | - reg : Offset and length of the register set for this device | ||
| 489 | - interrupts : the interrupt number for this device | ||
| 490 | - interrupt-parent : the phandle for the interrupt controller | ||
| 491 | that services interrupts for this device. | ||
| 492 | |||
| 493 | Example Discovery PCI Error Handler node: | ||
| 494 | pci-error@1d40 { | ||
| 495 | compatible = "marvell,mv64360-pci-error"; | ||
| 496 | reg = <0x1d40 0x40 0xc28 0x4>; | ||
| 497 | interrupts = <12>; | ||
| 498 | interrupt-parent = <&PIC>; | ||
| 499 | }; | ||
| 500 | |||
| 501 | |||
| 502 | s) Marvell Discovery Memory Controller nodes | ||
| 503 | |||
| 504 | Represent the Discovery's memory controller device. | ||
| 505 | |||
| 506 | Required properties: | ||
| 507 | - compatible : "marvell,mv64360-mem-ctrl" | ||
| 508 | - reg : Offset and length of the register set for this device | ||
| 509 | - interrupts : the interrupt number for this device | ||
| 510 | - interrupt-parent : the phandle for the interrupt controller | ||
| 511 | that services interrupts for this device. | ||
| 512 | |||
| 513 | Example Discovery Memory Controller node: | ||
| 514 | mem-ctrl@1400 { | ||
| 515 | compatible = "marvell,mv64360-mem-ctrl"; | ||
| 516 | reg = <0x1400 0x60>; | ||
| 517 | interrupts = <17>; | ||
| 518 | interrupt-parent = <&PIC>; | ||
| 519 | }; | ||
| 520 | |||
| 521 | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | PHY nodes | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | |||
| 5 | - device_type : Should be "ethernet-phy" | ||
| 6 | - interrupts : <a b> where a is the interrupt number and b is a | ||
| 7 | field that represents an encoding of the sense and level | ||
| 8 | information for the interrupt. This should be encoded based on | ||
| 9 | the information in section 2) depending on the type of interrupt | ||
| 10 | controller you have. | ||
| 11 | - interrupt-parent : the phandle for the interrupt controller that | ||
| 12 | services interrupts for this device. | ||
| 13 | - reg : The ID number for the phy, usually a small integer | ||
| 14 | - linux,phandle : phandle for this node; likely referenced by an | ||
| 15 | ethernet controller node. | ||
| 16 | |||
| 17 | Example: | ||
| 18 | |||
| 19 | ethernet-phy@0 { | ||
| 20 | linux,phandle = <2452000> | ||
| 21 | interrupt-parent = <40000>; | ||
| 22 | interrupts = <35 1>; | ||
| 23 | reg = <0>; | ||
| 24 | device_type = "ethernet-phy"; | ||
| 25 | }; | ||
| @@ -0,0 +1,57 @@ | |||
| 1 | SPI (Serial Peripheral Interface) busses | ||
| 2 | |||
| 3 | SPI busses can be described with a node for the SPI master device | ||
| 4 | and a set of child nodes for each SPI slave on the bus. For this | ||
| 5 | discussion, it is assumed that the system's SPI controller is in | ||
| 6 | SPI master mode. This binding does not describe SPI controllers | ||
| 7 | in slave mode. | ||
| 8 | |||
| 9 | The SPI master node requires the following properties: | ||
| 10 | - #address-cells - number of cells required to define a chip select | ||
| 11 | address on the SPI bus. | ||
| 12 | - #size-cells - should be zero. | ||
| 13 | - compatible - name of SPI bus controller following generic names | ||
| 14 | recommended practice. | ||
| 15 | No other properties are required in the SPI bus node. It is assumed | ||
| 16 | that a driver for an SPI bus device will understand that it is an SPI bus. | ||
| 17 | However, the binding does not attempt to define the specific method for | ||
| 18 | assigning chip select numbers. Since SPI chip select configuration is | ||
| 19 | flexible and non-standardized, it is left out of this binding with the | ||
| 20 | assumption that board specific platform code will be used to manage | ||
| 21 | chip selects. Individual drivers can define additional properties to | ||
| 22 | support describing the chip select layout. | ||
| 23 | |||
| 24 | SPI slave nodes must be children of the SPI master node and can | ||
| 25 | contain the following properties. | ||
| 26 | - reg - (required) chip select address of device. | ||
| 27 | - compatible - (required) name of SPI device following generic names | ||
| 28 | recommended practice | ||
| 29 | - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz | ||
| 30 | - spi-cpol - (optional) Empty property indicating device requires | ||
| 31 | inverse clock polarity (CPOL) mode | ||
| 32 | - spi-cpha - (optional) Empty property indicating device requires | ||
| 33 | shifted clock phase (CPHA) mode | ||
| 34 | - spi-cs-high - (optional) Empty property indicating device requires | ||
| 35 | chip select active high | ||
| 36 | |||
| 37 | SPI example for an MPC5200 SPI bus: | ||
| 38 | spi@f00 { | ||
| 39 | #address-cells = <1>; | ||
| 40 | #size-cells = <0>; | ||
| 41 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; | ||
| 42 | reg = <0xf00 0x20>; | ||
| 43 | interrupts = <2 13 0 2 14 0>; | ||
| 44 | interrupt-parent = <&mpc5200_pic>; | ||
| 45 | |||
| 46 | ethernet-switch@0 { | ||
| 47 | compatible = "micrel,ks8995m"; | ||
| 48 | spi-max-frequency = <1000000>; | ||
| 49 | reg = <0>; | ||
| 50 | }; | ||
| 51 | |||
| 52 | codec@1 { | ||
| 53 | compatible = "ti,tlv320aic26"; | ||
| 54 | spi-max-frequency = <100000>; | ||
| 55 | reg = <1>; | ||
| 56 | }; | ||
| 57 | }; | ||
| @@ -0,0 +1,25 @@ | |||
| 1 | USB EHCI controllers | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible : should be "usb-ehci". | ||
| 5 | - reg : should contain at least address and length of the standard EHCI | ||
| 6 | register set for the device. Optional platform-dependent registers | ||
| 7 | (debug-port or other) can be also specified here, but only after | ||
| 8 | definition of standard EHCI registers. | ||
| 9 | - interrupts : one EHCI interrupt should be described here. | ||
| 10 | If device registers are implemented in big endian mode, the device | ||
| 11 | node should have "big-endian-regs" property. | ||
| 12 | If controller implementation operates with big endian descriptors, | ||
| 13 | "big-endian-desc" property should be specified. | ||
| 14 | If both big endian registers and descriptors are used by the controller | ||
| 15 | implementation, "big-endian" property can be specified instead of having | ||
| 16 | both "big-endian-regs" and "big-endian-desc". | ||
| 17 | |||
| 18 | Example (Sequoia 440EPx): | ||
| 19 | ehci@e0000300 { | ||
| 20 | compatible = "ibm,usb-ehci-440epx", "usb-ehci"; | ||
| 21 | interrupt-parent = <&UIC0>; | ||
| 22 | interrupts = <1a 4>; | ||
| 23 | reg = <0 e0000300 90 0 e0000390 70>; | ||
| 24 | big-endian; | ||
| 25 | }; | ||
| @@ -0,0 +1,295 @@ | |||
| 1 | d) Xilinx IP cores | ||
| 2 | |||
| 3 | The Xilinx EDK toolchain ships with a set of IP cores (devices) for use | ||
| 4 | in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range | ||
| 5 | of standard device types (network, serial, etc.) and miscellaneous | ||
| 6 | devices (gpio, LCD, spi, etc). Also, since these devices are | ||
| 7 | implemented within the fpga fabric every instance of the device can be | ||
| 8 | synthesised with different options that change the behaviour. | ||
| 9 | |||
| 10 | Each IP-core has a set of parameters which the FPGA designer can use to | ||
| 11 | control how the core is synthesized. Historically, the EDK tool would | ||
| 12 | extract the device parameters relevant to device drivers and copy them | ||
| 13 | into an 'xparameters.h' in the form of #define symbols. This tells the | ||
| 14 | device drivers how the IP cores are configured, but it requres the kernel | ||
| 15 | to be recompiled every time the FPGA bitstream is resynthesized. | ||
| 16 | |||
| 17 | The new approach is to export the parameters into the device tree and | ||
| 18 | generate a new device tree each time the FPGA bitstream changes. The | ||
| 19 | parameters which used to be exported as #defines will now become | ||
| 20 | properties of the device node. In general, device nodes for IP-cores | ||
| 21 | will take the following form: | ||
| 22 | |||
| 23 | (name): (generic-name)@(base-address) { | ||
| 24 | compatible = "xlnx,(ip-core-name)-(HW_VER)" | ||
| 25 | [, (list of compatible devices), ...]; | ||
| 26 | reg = <(baseaddr) (size)>; | ||
| 27 | interrupt-parent = <&interrupt-controller-phandle>; | ||
| 28 | interrupts = < ... >; | ||
| 29 | xlnx,(parameter1) = "(string-value)"; | ||
| 30 | xlnx,(parameter2) = <(int-value)>; | ||
| 31 | }; | ||
| 32 | |||
| 33 | (generic-name): an open firmware-style name that describes the | ||
| 34 | generic class of device. Preferably, this is one word, such | ||
| 35 | as 'serial' or 'ethernet'. | ||
| 36 | (ip-core-name): the name of the ip block (given after the BEGIN | ||
| 37 | directive in system.mhs). Should be in lowercase | ||
| 38 | and all underscores '_' converted to dashes '-'. | ||
| 39 | (name): is derived from the "PARAMETER INSTANCE" value. | ||
| 40 | (parameter#): C_* parameters from system.mhs. The C_ prefix is | ||
| 41 | dropped from the parameter name, the name is converted | ||
| 42 | to lowercase and all underscore '_' characters are | ||
| 43 | converted to dashes '-'. | ||
| 44 | (baseaddr): the baseaddr parameter value (often named C_BASEADDR). | ||
| 45 | (HW_VER): from the HW_VER parameter. | ||
| 46 | (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1). | ||
| 47 | |||
| 48 | Typically, the compatible list will include the exact IP core version | ||
| 49 | followed by an older IP core version which implements the same | ||
| 50 | interface or any other device with the same interface. | ||
| 51 | |||
| 52 | 'reg', 'interrupt-parent' and 'interrupts' are all optional properties. | ||
| 53 | |||
| 54 | For example, the following block from system.mhs: | ||
| 55 | |||
| 56 | BEGIN opb_uartlite | ||
| 57 | PARAMETER INSTANCE = opb_uartlite_0 | ||
| 58 | PARAMETER HW_VER = 1.00.b | ||
| 59 | PARAMETER C_BAUDRATE = 115200 | ||
| 60 | PARAMETER C_DATA_BITS = 8 | ||
| 61 | PARAMETER C_ODD_PARITY = 0 | ||
| 62 | PARAMETER C_USE_PARITY = 0 | ||
| 63 | PARAMETER C_CLK_FREQ = 50000000 | ||
| 64 | PARAMETER C_BASEADDR = 0xEC100000 | ||
| 65 | PARAMETER C_HIGHADDR = 0xEC10FFFF | ||
| 66 | BUS_INTERFACE SOPB = opb_7 | ||
| 67 | PORT OPB_Clk = CLK_50MHz | ||
| 68 | PORT Interrupt = opb_uartlite_0_Interrupt | ||
| 69 | PORT RX = opb_uartlite_0_RX | ||
| 70 | PORT TX = opb_uartlite_0_TX | ||
| 71 | PORT OPB_Rst = sys_bus_reset_0 | ||
| 72 | END | ||
| 73 | |||
| 74 | becomes the following device tree node: | ||
| 75 | |||
| 76 | opb_uartlite_0: serial@ec100000 { | ||
| 77 | device_type = "serial"; | ||
| 78 | compatible = "xlnx,opb-uartlite-1.00.b"; | ||
| 79 | reg = <ec100000 10000>; | ||
| 80 | interrupt-parent = <&opb_intc_0>; | ||
| 81 | interrupts = <1 0>; // got this from the opb_intc parameters | ||
| 82 | current-speed = <d#115200>; // standard serial device prop | ||
| 83 | clock-frequency = <d#50000000>; // standard serial device prop | ||
| 84 | xlnx,data-bits = <8>; | ||
| 85 | xlnx,odd-parity = <0>; | ||
| 86 | xlnx,use-parity = <0>; | ||
| 87 | }; | ||
| 88 | |||
| 89 | Some IP cores actually implement 2 or more logical devices. In | ||
| 90 | this case, the device should still describe the whole IP core with | ||
| 91 | a single node and add a child node for each logical device. The | ||
| 92 | ranges property can be used to translate from parent IP-core to the | ||
| 93 | registers of each device. In addition, the parent node should be | ||
| 94 | compatible with the bus type 'xlnx,compound', and should contain | ||
| 95 | #address-cells and #size-cells, as with any other bus. (Note: this | ||
| 96 | makes the assumption that both logical devices have the same bus | ||
| 97 | binding. If this is not true, then separate nodes should be used | ||
| 98 | for each logical device). The 'cell-index' property can be used to | ||
| 99 | enumerate logical devices within an IP core. For example, the | ||
| 100 | following is the system.mhs entry for the dual ps2 controller found | ||
| 101 | on the ml403 reference design. | ||
| 102 | |||
| 103 | BEGIN opb_ps2_dual_ref | ||
| 104 | PARAMETER INSTANCE = opb_ps2_dual_ref_0 | ||
| 105 | PARAMETER HW_VER = 1.00.a | ||
| 106 | PARAMETER C_BASEADDR = 0xA9000000 | ||
| 107 | PARAMETER C_HIGHADDR = 0xA9001FFF | ||
| 108 | BUS_INTERFACE SOPB = opb_v20_0 | ||
| 109 | PORT Sys_Intr1 = ps2_1_intr | ||
| 110 | PORT Sys_Intr2 = ps2_2_intr | ||
| 111 | PORT Clkin1 = ps2_clk_rx_1 | ||
| 112 | PORT Clkin2 = ps2_clk_rx_2 | ||
| 113 | PORT Clkpd1 = ps2_clk_tx_1 | ||
| 114 | PORT Clkpd2 = ps2_clk_tx_2 | ||
| 115 | PORT Rx1 = ps2_d_rx_1 | ||
| 116 | PORT Rx2 = ps2_d_rx_2 | ||
| 117 | PORT Txpd1 = ps2_d_tx_1 | ||
| 118 | PORT Txpd2 = ps2_d_tx_2 | ||
| 119 | END | ||
| 120 | |||
| 121 | It would result in the following device tree nodes: | ||
| 122 | |||
| 123 | opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 { | ||
| 124 | #address-cells = <1>; | ||
| 125 | #size-cells = <1>; | ||
| 126 | compatible = "xlnx,compound"; | ||
| 127 | ranges = <0 a9000000 2000>; | ||
| 128 | // If this device had extra parameters, then they would | ||
| 129 | // go here. | ||
| 130 | ps2@0 { | ||
| 131 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | ||
| 132 | reg = <0 40>; | ||
| 133 | interrupt-parent = <&opb_intc_0>; | ||
| 134 | interrupts = <3 0>; | ||
| 135 | cell-index = <0>; | ||
| 136 | }; | ||
| 137 | ps2@1000 { | ||
| 138 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | ||
| 139 | reg = <1000 40>; | ||
| 140 | interrupt-parent = <&opb_intc_0>; | ||
| 141 | interrupts = <3 0>; | ||
| 142 | cell-index = <0>; | ||
| 143 | }; | ||
| 144 | }; | ||
| 145 | |||
| 146 | Also, the system.mhs file defines bus attachments from the processor | ||
| 147 | to the devices. The device tree structure should reflect the bus | ||
| 148 | attachments. Again an example; this system.mhs fragment: | ||
| 149 | |||
| 150 | BEGIN ppc405_virtex4 | ||
| 151 | PARAMETER INSTANCE = ppc405_0 | ||
| 152 | PARAMETER HW_VER = 1.01.a | ||
| 153 | BUS_INTERFACE DPLB = plb_v34_0 | ||
| 154 | BUS_INTERFACE IPLB = plb_v34_0 | ||
| 155 | END | ||
| 156 | |||
| 157 | BEGIN opb_intc | ||
| 158 | PARAMETER INSTANCE = opb_intc_0 | ||
| 159 | PARAMETER HW_VER = 1.00.c | ||
| 160 | PARAMETER C_BASEADDR = 0xD1000FC0 | ||
| 161 | PARAMETER C_HIGHADDR = 0xD1000FDF | ||
| 162 | BUS_INTERFACE SOPB = opb_v20_0 | ||
| 163 | END | ||
| 164 | |||
| 165 | BEGIN opb_uart16550 | ||
| 166 | PARAMETER INSTANCE = opb_uart16550_0 | ||
| 167 | PARAMETER HW_VER = 1.00.d | ||
| 168 | PARAMETER C_BASEADDR = 0xa0000000 | ||
| 169 | PARAMETER C_HIGHADDR = 0xa0001FFF | ||
| 170 | BUS_INTERFACE SOPB = opb_v20_0 | ||
| 171 | END | ||
| 172 | |||
| 173 | BEGIN plb_v34 | ||
| 174 | PARAMETER INSTANCE = plb_v34_0 | ||
| 175 | PARAMETER HW_VER = 1.02.a | ||
| 176 | END | ||
| 177 | |||
| 178 | BEGIN plb_bram_if_cntlr | ||
| 179 | PARAMETER INSTANCE = plb_bram_if_cntlr_0 | ||
| 180 | PARAMETER HW_VER = 1.00.b | ||
| 181 | PARAMETER C_BASEADDR = 0xFFFF0000 | ||
| 182 | PARAMETER C_HIGHADDR = 0xFFFFFFFF | ||
| 183 | BUS_INTERFACE SPLB = plb_v34_0 | ||
| 184 | END | ||
| 185 | |||
| 186 | BEGIN plb2opb_bridge | ||
| 187 | PARAMETER INSTANCE = plb2opb_bridge_0 | ||
| 188 | PARAMETER HW_VER = 1.01.a | ||
| 189 | PARAMETER C_RNG0_BASEADDR = 0x20000000 | ||
| 190 | PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF | ||
| 191 | PARAMETER C_RNG1_BASEADDR = 0x60000000 | ||
| 192 | PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF | ||
| 193 | PARAMETER C_RNG2_BASEADDR = 0x80000000 | ||
| 194 | PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF | ||
| 195 | PARAMETER C_RNG3_BASEADDR = 0xC0000000 | ||
| 196 | PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF | ||
| 197 | BUS_INTERFACE SPLB = plb_v34_0 | ||
| 198 | BUS_INTERFACE MOPB = opb_v20_0 | ||
| 199 | END | ||
| 200 | |||
| 201 | Gives this device tree (some properties removed for clarity): | ||
| 202 | |||
| 203 | plb@0 { | ||
| 204 | #address-cells = <1>; | ||
| 205 | #size-cells = <1>; | ||
| 206 | compatible = "xlnx,plb-v34-1.02.a"; | ||
| 207 | device_type = "ibm,plb"; | ||
| 208 | ranges; // 1:1 translation | ||
| 209 | |||
| 210 | plb_bram_if_cntrl_0: bram@ffff0000 { | ||
| 211 | reg = <ffff0000 10000>; | ||
| 212 | } | ||
| 213 | |||
| 214 | opb@20000000 { | ||
| 215 | #address-cells = <1>; | ||
| 216 | #size-cells = <1>; | ||
| 217 | ranges = <20000000 20000000 20000000 | ||
| 218 | 60000000 60000000 20000000 | ||
| 219 | 80000000 80000000 40000000 | ||
| 220 | c0000000 c0000000 20000000>; | ||
| 221 | |||
| 222 | opb_uart16550_0: serial@a0000000 { | ||
| 223 | reg = <a00000000 2000>; | ||
| 224 | }; | ||
| 225 | |||
| 226 | opb_intc_0: interrupt-controller@d1000fc0 { | ||
| 227 | reg = <d1000fc0 20>; | ||
| 228 | }; | ||
| 229 | }; | ||
| 230 | }; | ||
| 231 | |||
| 232 | That covers the general approach to binding xilinx IP cores into the | ||
| 233 | device tree. The following are bindings for specific devices: | ||
| 234 | |||
| 235 | i) Xilinx ML300 Framebuffer | ||
| 236 | |||
| 237 | Simple framebuffer device from the ML300 reference design (also on the | ||
| 238 | ML403 reference design as well as others). | ||
| 239 | |||
| 240 | Optional properties: | ||
| 241 | - resolution = <xres yres> : pixel resolution of framebuffer. Some | ||
| 242 | implementations use a different resolution. | ||
| 243 | Default is <d#640 d#480> | ||
| 244 | - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory. | ||
| 245 | Default is <d#1024 d#480>. | ||
| 246 | - rotate-display (empty) : rotate display 180 degrees. | ||
| 247 | |||
| 248 | ii) Xilinx SystemACE | ||
| 249 | |||
| 250 | The Xilinx SystemACE device is used to program FPGAs from an FPGA | ||
| 251 | bitstream stored on a CF card. It can also be used as a generic CF | ||
| 252 | interface device. | ||
| 253 | |||
| 254 | Optional properties: | ||
| 255 | - 8-bit (empty) : Set this property for SystemACE in 8 bit mode | ||
| 256 | |||
| 257 | iii) Xilinx EMAC and Xilinx TEMAC | ||
| 258 | |||
| 259 | Xilinx Ethernet devices. In addition to general xilinx properties | ||
| 260 | listed above, nodes for these devices should include a phy-handle | ||
| 261 | property, and may include other common network device properties | ||
| 262 | like local-mac-address. | ||
| 263 | |||
| 264 | iv) Xilinx Uartlite | ||
| 265 | |||
| 266 | Xilinx uartlite devices are simple fixed speed serial ports. | ||
| 267 | |||
| 268 | Required properties: | ||
| 269 | - current-speed : Baud rate of uartlite | ||
| 270 | |||
| 271 | v) Xilinx hwicap | ||
| 272 | |||
| 273 | Xilinx hwicap devices provide access to the configuration logic | ||
| 274 | of the FPGA through the Internal Configuration Access Port | ||
| 275 | (ICAP). The ICAP enables partial reconfiguration of the FPGA, | ||
| 276 | readback of the configuration information, and some control over | ||
| 277 | 'warm boots' of the FPGA fabric. | ||
| 278 | |||
| 279 | Required properties: | ||
| 280 | - xlnx,family : The family of the FPGA, necessary since the | ||
| 281 | capabilities of the underlying ICAP hardware | ||
| 282 | differ between different families. May be | ||
| 283 | 'virtex2p', 'virtex4', or 'virtex5'. | ||
| 284 | |||
| 285 | vi) Xilinx Uart 16550 | ||
| 286 | |||
| 287 | Xilinx UART 16550 devices are very similar to the NS16550 but with | ||
| 288 | different register spacing and an offset from the base address. | ||
| 289 | |||
| 290 | Required properties: | ||
| 291 | - clock-frequency : Frequency of the clock input | ||
| 292 | - reg-offset : A value of 3 is required | ||
| 293 | - reg-shift : A value of 2 is required | ||
| 294 | |||
| 295 | |||
| @@ -111,6 +111,8 @@ following attributes: · 110 unmodified lines | |||
| 111 | 111 | ||
| 112 | name: Name assigned by driver to this key (interface or driver name). | 112 | name: Name assigned by driver to this key (interface or driver name). |
| 113 | type: Driver type string ("wlan", "bluetooth", etc). | 113 | type: Driver type string ("wlan", "bluetooth", etc). |
| 114 | persistent: Whether the soft blocked state is initialised from | ||
| 115 | non-volatile storage at startup. | ||
| 114 | state: Current state of the transmitter | 116 | state: Current state of the transmitter |
| 115 | 0: RFKILL_STATE_SOFT_BLOCKED | 117 | 0: RFKILL_STATE_SOFT_BLOCKED |
| 116 | transmitter is turned off by software | 118 | transmitter is turned off by software |
| @@ -240,6 +240,7 @@ AD1986A · 239 unmodified lines | |||
| 240 | laptop-automute 2-channel with EAPD and HP-automute (Lenovo N100) | 240 | laptop-automute 2-channel with EAPD and HP-automute (Lenovo N100) |
| 241 | ultra 2-channel with EAPD (Samsung Ultra tablet PC) | 241 | ultra 2-channel with EAPD (Samsung Ultra tablet PC) |
| 242 | samsung 2-channel with EAPD (Samsung R65) | 242 | samsung 2-channel with EAPD (Samsung R65) |
| 243 | samsung-p50 2-channel with HP-automute (Samsung P50) | ||
| 243 | 244 | ||
| 244 | AD1988/AD1988B/AD1989A/AD1989B | 245 | AD1988/AD1988B/AD1989A/AD1989B |
| 245 | ============================== | 246 | ============================== |
| @@ -99,11 +99,13 @@ void parse_opts(int argc, char *argv[]) · 98 unmodified lines | |||
| 99 | { "lsb", 0, 0, 'L' }, | 99 | { "lsb", 0, 0, 'L' }, |
| 100 | { "cs-high", 0, 0, 'C' }, | 100 | { "cs-high", 0, 0, 'C' }, |
| 101 | { "3wire", 0, 0, '3' }, | 101 | { "3wire", 0, 0, '3' }, |
| 102 | { "no-cs", 0, 0, 'N' }, | ||
| 103 | { "ready", 0, 0, 'R' }, | ||
| 102 | { NULL, 0, 0, 0 }, | 104 | { NULL, 0, 0, 0 }, |
| 103 | }; | 105 | }; |
| 104 | int c; | 106 | int c; |
| 105 | 107 | ||
| 106 | c = getopt_long(argc, argv, "D:s:d:b:lHOLC3", lopts, NULL); | 108 | c = getopt_long(argc, argv, "D:s:d:b:lHOLC3NR", lopts, NULL); |
| 107 | 109 | ||
| 108 | if (c == -1) | 110 | if (c == -1) |
| 109 | break; | 111 | break; |
| @@ -139,6 +141,12 @@ void parse_opts(int argc, char *argv[]) · 29 unmodified lines | |||
| 139 | case '3': | 141 | case '3': |
| 140 | mode |= SPI_3WIRE; | 142 | mode |= SPI_3WIRE; |
| 141 | break; | 143 | break; |
| 144 | case 'N': | ||
| 145 | mode |= SPI_NO_CS; | ||
| 146 | break; | ||
| 147 | case 'R': | ||
| 148 | mode |= SPI_READY; | ||
| 149 | break; | ||
| 142 | default: | 150 | default: |
| 143 | print_usage(argv[0]); | 151 | print_usage(argv[0]); |
| 144 | break; | 152 | break; |
| @@ -6,8 +6,8 @@ · 5 unmodified lines | |||
| 6 | 5 -> Leadtek Winfast 2000XP Expert [107d:6611,107d:6613] | 6 | 5 -> Leadtek Winfast 2000XP Expert [107d:6611,107d:6613] |
| 7 | 6 -> AverTV Studio 303 (M126) [1461:000b] | 7 | 6 -> AverTV Studio 303 (M126) [1461:000b] |
| 8 | 7 -> MSI TV-@nywhere Master [1462:8606] | 8 | 7 -> MSI TV-@nywhere Master [1462:8606] |
| 9 | 8 -> Leadtek Winfast DV2000 [107d:6620] | 9 | 8 -> Leadtek Winfast DV2000 [107d:6620,107d:6621] |
| 10 | 9 -> Leadtek PVR 2000 [107d:663b,107d:663c,107d:6632] | 10 | 9 -> Leadtek PVR 2000 [107d:663b,107d:663c,107d:6632,107d:6630,107d:6638,107d:6631,107d:6637,107d:663d] |
| 11 | 10 -> IODATA GV-VCP3/PCI [10fc:d003] | 11 | 10 -> IODATA GV-VCP3/PCI [10fc:d003] |
| 12 | 11 -> Prolink PlayTV PVR | 12 | 11 -> Prolink PlayTV PVR |
| 13 | 12 -> ASUS PVR-416 [1043:4823,1461:c111] | 13 | 12 -> ASUS PVR-416 [1043:4823,1461:c111] |
| @@ -59,7 +59,7 @@ · 45 unmodified lines | |||
| 59 | 58 -> Pinnacle PCTV HD 800i [11bd:0051] | 59 | 58 -> Pinnacle PCTV HD 800i [11bd:0051] |
| 60 | 59 -> DViCO FusionHDTV 5 PCI nano [18ac:d530] | 60 | 59 -> DViCO FusionHDTV 5 PCI nano [18ac:d530] |
| 61 | 60 -> Pinnacle Hybrid PCTV [12ab:1788] | 61 | 60 -> Pinnacle Hybrid PCTV [12ab:1788] |
| 62 | 61 -> Winfast TV2000 XP Global [107d:6f18] | 62 | 61 -> Leadtek TV2000 XP Global [107d:6f18,107d:6618] |
| 63 | 62 -> PowerColor RA330 [14f1:ea3d] | 63 | 62 -> PowerColor RA330 [14f1:ea3d] |
| 64 | 63 -> Geniatech X8000-MT DVBT [14f1:8852] | 64 | 63 -> Geniatech X8000-MT DVBT [14f1:8852] |
| 65 | 64 -> DViCO FusionHDTV DVB-T PRO [18ac:db30] | 65 | 64 -> DViCO FusionHDTV DVB-T PRO [18ac:db30] |
| @@ -65,3 +65,4 @@ · 64 unmodified lines | |||
| 65 | 67 -> Terratec Grabby (em2860) [0ccd:0096] | 65 | 67 -> Terratec Grabby (em2860) [0ccd:0096] |
| 66 | 68 -> Terratec AV350 (em2860) [0ccd:0084] | 66 | 68 -> Terratec AV350 (em2860) [0ccd:0084] |
| 67 | 69 -> KWorld ATSC 315U HDTV TV Box (em2882) [eb1a:a313] | 67 | 69 -> KWorld ATSC 315U HDTV TV Box (em2882) [eb1a:a313] |
| 68 | 70 -> Evga inDtube (em2882) | ||
| @@ -390,6 +390,30 @@ later date. It differs between i2c drivers and as such can be confusing. · 389 unmodified lines | |||
| 390 | To see which chip variants are supported you can look in the i2c driver code | 390 | To see which chip variants are supported you can look in the i2c driver code |
| 391 | for the i2c_device_id table. This lists all the possibilities. | 391 | for the i2c_device_id table. This lists all the possibilities. |
| 392 | 392 | ||
| 393 | There are two more helper functions: | ||
| 394 | |||
| 395 | v4l2_i2c_new_subdev_cfg: this function adds new irq and platform_data | ||
| 396 | arguments and has both 'addr' and 'probed_addrs' arguments: if addr is not | ||
| 397 | 0 then that will be used (non-probing variant), otherwise the probed_addrs | ||
| 398 | are probed. | ||
| 399 | |||
| 400 | For example: this will probe for address 0x10: | ||
| 401 | |||
| 402 | struct v4l2_subdev *sd = v4l2_i2c_new_subdev_cfg(v4l2_dev, adapter, | ||
| 403 | "module_foo", "chipid", 0, NULL, 0, I2C_ADDRS(0x10)); | ||
| 404 | |||
| 405 | v4l2_i2c_new_subdev_board uses an i2c_board_info struct which is passed | ||
| 406 | to the i2c driver and replaces the irq, platform_data and addr arguments. | ||
| 407 | |||
| 408 | If the subdev supports the s_config core ops, then that op is called with | ||
| 409 | the irq and platform_data arguments after the subdev was setup. The older | ||
| 410 | v4l2_i2c_new_(probed_)subdev functions will call s_config as well, but with | ||
| 411 | irq set to 0 and platform_data set to NULL. | ||
| 412 | |||
| 413 | Note that in the next kernel release the functions v4l2_i2c_new_subdev, | ||
| 414 | v4l2_i2c_new_probed_subdev and v4l2_i2c_new_probed_subdev_addr will all be | ||
| 415 | replaced by a single v4l2_i2c_new_subdev that is identical to | ||
| 416 | v4l2_i2c_new_subdev_cfg but without the irq and platform_data arguments. | ||
| 393 | 417 | ||
| 394 | struct video_device | 418 | struct video_device |
| 395 | ------------------- | 419 | ------------------- |
| @@ -19,30 +19,41 @@ Last reviewed: 06/02/2009 · 18 unmodified lines | |||
| 19 | not be updated in a timely fashion and a hardware system reset (also known as | 19 | not be updated in a timely fashion and a hardware system reset (also known as |
| 20 | an Automatic Server Recovery (ASR)) event will occur. | 20 | an Automatic Server Recovery (ASR)) event will occur. |
| 21 | 21 | ||
| 22 | The hpwdt driver also has three (3) module parameters. They are the following: | 22 | The hpwdt driver also has four (4) module parameters. They are the following: |
| 23 | 23 | ||
| 24 | soft_margin - allows the user to set the watchdog timer value | 24 | soft_margin - allows the user to set the watchdog timer value |
| 25 | allow_kdump - allows the user to save off a kernel dump image after an NMI | 25 | allow_kdump - allows the user to save off a kernel dump image after an NMI |
| 26 | nowayout - basic watchdog parameter that does not allow the timer to | 26 | nowayout - basic watchdog parameter that does not allow the timer to |
| 27 | be restarted or an impending ASR to be escaped. | 27 | be restarted or an impending ASR to be escaped. |
| 28 | priority - determines whether or not the hpwdt driver is first on the | ||
| 29 | die_notify list to handle NMIs or last. The default value | ||
| 30 | for this module parameter is 0 or LAST. If the user wants to | ||
| 31 | enable NMI sourcing then reload the hpwdt driver with | ||
| 32 | priority=1 (and boot with nmi_watchdog=0). | ||
| 28 | 33 | ||
| 29 | NOTE: More information about watchdog drivers in general, including the ioctl | 34 | NOTE: More information about watchdog drivers in general, including the ioctl |
| 30 | interface to /dev/watchdog can be found in | 35 | interface to /dev/watchdog can be found in |
| 31 | Documentation/watchdog/watchdog-api.txt and Documentation/IPMI.txt. | 36 | Documentation/watchdog/watchdog-api.txt and Documentation/IPMI.txt. |
| 32 | 37 | ||
| 33 | The NMI sourcing capability is disabled when the driver discovers that the | 38 | The priority parameter was introduced due to other kernel software that relied |
| 34 | nmi_watchdog is turned on (nmi_watchdog = 1). This is due to the inability to | 39 | on handling NMIs (like oprofile). Keeping hpwdt's priority at 0 (or LAST) |
| 40 | enables the users of NMIs for non critical events to be work as expected. | ||
| 41 | |||
| 42 | The NMI sourcing capability is disabled by default due to the inability to | ||
| 35 | distinguish between "NMI Watchdog Ticks" and "HW generated NMI events" in the | 43 | distinguish between "NMI Watchdog Ticks" and "HW generated NMI events" in the |
| 36 | Linux kernel. What this means is that the hpwdt nmi handler code is called | 44 | Linux kernel. What this means is that the hpwdt nmi handler code is called |
| 37 | each time the NMI signal fires off. This could amount to several thousands of | 45 | each time the NMI signal fires off. This could amount to several thousands of |
| 38 | NMIs in a matter of seconds. If a user sees the Linux kernel's "dazed and | 46 | NMIs in a matter of seconds. If a user sees the Linux kernel's "dazed and |
| 39 | confused" message in the logs or if the system gets into a hung state, then | 47 | confused" message in the logs or if the system gets into a hung state, then |
| 40 | the user should reboot with nmi_watchdog=0. | 48 | the hpwdt driver can be reloaded with the "priority" module parameter set |
| 49 | (priority=1). | ||
| 41 | 50 | ||
| 42 | 1. If the kernel has not been booted with nmi_watchdog turned off then | 51 | 1. If the kernel has not been booted with nmi_watchdog turned off then |
| 43 | edit /boot/grub/menu.lst and place the nmi_watchdog=0 at the end of the | 52 | edit /boot/grub/menu.lst and place the nmi_watchdog=0 at the end of the |
| 44 | currently booting kernel line. | 53 | currently booting kernel line. |
| 45 | 2. reboot the sever | 54 | 2. reboot the sever |
| 55 | 3. Once the system comes up perform a rmmod hpwdt | ||
| 56 | 4. insmod /lib/modules/`uname -r`/kernel/drivers/char/watchdog/hpwdt.ko priority=1 | ||
| 46 | 57 | ||
| 47 | Now, the hpwdt can successfully receive and source the NMI and provide a log | 58 | Now, the hpwdt can successfully receive and source the NMI and provide a log |
| 48 | message that details the reason for the NMI (as determined by the HP BIOS). | 59 | message that details the reason for the NMI (as determined by the HP BIOS). |
| @@ -230,6 +230,13 @@ L: linux-acenic@sunsite.dk · 229 unmodified lines | |||
| 230 | S: Maintained | 230 | S: Maintained |
| 231 | F: drivers/net/acenic* | 231 | F: drivers/net/acenic* |
| 232 | 232 | ||
| 233 | ACER ASPIRE ONE TEMPERATURE AND FAN DRIVER | ||
| 234 | P: Peter Feuerer | ||
| 235 | M: peter@piie.net | ||
| 236 | W: http://piie.net/?section=acerhdf | ||
| 237 | S: Maintained | ||
| 238 | F: drivers/platform/x86/acerhdf.c | ||
| 239 | |||
| 233 | ACER WMI LAPTOP EXTRAS | 240 | ACER WMI LAPTOP EXTRAS |
| 234 | P: Carlos Corbacho | 241 | P: Carlos Corbacho |
| 235 | M: carlos@strangeworlds.co.uk | 242 | M: carlos@strangeworlds.co.uk |
| @@ -653,6 +660,8 @@ M: laforge@openezx.org · 417 unmodified lines | |||
| 653 | L: openezx-devel@lists.openezx.org (subscribers-only) | 660 | L: openezx-devel@lists.openezx.org (subscribers-only) |
| 654 | W: http://www.openezx.org/ | 661 | W: http://www.openezx.org/ |
| 655 | S: Maintained | 662 | S: Maintained |
| 663 | T: topgit git://git.openezx.org/openezx.git | ||
| 664 | F: arch/arm/mach-pxa/ezx.c | ||
| 656 | 665 | ||
| 657 | ARM/FARADAY FA526 PORT | 666 | ARM/FARADAY FA526 PORT |
| 658 | P: Paulius Zaleckas | 667 | P: Paulius Zaleckas |
| @@ -774,11 +783,25 @@ P: Philipp Zabel · 115 unmodified lines | |||
| 774 | M: philipp.zabel@gmail.com | 783 | M: philipp.zabel@gmail.com |
| 775 | S: Maintained | 784 | S: Maintained |
| 776 | 785 | ||
| 786 | ARM/MIOA701 MACHINE SUPPORT | ||
| 787 | P: Robert Jarzmik | ||
| 788 | M: robert.jarzmik@free.fr | ||
| 789 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 790 | F: arch/arm/mach-pxa/mioa701.c | ||
| 791 | S: Maintained | ||
| 792 | |||
| 777 | ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT | 793 | ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT |
| 778 | P: Michael Petchkovsky | 794 | P: Michael Petchkovsky |
| 779 | M: mkpetch@internode.on.net | 795 | M: mkpetch@internode.on.net |
| 780 | S: Maintained | 796 | S: Maintained |
| 781 | 797 | ||
| 798 | ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT | ||
| 799 | P: Nelson Castillo | ||
| 800 | M: arhuaco@freaks-unidos.net | ||
| 801 | L: openmoko-kernel@lists.openmoko.org (subscribers-only) | ||
| 802 | W: http://wiki.openmoko.org/wiki/Neo_FreeRunner | ||
| 803 | S: Supported | ||
| 804 | |||
| 782 | ARM/TOSA MACHINE SUPPORT | 805 | ARM/TOSA MACHINE SUPPORT |
| 783 | P: Dmitry Eremin-Solenikov | 806 | P: Dmitry Eremin-Solenikov |
| 784 | M: dbaryshkov@gmail.com | 807 | M: dbaryshkov@gmail.com |
| @@ -792,6 +815,12 @@ M: marek.vasut@gmail.com · 7 unmodified lines | |||
| 792 | W: http://hackndev.com | 815 | W: http://hackndev.com |
| 793 | S: Maintained | 816 | S: Maintained |
| 794 | 817 | ||
| 818 | ARM/PALM TREO 680 SUPPORT | ||
| 819 | P: Tomas Cech | ||
| 820 | M: sleep_walker@suse.cz | ||
| 821 | W: http://hackndev.com | ||
| 822 | S: Maintained | ||
| 823 | |||
| 795 | ARM/PALMZ72 SUPPORT | 824 | ARM/PALMZ72 SUPPORT |
| 796 | P: Sergey Lapin | 825 | P: Sergey Lapin |
| 797 | M: slapin@ossfans.org | 826 | M: slapin@ossfans.org |
| @@ -838,12 +867,22 @@ M: alex@shark-linux.de · 40 unmodified lines | |||
| 838 | W: http://www.shark-linux.de/shark.html | 867 | W: http://www.shark-linux.de/shark.html |
| 839 | S: Maintained | 868 | S: Maintained |
| 840 | 869 | ||
| 870 | ARM/SAMSUNG ARM ARCHITECTURES | ||
| 871 | P: Ben Dooks | ||
| 872 | M: ben-linux@fluff.org | ||
| 873 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 874 | W: http://www.fluff.org/ben/linux/ | ||
| 875 | S: Maintained | ||
| 876 | F: arch/arm/plat-s3c/ | ||
| 877 | F: arch/arm/plat-s3c24xx/ | ||
| 878 | |||
| 841 | ARM/S3C2410 ARM ARCHITECTURE | 879 | ARM/S3C2410 ARM ARCHITECTURE |
| 842 | P: Ben Dooks | 880 | P: Ben Dooks |
| 843 | M: ben-linux@fluff.org | 881 | M: ben-linux@fluff.org |
| 844 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | 882 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) |
| 845 | W: http://www.fluff.org/ben/linux/ | 883 | W: http://www.fluff.org/ben/linux/ |
| 846 | S: Maintained | 884 | S: Maintained |
| 885 | F: arch/arm/mach-s3c2410/ | ||
| 847 | 886 | ||
| 848 | ARM/S3C2440 ARM ARCHITECTURE | 887 | ARM/S3C2440 ARM ARCHITECTURE |
| 849 | P: Ben Dooks | 888 | P: Ben Dooks |
| @@ -851,6 +890,39 @@ M: ben-linux@fluff.org · 1 unmodified line | |||
| 851 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | 890 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) |
| 852 | W: http://www.fluff.org/ben/linux/ | 891 | W: http://www.fluff.org/ben/linux/ |
| 853 | S: Maintained | 892 | S: Maintained |
| 893 | F: arch/arm/mach-s3c2440/ | ||
| 894 | |||
| 895 | ARM/S3C2442 ARM ARCHITECTURE | ||
| 896 | P: Ben Dooks | ||
| 897 | M: ben-linux@fluff.org | ||
| 898 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 899 | W: http://www.fluff.org/ben/linux/ | ||
| 900 | S: Maintained | ||
| 901 | F: arch/arm/mach-s3c2442/ | ||
| 902 | |||
| 903 | ARM/S3C2443 ARM ARCHITECTURE | ||
| 904 | P: Ben Dooks | ||
| 905 | M: ben-linux@fluff.org | ||
| 906 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 907 | W: http://www.fluff.org/ben/linux/ | ||
| 908 | S: Maintained | ||
| 909 | F: arch/arm/mach-s3c2443/ | ||
| 910 | |||
| 911 | ARM/S3C6400 ARM ARCHITECTURE | ||
| 912 | P: Ben Dooks | ||
| 913 | M: ben-linux@fluff.org | ||
| 914 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 915 | W: http://www.fluff.org/ben/linux/ | ||
| 916 | S: Maintained | ||
| 917 | F: arch/arm/mach-s3c6400/ | ||
| 918 | |||
| 919 | ARM/S3C6410 ARM ARCHITECTURE | ||
| 920 | P: Ben Dooks | ||
| 921 | M: ben-linux@fluff.org | ||
| 922 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 923 | W: http://www.fluff.org/ben/linux/ | ||
| 924 | S: Maintained | ||
| 925 | F: arch/arm/mach-s3c6410/ | ||
| 854 | 926 | ||
| 855 | ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT | 927 | ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT |
| 856 | P: Lennert Buytenhek | 928 | P: Lennert Buytenhek |
| @@ -891,8 +963,7 @@ M: corentincj@iksaif.net · 34 unmodified lines | |||
| 891 | P: Karol Kozimor | 963 | P: Karol Kozimor |
| 892 | M: sziwan@users.sourceforge.net | 964 | M: sziwan@users.sourceforge.net |
| 893 | L: acpi4asus-user@lists.sourceforge.net | 965 | L: acpi4asus-user@lists.sourceforge.net |
| 894 | W: http://sourceforge.net/projects/acpi4asus | 966 | W: http://acpi4asus.sf.net |
| 895 | W: http://xf.iksaif.net/acpi4asus | ||
| 896 | S: Maintained | 967 | S: Maintained |
| 897 | F: arch/x86/kernel/acpi/boot.c | 968 | F: arch/x86/kernel/acpi/boot.c |
| 898 | F: drivers/platform/x86/asus_acpi.c | 969 | F: drivers/platform/x86/asus_acpi.c |
| @@ -908,8 +979,7 @@ ASUS LAPTOP EXTRAS DRIVER · 9 unmodified lines | |||
| 908 | P: Corentin Chary | 979 | P: Corentin Chary |
| 909 | M: corentincj@iksaif.net | 980 | M: corentincj@iksaif.net |
| 910 | L: acpi4asus-user@lists.sourceforge.net | 981 | L: acpi4asus-user@lists.sourceforge.net |
| 911 | W: http://sourceforge.net/projects/acpi4asus | 982 | W: http://acpi4asus.sf.net |
| 912 | W: http://xf.iksaif.net/acpi4asus | ||
| 913 | S: Maintained | 983 | S: Maintained |
| 914 | F: drivers/platform/x86/asus-laptop.c | 984 | F: drivers/platform/x86/asus-laptop.c |
| 915 | 985 | ||
| @@ -1614,7 +1684,7 @@ P: Mikael Starvik · 698 unmodified lines | |||
| 1614 | M: starvik@axis.com | 1684 | M: starvik@axis.com |
| 1615 | P: Jesper Nilsson | 1685 | P: Jesper Nilsson |
| 1616 | M: jesper.nilsson@axis.com | 1686 | M: jesper.nilsson@axis.com |
| 1617 | L: dev-etrax@axis.com | 1687 | L: linux-cris-kernel@axis.com |
| 1618 | W: http://developer.axis.com | 1688 | W: http://developer.axis.com |
| 1619 | S: Maintained | 1689 | S: Maintained |
| 1620 | F: arch/cris/ | 1690 | F: arch/cris/ |
| @@ -2060,9 +2130,9 @@ F: drivers/edac/i5400_edac.c · 439 unmodified lines | |||
| 2060 | 2130 | ||
| 2061 | EDAC-I82975X | 2131 | EDAC-I82975X |
| 2062 | P: Ranganathan Desikan | 2132 | P: Ranganathan Desikan |
| 2063 | M: rdesikan@jetzbroadband.com | 2133 | M: ravi@jetztechnologies.com |
| 2064 | P: Arvind R. | 2134 | P: Arvind R. |
| 2065 | M: arvind@acarlab.com | 2135 | M: arvind@jetztechnologies.com |
| 2066 | L: bluesmoke-devel@lists.sourceforge.net (moderated for non-subscribers) | 2136 | L: bluesmoke-devel@lists.sourceforge.net (moderated for non-subscribers) |
| 2067 | W: bluesmoke.sourceforge.net | 2137 | W: bluesmoke.sourceforge.net |
| 2068 | S: Maintained | 2138 | S: Maintained |
| @@ -2088,7 +2158,7 @@ EEEPC LAPTOP EXTRAS DRIVER · 19 unmodified lines | |||
| 2088 | P: Corentin Chary | 2158 | P: Corentin Chary |
| 2089 | M: corentincj@iksaif.net | 2159 | M: corentincj@iksaif.net |
| 2090 | L: acpi4asus-user@lists.sourceforge.net | 2160 | L: acpi4asus-user@lists.sourceforge.net |
| 2091 | W: http://sourceforge.net/projects/acpi4asus | 2161 | W: http://acpi4asus.sf.net |
| 2092 | S: Maintained | 2162 | S: Maintained |
| 2093 | F: drivers/platform/x86/eeepc-laptop.c | 2163 | F: drivers/platform/x86/eeepc-laptop.c |
| 2094 | 2164 | ||
| @@ -2460,6 +2530,14 @@ F: drivers/net/wan/pc300too.c · 365 unmodified lines | |||
| 2460 | F: drivers/net/wan/pci200syn.c | 2530 | F: drivers/net/wan/pci200syn.c |
| 2461 | F: drivers/net/wan/wanxl* | 2531 | F: drivers/net/wan/wanxl* |
| 2462 | 2532 | ||
| 2533 | GENERIC INCLUDE/ASM HEADER FILES | ||
| 2534 | P: Arnd Bergmann | ||
| 2535 | M: arnd@arndb.de | ||
| 2536 | L: linux-arch@vger.kernel.org | ||
| 2537 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic.git | ||
| 2538 | S: Maintained | ||
| 2539 | F: include/asm-generic | ||
| 2540 | |||
| 2463 | GFS2 FILE SYSTEM | 2541 | GFS2 FILE SYSTEM |
| 2464 | P: Steven Whitehouse | 2542 | P: Steven Whitehouse |
| 2465 | M: swhiteho@redhat.com | 2543 | M: swhiteho@redhat.com |
| @@ -2773,7 +2851,9 @@ S: Maintained · 307 unmodified lines | |||
| 2773 | 2851 | ||
| 2774 | IA64 (Itanium) PLATFORM | 2852 | IA64 (Itanium) PLATFORM |
| 2775 | P: Tony Luck | 2853 | P: Tony Luck |
| 2854 | P: Fenghua Yu | ||
| 2776 | M: tony.luck@intel.com | 2855 | M: tony.luck@intel.com |
| 2856 | M: fenghua.yu@intel.com | ||
| 2777 | L: linux-ia64@vger.kernel.org | 2857 | L: linux-ia64@vger.kernel.org |
| 2778 | W: http://www.ia64-linux.org/ | 2858 | W: http://www.ia64-linux.org/ |
| 2779 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6.git | 2859 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6.git |
| @@ -2802,10 +2882,10 @@ S: Supported · 22 unmodified lines | |||
| 2802 | F: drivers/scsi/ips.* | 2882 | F: drivers/scsi/ips.* |
| 2803 | 2883 | ||
| 2804 | IDE SUBSYSTEM | 2884 | IDE SUBSYSTEM |
| 2805 | P: Bartlomiej Zolnierkiewicz | 2885 | P: David S. Miller |
| 2806 | M: bzolnier@gmail.com | 2886 | M: davem@davemloft.net |
| 2807 | L: linux-ide@vger.kernel.org | 2887 | L: linux-ide@vger.kernel.org |
| 2808 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6.git | 2888 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-2.6.git |
| 2809 | S: Maintained | 2889 | S: Maintained |
| 2810 | F: Documentation/ide/ | 2890 | F: Documentation/ide/ |
| 2811 | F: drivers/ide/ | 2891 | F: drivers/ide/ |
| @@ -2851,9 +2931,9 @@ P: Dmitry Eremin-Solenikov · 39 unmodified lines | |||
| 2851 | M: dbaryshkov@gmail.com | 2931 | M: dbaryshkov@gmail.com |
| 2852 | P: Sergey Lapin | 2932 | P: Sergey Lapin |
| 2853 | M: slapin@ossfans.org | 2933 | M: slapin@ossfans.org |
| 2854 | L: linux-zigbee-devel@lists.sourceforge.net | 2934 | L: linux-zigbee-devel@lists.sourceforge.net (moderated for non-subscribers) |
| 2855 | W: http://apps.sourceforge.net/trac/linux-zigbee | 2935 | W: http://apps.sourceforge.net/trac/linux-zigbee |
| 2856 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/lumag/lowpan.git | 2936 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/lowpan/lowpan.git |
| 2857 | S: Maintained | 2937 | S: Maintained |
| 2858 | F: net/ieee802154/ | 2938 | F: net/ieee802154/ |
| 2859 | F: drivers/ieee802154/ | 2939 | F: drivers/ieee802154/ |
| @@ -3230,7 +3310,6 @@ W: http://www.linux-mtd.infradead.org/doc/jffs2.html · 370 unmodified lines | |||
| 3230 | S: Maintained | 3310 | S: Maintained |
| 3231 | F: fs/jffs2/ | 3311 | F: fs/jffs2/ |
| 3232 | F: include/linux/jffs2.h | 3312 | F: include/linux/jffs2.h |
| 3233 | F: include/mtd/jffs2-user.h | ||
| 3234 | 3313 | ||
| 3235 | JOURNALLING LAYER FOR BLOCK DEVICES (JBD) | 3314 | JOURNALLING LAYER FOR BLOCK DEVICES (JBD) |
| 3236 | P: Stephen Tweedie | 3315 | P: Stephen Tweedie |
| @@ -5499,8 +5578,8 @@ F: drivers/staging/ · 2262 unmodified lines | |||
| 5499 | 5578 | ||
| 5500 | STARFIRE/DURALAN NETWORK DRIVER | 5579 | STARFIRE/DURALAN NETWORK DRIVER |
| 5501 | P: Ion Badulescu | 5580 | P: Ion Badulescu |
| 5502 | M: ionut@cs.columbia.edu | 5581 | M: ionut@badula.org |
| 5503 | S: Maintained | 5582 | S: Odd Fixes |
| 5504 | F: drivers/net/starfire* | 5583 | F: drivers/net/starfire* |
| 5505 | 5584 | ||
| 5506 | STARMODE RADIO IP (STRIP) PROTOCOL DRIVER | 5585 | STARMODE RADIO IP (STRIP) PROTOCOL DRIVER |
| @@ -5634,6 +5713,13 @@ F: drivers/misc/tifm* · 127 unmodified lines | |||
| 5634 | F: drivers/mmc/host/tifm_sd.c | 5713 | F: drivers/mmc/host/tifm_sd.c |
| 5635 | F: include/linux/tifm.h | 5714 | F: include/linux/tifm.h |
| 5636 | 5715 | ||
| 5716 | TI TWL4030 SERIES SOC CODEC DRIVER | ||
| 5717 | P: Peter Ujfalusi | ||
| 5718 | M: peter.ujfalusi@nokia.com | ||
| 5719 | L: alsa-devel@alsa-project.org (moderated for non-subscribers) | ||
| 5720 | S: Maintained | ||
| 5721 | F: sound/soc/codecs/twl4030* | ||
| 5722 | |||
| 5637 | TIPC NETWORK LAYER | 5723 | TIPC NETWORK LAYER |
| 5638 | P: Per Liden | 5724 | P: Per Liden |
| 5639 | M: per.liden@ericsson.com | 5725 | M: per.liden@ericsson.com |
| @@ -1,7 +1,7 @@ | |||
| 1 | VERSION = 2 | 1 | VERSION = 2 |
| 2 | PATCHLEVEL = 6 | 2 | PATCHLEVEL = 6 |
| 3 | SUBLEVEL = 30 | 3 | SUBLEVEL = 31 |
| 4 | EXTRAVERSION = | 4 | EXTRAVERSION = -rc1 |
| 5 | NAME = Man-Eating Seals of Antiquity | 5 | NAME = Man-Eating Seals of Antiquity |
| 6 | 6 | ||
| 7 | # *DOCUMENTATION* | 7 | # *DOCUMENTATION* |
| @@ -1241,7 +1241,7 @@ endmenu · 1240 unmodified lines | |||
| 1241 | 1241 | ||
| 1242 | menu "CPU Power Management" | 1242 | menu "CPU Power Management" |
| 1243 | 1243 | ||
| 1244 | if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA) | 1244 | if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX) |
| 1245 | 1245 | ||
| 1246 | source "drivers/cpufreq/Kconfig" | 1246 | source "drivers/cpufreq/Kconfig" |
| 1247 | 1247 | ||
| @@ -1272,6 +1272,10 @@ config CPU_FREQ_PXA · 24 unmodified lines | |||
| 1272 | default y | 1272 | default y |
| 1273 | select CPU_FREQ_DEFAULT_GOV_USERSPACE | 1273 | select CPU_FREQ_DEFAULT_GOV_USERSPACE |
| 1274 | 1274 | ||
| 1275 | config CPU_FREQ_S3C64XX | ||
| 1276 | bool "CPUfreq support for Samsung S3C64XX CPUs" | ||
| 1277 | depends on CPU_FREQ && CPU_S3C6410 | ||
| 1278 | |||
| 1275 | endif | 1279 | endif |
| 1276 | 1280 | ||
| 1277 | source "drivers/cpuidle/Kconfig" | 1281 | source "drivers/cpuidle/Kconfig" |
| @@ -99,14 +99,6 @@ config DEBUG_CLPS711X_UART2 · 98 unmodified lines | |||
| 99 | output to the second serial port on these devices. Saying N will | 99 | output to the second serial port on these devices. Saying N will |
| 100 | cause the debug messages to appear on the first serial port. | 100 | cause the debug messages to appear on the first serial port. |
| 101 | 101 | ||
| 102 | config DEBUG_S3C_PORT | ||
| 103 | depends on DEBUG_LL && PLAT_S3C | ||
| 104 | bool "Kernel low-level debugging messages via S3C UART" | ||
| 105 | help | ||
| 106 | Say Y here if you want debug print routines to go to one of the | ||
| 107 | S3C internal UARTs. The chosen UART must have been configured | ||
| 108 | before it is used. | ||
| 109 | |||
| 110 | config DEBUG_S3C_UART | 102 | config DEBUG_S3C_UART |
| 111 | depends on PLAT_S3C | 103 | depends on PLAT_S3C |
| 112 | int "S3C UART to use for low-level debug" | 104 | int "S3C UART to use for low-level debug" |
| @@ -674,6 +674,15 @@ proc_types: · 673 unmodified lines | |||
| 674 | b __armv4_mmu_cache_off | 674 | b __armv4_mmu_cache_off |
| 675 | b __armv5tej_mmu_cache_flush | 675 | b __armv5tej_mmu_cache_flush |
| 676 | 676 | ||
| 677 | #ifdef CONFIG_CPU_FEROCEON_OLD_ID | ||
| 678 | /* this conflicts with the standard ARMv5TE entry */ | ||
| 679 | .long 0x41009260 @ Old Feroceon | ||
| 680 | .long 0xff00fff0 | ||
| 681 | b __armv4_mmu_cache_on | ||
| 682 | b __armv4_mmu_cache_off | ||
| 683 | b __armv5tej_mmu_cache_flush | ||
| 684 | #endif | ||
| 685 | |||
| 677 | .word 0x66015261 @ FA526 | 686 | .word 0x66015261 @ FA526 |
| 678 | .word 0xff01fff1 | 687 | .word 0xff01fff1 |
| 679 | b __fa526_cache_on | 688 | b __fa526_cache_on |
| @@ -117,7 +117,7 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val) · 116 unmodified lines | |||
| 117 | u32 val; | 117 | u32 val; |
| 118 | 118 | ||
| 119 | spin_lock(&irq_controller_lock); | 119 | spin_lock(&irq_controller_lock); |
| 120 | irq_desc[irq].cpu = cpu; | 120 | irq_desc[irq].node = cpu; |
| 121 | val = readl(reg) & ~(0xff << shift); | 121 | val = readl(reg) & ~(0xff << shift); |
| 122 | val |= 1 << (cpu + shift); | 122 | val |= 1 << (cpu + shift); |
| 123 | writel(val, reg); | 123 | writel(val, reg); |
| @@ -229,14 +229,18 @@ static int vic_set_wake(unsigned int irq, unsigned int on) · 228 unmodified lines | |||
| 229 | { | 229 | { |
| 230 | struct vic_device *v = vic_from_irq(irq); | 230 | struct vic_device *v = vic_from_irq(irq); |
| 231 | unsigned int off = irq & 31; | 231 | unsigned int off = irq & 31; |
| 232 | u32 bit = 1 << off; | ||
| 232 | 233 | ||
| 233 | if (!v) | 234 | if (!v) |
| 234 | return -EINVAL; | 235 | return -EINVAL; |
| 235 | 236 | ||
| 237 | if (!(bit & v->resume_sources)) | ||
| 238 | return -EINVAL; | ||
| 239 | |||
| 236 | if (on) | 240 | if (on) |
| 237 | v->resume_irqs |= 1 << off; | 241 | v->resume_irqs |= bit; |
| 238 | else | 242 | else |
| 239 | v->resume_irqs &= ~(1 << off); | 243 | v->resume_irqs &= ~bit; |
| 240 | 244 | ||
| 241 | return 0; | 245 | return 0; |
| 242 | } | 246 | } |
| @@ -0,0 +1,2097 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.30-rc6 | ||
| 4 | # Wed May 20 12:29:51 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_HAVE_PWM=y | ||
| 8 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 9 | CONFIG_GENERIC_GPIO=y | ||
| 10 | # CONFIG_GENERIC_TIME is not set | ||
| 11 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 12 | CONFIG_MMU=y | ||
| 13 | CONFIG_NO_IOPORT=y | ||
| 14 | CONFIG_GENERIC_HARDIRQS=y | ||
| 15 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 16 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 17 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 18 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 19 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 20 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 21 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 23 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 24 | CONFIG_GENERIC_HWEIGHT=y | ||
| 25 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 29 | |||
| 30 | # | ||
| 31 | # General setup | ||
| 32 | # | ||
| 33 | CONFIG_EXPERIMENTAL=y | ||
| 34 | CONFIG_BROKEN_ON_SMP=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | CONFIG_SYSVIPC=y | ||
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 41 | CONFIG_POSIX_MQUEUE=y | ||
| 42 | CONFIG_POSIX_MQUEUE_SYSCTL=y | ||
| 43 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 44 | # CONFIG_TASKSTATS is not set | ||
| 45 | # CONFIG_AUDIT is not set | ||
| 46 | |||
| 47 | # | ||
| 48 | # RCU Subsystem | ||
| 49 | # | ||
| 50 | CONFIG_CLASSIC_RCU=y | ||
| 51 | # CONFIG_TREE_RCU is not set | ||
| 52 | # CONFIG_PREEMPT_RCU is not set | ||
| 53 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 54 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 55 | # CONFIG_IKCONFIG is not set | ||
| 56 | CONFIG_LOG_BUF_SHIFT=17 | ||
| 57 | # CONFIG_GROUP_SCHED is not set | ||
| 58 | # CONFIG_CGROUPS is not set | ||
| 59 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 60 | CONFIG_RELAY=y | ||
| 61 | CONFIG_NAMESPACES=y | ||
| 62 | CONFIG_UTS_NS=y | ||
| 63 | CONFIG_IPC_NS=y | ||
| 64 | # CONFIG_USER_NS is not set | ||
| 65 | # CONFIG_PID_NS is not set | ||
| 66 | # CONFIG_NET_NS is not set | ||
| 67 | CONFIG_BLK_DEV_INITRD=y | ||
| 68 | CONFIG_INITRAMFS_SOURCE="" | ||
| 69 | CONFIG_RD_GZIP=y | ||
| 70 | CONFIG_RD_BZIP2=y | ||
| 71 | CONFIG_RD_LZMA=y | ||
| 72 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 73 | CONFIG_SYSCTL=y | ||
| 74 | CONFIG_ANON_INODES=y | ||
| 75 | # CONFIG_EMBEDDED is not set | ||
| 76 | CONFIG_UID16=y | ||
| 77 | CONFIG_SYSCTL_SYSCALL=y | ||
| 78 | CONFIG_KALLSYMS=y | ||
| 79 | # CONFIG_KALLSYMS_ALL is not set | ||
| 80 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 81 | CONFIG_STRIP_ASM_SYMS=y | ||
| 82 | CONFIG_HOTPLUG=y | ||
| 83 | CONFIG_PRINTK=y | ||
| 84 | CONFIG_BUG=y | ||
| 85 | CONFIG_ELF_CORE=y | ||
| 86 | CONFIG_BASE_FULL=y | ||
| 87 | CONFIG_FUTEX=y | ||
| 88 | CONFIG_EPOLL=y | ||
| 89 | CONFIG_SIGNALFD=y | ||
| 90 | CONFIG_TIMERFD=y | ||
| 91 | CONFIG_EVENTFD=y | ||
| 92 | CONFIG_SHMEM=y | ||
| 93 | CONFIG_AIO=y | ||
| 94 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 95 | CONFIG_SLUB_DEBUG=y | ||
| 96 | # CONFIG_COMPAT_BRK is not set | ||
| 97 | # CONFIG_SLAB is not set | ||
| 98 | CONFIG_SLUB=y | ||
| 99 | # CONFIG_SLOB is not set | ||
| 100 | # CONFIG_PROFILING is not set | ||
| 101 | # CONFIG_MARKERS is not set | ||
| 102 | CONFIG_HAVE_OPROFILE=y | ||
| 103 | # CONFIG_KPROBES is not set | ||
| 104 | CONFIG_HAVE_KPROBES=y | ||
| 105 | CONFIG_HAVE_KRETPROBES=y | ||
| 106 | CONFIG_HAVE_CLK=y | ||
| 107 | # CONFIG_SLOW_WORK is not set | ||
| 108 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 109 | CONFIG_SLABINFO=y | ||
| 110 | CONFIG_RT_MUTEXES=y | ||
| 111 | CONFIG_BASE_SMALL=0 | ||
| 112 | CONFIG_MODULES=y | ||
| 113 | CONFIG_MODULE_FORCE_LOAD=y | ||
| 114 | CONFIG_MODULE_UNLOAD=y | ||
| 115 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 116 | # CONFIG_MODVERSIONS is not set | ||
| 117 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 118 | CONFIG_BLOCK=y | ||
| 119 | CONFIG_LBD=y | ||
| 120 | # CONFIG_BLK_DEV_BSG is not set | ||
| 121 | CONFIG_BLK_DEV_INTEGRITY=y | ||
| 122 | |||
| 123 | # | ||
| 124 | # IO Schedulers | ||
| 125 | # | ||
| 126 | CONFIG_IOSCHED_NOOP=y | ||
| 127 | CONFIG_IOSCHED_AS=y | ||
| 128 | CONFIG_IOSCHED_DEADLINE=y | ||
| 129 | CONFIG_IOSCHED_CFQ=y | ||
| 130 | CONFIG_DEFAULT_AS=y | ||
| 131 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 132 | # CONFIG_DEFAULT_CFQ is not set | ||
| 133 | # CONFIG_DEFAULT_NOOP is not set | ||
| 134 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 135 | CONFIG_FREEZER=y | ||
| 136 | |||
| 137 | # | ||
| 138 | # System Type | ||
| 139 | # | ||
| 140 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 141 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 142 | # CONFIG_ARCH_REALVIEW is not set | ||
| 143 | # CONFIG_ARCH_VERSATILE is not set | ||
| 144 | # CONFIG_ARCH_AT91 is not set | ||
| 145 | # CONFIG_ARCH_CLPS711X is not set | ||
| 146 | # CONFIG_ARCH_EBSA110 is not set | ||
| 147 | # CONFIG_ARCH_EP93XX is not set | ||
| 148 | # CONFIG_ARCH_GEMINI is not set | ||
| 149 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 150 | # CONFIG_ARCH_NETX is not set | ||
| 151 | # CONFIG_ARCH_H720X is not set | ||
| 152 | # CONFIG_ARCH_IMX is not set | ||
| 153 | # CONFIG_ARCH_IOP13XX is not set | ||
| 154 | # CONFIG_ARCH_IOP32X is not set | ||
| 155 | # CONFIG_ARCH_IOP33X is not set | ||
| 156 | # CONFIG_ARCH_IXP23XX is not set | ||
| 157 | # CONFIG_ARCH_IXP2000 is not set | ||
| 158 | # CONFIG_ARCH_IXP4XX is not set | ||
| 159 | # CONFIG_ARCH_L7200 is not set | ||
| 160 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 161 | # CONFIG_ARCH_KS8695 is not set | ||
| 162 | # CONFIG_ARCH_NS9XXX is not set | ||
| 163 | # CONFIG_ARCH_LOKI is not set | ||
| 164 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 165 | # CONFIG_ARCH_MXC is not set | ||
| 166 | # CONFIG_ARCH_ORION5X is not set | ||
| 167 | # CONFIG_ARCH_PNX4008 is not set | ||
| 168 | # CONFIG_ARCH_PXA is not set | ||
| 169 | # CONFIG_ARCH_MMP is not set | ||
| 170 | # CONFIG_ARCH_RPC is not set | ||
| 171 | # CONFIG_ARCH_SA1100 is not set | ||
| 172 | CONFIG_ARCH_S3C2410=y | ||
| 173 | # CONFIG_ARCH_S3C64XX is not set | ||
| 174 | # CONFIG_ARCH_SHARK is not set | ||
| 175 | # CONFIG_ARCH_LH7A40X is not set | ||
| 176 | # CONFIG_ARCH_DAVINCI is not set | ||
| 177 | # CONFIG_ARCH_OMAP is not set | ||
| 178 | # CONFIG_ARCH_MSM is not set | ||
| 179 | # CONFIG_ARCH_W90X900 is not set | ||
| 180 | CONFIG_PLAT_S3C24XX=y | ||
| 181 | CONFIG_S3C2410_CLOCK=y | ||
| 182 | CONFIG_CPU_S3C244X=y | ||
| 183 | CONFIG_S3C24XX_PWM=y | ||
| 184 | CONFIG_S3C24XX_GPIO_EXTRA=0 | ||
| 185 | CONFIG_S3C2410_DMA=y | ||
| 186 | # CONFIG_S3C2410_DMA_DEBUG is not set | ||
| 187 | CONFIG_S3C24XX_ADC=y | ||
| 188 | CONFIG_PLAT_S3C=y | ||
| 189 | CONFIG_CPU_LLSERIAL_S3C2440_ONLY=y | ||
| 190 | CONFIG_CPU_LLSERIAL_S3C2440=y | ||
| 191 | |||
| 192 | # | ||
| 193 | # Boot options | ||
| 194 | # | ||
| 195 | # CONFIG_S3C_BOOT_WATCHDOG is not set | ||
| 196 | # CONFIG_S3C_BOOT_ERROR_RESET is not set | ||
| 197 | CONFIG_S3C_BOOT_UART_FORCE_FIFO=y | ||
| 198 | |||
| 199 | # | ||
| 200 | # Power management | ||
| 201 | # | ||
| 202 | # CONFIG_S3C2410_PM_DEBUG is not set | ||
| 203 | # CONFIG_S3C2410_PM_CHECK is not set | ||
| 204 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 | ||
| 205 | CONFIG_S3C_GPIO_SPACE=0 | ||
| 206 | |||
| 207 | # | ||
| 208 | # S3C2400 Machines | ||
| 209 | # | ||
| 210 | CONFIG_S3C2410_PM=y | ||
| 211 | CONFIG_S3C2410_GPIO=y | ||
| 212 | |||
| 213 | # | ||
| 214 | # S3C2410 Machines | ||
| 215 | # | ||
| 216 | # CONFIG_ARCH_SMDK2410 is not set | ||
| 217 | # CONFIG_ARCH_H1940 is not set | ||
| 218 | # CONFIG_MACH_N30 is not set | ||
| 219 | # CONFIG_ARCH_BAST is not set | ||
| 220 | # CONFIG_MACH_OTOM is not set | ||
| 221 | # CONFIG_MACH_AML_M5900 is not set | ||
| 222 | # CONFIG_MACH_TCT_HAMMER is not set | ||
| 223 | # CONFIG_MACH_VR1000 is not set | ||
| 224 | # CONFIG_MACH_QT2410 is not set | ||
| 225 | |||
| 226 | # | ||
| 227 | # S3C2412 Machines | ||
| 228 | # | ||
| 229 | # CONFIG_MACH_JIVE is not set | ||
| 230 | # CONFIG_MACH_SMDK2413 is not set | ||
| 231 | # CONFIG_MACH_SMDK2412 is not set | ||
| 232 | # CONFIG_MACH_VSTMS is not set | ||
| 233 | CONFIG_CPU_S3C2440=y | ||
| 234 | CONFIG_S3C2440_DMA=y | ||
| 235 | |||
| 236 | # | ||
| 237 | # S3C2440 Machines | ||
| 238 | # | ||
| 239 | # CONFIG_MACH_ANUBIS is not set | ||
| 240 | # CONFIG_MACH_OSIRIS is not set | ||
| 241 | # CONFIG_MACH_RX3715 is not set | ||
| 242 | # CONFIG_ARCH_S3C2440 is not set | ||
| 243 | # CONFIG_MACH_NEXCODER_2440 is not set | ||
| 244 | # CONFIG_MACH_AT2440EVB is not set | ||
| 245 | CONFIG_MACH_MINI2440=y | ||
| 246 | |||
| 247 | # | ||
| 248 | # S3C2442 Machines | ||
| 249 | # | ||
| 250 | |||
| 251 | # | ||
| 252 | # S3C2443 Machines | ||
| 253 | # | ||
| 254 | # CONFIG_MACH_SMDK2443 is not set | ||
| 255 | |||
| 256 | # | ||
| 257 | # Processor Type | ||
| 258 | # | ||
| 259 | CONFIG_CPU_32=y | ||
| 260 | CONFIG_CPU_ARM920T=y | ||
| 261 | CONFIG_CPU_32v4T=y | ||
| 262 | CONFIG_CPU_ABRT_EV4T=y | ||
| 263 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 264 | CONFIG_CPU_CACHE_V4WT=y | ||
| 265 | CONFIG_CPU_CACHE_VIVT=y | ||
| 266 | CONFIG_CPU_COPY_V4WB=y | ||
| 267 | CONFIG_CPU_TLB_V4WBI=y | ||
| 268 | CONFIG_CPU_CP15=y | ||
| 269 | CONFIG_CPU_CP15_MMU=y | ||
| 270 | |||
| 271 | # | ||
| 272 | # Processor Features | ||
| 273 | # | ||
| 274 | CONFIG_ARM_THUMB=y | ||
| 275 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 276 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 277 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 278 | # CONFIG_OUTER_CACHE is not set | ||
| 279 | |||
| 280 | # | ||
| 281 | # Bus support | ||
| 282 | # | ||
| 283 | # CONFIG_PCI_SYSCALL is not set | ||
| 284 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 285 | # CONFIG_PCCARD is not set | ||
| 286 | |||
| 287 | # | ||
| 288 | # Kernel Features | ||
| 289 | # | ||
| 290 | CONFIG_VMSPLIT_3G=y | ||
| 291 | # CONFIG_VMSPLIT_2G is not set | ||
| 292 | # CONFIG_VMSPLIT_1G is not set | ||
| 293 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 294 | # CONFIG_PREEMPT is not set | ||
| 295 | CONFIG_HZ=200 | ||
| 296 | CONFIG_AEABI=y | ||
| 297 | # CONFIG_OABI_COMPAT is not set | ||
| 298 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 299 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 300 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 301 | # CONFIG_HIGHMEM is not set | ||
| 302 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 303 | CONFIG_FLATMEM_MANUAL=y | ||
| 304 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 305 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 306 | CONFIG_FLATMEM=y | ||
| 307 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 308 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 309 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 310 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 311 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 312 | CONFIG_VIRT_TO_BUS=y | ||
| 313 | CONFIG_UNEVICTABLE_LRU=y | ||
| 314 | CONFIG_HAVE_MLOCK=y | ||
| 315 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 316 | CONFIG_ALIGNMENT_TRAP=y | ||
| 317 | |||
| 318 | # | ||
| 319 | # Boot options | ||
| 320 | # | ||
| 321 | CONFIG_ZBOOT_ROM_TEXT=0 | ||
| 322 | CONFIG_ZBOOT_ROM_BSS=0 | ||
| 323 | CONFIG_CMDLINE="" | ||
| 324 | # CONFIG_XIP_KERNEL is not set | ||
| 325 | CONFIG_KEXEC=y | ||
| 326 | CONFIG_ATAGS_PROC=y | ||
| 327 | |||
| 328 | # | ||
| 329 | # CPU Power Management | ||
| 330 | # | ||
| 331 | CONFIG_CPU_IDLE=y | ||
| 332 | CONFIG_CPU_IDLE_GOV_LADDER=y | ||
| 333 | |||
| 334 | # | ||
| 335 | # Floating point emulation | ||
| 336 | # | ||
| 337 | |||
| 338 | # | ||
| 339 | # At least one emulation must be selected | ||
| 340 | # | ||
| 341 | |||
| 342 | # | ||
| 343 | # Userspace binary formats | ||
| 344 | # | ||
| 345 | CONFIG_BINFMT_ELF=y | ||
| 346 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 347 | CONFIG_HAVE_AOUT=y | ||
| 348 | CONFIG_BINFMT_AOUT=m | ||
| 349 | CONFIG_BINFMT_MISC=m | ||
| 350 | |||
| 351 | # | ||
| 352 | # Power management options | ||
| 353 | # | ||
| 354 | CONFIG_PM=y | ||
| 355 | # CONFIG_PM_DEBUG is not set | ||
| 356 | CONFIG_PM_SLEEP=y | ||
| 357 | CONFIG_SUSPEND=y | ||
| 358 | CONFIG_SUSPEND_FREEZER=y | ||
| 359 | CONFIG_APM_EMULATION=y | ||
| 360 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 361 | CONFIG_NET=y | ||
| 362 | |||
| 363 | # | ||
| 364 | # Networking options | ||
| 365 | # | ||
| 366 | CONFIG_PACKET=y | ||
| 367 | CONFIG_PACKET_MMAP=y | ||
| 368 | CONFIG_UNIX=y | ||
| 369 | CONFIG_XFRM=y | ||
| 370 | CONFIG_XFRM_USER=m | ||
| 371 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 372 | # CONFIG_XFRM_MIGRATE is not set | ||
| 373 | # CONFIG_XFRM_STATISTICS is not set | ||
| 374 | CONFIG_NET_KEY=m | ||
| 375 | # CONFIG_NET_KEY_MIGRATE is not set | ||
| 376 | CONFIG_INET=y | ||
| 377 | CONFIG_IP_MULTICAST=y | ||
| 378 | CONFIG_IP_ADVANCED_ROUTER=y | ||
| 379 | CONFIG_ASK_IP_FIB_HASH=y | ||
| 380 | # CONFIG_IP_FIB_TRIE is not set | ||
| 381 | CONFIG_IP_FIB_HASH=y | ||
| 382 | CONFIG_IP_MULTIPLE_TABLES=y | ||
| 383 | CONFIG_IP_ROUTE_MULTIPATH=y | ||
| 384 | CONFIG_IP_ROUTE_VERBOSE=y | ||
| 385 | CONFIG_IP_PNP=y | ||
| 386 | CONFIG_IP_PNP_DHCP=y | ||
| 387 | CONFIG_IP_PNP_BOOTP=y | ||
| 388 | CONFIG_IP_PNP_RARP=y | ||
| 389 | # CONFIG_NET_IPIP is not set | ||
| 390 | # CONFIG_NET_IPGRE is not set | ||
| 391 | CONFIG_IP_MROUTE=y | ||
| 392 | CONFIG_IP_PIMSM_V1=y | ||
| 393 | CONFIG_IP_PIMSM_V2=y | ||
| 394 | # CONFIG_ARPD is not set | ||
| 395 | CONFIG_SYN_COOKIES=y | ||
| 396 | # CONFIG_INET_AH is not set | ||
| 397 | # CONFIG_INET_ESP is not set | ||
| 398 | # CONFIG_INET_IPCOMP is not set | ||
| 399 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 400 | # CONFIG_INET_TUNNEL is not set | ||
| 401 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 402 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 403 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 404 | # CONFIG_INET_LRO is not set | ||
| 405 | CONFIG_INET_DIAG=m | ||
| 406 | CONFIG_INET_TCP_DIAG=m | ||
| 407 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 408 | CONFIG_TCP_CONG_CUBIC=y | ||
| 409 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 410 | # CONFIG_TCP_MD5SIG is not set | ||
| 411 | # CONFIG_IPV6 is not set | ||
| 412 | # CONFIG_NETWORK_SECMARK is not set | ||
| 413 | CONFIG_NETFILTER=y | ||
| 414 | # CONFIG_NETFILTER_DEBUG is not set | ||
| 415 | CONFIG_NETFILTER_ADVANCED=y | ||
| 416 | CONFIG_BRIDGE_NETFILTER=y | ||
| 417 | |||
| 418 | # | ||
| 419 | # Core Netfilter Configuration | ||
| 420 | # | ||
| 421 | # CONFIG_NETFILTER_NETLINK_QUEUE is not set | ||
| 422 | # CONFIG_NETFILTER_NETLINK_LOG is not set | ||
| 423 | # CONFIG_NF_CONNTRACK is not set | ||
| 424 | # CONFIG_NETFILTER_XTABLES is not set | ||
| 425 | # CONFIG_IP_VS is not set | ||
| 426 | |||
| 427 | # | ||
| 428 | # IP: Netfilter Configuration | ||
| 429 | # | ||
| 430 | # CONFIG_NF_DEFRAG_IPV4 is not set | ||
| 431 | # CONFIG_IP_NF_QUEUE is not set | ||
| 432 | # CONFIG_IP_NF_IPTABLES is not set | ||
| 433 | # CONFIG_IP_NF_ARPTABLES is not set | ||
| 434 | # CONFIG_BRIDGE_NF_EBTABLES is not set | ||
| 435 | # CONFIG_IP_DCCP is not set | ||
| 436 | # CONFIG_IP_SCTP is not set | ||
| 437 | # CONFIG_TIPC is not set | ||
| 438 | # CONFIG_ATM is not set | ||
| 439 | CONFIG_STP=m | ||
| 440 | CONFIG_GARP=m | ||
| 441 | CONFIG_BRIDGE=m | ||
| 442 | # CONFIG_NET_DSA is not set | ||
| 443 | CONFIG_VLAN_8021Q=m | ||
| 444 | CONFIG_VLAN_8021Q_GVRP=y | ||
| 445 | # CONFIG_DECNET is not set | ||
| 446 | CONFIG_LLC=m | ||
| 447 | # CONFIG_LLC2 is not set | ||
| 448 | # CONFIG_IPX is not set | ||
| 449 | # CONFIG_ATALK is not set | ||
| 450 | # CONFIG_X25 is not set | ||
| 451 | # CONFIG_LAPB is not set | ||
| 452 | # CONFIG_ECONET is not set | ||
| 453 | # CONFIG_WAN_ROUTER is not set | ||
| 454 | # CONFIG_PHONET is not set | ||
| 455 | # CONFIG_NET_SCHED is not set | ||
| 456 | # CONFIG_DCB is not set | ||
| 457 | |||
| 458 | # | ||
| 459 | # Network testing | ||
| 460 | # | ||
| 461 | CONFIG_NET_PKTGEN=m | ||
| 462 | # CONFIG_HAMRADIO is not set | ||
| 463 | # CONFIG_CAN is not set | ||
| 464 | # CONFIG_IRDA is not set | ||
| 465 | CONFIG_BT=m | ||
| 466 | CONFIG_BT_L2CAP=m | ||
| 467 | CONFIG_BT_SCO=m | ||
| 468 | CONFIG_BT_RFCOMM=m | ||
| 469 | CONFIG_BT_RFCOMM_TTY=y | ||
| 470 | CONFIG_BT_BNEP=m | ||
| 471 | CONFIG_BT_BNEP_MC_FILTER=y | ||
| 472 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
| 473 | CONFIG_BT_HIDP=m | ||
| 474 | |||
| 475 | # | ||
| 476 | # Bluetooth device drivers | ||
| 477 | # | ||
| 478 | CONFIG_BT_HCIBTUSB=m | ||
| 479 | CONFIG_BT_HCIBTSDIO=m | ||
| 480 | CONFIG_BT_HCIUART=m | ||
| 481 | CONFIG_BT_HCIUART_H4=y | ||
| 482 | CONFIG_BT_HCIUART_BCSP=y | ||
| 483 | CONFIG_BT_HCIUART_LL=y | ||
| 484 | CONFIG_BT_HCIBCM203X=m | ||
| 485 | CONFIG_BT_HCIBPA10X=m | ||
| 486 | CONFIG_BT_HCIBFUSB=m | ||
| 487 | CONFIG_BT_HCIVHCI=m | ||
| 488 | # CONFIG_AF_RXRPC is not set | ||
| 489 | CONFIG_FIB_RULES=y | ||
| 490 | CONFIG_WIRELESS=y | ||
| 491 | CONFIG_CFG80211=m | ||
| 492 | CONFIG_CFG80211_REG_DEBUG=y | ||
| 493 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 494 | CONFIG_WIRELESS_EXT=y | ||
| 495 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 496 | CONFIG_LIB80211=m | ||
| 497 | CONFIG_LIB80211_CRYPT_WEP=m | ||
| 498 | CONFIG_LIB80211_CRYPT_CCMP=m | ||
| 499 | CONFIG_LIB80211_CRYPT_TKIP=m | ||
| 500 | # CONFIG_LIB80211_DEBUG is not set | ||
| 501 | CONFIG_MAC80211=m | ||
| 502 | |||
| 503 | # | ||
| 504 | # Rate control algorithm selection | ||
| 505 | # | ||
| 506 | CONFIG_MAC80211_RC_MINSTREL=y | ||
| 507 | # CONFIG_MAC80211_RC_DEFAULT_PID is not set | ||
| 508 | CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y | ||
| 509 | CONFIG_MAC80211_RC_DEFAULT="minstrel" | ||
| 510 | CONFIG_MAC80211_MESH=y | ||
| 511 | CONFIG_MAC80211_LEDS=y | ||
| 512 | # CONFIG_MAC80211_DEBUGFS is not set | ||
| 513 | # CONFIG_MAC80211_DEBUG_MENU is not set | ||
| 514 | # CONFIG_WIMAX is not set | ||
| 515 | # CONFIG_RFKILL is not set | ||
| 516 | # CONFIG_NET_9P is not set | ||
| 517 | |||
| 518 | # | ||
| 519 | # Device Drivers | ||
| 520 | # | ||
| 521 | |||
| 522 | # | ||
| 523 | # Generic Driver Options | ||
| 524 | # | ||
| 525 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 526 | CONFIG_STANDALONE=y | ||
| 527 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 528 | CONFIG_FW_LOADER=y | ||
| 529 | # CONFIG_FIRMWARE_IN_KERNEL is not set | ||
| 530 | CONFIG_EXTRA_FIRMWARE="" | ||
| 531 | # CONFIG_DEBUG_DRIVER is not set | ||
| 532 | # CONFIG_DEBUG_DEVRES is not set | ||
| 533 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 534 | CONFIG_CONNECTOR=m | ||
| 535 | CONFIG_MTD=y | ||
| 536 | # CONFIG_MTD_DEBUG is not set | ||
| 537 | CONFIG_MTD_CONCAT=y | ||
| 538 | CONFIG_MTD_PARTITIONS=y | ||
| 539 | # CONFIG_MTD_TESTS is not set | ||
| 540 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 541 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 542 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 543 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 544 | |||
| 545 | # | ||
| 546 | # User Modules And Translation Layers | ||
| 547 | # | ||
| 548 | CONFIG_MTD_CHAR=y | ||
| 549 | CONFIG_MTD_BLKDEVS=y | ||
| 550 | CONFIG_MTD_BLOCK=y | ||
| 551 | CONFIG_FTL=y | ||
| 552 | CONFIG_NFTL=y | ||
| 553 | CONFIG_NFTL_RW=y | ||
| 554 | CONFIG_INFTL=y | ||
| 555 | CONFIG_RFD_FTL=y | ||
| 556 | # CONFIG_SSFDC is not set | ||
| 557 | # CONFIG_MTD_OOPS is not set | ||
| 558 | |||
| 559 | # | ||
| 560 | # RAM/ROM/Flash chip drivers | ||
| 561 | # | ||
| 562 | CONFIG_MTD_CFI=y | ||
| 563 | CONFIG_MTD_JEDECPROBE=y | ||
| 564 | CONFIG_MTD_GEN_PROBE=y | ||
| 565 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 566 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 567 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 568 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 569 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 570 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 571 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 572 | CONFIG_MTD_CFI_I1=y | ||
| 573 | CONFIG_MTD_CFI_I2=y | ||
| 574 | # CONFIG_MTD_CFI_I4 is not set | ||
| 575 | # CONFIG_MTD_CFI_I8 is not set | ||
| 576 | # CONFIG_MTD_CFI_INTELEXT is not set | ||
| 577 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 578 | CONFIG_MTD_CFI_STAA=y | ||
| 579 | CONFIG_MTD_CFI_UTIL=y | ||
| 580 | CONFIG_MTD_RAM=y | ||
| 581 | CONFIG_MTD_ROM=y | ||
| 582 | # CONFIG_MTD_ABSENT is not set | ||
| 583 | |||
| 584 | # | ||
| 585 | # Mapping drivers for chip access | ||
| 586 | # | ||
| 587 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 588 | # CONFIG_MTD_PHYSMAP is not set | ||
| 589 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 590 | # CONFIG_MTD_IMPA7 is not set | ||
| 591 | # CONFIG_MTD_PLATRAM is not set | ||
| 592 | |||
| 593 | # | ||
| 594 | # Self-contained MTD device drivers | ||
| 595 | # | ||
| 596 | # CONFIG_MTD_DATAFLASH is not set | ||
| 597 | # CONFIG_MTD_M25P80 is not set | ||
| 598 | # CONFIG_MTD_SLRAM is not set | ||
| 599 | # CONFIG_MTD_PHRAM is not set | ||
| 600 | # CONFIG_MTD_MTDRAM is not set | ||
| 601 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 602 | |||
| 603 | # | ||
| 604 | # Disk-On-Chip Device Drivers | ||
| 605 | # | ||
| 606 | # CONFIG_MTD_DOC2000 is not set | ||
| 607 | # CONFIG_MTD_DOC2001 is not set | ||
| 608 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 609 | CONFIG_MTD_NAND=y | ||
| 610 | CONFIG_MTD_NAND_VERIFY_WRITE=y | ||
| 611 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 612 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 613 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 614 | CONFIG_MTD_NAND_IDS=y | ||
| 615 | CONFIG_MTD_NAND_S3C2410=y | ||
| 616 | # CONFIG_MTD_NAND_S3C2410_DEBUG is not set | ||
| 617 | # CONFIG_MTD_NAND_S3C2410_HWECC is not set | ||
| 618 | # CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set | ||
| 619 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 620 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 621 | CONFIG_MTD_NAND_PLATFORM=y | ||
| 622 | # CONFIG_MTD_ALAUDA is not set | ||
| 623 | # CONFIG_MTD_ONENAND is not set | ||
| 624 | |||
| 625 | # | ||
| 626 | # LPDDR flash memory drivers | ||
| 627 | # | ||
| 628 | CONFIG_MTD_LPDDR=y | ||
| 629 | CONFIG_MTD_QINFO_PROBE=y | ||
| 630 | |||
| 631 | # | ||
| 632 | # UBI - Unsorted block images | ||
| 633 | # | ||
| 634 | # CONFIG_MTD_UBI is not set | ||
| 635 | # CONFIG_PARPORT is not set | ||
| 636 | CONFIG_BLK_DEV=y | ||
| 637 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 638 | CONFIG_BLK_DEV_LOOP=m | ||
| 639 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 640 | CONFIG_BLK_DEV_NBD=m | ||
| 641 | # CONFIG_BLK_DEV_UB is not set | ||
| 642 | CONFIG_BLK_DEV_RAM=y | ||
| 643 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 644 | CONFIG_BLK_DEV_RAM_SIZE=65536 | ||
| 645 | # CONFIG_BLK_DEV_XIP is not set | ||
| 646 | CONFIG_CDROM_PKTCDVD=m | ||
| 647 | CONFIG_CDROM_PKTCDVD_BUFFERS=8 | ||
| 648 | # CONFIG_CDROM_PKTCDVD_WCACHE is not set | ||
| 649 | # CONFIG_ATA_OVER_ETH is not set | ||
| 650 | CONFIG_MISC_DEVICES=y | ||
| 651 | # CONFIG_ICS932S401 is not set | ||
| 652 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 653 | # CONFIG_ISL29003 is not set | ||
| 654 | # CONFIG_C2PORT is not set | ||
| 655 | |||
| 656 | # | ||
| 657 | # EEPROM support | ||
| 658 | # | ||
| 659 | CONFIG_EEPROM_AT24=y | ||
| 660 | # CONFIG_EEPROM_AT25 is not set | ||
| 661 | # CONFIG_EEPROM_LEGACY is not set | ||
| 662 | # CONFIG_EEPROM_93CX6 is not set | ||
| 663 | CONFIG_HAVE_IDE=y | ||
| 664 | # CONFIG_IDE is not set | ||
| 665 | |||
| 666 | # | ||
| 667 | # SCSI device support | ||
| 668 | # | ||
| 669 | # CONFIG_RAID_ATTRS is not set | ||
| 670 | CONFIG_SCSI=m | ||
| 671 | CONFIG_SCSI_DMA=y | ||
| 672 | # CONFIG_SCSI_TGT is not set | ||
| 673 | # CONFIG_SCSI_NETLINK is not set | ||
| 674 | # CONFIG_SCSI_PROC_FS is not set | ||
| 675 | |||
| 676 | # | ||
| 677 | # SCSI support type (disk, tape, CD-ROM) | ||
| 678 | # | ||
| 679 | CONFIG_BLK_DEV_SD=m | ||
| 680 | # CONFIG_CHR_DEV_ST is not set | ||
| 681 | # CONFIG_CHR_DEV_OSST is not set | ||
| 682 | # CONFIG_BLK_DEV_SR is not set | ||
| 683 | CONFIG_CHR_DEV_SG=m | ||
| 684 | # CONFIG_CHR_DEV_SCH is not set | ||
| 685 | |||
| 686 | # | ||
| 687 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 688 | # | ||
| 689 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 690 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 691 | # CONFIG_SCSI_LOGGING is not set | ||
| 692 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 693 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 694 | |||
| 695 | # | ||
| 696 | # SCSI Transports | ||
| 697 | # | ||
| 698 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 699 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 700 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 701 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 702 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 703 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 704 | # CONFIG_SCSI_DH is not set | ||
| 705 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 706 | # CONFIG_ATA is not set | ||
| 707 | # CONFIG_MD is not set | ||
| 708 | CONFIG_NETDEVICES=y | ||
| 709 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 710 | # CONFIG_DUMMY is not set | ||
| 711 | # CONFIG_BONDING is not set | ||
| 712 | # CONFIG_MACVLAN is not set | ||
| 713 | # CONFIG_EQUALIZER is not set | ||
| 714 | CONFIG_TUN=m | ||
| 715 | # CONFIG_VETH is not set | ||
| 716 | # CONFIG_PHYLIB is not set | ||
| 717 | CONFIG_NET_ETHERNET=y | ||
| 718 | CONFIG_MII=y | ||
| 719 | # CONFIG_AX88796 is not set | ||
| 720 | # CONFIG_SMC91X is not set | ||
| 721 | CONFIG_DM9000=y | ||
| 722 | CONFIG_DM9000_DEBUGLEVEL=4 | ||
| 723 | # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set | ||
| 724 | # CONFIG_ENC28J60 is not set | ||
| 725 | # CONFIG_ETHOC is not set | ||
| 726 | # CONFIG_SMC911X is not set | ||
| 727 | # CONFIG_SMSC911X is not set | ||
| 728 | # CONFIG_DNET is not set | ||
| 729 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 730 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 731 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 732 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 733 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 734 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 735 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 736 | # CONFIG_B44 is not set | ||
| 737 | # CONFIG_NETDEV_1000 is not set | ||
| 738 | # CONFIG_NETDEV_10000 is not set | ||
| 739 | |||
| 740 | # | ||
| 741 | # Wireless LAN | ||
| 742 | # | ||
| 743 | # CONFIG_WLAN_PRE80211 is not set | ||
| 744 | CONFIG_WLAN_80211=y | ||
| 745 | CONFIG_LIBERTAS=m | ||
| 746 | # CONFIG_LIBERTAS_USB is not set | ||
| 747 | CONFIG_LIBERTAS_SDIO=m | ||
| 748 | # CONFIG_LIBERTAS_SPI is not set | ||
| 749 | # CONFIG_LIBERTAS_DEBUG is not set | ||
| 750 | # CONFIG_LIBERTAS_THINFIRM is not set | ||
| 751 | # CONFIG_AT76C50X_USB is not set | ||
| 752 | # CONFIG_USB_ZD1201 is not set | ||
| 753 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 754 | # CONFIG_RTL8187 is not set | ||
| 755 | # CONFIG_MAC80211_HWSIM is not set | ||
| 756 | # CONFIG_P54_COMMON is not set | ||
| 757 | # CONFIG_AR9170_USB is not set | ||
| 758 | CONFIG_HOSTAP=m | ||
| 759 | CONFIG_HOSTAP_FIRMWARE=y | ||
| 760 | CONFIG_HOSTAP_FIRMWARE_NVRAM=y | ||
| 761 | # CONFIG_B43 is not set | ||
| 762 | # CONFIG_B43LEGACY is not set | ||
| 763 | CONFIG_ZD1211RW=m | ||
| 764 | CONFIG_ZD1211RW_DEBUG=y | ||
| 765 | # CONFIG_RT2X00 is not set | ||
| 766 | |||
| 767 | # | ||
| 768 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 769 | # | ||
| 770 | |||
| 771 | # | ||
| 772 | # USB Network Adapters | ||
| 773 | # | ||
| 774 | # CONFIG_USB_CATC is not set | ||
| 775 | # CONFIG_USB_KAWETH is not set | ||
| 776 | # CONFIG_USB_PEGASUS is not set | ||
| 777 | # CONFIG_USB_RTL8150 is not set | ||
| 778 | # CONFIG_USB_USBNET is not set | ||
| 779 | # CONFIG_WAN is not set | ||
| 780 | CONFIG_PPP=m | ||
| 781 | CONFIG_PPP_MULTILINK=y | ||
| 782 | CONFIG_PPP_FILTER=y | ||
| 783 | CONFIG_PPP_ASYNC=m | ||
| 784 | CONFIG_PPP_SYNC_TTY=m | ||
| 785 | CONFIG_PPP_DEFLATE=m | ||
| 786 | CONFIG_PPP_BSDCOMP=m | ||
| 787 | CONFIG_PPP_MPPE=m | ||
| 788 | # CONFIG_PPPOE is not set | ||
| 789 | # CONFIG_PPPOL2TP is not set | ||
| 790 | # CONFIG_SLIP is not set | ||
| 791 | CONFIG_SLHC=m | ||
| 792 | # CONFIG_NETCONSOLE is not set | ||
| 793 | # CONFIG_NETPOLL is not set | ||
| 794 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 795 | # CONFIG_ISDN is not set | ||
| 796 | |||
| 797 | # | ||
| 798 | # Input device support | ||
| 799 | # | ||
| 800 | CONFIG_INPUT=y | ||
| 801 | CONFIG_INPUT_FF_MEMLESS=y | ||
| 802 | # CONFIG_INPUT_POLLDEV is not set | ||
| 803 | |||
| 804 | # | ||
| 805 | # Userland interfaces | ||
| 806 | # | ||
| 807 | CONFIG_INPUT_MOUSEDEV=y | ||
| 808 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 809 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 810 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 811 | # CONFIG_INPUT_JOYDEV is not set | ||
| 812 | CONFIG_INPUT_EVDEV=y | ||
| 813 | CONFIG_INPUT_EVBUG=m | ||
| 814 | |||
| 815 | # | ||
| 816 | # Input Device Drivers | ||
| 817 | # | ||
| 818 | CONFIG_INPUT_KEYBOARD=y | ||
| 819 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 820 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 821 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 822 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 823 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 824 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 825 | CONFIG_KEYBOARD_GPIO=y | ||
| 826 | CONFIG_INPUT_MOUSE=y | ||
| 827 | CONFIG_MOUSE_PS2=y | ||
| 828 | CONFIG_MOUSE_PS2_ALPS=y | ||
| 829 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
| 830 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
| 831 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
| 832 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
| 833 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
| 834 | # CONFIG_MOUSE_SERIAL is not set | ||
| 835 | # CONFIG_MOUSE_APPLETOUCH is not set | ||
| 836 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 837 | # CONFIG_MOUSE_VSXXXAA is not set | ||
| 838 | # CONFIG_MOUSE_GPIO is not set | ||
| 839 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 840 | # CONFIG_INPUT_TABLET is not set | ||
| 841 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 842 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 843 | # CONFIG_TOUCHSCREEN_AD7877 is not set | ||
| 844 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
| 845 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | ||
| 846 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
| 847 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 848 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 849 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 850 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 851 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 852 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 853 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 854 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 855 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 856 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 857 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 858 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 859 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 860 | # CONFIG_INPUT_MISC is not set | ||
| 861 | |||
| 862 | # | ||
| 863 | # Hardware I/O ports | ||
| 864 | # | ||
| 865 | CONFIG_SERIO=y | ||
| 866 | CONFIG_SERIO_SERPORT=y | ||
| 867 | CONFIG_SERIO_LIBPS2=y | ||
| 868 | CONFIG_SERIO_RAW=y | ||
| 869 | # CONFIG_GAMEPORT is not set | ||
| 870 | |||
| 871 | # | ||
| 872 | # Character devices | ||
| 873 | # | ||
| 874 | CONFIG_VT=y | ||
| 875 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 876 | CONFIG_VT_CONSOLE=y | ||
| 877 | CONFIG_HW_CONSOLE=y | ||
| 878 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
| 879 | CONFIG_DEVKMEM=y | ||
| 880 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 881 | |||
| 882 | # | ||
| 883 | # Serial drivers | ||
| 884 | # | ||
| 885 | # CONFIG_SERIAL_8250 is not set | ||
| 886 | |||
| 887 | # | ||
| 888 | # Non-8250 serial port support | ||
| 889 | # | ||
| 890 | CONFIG_SERIAL_SAMSUNG=y | ||
| 891 | CONFIG_SERIAL_SAMSUNG_UARTS=3 | ||
| 892 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y | ||
| 893 | CONFIG_SERIAL_S3C2440=y | ||
| 894 | # CONFIG_SERIAL_MAX3100 is not set | ||
| 895 | CONFIG_SERIAL_CORE=y | ||
| 896 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 897 | CONFIG_UNIX98_PTYS=y | ||
| 898 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 899 | CONFIG_LEGACY_PTYS=y | ||
| 900 | CONFIG_LEGACY_PTY_COUNT=128 | ||
| 901 | CONFIG_IPMI_HANDLER=m | ||
| 902 | # CONFIG_IPMI_PANIC_EVENT is not set | ||
| 903 | CONFIG_IPMI_DEVICE_INTERFACE=m | ||
| 904 | CONFIG_IPMI_SI=m | ||
| 905 | CONFIG_IPMI_WATCHDOG=m | ||
| 906 | CONFIG_IPMI_POWEROFF=m | ||
| 907 | CONFIG_HW_RANDOM=y | ||
| 908 | # CONFIG_HW_RANDOM_TIMERIOMEM is not set | ||
| 909 | # CONFIG_R3964 is not set | ||
| 910 | # CONFIG_RAW_DRIVER is not set | ||
| 911 | # CONFIG_TCG_TPM is not set | ||
| 912 | CONFIG_I2C=y | ||
| 913 | CONFIG_I2C_BOARDINFO=y | ||
| 914 | CONFIG_I2C_CHARDEV=y | ||
| 915 | CONFIG_I2C_HELPER_AUTO=y | ||
| 916 | CONFIG_I2C_ALGOBIT=y | ||
| 917 | |||
| 918 | # | ||
| 919 | # I2C Hardware Bus support | ||
| 920 | # | ||
| 921 | |||
| 922 | # | ||
| 923 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 924 | # | ||
| 925 | # CONFIG_I2C_GPIO is not set | ||
| 926 | # CONFIG_I2C_OCORES is not set | ||
| 927 | CONFIG_I2C_S3C2410=y | ||
| 928 | CONFIG_I2C_SIMTEC=y | ||
| 929 | |||
| 930 | # | ||
| 931 | # External I2C/SMBus adapter drivers | ||
| 932 | # | ||
| 933 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 934 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 935 | # CONFIG_I2C_TINY_USB is not set | ||
| 936 | |||
| 937 | # | ||
| 938 | # Other I2C/SMBus bus drivers | ||
| 939 | # | ||
| 940 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 941 | # CONFIG_I2C_STUB is not set | ||
| 942 | |||
| 943 | # | ||
| 944 | # Miscellaneous I2C Chip support | ||
| 945 | # | ||
| 946 | # CONFIG_DS1682 is not set | ||
| 947 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 948 | # CONFIG_PCF8575 is not set | ||
| 949 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 950 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 951 | CONFIG_SENSORS_TSL2550=m | ||
| 952 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 953 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 954 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 955 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 956 | CONFIG_SPI=y | ||
| 957 | # CONFIG_SPI_DEBUG is not set | ||
| 958 | CONFIG_SPI_MASTER=y | ||
| 959 | |||
| 960 | # | ||
| 961 | # SPI Master Controller Drivers | ||
| 962 | # | ||
| 963 | CONFIG_SPI_BITBANG=y | ||
| 964 | # CONFIG_SPI_GPIO is not set | ||
| 965 | CONFIG_SPI_S3C24XX=y | ||
| 966 | # CONFIG_SPI_S3C24XX_GPIO is not set | ||
| 967 | |||
| 968 | # | ||
| 969 | # SPI Protocol Masters | ||
| 970 | # | ||
| 971 | CONFIG_SPI_SPIDEV=y | ||
| 972 | # CONFIG_SPI_TLE62X0 is not set | ||
| 973 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 974 | CONFIG_GPIOLIB=y | ||
| 975 | # CONFIG_DEBUG_GPIO is not set | ||
| 976 | CONFIG_GPIO_SYSFS=y | ||
| 977 | |||
| 978 | # | ||
| 979 | # Memory mapped GPIO expanders: | ||
| 980 | # | ||
| 981 | |||
| 982 | # | ||
| 983 | # I2C GPIO expanders: | ||
| 984 | # | ||
| 985 | # CONFIG_GPIO_MAX732X is not set | ||
| 986 | # CONFIG_GPIO_PCA953X is not set | ||
| 987 | # CONFIG_GPIO_PCF857X is not set | ||
| 988 | |||
| 989 | # | ||
| 990 | # PCI GPIO expanders: | ||
| 991 | # | ||
| 992 | |||
| 993 | # | ||
| 994 | # SPI GPIO expanders: | ||
| 995 | # | ||
| 996 | # CONFIG_GPIO_MAX7301 is not set | ||
| 997 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 998 | # CONFIG_W1 is not set | ||
| 999 | # CONFIG_POWER_SUPPLY is not set | ||
| 1000 | CONFIG_HWMON=y | ||
| 1001 | # CONFIG_HWMON_VID is not set | ||
| 1002 | # CONFIG_SENSORS_AD7414 is not set | ||
| 1003 | # CONFIG_SENSORS_AD7418 is not set | ||
| 1004 | # CONFIG_SENSORS_ADCXX is not set | ||
| 1005 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 1006 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 1007 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 1008 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 1009 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 1010 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 1011 | # CONFIG_SENSORS_ADT7462 is not set | ||
| 1012 | # CONFIG_SENSORS_ADT7470 is not set | ||
| 1013 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 1014 | # CONFIG_SENSORS_ADT7475 is not set | ||
| 1015 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 1016 | # CONFIG_SENSORS_DS1621 is not set | ||
| 1017 | # CONFIG_SENSORS_F71805F is not set | ||
| 1018 | # CONFIG_SENSORS_F71882FG is not set | ||
| 1019 | # CONFIG_SENSORS_F75375S is not set | ||
| 1020 | # CONFIG_SENSORS_G760A is not set | ||
| 1021 | # CONFIG_SENSORS_GL518SM is not set | ||
| 1022 | # CONFIG_SENSORS_GL520SM is not set | ||
| 1023 | # CONFIG_SENSORS_IBMAEM is not set | ||
| 1024 | # CONFIG_SENSORS_IBMPEX is not set | ||
| 1025 | # CONFIG_SENSORS_IT87 is not set | ||
| 1026 | # CONFIG_SENSORS_LM63 is not set | ||
| 1027 | # CONFIG_SENSORS_LM70 is not set | ||
| 1028 | CONFIG_SENSORS_LM75=y | ||
| 1029 | # CONFIG_SENSORS_LM77 is not set | ||
| 1030 | # CONFIG_SENSORS_LM78 is not set | ||
| 1031 | # CONFIG_SENSORS_LM80 is not set | ||
| 1032 | # CONFIG_SENSORS_LM83 is not set | ||
| 1033 | # CONFIG_SENSORS_LM85 is not set | ||
| 1034 | # CONFIG_SENSORS_LM87 is not set | ||
| 1035 | # CONFIG_SENSORS_LM90 is not set | ||
| 1036 | # CONFIG_SENSORS_LM92 is not set | ||
| 1037 | # CONFIG_SENSORS_LM93 is not set | ||
| 1038 | # CONFIG_SENSORS_LTC4215 is not set | ||
| 1039 | # CONFIG_SENSORS_LTC4245 is not set | ||
| 1040 | # CONFIG_SENSORS_LM95241 is not set | ||
| 1041 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 1042 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 1043 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 1044 | # CONFIG_SENSORS_PC87360 is not set | ||
| 1045 | # CONFIG_SENSORS_PC87427 is not set | ||
| 1046 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 1047 | # CONFIG_SENSORS_SHT15 is not set | ||
| 1048 | # CONFIG_SENSORS_DME1737 is not set | ||
| 1049 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 1050 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 1051 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 1052 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 1053 | # CONFIG_SENSORS_THMC50 is not set | ||
| 1054 | # CONFIG_SENSORS_VT1211 is not set | ||
| 1055 | # CONFIG_SENSORS_W83781D is not set | ||
| 1056 | # CONFIG_SENSORS_W83791D is not set | ||
| 1057 | # CONFIG_SENSORS_W83792D is not set | ||
| 1058 | # CONFIG_SENSORS_W83793 is not set | ||
| 1059 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 1060 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 1061 | # CONFIG_SENSORS_W83627HF is not set | ||
| 1062 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 1063 | # CONFIG_SENSORS_LIS3_SPI is not set | ||
| 1064 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 1065 | CONFIG_THERMAL=m | ||
| 1066 | # CONFIG_THERMAL_HWMON is not set | ||
| 1067 | CONFIG_WATCHDOG=y | ||
| 1068 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 1069 | |||
| 1070 | # | ||
| 1071 | # Watchdog Device Drivers | ||
| 1072 | # | ||
| 1073 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 1074 | CONFIG_S3C2410_WATCHDOG=y | ||
| 1075 | |||
| 1076 | # | ||
| 1077 | # USB-based Watchdog Cards | ||
| 1078 | # | ||
| 1079 | # CONFIG_USBPCWATCHDOG is not set | ||
| 1080 | CONFIG_SSB_POSSIBLE=y | ||
| 1081 | |||
| 1082 | # | ||
| 1083 | # Sonics Silicon Backplane | ||
| 1084 | # | ||
| 1085 | # CONFIG_SSB is not set | ||
| 1086 | |||
| 1087 | # | ||
| 1088 | # Multifunction device drivers | ||
| 1089 | # | ||
| 1090 | # CONFIG_MFD_CORE is not set | ||
| 1091 | # CONFIG_MFD_SM501 is not set | ||
| 1092 | # CONFIG_MFD_ASIC3 is not set | ||
| 1093 | # CONFIG_HTC_EGPIO is not set | ||
| 1094 | # CONFIG_HTC_PASIC3 is not set | ||
| 1095 | # CONFIG_TPS65010 is not set | ||
| 1096 | # CONFIG_TWL4030_CORE is not set | ||
| 1097 | # CONFIG_MFD_TMIO is not set | ||
| 1098 | # CONFIG_MFD_T7L66XB is not set | ||
| 1099 | # CONFIG_MFD_TC6387XB is not set | ||
| 1100 | # CONFIG_MFD_TC6393XB is not set | ||
| 1101 | # CONFIG_PMIC_DA903X is not set | ||
| 1102 | # CONFIG_MFD_WM8400 is not set | ||
| 1103 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1104 | # CONFIG_MFD_PCF50633 is not set | ||
| 1105 | |||
| 1106 | # | ||
| 1107 | # Multimedia devices | ||
| 1108 | # | ||
| 1109 | |||
| 1110 | # | ||
| 1111 | # Multimedia core support | ||
| 1112 | # | ||
| 1113 | CONFIG_VIDEO_DEV=m | ||
| 1114 | CONFIG_VIDEO_V4L2_COMMON=m | ||
| 1115 | CONFIG_VIDEO_ALLOW_V4L1=y | ||
| 1116 | CONFIG_VIDEO_V4L1_COMPAT=y | ||
| 1117 | CONFIG_DVB_CORE=m | ||
| 1118 | CONFIG_VIDEO_MEDIA=m | ||
| 1119 | |||
| 1120 | # | ||
| 1121 | # Multimedia drivers | ||
| 1122 | # | ||
| 1123 | # CONFIG_MEDIA_ATTACH is not set | ||
| 1124 | CONFIG_MEDIA_TUNER=m | ||
| 1125 | # CONFIG_MEDIA_TUNER_CUSTOMISE is not set | ||
| 1126 | CONFIG_MEDIA_TUNER_SIMPLE=m | ||
| 1127 | CONFIG_MEDIA_TUNER_TDA8290=m | ||
| 1128 | CONFIG_MEDIA_TUNER_TDA9887=m | ||
| 1129 | CONFIG_MEDIA_TUNER_TEA5761=m | ||
| 1130 | CONFIG_MEDIA_TUNER_TEA5767=m | ||
| 1131 | CONFIG_MEDIA_TUNER_MT20XX=m | ||
| 1132 | CONFIG_MEDIA_TUNER_XC2028=m | ||
| 1133 | CONFIG_MEDIA_TUNER_XC5000=m | ||
| 1134 | CONFIG_MEDIA_TUNER_MC44S803=m | ||
| 1135 | CONFIG_VIDEO_V4L2=m | ||
| 1136 | CONFIG_VIDEO_V4L1=m | ||
| 1137 | CONFIG_VIDEOBUF_GEN=m | ||
| 1138 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | ||
| 1139 | # CONFIG_VIDEO_ADV_DEBUG is not set | ||
| 1140 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set | ||
| 1141 | CONFIG_VIDEO_HELPER_CHIPS_AUTO=y | ||
| 1142 | # CONFIG_VIDEO_VIVI is not set | ||
| 1143 | # CONFIG_VIDEO_CPIA is not set | ||
| 1144 | # CONFIG_VIDEO_CPIA2 is not set | ||
| 1145 | # CONFIG_VIDEO_SAA5246A is not set | ||
| 1146 | # CONFIG_VIDEO_SAA5249 is not set | ||
| 1147 | # CONFIG_VIDEO_AU0828 is not set | ||
| 1148 | CONFIG_SOC_CAMERA=m | ||
| 1149 | # CONFIG_SOC_CAMERA_MT9M001 is not set | ||
| 1150 | # CONFIG_SOC_CAMERA_MT9M111 is not set | ||
| 1151 | # CONFIG_SOC_CAMERA_MT9T031 is not set | ||
| 1152 | # CONFIG_SOC_CAMERA_MT9V022 is not set | ||
| 1153 | # CONFIG_SOC_CAMERA_TW9910 is not set | ||
| 1154 | CONFIG_SOC_CAMERA_PLATFORM=m | ||
| 1155 | # CONFIG_SOC_CAMERA_OV772X is not set | ||
| 1156 | # CONFIG_VIDEO_SH_MOBILE_CEU is not set | ||
| 1157 | CONFIG_V4L_USB_DRIVERS=y | ||
| 1158 | # CONFIG_USB_VIDEO_CLASS is not set | ||
| 1159 | CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y | ||
| 1160 | CONFIG_USB_GSPCA=m | ||
| 1161 | # CONFIG_USB_M5602 is not set | ||
| 1162 | # CONFIG_USB_STV06XX is not set | ||
| 1163 | # CONFIG_USB_GSPCA_CONEX is not set | ||
| 1164 | # CONFIG_USB_GSPCA_ETOMS is not set | ||
| 1165 | # CONFIG_USB_GSPCA_FINEPIX is not set | ||
| 1166 | # CONFIG_USB_GSPCA_MARS is not set | ||
| 1167 | # CONFIG_USB_GSPCA_MR97310A is not set | ||
| 1168 | # CONFIG_USB_GSPCA_OV519 is not set | ||
| 1169 | # CONFIG_USB_GSPCA_OV534 is not set | ||
| 1170 | # CONFIG_USB_GSPCA_PAC207 is not set | ||
| 1171 | # CONFIG_USB_GSPCA_PAC7311 is not set | ||
| 1172 | # CONFIG_USB_GSPCA_SONIXB is not set | ||
| 1173 | # CONFIG_USB_GSPCA_SONIXJ is not set | ||
| 1174 | # CONFIG_USB_GSPCA_SPCA500 is not set | ||
| 1175 | # CONFIG_USB_GSPCA_SPCA501 is not set | ||
| 1176 | # CONFIG_USB_GSPCA_SPCA505 is not set | ||
| 1177 | # CONFIG_USB_GSPCA_SPCA506 is not set | ||
| 1178 | # CONFIG_USB_GSPCA_SPCA508 is not set | ||
| 1179 | # CONFIG_USB_GSPCA_SPCA561 is not set | ||
| 1180 | # CONFIG_USB_GSPCA_SQ905 is not set | ||
| 1181 | # CONFIG_USB_GSPCA_SQ905C is not set | ||
| 1182 | # CONFIG_USB_GSPCA_STK014 is not set | ||
| 1183 | # CONFIG_USB_GSPCA_SUNPLUS is not set | ||
| 1184 | # CONFIG_USB_GSPCA_T613 is not set | ||
| 1185 | # CONFIG_USB_GSPCA_TV8532 is not set | ||
| 1186 | # CONFIG_USB_GSPCA_VC032X is not set | ||
| 1187 | CONFIG_USB_GSPCA_ZC3XX=m | ||
| 1188 | # CONFIG_VIDEO_PVRUSB2 is not set | ||
| 1189 | # CONFIG_VIDEO_HDPVR is not set | ||
| 1190 | # CONFIG_VIDEO_EM28XX is not set | ||
| 1191 | # CONFIG_VIDEO_CX231XX is not set | ||
| 1192 | # CONFIG_VIDEO_USBVISION is not set | ||
| 1193 | # CONFIG_USB_VICAM is not set | ||
| 1194 | # CONFIG_USB_IBMCAM is not set | ||
| 1195 | # CONFIG_USB_KONICAWC is not set | ||
| 1196 | # CONFIG_USB_QUICKCAM_MESSENGER is not set | ||
| 1197 | # CONFIG_USB_ET61X251 is not set | ||
| 1198 | # CONFIG_VIDEO_OVCAMCHIP is not set | ||
| 1199 | # CONFIG_USB_OV511 is not set | ||
| 1200 | # CONFIG_USB_SE401 is not set | ||
| 1201 | # CONFIG_USB_SN9C102 is not set | ||
| 1202 | # CONFIG_USB_STV680 is not set | ||
| 1203 | # CONFIG_USB_ZC0301 is not set | ||
| 1204 | # CONFIG_USB_PWC is not set | ||
| 1205 | # CONFIG_USB_PWC_INPUT_EVDEV is not set | ||
| 1206 | # CONFIG_USB_ZR364XX is not set | ||
| 1207 | # CONFIG_USB_STKWEBCAM is not set | ||
| 1208 | # CONFIG_USB_S2255 is not set | ||
| 1209 | CONFIG_RADIO_ADAPTERS=y | ||
| 1210 | # CONFIG_USB_DSBR is not set | ||
| 1211 | # CONFIG_USB_SI470X is not set | ||
| 1212 | # CONFIG_USB_MR800 is not set | ||
| 1213 | # CONFIG_RADIO_TEA5764 is not set | ||
| 1214 | # CONFIG_DVB_DYNAMIC_MINORS is not set | ||
| 1215 | CONFIG_DVB_CAPTURE_DRIVERS=y | ||
| 1216 | # CONFIG_TTPCI_EEPROM is not set | ||
| 1217 | |||
| 1218 | # | ||
| 1219 | # Supported USB Adapters | ||
| 1220 | # | ||
| 1221 | # CONFIG_DVB_USB is not set | ||
| 1222 | # CONFIG_DVB_SIANO_SMS1XXX is not set | ||
| 1223 | |||
| 1224 | # | ||
| 1225 | # Supported FlexCopII (B2C2) Adapters | ||
| 1226 | # | ||
| 1227 | # CONFIG_DVB_B2C2_FLEXCOP is not set | ||
| 1228 | |||
| 1229 | # | ||
| 1230 | # Supported DVB Frontends | ||
| 1231 | # | ||
| 1232 | # CONFIG_DVB_FE_CUSTOMISE is not set | ||
| 1233 | # CONFIG_DAB is not set | ||
| 1234 | |||
| 1235 | # | ||
| 1236 | # Graphics support | ||
| 1237 | # | ||
| 1238 | # CONFIG_VGASTATE is not set | ||
| 1239 | CONFIG_VIDEO_OUTPUT_CONTROL=y | ||
| 1240 | CONFIG_FB=y | ||
| 1241 | CONFIG_FIRMWARE_EDID=y | ||
| 1242 | # CONFIG_FB_DDC is not set | ||
| 1243 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 1244 | CONFIG_FB_CFB_FILLRECT=y | ||
| 1245 | CONFIG_FB_CFB_COPYAREA=y | ||
| 1246 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 1247 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 1248 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 1249 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 1250 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 1251 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 1252 | # CONFIG_FB_SYS_FOPS is not set | ||
| 1253 | # CONFIG_FB_SVGALIB is not set | ||
| 1254 | # CONFIG_FB_MACMODES is not set | ||
| 1255 | # CONFIG_FB_BACKLIGHT is not set | ||
| 1256 | CONFIG_FB_MODE_HELPERS=y | ||
| 1257 | CONFIG_FB_TILEBLITTING=y | ||
| 1258 | |||
| 1259 | # | ||
| 1260 | # Frame buffer hardware drivers | ||
| 1261 | # | ||
| 1262 | # CONFIG_FB_UVESA is not set | ||
| 1263 | # CONFIG_FB_S1D13XXX is not set | ||
| 1264 | CONFIG_FB_S3C2410=y | ||
| 1265 | # CONFIG_FB_S3C2410_DEBUG is not set | ||
| 1266 | # CONFIG_FB_VIRTUAL is not set | ||
| 1267 | # CONFIG_FB_METRONOME is not set | ||
| 1268 | # CONFIG_FB_MB862XX is not set | ||
| 1269 | # CONFIG_FB_BROADSHEET is not set | ||
| 1270 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 1271 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 1272 | # CONFIG_LCD_LTV350QV is not set | ||
| 1273 | # CONFIG_LCD_ILI9320 is not set | ||
| 1274 | # CONFIG_LCD_TDO24M is not set | ||
| 1275 | # CONFIG_LCD_VGG2432A4 is not set | ||
| 1276 | CONFIG_LCD_PLATFORM=y | ||
| 1277 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 1278 | # CONFIG_BACKLIGHT_GENERIC is not set | ||
| 1279 | CONFIG_BACKLIGHT_PWM=y | ||
| 1280 | |||
| 1281 | # | ||
| 1282 | # Display device support | ||
| 1283 | # | ||
| 1284 | CONFIG_DISPLAY_SUPPORT=y | ||
| 1285 | |||
| 1286 | # | ||
| 1287 | # Display hardware drivers | ||
| 1288 | # | ||
| 1289 | |||
| 1290 | # | ||
| 1291 | # Console display driver support | ||
| 1292 | # | ||
| 1293 | # CONFIG_VGA_CONSOLE is not set | ||
| 1294 | CONFIG_DUMMY_CONSOLE=y | ||
| 1295 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 1296 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y | ||
| 1297 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | ||
| 1298 | CONFIG_FONTS=y | ||
| 1299 | CONFIG_FONT_8x8=y | ||
| 1300 | # CONFIG_FONT_8x16 is not set | ||
| 1301 | # CONFIG_FONT_6x11 is not set | ||
| 1302 | # CONFIG_FONT_7x14 is not set | ||
| 1303 | # CONFIG_FONT_PEARL_8x8 is not set | ||
| 1304 | # CONFIG_FONT_ACORN_8x8 is not set | ||
| 1305 | CONFIG_FONT_MINI_4x6=y | ||
| 1306 | # CONFIG_FONT_SUN8x16 is not set | ||
| 1307 | # CONFIG_FONT_SUN12x22 is not set | ||
| 1308 | # CONFIG_FONT_10x18 is not set | ||
| 1309 | CONFIG_LOGO=y | ||
| 1310 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 1311 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 1312 | CONFIG_LOGO_LINUX_CLUT224=y | ||
| 1313 | CONFIG_SOUND=y | ||
| 1314 | CONFIG_SOUND_OSS_CORE=y | ||
| 1315 | CONFIG_SND=y | ||
| 1316 | CONFIG_SND_TIMER=y | ||
| 1317 | CONFIG_SND_PCM=y | ||
| 1318 | CONFIG_SND_HWDEP=m | ||
| 1319 | CONFIG_SND_RAWMIDI=m | ||
| 1320 | CONFIG_SND_JACK=y | ||
| 1321 | CONFIG_SND_SEQUENCER=m | ||
| 1322 | CONFIG_SND_SEQ_DUMMY=m | ||
| 1323 | CONFIG_SND_OSSEMUL=y | ||
| 1324 | CONFIG_SND_MIXER_OSS=m | ||
| 1325 | CONFIG_SND_PCM_OSS=m | ||
| 1326 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
| 1327 | CONFIG_SND_SEQUENCER_OSS=y | ||
| 1328 | CONFIG_SND_DYNAMIC_MINORS=y | ||
| 1329 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 1330 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 1331 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 1332 | # CONFIG_SND_DEBUG is not set | ||
| 1333 | # CONFIG_SND_DRIVERS is not set | ||
| 1334 | # CONFIG_SND_ARM is not set | ||
| 1335 | # CONFIG_SND_SPI is not set | ||
| 1336 | CONFIG_SND_USB=y | ||
| 1337 | CONFIG_SND_USB_AUDIO=m | ||
| 1338 | CONFIG_SND_USB_CAIAQ=m | ||
| 1339 | CONFIG_SND_USB_CAIAQ_INPUT=y | ||
| 1340 | CONFIG_SND_SOC=y | ||
| 1341 | CONFIG_SND_S3C24XX_SOC=y | ||
| 1342 | CONFIG_SND_S3C24XX_SOC_I2S=y | ||
| 1343 | # CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set | ||
| 1344 | CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=y | ||
| 1345 | CONFIG_SND_SOC_I2C_AND_SPI=y | ||
| 1346 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 1347 | CONFIG_SND_SOC_L3=y | ||
| 1348 | CONFIG_SND_SOC_UDA134X=y | ||
| 1349 | # CONFIG_SOUND_PRIME is not set | ||
| 1350 | CONFIG_HID_SUPPORT=y | ||
| 1351 | CONFIG_HID=y | ||
| 1352 | # CONFIG_HID_DEBUG is not set | ||
| 1353 | CONFIG_HIDRAW=y | ||
| 1354 | |||
| 1355 | # | ||
| 1356 | # USB Input Devices | ||
| 1357 | # | ||
| 1358 | CONFIG_USB_HID=y | ||
| 1359 | CONFIG_HID_PID=y | ||
| 1360 | CONFIG_USB_HIDDEV=y | ||
| 1361 | |||
| 1362 | # | ||
| 1363 | # Special HID drivers | ||
| 1364 | # | ||
| 1365 | CONFIG_HID_A4TECH=y | ||
| 1366 | CONFIG_HID_APPLE=y | ||
| 1367 | CONFIG_HID_BELKIN=y | ||
| 1368 | CONFIG_HID_CHERRY=y | ||
| 1369 | CONFIG_HID_CHICONY=y | ||
| 1370 | CONFIG_HID_CYPRESS=y | ||
| 1371 | # CONFIG_DRAGONRISE_FF is not set | ||
| 1372 | CONFIG_HID_EZKEY=y | ||
| 1373 | CONFIG_HID_KYE=y | ||
| 1374 | CONFIG_HID_GYRATION=y | ||
| 1375 | CONFIG_HID_KENSINGTON=y | ||
| 1376 | CONFIG_HID_LOGITECH=y | ||
| 1377 | # CONFIG_LOGITECH_FF is not set | ||
| 1378 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1379 | CONFIG_HID_MICROSOFT=y | ||
| 1380 | CONFIG_HID_MONTEREY=y | ||
| 1381 | CONFIG_HID_NTRIG=y | ||
| 1382 | CONFIG_HID_PANTHERLORD=y | ||
| 1383 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1384 | CONFIG_HID_PETALYNX=y | ||
| 1385 | CONFIG_HID_SAMSUNG=y | ||
| 1386 | CONFIG_HID_SONY=y | ||
| 1387 | CONFIG_HID_SUNPLUS=y | ||
| 1388 | # CONFIG_GREENASIA_FF is not set | ||
| 1389 | CONFIG_HID_TOPSEED=y | ||
| 1390 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1391 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1392 | CONFIG_USB_SUPPORT=y | ||
| 1393 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 1394 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 1395 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 1396 | CONFIG_USB=y | ||
| 1397 | # CONFIG_USB_DEBUG is not set | ||
| 1398 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 1399 | |||
| 1400 | # | ||
| 1401 | # Miscellaneous USB options | ||
| 1402 | # | ||
| 1403 | CONFIG_USB_DEVICEFS=y | ||
| 1404 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 1405 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 1406 | # CONFIG_USB_SUSPEND is not set | ||
| 1407 | # CONFIG_USB_OTG is not set | ||
| 1408 | # CONFIG_USB_MON is not set | ||
| 1409 | # CONFIG_USB_WUSB is not set | ||
| 1410 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1411 | |||
| 1412 | # | ||
| 1413 | # USB Host Controller Drivers | ||
| 1414 | # | ||
| 1415 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1416 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1417 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 1418 | # CONFIG_USB_ISP1760_HCD is not set | ||
| 1419 | CONFIG_USB_OHCI_HCD=y | ||
| 1420 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 1421 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 1422 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 1423 | # CONFIG_USB_SL811_HCD is not set | ||
| 1424 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 1425 | # CONFIG_USB_HWA_HCD is not set | ||
| 1426 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 1427 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 1428 | |||
| 1429 | # | ||
| 1430 | # USB Device Class drivers | ||
| 1431 | # | ||
| 1432 | CONFIG_USB_ACM=m | ||
| 1433 | # CONFIG_USB_PRINTER is not set | ||
| 1434 | CONFIG_USB_WDM=m | ||
| 1435 | # CONFIG_USB_TMC is not set | ||
| 1436 | |||
| 1437 | # | ||
| 1438 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | ||
| 1439 | # | ||
| 1440 | |||
| 1441 | # | ||
| 1442 | # also be needed; see USB_STORAGE Help for more info | ||
| 1443 | # | ||
| 1444 | CONFIG_USB_STORAGE=m | ||
| 1445 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1446 | CONFIG_USB_STORAGE_DATAFAB=m | ||
| 1447 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 1448 | CONFIG_USB_STORAGE_ISD200=m | ||
| 1449 | CONFIG_USB_STORAGE_USBAT=m | ||
| 1450 | CONFIG_USB_STORAGE_SDDR09=m | ||
| 1451 | CONFIG_USB_STORAGE_SDDR55=m | ||
| 1452 | CONFIG_USB_STORAGE_JUMPSHOT=m | ||
| 1453 | CONFIG_USB_STORAGE_ALAUDA=m | ||
| 1454 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1455 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1456 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1457 | CONFIG_USB_LIBUSUAL=y | ||
| 1458 | |||
| 1459 | # | ||
| 1460 | # USB Imaging devices | ||
| 1461 | # | ||
| 1462 | # CONFIG_USB_MDC800 is not set | ||
| 1463 | # CONFIG_USB_MICROTEK is not set | ||
| 1464 | |||
| 1465 | # | ||
| 1466 | # USB port drivers | ||
| 1467 | # | ||
| 1468 | CONFIG_USB_SERIAL=m | ||
| 1469 | # CONFIG_USB_EZUSB is not set | ||
| 1470 | # CONFIG_USB_SERIAL_GENERIC is not set | ||
| 1471 | # CONFIG_USB_SERIAL_AIRCABLE is not set | ||
| 1472 | # CONFIG_USB_SERIAL_ARK3116 is not set | ||
| 1473 | # CONFIG_USB_SERIAL_BELKIN is not set | ||
| 1474 | # CONFIG_USB_SERIAL_CH341 is not set | ||
| 1475 | # CONFIG_USB_SERIAL_WHITEHEAT is not set | ||
| 1476 | # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set | ||
| 1477 | CONFIG_USB_SERIAL_CP210X=m | ||
| 1478 | # CONFIG_USB_SERIAL_CYPRESS_M8 is not set | ||
| 1479 | # CONFIG_USB_SERIAL_EMPEG is not set | ||
| 1480 | CONFIG_USB_SERIAL_FTDI_SIO=m | ||
| 1481 | # CONFIG_USB_SERIAL_FUNSOFT is not set | ||
| 1482 | # CONFIG_USB_SERIAL_VISOR is not set | ||
| 1483 | # CONFIG_USB_SERIAL_IPAQ is not set | ||
| 1484 | # CONFIG_USB_SERIAL_IR is not set | ||
| 1485 | # CONFIG_USB_SERIAL_EDGEPORT is not set | ||
| 1486 | # CONFIG_USB_SERIAL_EDGEPORT_TI is not set | ||
| 1487 | # CONFIG_USB_SERIAL_GARMIN is not set | ||
| 1488 | # CONFIG_USB_SERIAL_IPW is not set | ||
| 1489 | # CONFIG_USB_SERIAL_IUU is not set | ||
| 1490 | # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set | ||
| 1491 | # CONFIG_USB_SERIAL_KEYSPAN is not set | ||
| 1492 | # CONFIG_USB_SERIAL_KLSI is not set | ||
| 1493 | # CONFIG_USB_SERIAL_KOBIL_SCT is not set | ||
| 1494 | # CONFIG_USB_SERIAL_MCT_U232 is not set | ||
| 1495 | # CONFIG_USB_SERIAL_MOS7720 is not set | ||
| 1496 | # CONFIG_USB_SERIAL_MOS7840 is not set | ||
| 1497 | # CONFIG_USB_SERIAL_MOTOROLA is not set | ||
| 1498 | # CONFIG_USB_SERIAL_NAVMAN is not set | ||
| 1499 | # CONFIG_USB_SERIAL_PL2303 is not set | ||
| 1500 | # CONFIG_USB_SERIAL_OTI6858 is not set | ||
| 1501 | # CONFIG_USB_SERIAL_QUALCOMM is not set | ||
| 1502 | CONFIG_USB_SERIAL_SPCP8X5=m | ||
| 1503 | # CONFIG_USB_SERIAL_HP4X is not set | ||
| 1504 | # CONFIG_USB_SERIAL_SAFE is not set | ||
| 1505 | # CONFIG_USB_SERIAL_SIEMENS_MPI is not set | ||
| 1506 | # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set | ||
| 1507 | # CONFIG_USB_SERIAL_SYMBOL is not set | ||
| 1508 | # CONFIG_USB_SERIAL_TI is not set | ||
| 1509 | # CONFIG_USB_SERIAL_CYBERJACK is not set | ||
| 1510 | # CONFIG_USB_SERIAL_XIRCOM is not set | ||
| 1511 | # CONFIG_USB_SERIAL_OPTION is not set | ||
| 1512 | # CONFIG_USB_SERIAL_OMNINET is not set | ||
| 1513 | # CONFIG_USB_SERIAL_OPTICON is not set | ||
| 1514 | # CONFIG_USB_SERIAL_DEBUG is not set | ||
| 1515 | |||
| 1516 | # | ||
| 1517 | # USB Miscellaneous drivers | ||
| 1518 | # | ||
| 1519 | # CONFIG_USB_EMI62 is not set | ||
| 1520 | # CONFIG_USB_EMI26 is not set | ||
| 1521 | # CONFIG_USB_ADUTUX is not set | ||
| 1522 | # CONFIG_USB_SEVSEG is not set | ||
| 1523 | # CONFIG_USB_RIO500 is not set | ||
| 1524 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1525 | # CONFIG_USB_LCD is not set | ||
| 1526 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1527 | # CONFIG_USB_LED is not set | ||
| 1528 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1529 | # CONFIG_USB_CYTHERM is not set | ||
| 1530 | # CONFIG_USB_IDMOUSE is not set | ||
| 1531 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1532 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1533 | # CONFIG_USB_LD is not set | ||
| 1534 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1535 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1536 | # CONFIG_USB_TEST is not set | ||
| 1537 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1538 | # CONFIG_USB_VST is not set | ||
| 1539 | CONFIG_USB_GADGET=y | ||
| 1540 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 1541 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 1542 | # CONFIG_USB_GADGET_DEBUG_FS is not set | ||
| 1543 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 1544 | CONFIG_USB_GADGET_SELECTED=y | ||
| 1545 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1546 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1547 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1548 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1549 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1550 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1551 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1552 | CONFIG_USB_GADGET_S3C2410=y | ||
| 1553 | CONFIG_USB_S3C2410=y | ||
| 1554 | # CONFIG_USB_S3C2410_DEBUG is not set | ||
| 1555 | # CONFIG_USB_GADGET_IMX is not set | ||
| 1556 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1557 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1558 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1559 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1560 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1561 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1562 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1563 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 1564 | CONFIG_USB_ZERO=m | ||
| 1565 | CONFIG_USB_ETH=m | ||
| 1566 | CONFIG_USB_ETH_RNDIS=y | ||
| 1567 | CONFIG_USB_GADGETFS=m | ||
| 1568 | CONFIG_USB_FILE_STORAGE=m | ||
| 1569 | # CONFIG_USB_FILE_STORAGE_TEST is not set | ||
| 1570 | CONFIG_USB_G_SERIAL=m | ||
| 1571 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1572 | # CONFIG_USB_G_PRINTER is not set | ||
| 1573 | CONFIG_USB_CDC_COMPOSITE=m | ||
| 1574 | |||
| 1575 | # | ||
| 1576 | # OTG and related infrastructure | ||
| 1577 | # | ||
| 1578 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1579 | # CONFIG_NOP_USB_XCEIV is not set | ||
| 1580 | CONFIG_MMC=y | ||
| 1581 | # CONFIG_MMC_DEBUG is not set | ||
| 1582 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 1583 | |||
| 1584 | # | ||
| 1585 | # MMC/SD/SDIO Card Drivers | ||
| 1586 | # | ||
| 1587 | CONFIG_MMC_BLOCK=y | ||
| 1588 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1589 | CONFIG_SDIO_UART=y | ||
| 1590 | # CONFIG_MMC_TEST is not set | ||
| 1591 | |||
| 1592 | # | ||
| 1593 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1594 | # | ||
| 1595 | CONFIG_MMC_SDHCI=y | ||
| 1596 | CONFIG_MMC_SPI=y | ||
| 1597 | CONFIG_MMC_S3C=y | ||
| 1598 | # CONFIG_MEMSTICK is not set | ||
| 1599 | # CONFIG_ACCESSIBILITY is not set | ||
| 1600 | CONFIG_NEW_LEDS=y | ||
| 1601 | CONFIG_LEDS_CLASS=y | ||
| 1602 | |||
| 1603 | # | ||
| 1604 | # LED drivers | ||
| 1605 | # | ||
| 1606 | CONFIG_LEDS_S3C24XX=y | ||
| 1607 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1608 | CONFIG_LEDS_GPIO=y | ||
| 1609 | CONFIG_LEDS_GPIO_PLATFORM=y | ||
| 1610 | # CONFIG_LEDS_LP5521 is not set | ||
| 1611 | # CONFIG_LEDS_PCA955X is not set | ||
| 1612 | # CONFIG_LEDS_DAC124S085 is not set | ||
| 1613 | # CONFIG_LEDS_PWM is not set | ||
| 1614 | # CONFIG_LEDS_BD2802 is not set | ||
| 1615 | |||
| 1616 | # | ||
| 1617 | # LED Triggers | ||
| 1618 | # | ||
| 1619 | CONFIG_LEDS_TRIGGERS=y | ||
| 1620 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 1621 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1622 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y | ||
| 1623 | CONFIG_LEDS_TRIGGER_GPIO=y | ||
| 1624 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 1625 | |||
| 1626 | # | ||
| 1627 | # iptables trigger is under Netfilter config (LED target) | ||
| 1628 | # | ||
| 1629 | CONFIG_RTC_LIB=y | ||
| 1630 | CONFIG_RTC_CLASS=y | ||
| 1631 | CONFIG_RTC_HCTOSYS=y | ||
| 1632 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 1633 | # CONFIG_RTC_DEBUG is not set | ||
| 1634 | |||
| 1635 | # | ||
| 1636 | # RTC interfaces | ||
| 1637 | # | ||
| 1638 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1639 | CONFIG_RTC_INTF_PROC=y | ||
| 1640 | CONFIG_RTC_INTF_DEV=y | ||
| 1641 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y | ||
| 1642 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1643 | |||
| 1644 | # | ||
| 1645 | # I2C RTC drivers | ||
| 1646 | # | ||
| 1647 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 1648 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1649 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1650 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1651 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1652 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1653 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1654 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1655 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1656 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1657 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1658 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1659 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1660 | |||
| 1661 | # | ||
| 1662 | # SPI RTC drivers | ||
| 1663 | # | ||
| 1664 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1665 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1666 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1667 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1668 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1669 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1670 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1671 | |||
| 1672 | # | ||
| 1673 | # Platform RTC drivers | ||
| 1674 | # | ||
| 1675 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1676 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1677 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1678 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1679 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1680 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1681 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1682 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1683 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1684 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1685 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1686 | |||
| 1687 | # | ||
| 1688 | # on-CPU RTC drivers | ||
| 1689 | # | ||
| 1690 | CONFIG_RTC_DRV_S3C=y | ||
| 1691 | CONFIG_DMADEVICES=y | ||
| 1692 | |||
| 1693 | # | ||
| 1694 | # DMA Devices | ||
| 1695 | # | ||
| 1696 | # CONFIG_AUXDISPLAY is not set | ||
| 1697 | # CONFIG_REGULATOR is not set | ||
| 1698 | # CONFIG_UIO is not set | ||
| 1699 | # CONFIG_STAGING is not set | ||
| 1700 | |||
| 1701 | # | ||
| 1702 | # File systems | ||
| 1703 | # | ||
| 1704 | CONFIG_EXT2_FS=m | ||
| 1705 | CONFIG_EXT2_FS_XATTR=y | ||
| 1706 | CONFIG_EXT2_FS_POSIX_ACL=y | ||
| 1707 | CONFIG_EXT2_FS_SECURITY=y | ||
| 1708 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1709 | CONFIG_EXT3_FS=y | ||
| 1710 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 1711 | CONFIG_EXT3_FS_XATTR=y | ||
| 1712 | CONFIG_EXT3_FS_POSIX_ACL=y | ||
| 1713 | CONFIG_EXT3_FS_SECURITY=y | ||
| 1714 | # CONFIG_EXT4_FS is not set | ||
| 1715 | CONFIG_JBD=y | ||
| 1716 | # CONFIG_JBD_DEBUG is not set | ||
| 1717 | CONFIG_FS_MBCACHE=y | ||
| 1718 | # CONFIG_REISERFS_FS is not set | ||
| 1719 | # CONFIG_JFS_FS is not set | ||
| 1720 | CONFIG_FS_POSIX_ACL=y | ||
| 1721 | CONFIG_FILE_LOCKING=y | ||
| 1722 | # CONFIG_XFS_FS is not set | ||
| 1723 | # CONFIG_GFS2_FS is not set | ||
| 1724 | # CONFIG_OCFS2_FS is not set | ||
| 1725 | # CONFIG_BTRFS_FS is not set | ||
| 1726 | CONFIG_DNOTIFY=y | ||
| 1727 | CONFIG_INOTIFY=y | ||
| 1728 | CONFIG_INOTIFY_USER=y | ||
| 1729 | # CONFIG_QUOTA is not set | ||
| 1730 | CONFIG_AUTOFS_FS=y | ||
| 1731 | CONFIG_AUTOFS4_FS=y | ||
| 1732 | # CONFIG_FUSE_FS is not set | ||
| 1733 | CONFIG_GENERIC_ACL=y | ||
| 1734 | |||
| 1735 | # | ||
| 1736 | # Caches | ||
| 1737 | # | ||
| 1738 | # CONFIG_FSCACHE is not set | ||
| 1739 | |||
| 1740 | # | ||
| 1741 | # CD-ROM/DVD Filesystems | ||
| 1742 | # | ||
| 1743 | # CONFIG_ISO9660_FS is not set | ||
| 1744 | # CONFIG_UDF_FS is not set | ||
| 1745 | |||
| 1746 | # | ||
| 1747 | # DOS/FAT/NT Filesystems | ||
| 1748 | # | ||
| 1749 | CONFIG_FAT_FS=y | ||
| 1750 | CONFIG_MSDOS_FS=y | ||
| 1751 | CONFIG_VFAT_FS=y | ||
| 1752 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1753 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1754 | # CONFIG_NTFS_FS is not set | ||
| 1755 | |||
| 1756 | # | ||
| 1757 | # Pseudo filesystems | ||
| 1758 | # | ||
| 1759 | CONFIG_PROC_FS=y | ||
| 1760 | CONFIG_PROC_SYSCTL=y | ||
| 1761 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1762 | CONFIG_SYSFS=y | ||
| 1763 | CONFIG_TMPFS=y | ||
| 1764 | CONFIG_TMPFS_POSIX_ACL=y | ||
| 1765 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1766 | CONFIG_CONFIGFS_FS=m | ||
| 1767 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1768 | # CONFIG_ADFS_FS is not set | ||
| 1769 | # CONFIG_AFFS_FS is not set | ||
| 1770 | # CONFIG_ECRYPT_FS is not set | ||
| 1771 | # CONFIG_HFS_FS is not set | ||
| 1772 | # CONFIG_HFSPLUS_FS is not set | ||
| 1773 | # CONFIG_BEFS_FS is not set | ||
| 1774 | # CONFIG_BFS_FS is not set | ||
| 1775 | # CONFIG_EFS_FS is not set | ||
| 1776 | CONFIG_JFFS2_FS=y | ||
| 1777 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1778 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1779 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1780 | # CONFIG_JFFS2_SUMMARY is not set | ||
| 1781 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1782 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 1783 | CONFIG_JFFS2_ZLIB=y | ||
| 1784 | # CONFIG_JFFS2_LZO is not set | ||
| 1785 | CONFIG_JFFS2_RTIME=y | ||
| 1786 | # CONFIG_JFFS2_RUBIN is not set | ||
| 1787 | CONFIG_CRAMFS=y | ||
| 1788 | # CONFIG_SQUASHFS is not set | ||
| 1789 | # CONFIG_VXFS_FS is not set | ||
| 1790 | # CONFIG_MINIX_FS is not set | ||
| 1791 | # CONFIG_OMFS_FS is not set | ||
| 1792 | # CONFIG_HPFS_FS is not set | ||
| 1793 | # CONFIG_QNX4FS_FS is not set | ||
| 1794 | CONFIG_ROMFS_FS=y | ||
| 1795 | # CONFIG_ROMFS_BACKED_BY_BLOCK is not set | ||
| 1796 | # CONFIG_ROMFS_BACKED_BY_MTD is not set | ||
| 1797 | CONFIG_ROMFS_BACKED_BY_BOTH=y | ||
| 1798 | CONFIG_ROMFS_ON_BLOCK=y | ||
| 1799 | CONFIG_ROMFS_ON_MTD=y | ||
| 1800 | # CONFIG_SYSV_FS is not set | ||
| 1801 | # CONFIG_UFS_FS is not set | ||
| 1802 | # CONFIG_NILFS2_FS is not set | ||
| 1803 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1804 | CONFIG_NFS_FS=y | ||
| 1805 | CONFIG_NFS_V3=y | ||
| 1806 | CONFIG_NFS_V3_ACL=y | ||
| 1807 | CONFIG_NFS_V4=y | ||
| 1808 | CONFIG_ROOT_NFS=y | ||
| 1809 | # CONFIG_NFSD is not set | ||
| 1810 | CONFIG_LOCKD=y | ||
| 1811 | CONFIG_LOCKD_V4=y | ||
| 1812 | CONFIG_NFS_ACL_SUPPORT=y | ||
| 1813 | CONFIG_NFS_COMMON=y | ||
| 1814 | CONFIG_SUNRPC=y | ||
| 1815 | CONFIG_SUNRPC_GSS=y | ||
| 1816 | CONFIG_RPCSEC_GSS_KRB5=y | ||
| 1817 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1818 | # CONFIG_SMB_FS is not set | ||
| 1819 | # CONFIG_CIFS is not set | ||
| 1820 | # CONFIG_NCP_FS is not set | ||
| 1821 | # CONFIG_CODA_FS is not set | ||
| 1822 | # CONFIG_AFS_FS is not set | ||
| 1823 | |||
| 1824 | # | ||
| 1825 | # Partition Types | ||
| 1826 | # | ||
| 1827 | CONFIG_PARTITION_ADVANCED=y | ||
| 1828 | # CONFIG_ACORN_PARTITION is not set | ||
| 1829 | # CONFIG_OSF_PARTITION is not set | ||
| 1830 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1831 | # CONFIG_ATARI_PARTITION is not set | ||
| 1832 | # CONFIG_MAC_PARTITION is not set | ||
| 1833 | CONFIG_MSDOS_PARTITION=y | ||
| 1834 | CONFIG_BSD_DISKLABEL=y | ||
| 1835 | CONFIG_MINIX_SUBPARTITION=y | ||
| 1836 | CONFIG_SOLARIS_X86_PARTITION=y | ||
| 1837 | CONFIG_UNIXWARE_DISKLABEL=y | ||
| 1838 | CONFIG_LDM_PARTITION=y | ||
| 1839 | # CONFIG_LDM_DEBUG is not set | ||
| 1840 | # CONFIG_SGI_PARTITION is not set | ||
| 1841 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1842 | # CONFIG_SUN_PARTITION is not set | ||
| 1843 | # CONFIG_KARMA_PARTITION is not set | ||
| 1844 | CONFIG_EFI_PARTITION=y | ||
| 1845 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1846 | CONFIG_NLS=y | ||
| 1847 | CONFIG_NLS_DEFAULT="cp437" | ||
| 1848 | CONFIG_NLS_CODEPAGE_437=m | ||
| 1849 | CONFIG_NLS_CODEPAGE_737=m | ||
| 1850 | CONFIG_NLS_CODEPAGE_775=m | ||
| 1851 | CONFIG_NLS_CODEPAGE_850=m | ||
| 1852 | CONFIG_NLS_CODEPAGE_852=m | ||
| 1853 | CONFIG_NLS_CODEPAGE_855=m | ||
| 1854 | CONFIG_NLS_CODEPAGE_857=m | ||
| 1855 | CONFIG_NLS_CODEPAGE_860=m | ||
| 1856 | CONFIG_NLS_CODEPAGE_861=m | ||
| 1857 | CONFIG_NLS_CODEPAGE_862=m | ||
| 1858 | CONFIG_NLS_CODEPAGE_863=m | ||
| 1859 | CONFIG_NLS_CODEPAGE_864=m | ||
| 1860 | CONFIG_NLS_CODEPAGE_865=m | ||
| 1861 | CONFIG_NLS_CODEPAGE_866=m | ||
| 1862 | CONFIG_NLS_CODEPAGE_869=m | ||
| 1863 | CONFIG_NLS_CODEPAGE_936=m | ||
| 1864 | CONFIG_NLS_CODEPAGE_950=m | ||
| 1865 | CONFIG_NLS_CODEPAGE_932=m | ||
| 1866 | CONFIG_NLS_CODEPAGE_949=m | ||
| 1867 | CONFIG_NLS_CODEPAGE_874=m | ||
| 1868 | CONFIG_NLS_ISO8859_8=m | ||
| 1869 | CONFIG_NLS_CODEPAGE_1250=m | ||
| 1870 | CONFIG_NLS_CODEPAGE_1251=m | ||
| 1871 | CONFIG_NLS_ASCII=m | ||
| 1872 | CONFIG_NLS_ISO8859_1=m | ||
| 1873 | CONFIG_NLS_ISO8859_2=m | ||
| 1874 | CONFIG_NLS_ISO8859_3=m | ||
| 1875 | CONFIG_NLS_ISO8859_4=m | ||
| 1876 | CONFIG_NLS_ISO8859_5=m | ||
| 1877 | CONFIG_NLS_ISO8859_6=m | ||
| 1878 | CONFIG_NLS_ISO8859_7=m | ||
| 1879 | CONFIG_NLS_ISO8859_9=m | ||
| 1880 | CONFIG_NLS_ISO8859_13=m | ||
| 1881 | CONFIG_NLS_ISO8859_14=m | ||
| 1882 | CONFIG_NLS_ISO8859_15=m | ||
| 1883 | CONFIG_NLS_KOI8_R=m | ||
| 1884 | CONFIG_NLS_KOI8_U=m | ||
| 1885 | CONFIG_NLS_UTF8=m | ||
| 1886 | # CONFIG_DLM is not set | ||
| 1887 | |||
| 1888 | # | ||
| 1889 | # Kernel hacking | ||
| 1890 | # | ||
| 1891 | # CONFIG_PRINTK_TIME is not set | ||
| 1892 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | ||
| 1893 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 1894 | CONFIG_FRAME_WARN=1024 | ||
| 1895 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1896 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1897 | CONFIG_DEBUG_FS=y | ||
| 1898 | # CONFIG_HEADERS_CHECK is not set | ||
| 1899 | CONFIG_DEBUG_KERNEL=y | ||
| 1900 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1901 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1902 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1903 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1904 | CONFIG_DETECT_HUNG_TASK=y | ||
| 1905 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
| 1906 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
| 1907 | # CONFIG_SCHED_DEBUG is not set | ||
| 1908 | # CONFIG_SCHEDSTATS is not set | ||
| 1909 | # CONFIG_TIMER_STATS is not set | ||
| 1910 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1911 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1912 | # CONFIG_SLUB_STATS is not set | ||
| 1913 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1914 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1915 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1916 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1917 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1918 | # CONFIG_PROVE_LOCKING is not set | ||
| 1919 | # CONFIG_LOCK_STAT is not set | ||
| 1920 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1921 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1922 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1923 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1924 | CONFIG_DEBUG_INFO=y | ||
| 1925 | # CONFIG_DEBUG_VM is not set | ||
| 1926 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1927 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1928 | # CONFIG_DEBUG_LIST is not set | ||
| 1929 | # CONFIG_DEBUG_SG is not set | ||
| 1930 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1931 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1932 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1933 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1934 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1935 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1936 | # CONFIG_FAULT_INJECTION is not set | ||
| 1937 | # CONFIG_LATENCYTOP is not set | ||
| 1938 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 1939 | # CONFIG_PAGE_POISONING is not set | ||
| 1940 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1941 | CONFIG_TRACING_SUPPORT=y | ||
| 1942 | |||
| 1943 | # | ||
| 1944 | # Tracers | ||
| 1945 | # | ||
| 1946 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1947 | # CONFIG_SCHED_TRACER is not set | ||
| 1948 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1949 | # CONFIG_EVENT_TRACER is not set | ||
| 1950 | # CONFIG_BOOT_TRACER is not set | ||
| 1951 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1952 | # CONFIG_STACK_TRACER is not set | ||
| 1953 | # CONFIG_KMEMTRACE is not set | ||
| 1954 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 1955 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 1956 | # CONFIG_DYNAMIC_DEBUG is not set | ||
| 1957 | # CONFIG_SAMPLES is not set | ||
| 1958 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1959 | # CONFIG_KGDB is not set | ||
| 1960 | CONFIG_ARM_UNWIND=y | ||
| 1961 | CONFIG_DEBUG_USER=y | ||
| 1962 | # CONFIG_DEBUG_ERRORS is not set | ||
| 1963 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1964 | # CONFIG_DEBUG_LL is not set | ||
| 1965 | CONFIG_DEBUG_S3C_UART=0 | ||
| 1966 | |||
| 1967 | # | ||
| 1968 | # Security options | ||
| 1969 | # | ||
| 1970 | CONFIG_KEYS=y | ||
| 1971 | # CONFIG_KEYS_DEBUG_PROC_KEYS is not set | ||
| 1972 | # CONFIG_SECURITY is not set | ||
| 1973 | # CONFIG_SECURITYFS is not set | ||
| 1974 | CONFIG_SECURITY_FILE_CAPABILITIES=y | ||
| 1975 | CONFIG_CRYPTO=y | ||
| 1976 | |||
| 1977 | # | ||
| 1978 | # Crypto core or helper | ||
| 1979 | # | ||
| 1980 | CONFIG_CRYPTO_FIPS=y | ||
| 1981 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1982 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1983 | CONFIG_CRYPTO_AEAD=m | ||
| 1984 | CONFIG_CRYPTO_AEAD2=y | ||
| 1985 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1986 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1987 | CONFIG_CRYPTO_HASH=y | ||
| 1988 | CONFIG_CRYPTO_HASH2=y | ||
| 1989 | CONFIG_CRYPTO_RNG=m | ||
| 1990 | CONFIG_CRYPTO_RNG2=y | ||
| 1991 | CONFIG_CRYPTO_PCOMP=y | ||
| 1992 | CONFIG_CRYPTO_MANAGER=y | ||
| 1993 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1994 | CONFIG_CRYPTO_GF128MUL=m | ||
| 1995 | CONFIG_CRYPTO_NULL=m | ||
| 1996 | CONFIG_CRYPTO_WORKQUEUE=y | ||
| 1997 | CONFIG_CRYPTO_CRYPTD=m | ||
| 1998 | CONFIG_CRYPTO_AUTHENC=m | ||
| 1999 | CONFIG_CRYPTO_TEST=m | ||
| 2000 | |||
| 2001 | # | ||
| 2002 | # Authenticated Encryption with Associated Data | ||
| 2003 | # | ||
| 2004 | CONFIG_CRYPTO_CCM=m | ||
| 2005 | CONFIG_CRYPTO_GCM=m | ||
| 2006 | CONFIG_CRYPTO_SEQIV=m | ||
| 2007 | |||
| 2008 | # | ||
| 2009 | # Block modes | ||
| 2010 | # | ||
| 2011 | CONFIG_CRYPTO_CBC=y | ||
| 2012 | CONFIG_CRYPTO_CTR=m | ||
| 2013 | CONFIG_CRYPTO_CTS=m | ||
| 2014 | CONFIG_CRYPTO_ECB=y | ||
| 2015 | CONFIG_CRYPTO_LRW=m | ||
| 2016 | CONFIG_CRYPTO_PCBC=m | ||
| 2017 | CONFIG_CRYPTO_XTS=m | ||
| 2018 | |||
| 2019 | # | ||
| 2020 | # Hash modes | ||
| 2021 | # | ||
| 2022 | CONFIG_CRYPTO_HMAC=y | ||
| 2023 | CONFIG_CRYPTO_XCBC=m | ||
| 2024 | |||
| 2025 | # | ||
| 2026 | # Digest | ||
| 2027 | # | ||
| 2028 | CONFIG_CRYPTO_CRC32C=m | ||
| 2029 | CONFIG_CRYPTO_MD4=m | ||
| 2030 | CONFIG_CRYPTO_MD5=y | ||
| 2031 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
| 2032 | CONFIG_CRYPTO_RMD128=m | ||
| 2033 | CONFIG_CRYPTO_RMD160=m | ||
| 2034 | CONFIG_CRYPTO_RMD256=m | ||
| 2035 | CONFIG_CRYPTO_RMD320=m | ||
| 2036 | CONFIG_CRYPTO_SHA1=m | ||
| 2037 | CONFIG_CRYPTO_SHA256=m | ||
| 2038 | CONFIG_CRYPTO_SHA512=m | ||
| 2039 | CONFIG_CRYPTO_TGR192=m | ||
| 2040 | CONFIG_CRYPTO_WP512=m | ||
| 2041 | |||
| 2042 | # | ||
| 2043 | # Ciphers | ||
| 2044 | # | ||
| 2045 | CONFIG_CRYPTO_AES=y | ||
| 2046 | CONFIG_CRYPTO_ANUBIS=m | ||
| 2047 | CONFIG_CRYPTO_ARC4=y | ||
| 2048 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 2049 | CONFIG_CRYPTO_CAMELLIA=m | ||
| 2050 | CONFIG_CRYPTO_CAST5=m | ||
| 2051 | CONFIG_CRYPTO_CAST6=m | ||
| 2052 | CONFIG_CRYPTO_DES=y | ||
| 2053 | CONFIG_CRYPTO_FCRYPT=m | ||
| 2054 | CONFIG_CRYPTO_KHAZAD=m | ||
| 2055 | CONFIG_CRYPTO_SALSA20=m | ||
| 2056 | CONFIG_CRYPTO_SEED=m | ||
| 2057 | CONFIG_CRYPTO_SERPENT=m | ||
| 2058 | CONFIG_CRYPTO_TEA=m | ||
| 2059 | CONFIG_CRYPTO_TWOFISH=m | ||
| 2060 | CONFIG_CRYPTO_TWOFISH_COMMON=m | ||
| 2061 | |||
| 2062 | # | ||
| 2063 | # Compression | ||
| 2064 | # | ||
| 2065 | CONFIG_CRYPTO_DEFLATE=m | ||
| 2066 | CONFIG_CRYPTO_ZLIB=m | ||
| 2067 | CONFIG_CRYPTO_LZO=m | ||
| 2068 | |||
| 2069 | # | ||
| 2070 | # Random Number Generation | ||
| 2071 | # | ||
| 2072 | CONFIG_CRYPTO_ANSI_CPRNG=m | ||
| 2073 | CONFIG_CRYPTO_HW=y | ||
| 2074 | # CONFIG_BINARY_PRINTF is not set | ||
| 2075 | |||
| 2076 | # | ||
| 2077 | # Library routines | ||
| 2078 | # | ||
| 2079 | CONFIG_BITREVERSE=y | ||
| 2080 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 2081 | CONFIG_CRC_CCITT=m | ||
| 2082 | CONFIG_CRC16=m | ||
| 2083 | CONFIG_CRC_T10DIF=y | ||
| 2084 | CONFIG_CRC_ITU_T=y | ||
| 2085 | CONFIG_CRC32=y | ||
| 2086 | CONFIG_CRC7=y | ||
| 2087 | CONFIG_LIBCRC32C=m | ||
| 2088 | CONFIG_ZLIB_INFLATE=y | ||
| 2089 | CONFIG_ZLIB_DEFLATE=y | ||
| 2090 | CONFIG_LZO_COMPRESS=m | ||
| 2091 | CONFIG_LZO_DECOMPRESS=m | ||
| 2092 | CONFIG_DECOMPRESS_GZIP=y | ||
| 2093 | CONFIG_DECOMPRESS_BZIP2=y | ||
| 2094 | CONFIG_DECOMPRESS_LZMA=y | ||
| 2095 | CONFIG_HAS_IOMEM=y | ||
| 2096 | CONFIG_HAS_DMA=y | ||
| 2097 | CONFIG_NLATTR=y | ||
| @@ -260,6 +260,7 @@ CONFIG_MACH_NEXCODER_2440=y · 259 unmodified lines | |||
| 260 | CONFIG_SMDK2440_CPU2440=y | 260 | CONFIG_SMDK2440_CPU2440=y |
| 261 | CONFIG_MACH_AT2440EVB=y | 261 | CONFIG_MACH_AT2440EVB=y |
| 262 | CONFIG_CPU_S3C2442=y | 262 | CONFIG_CPU_S3C2442=y |
| 263 | CONFIG_MACH_MINI2440=y | ||
| 263 | 264 | ||
| 264 | # | 265 | # |
| 265 | # S3C2442 Machines | 266 | # S3C2442 Machines |
| @@ -2298,7 +2299,6 @@ CONFIG_DEBUG_ERRORS=y · 2032 unmodified lines | |||
| 2298 | # CONFIG_DEBUG_STACK_USAGE is not set | 2299 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 2299 | CONFIG_DEBUG_LL=y | 2300 | CONFIG_DEBUG_LL=y |
| 2300 | # CONFIG_DEBUG_ICEDCC is not set | 2301 | # CONFIG_DEBUG_ICEDCC is not set |
| 2301 | CONFIG_DEBUG_S3C_PORT=y | ||
| 2302 | CONFIG_DEBUG_S3C_UART=0 | 2302 | CONFIG_DEBUG_S3C_UART=0 |
| 2303 | 2303 | ||
| 2304 | # | 2304 | # |
| @@ -816,7 +816,6 @@ CONFIG_DEBUG_ERRORS=y · 815 unmodified lines | |||
| 816 | # CONFIG_DEBUG_STACK_USAGE is not set | 816 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 817 | CONFIG_DEBUG_LL=y | 817 | CONFIG_DEBUG_LL=y |
| 818 | # CONFIG_DEBUG_ICEDCC is not set | 818 | # CONFIG_DEBUG_ICEDCC is not set |
| 819 | CONFIG_DEBUG_S3C_PORT=y | ||
| 820 | CONFIG_DEBUG_S3C_UART=0 | 819 | CONFIG_DEBUG_S3C_UART=0 |
| 821 | 820 | ||
| 822 | # | 821 | # |
| @@ -857,7 +857,6 @@ CONFIG_DEBUG_ERRORS=y · 856 unmodified lines | |||
| 857 | # CONFIG_DEBUG_STACK_USAGE is not set | 857 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 858 | CONFIG_DEBUG_LL=y | 858 | CONFIG_DEBUG_LL=y |
| 859 | # CONFIG_DEBUG_ICEDCC is not set | 859 | # CONFIG_DEBUG_ICEDCC is not set |
| 860 | # CONFIG_DEBUG_S3C_PORT is not set | ||
| 861 | CONFIG_DEBUG_S3C_UART=0 | 860 | CONFIG_DEBUG_S3C_UART=0 |
| 862 | 861 | ||
| 863 | # | 862 | # |
| @@ -12,7 +12,7 @@ · 11 unmodified lines | |||
| 12 | 12 | ||
| 13 | /* PAGE_SHIFT determines the page size */ | 13 | /* PAGE_SHIFT determines the page size */ |
| 14 | #define PAGE_SHIFT 12 | 14 | #define PAGE_SHIFT 12 |
| 15 | #define PAGE_SIZE (1UL << PAGE_SHIFT) | 15 | #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) |
| 16 | #define PAGE_MASK (~(PAGE_SIZE-1)) | 16 | #define PAGE_MASK (~(PAGE_SIZE-1)) |
| 17 | 17 | ||
| 18 | #ifndef __ASSEMBLY__ | 18 | #ifndef __ASSEMBLY__ |
| @@ -389,6 +389,8 @@ · 388 unmodified lines | |||
| 389 | #define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) | 389 | #define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) |
| 390 | #define __NR_preadv (__NR_SYSCALL_BASE+361) | 390 | #define __NR_preadv (__NR_SYSCALL_BASE+361) |
| 391 | #define __NR_pwritev (__NR_SYSCALL_BASE+362) | 391 | #define __NR_pwritev (__NR_SYSCALL_BASE+362) |
| 392 | #define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) | ||
| 393 | #define __NR_perf_counter_open (__NR_SYSCALL_BASE+364) | ||
| 392 | 394 | ||
| 393 | /* | 395 | /* |
| 394 | * The following SWIs are ARM private. | 396 | * The following SWIs are ARM private. |
| @@ -372,6 +372,8 @@ · 371 unmodified lines | |||
| 372 | /* 360 */ CALL(sys_inotify_init1) | 372 | /* 360 */ CALL(sys_inotify_init1) |
| 373 | CALL(sys_preadv) | 373 | CALL(sys_preadv) |
| 374 | CALL(sys_pwritev) | 374 | CALL(sys_pwritev) |
| 375 | CALL(sys_rt_tgsigqueueinfo) | ||
| 376 | CALL(sys_perf_counter_open) | ||
| 375 | #ifndef syscalls_counted | 377 | #ifndef syscalls_counted |
| 376 | .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls | 378 | .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls |
| 377 | #define syscalls_counted | 379 | #define syscalls_counted |
| @@ -98,17 +98,6 @@ unlock: · 97 unmodified lines | |||
| 98 | return 0; | 98 | return 0; |
| 99 | } | 99 | } |
| 100 | 100 | ||
| 101 | /* Handle bad interrupts */ | ||
| 102 | static struct irq_desc bad_irq_desc = { | ||
| 103 | .handle_irq = handle_bad_irq, | ||
| 104 | .lock = __SPIN_LOCK_UNLOCKED(bad_irq_desc.lock), | ||
| 105 | }; | ||
| 106 | |||
| 107 | #ifdef CONFIG_CPUMASK_OFFSTACK | ||
| 108 | /* We are not allocating bad_irq_desc.affinity or .pending_mask */ | ||
| 109 | #error "ARM architecture does not support CONFIG_CPUMASK_OFFSTACK." | ||
| 110 | #endif | ||
| 111 | |||
| 112 | /* | 101 | /* |
| 113 | * do_IRQ handles all hardware IRQ's. Decoded IRQs should not | 102 | * do_IRQ handles all hardware IRQ's. Decoded IRQs should not |
| 114 | * come via this function. Instead, they should provide their | 103 | * come via this function. Instead, they should provide their |
| @@ -124,10 +113,13 @@ asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs) · 9 unmodified lines | |||
| 124 | * Some hardware gives randomly wrong interrupts. Rather | 113 | * Some hardware gives randomly wrong interrupts. Rather |
| 125 | * than crashing, do something sensible. | 114 | * than crashing, do something sensible. |
| 126 | */ | 115 | */ |
| 127 | if (irq >= NR_IRQS) | 116 | if (unlikely(irq >= NR_IRQS)) { |
| 128 | handle_bad_irq(irq, &bad_irq_desc); | 117 | if (printk_ratelimit()) |
| 129 | else | 118 | printk(KERN_WARNING "Bad IRQ%u\n", irq); |
| 119 | ack_bad_irq(irq); | ||
| 120 | } else { | ||
| 130 | generic_handle_irq(irq); | 121 | generic_handle_irq(irq); |
| 122 | } | ||
| 131 | 123 | ||
| 132 | /* AT91 specific workaround */ | 124 | /* AT91 specific workaround */ |
| 133 | irq_finish(irq); | 125 | irq_finish(irq); |
| @@ -165,10 +157,6 @@ void __init init_IRQ(void) · 31 unmodified lines | |||
| 165 | for (irq = 0; irq < NR_IRQS; irq++) | 157 | for (irq = 0; irq < NR_IRQS; irq++) |
| 166 | irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE; | 158 | irq_desc[irq].status |= IRQ_NOREQUEST | IRQ_NOPROBE; |
| 167 | 159 | ||
| 168 | #ifdef CONFIG_SMP | ||
| 169 | cpumask_setall(bad_irq_desc.affinity); | ||
| 170 | bad_irq_desc.cpu = smp_processor_id(); | ||
| 171 | #endif | ||
| 172 | init_arch_irq(); | 160 | init_arch_irq(); |
| 173 | } | 161 | } |
| 174 | 162 | ||
| @@ -176,7 +164,7 @@ void __init init_IRQ(void) · 1 unmodified line | |||
| 176 | 164 | ||
| 177 | static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) | 165 | static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu) |
| 178 | { | 166 | { |
| 179 | pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu); | 167 | pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->node, cpu); |
| 180 | 168 | ||
| 181 | spin_lock_irq(&desc->lock); | 169 | spin_lock_irq(&desc->lock); |
| 182 | desc->chip->set_affinity(irq, cpumask_of(cpu)); | 170 | desc->chip->set_affinity(irq, cpumask_of(cpu)); |
| @@ -195,7 +183,7 @@ void migrate_irqs(void) · 12 unmodified lines | |||
| 195 | for (i = 0; i < NR_IRQS; i++) { | 183 | for (i = 0; i < NR_IRQS; i++) { |
| 196 | struct irq_desc *desc = irq_desc + i; | 184 | struct irq_desc *desc = irq_desc + i; |
| 197 | 185 | ||
| 198 | if (desc->cpu == cpu) { | 186 | if (desc->node == cpu) { |
| 199 | unsigned int newcpu = cpumask_any_and(desc->affinity, | 187 | unsigned int newcpu = cpumask_any_and(desc->affinity, |
| 200 | cpu_online_mask); | 188 | cpu_online_mask); |
| 201 | if (newcpu >= nr_cpu_ids) { | 189 | if (newcpu >= nr_cpu_ids) { |
| @@ -114,9 +114,6 @@ void arm_machine_restart(char mode, const char *cmd) · 113 unmodified lines | |||
| 114 | /* | 114 | /* |
| 115 | * Function pointers to optional machine specific functions | 115 | * Function pointers to optional machine specific functions |
| 116 | */ | 116 | */ |
| 117 | void (*pm_idle)(void); | ||
| 118 | EXPORT_SYMBOL(pm_idle); | ||
| 119 | |||
| 120 | void (*pm_power_off)(void); | 117 | void (*pm_power_off)(void); |
| 121 | EXPORT_SYMBOL(pm_power_off); | 118 | EXPORT_SYMBOL(pm_power_off); |
| 122 | 119 | ||
| @@ -130,20 +127,19 @@ EXPORT_SYMBOL_GPL(arm_pm_restart); · 7 unmodified lines | |||
| 130 | */ | 127 | */ |
| 131 | static void default_idle(void) | 128 | static void default_idle(void) |
| 132 | { | 129 | { |
| 133 | if (hlt_counter) | 130 | if (!need_resched()) |
| 134 | cpu_relax(); | 131 | arch_idle(); |
| 135 | else { | 132 | local_irq_enable(); |
| 136 | local_irq_disable(); | ||
| 137 | if (!need_resched()) | ||
| 138 | arch_idle(); | ||
| 139 | local_irq_enable(); | ||
| 140 | } | ||
| 141 | } | 133 | } |
| 142 | 134 | ||
| 135 | void (*pm_idle)(void) = default_idle; | ||
| 136 | EXPORT_SYMBOL(pm_idle); | ||
| 137 | |||
| 143 | /* | 138 | /* |
| 144 | * The idle thread. We try to conserve power, while trying to keep | 139 | * The idle thread, has rather strange semantics for calling pm_idle, |
| 145 | * overall latency low. The architecture specific idle is passed | 140 | * but this is what x86 does and we need to do the same, so that |
| 146 | * a value to indicate the level of "idleness" of the system. | 141 | * things like cpuidle get called in the same way. The only difference |
| 142 | * is that we always respect 'hlt_counter' to prevent low power idle. | ||
| 147 | */ | 143 | */ |
| 148 | void cpu_idle(void) | 144 | void cpu_idle(void) |
| 149 | { | 145 | { |
| @@ -151,21 +147,31 @@ void cpu_idle(void) · 1 unmodified line | |||
| 151 | 147 | ||
| 152 | /* endless idle loop with no priority at all */ | 148 | /* endless idle loop with no priority at all */ |
| 153 | while (1) { | 149 | while (1) { |
| 154 | void (*idle)(void) = pm_idle; | 150 | tick_nohz_stop_sched_tick(1); |
| 155 | 151 | leds_event(led_idle_start); | |
| 152 | while (!need_resched()) { | ||
| 156 | #ifdef CONFIG_HOTPLUG_CPU | 153 | #ifdef CONFIG_HOTPLUG_CPU |
| 157 | if (cpu_is_offline(smp_processor_id())) { | 154 | if (cpu_is_offline(smp_processor_id())) |
| 158 | leds_event(led_idle_start); | 155 | cpu_die(); |
| 159 | cpu_die(); | ||
| 160 | } | ||
| 161 | #endif | 156 | #endif |
| 162 | 157 | ||
| 163 | if (!idle) | 158 | local_irq_disable(); |
| 164 | idle = default_idle; | 159 | if (hlt_counter) { |
| 165 | leds_event(led_idle_start); | 160 | local_irq_enable(); |
| 166 | tick_nohz_stop_sched_tick(1); | 161 | cpu_relax(); |
| 167 | while (!need_resched()) | 162 | } else { |
| 168 | idle(); | 163 | stop_critical_timings(); |
| 164 | pm_idle(); | ||
| 165 | start_critical_timings(); | ||
| 166 | /* | ||
| 167 | * This will eventually be removed - pm_idle | ||
| 168 | * functions should always return with IRQs | ||
| 169 | * enabled. | ||
| 170 | */ | ||
| 171 | WARN_ON(irqs_disabled()); | ||
| 172 | local_irq_enable(); | ||
| 173 | } | ||
| 174 | } | ||
| 169 | leds_event(led_idle_end); | 175 | leds_event(led_idle_end); |
| 170 | tick_nohz_restart_sched_tick(); | 176 | tick_nohz_restart_sched_tick(); |
| 171 | preempt_enable_no_resched(); | 177 | preempt_enable_no_resched(); |
| @@ -352,6 +358,23 @@ asm( ".section .text\n" · 180 unmodified lines | |||
| 352 | " .size kernel_thread_helper, . - kernel_thread_helper\n" | 358 | " .size kernel_thread_helper, . - kernel_thread_helper\n" |
| 353 | " .previous"); | 359 | " .previous"); |
| 354 | 360 | ||
| 361 | #ifdef CONFIG_ARM_UNWIND | ||
| 362 | extern void kernel_thread_exit(long code); | ||
| 363 | asm( ".section .text\n" | ||
| 364 | " .align\n" | ||
| 365 | " .type kernel_thread_exit, #function\n" | ||
| 366 | "kernel_thread_exit:\n" | ||
| 367 | " .fnstart\n" | ||
| 368 | " .cantunwind\n" | ||
| 369 | " bl do_exit\n" | ||
| 370 | " nop\n" | ||
| 371 | " .fnend\n" | ||
| 372 | " .size kernel_thread_exit, . - kernel_thread_exit\n" | ||
| 373 | " .previous"); | ||
| 374 | #else | ||
| 375 | #define kernel_thread_exit do_exit | ||
| 376 | #endif | ||
| 377 | |||
| 355 | /* | 378 | /* |
| 356 | * Create a kernel thread. | 379 | * Create a kernel thread. |
| 357 | */ | 380 | */ |
| @@ -363,7 +386,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) · 5 unmodified lines | |||
| 363 | 386 | ||
| 364 | regs.ARM_r1 = (unsigned long)arg; | 387 | regs.ARM_r1 = (unsigned long)arg; |
| 365 | regs.ARM_r2 = (unsigned long)fn; | 388 | regs.ARM_r2 = (unsigned long)fn; |
| 366 | regs.ARM_r3 = (unsigned long)do_exit; | 389 | regs.ARM_r3 = (unsigned long)kernel_thread_exit; |
| 367 | regs.ARM_pc = (unsigned long)kernel_thread_helper; | 390 | regs.ARM_pc = (unsigned long)kernel_thread_helper; |
| 368 | regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE; | 391 | regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE; |
| 369 | 392 | ||
| @@ -212,7 +212,8 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) · 211 unmodified lines | |||
| 212 | ctrl->vrs[14] = *vsp++; | 212 | ctrl->vrs[14] = *vsp++; |
| 213 | ctrl->vrs[SP] = (unsigned long)vsp; | 213 | ctrl->vrs[SP] = (unsigned long)vsp; |
| 214 | } else if (insn == 0xb0) { | 214 | } else if (insn == 0xb0) { |
| 215 | ctrl->vrs[PC] = ctrl->vrs[LR]; | 215 | if (ctrl->vrs[PC] == 0) |
| 216 | ctrl->vrs[PC] = ctrl->vrs[LR]; | ||
| 216 | /* no further processing */ | 217 | /* no further processing */ |
| 217 | ctrl->entries = 0; | 218 | ctrl->entries = 0; |
| 218 | } else if (insn == 0xb1) { | 219 | } else if (insn == 0xb1) { |
| @@ -309,18 +310,20 @@ int unwind_frame(struct stackframe *frame) · 90 unmodified lines | |||
| 309 | } | 310 | } |
| 310 | 311 | ||
| 311 | while (ctrl.entries > 0) { | 312 | while (ctrl.entries > 0) { |
| 312 | int urc; | 313 | int urc = unwind_exec_insn(&ctrl); |
| 313 | |||
| 314 | if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high) | ||
| 315 | return -URC_FAILURE; | ||
| 316 | urc = unwind_exec_insn(&ctrl); | ||
| 317 | if (urc < 0) | 314 | if (urc < 0) |
| 318 | return urc; | 315 | return urc; |
| 316 | if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high) | ||
| 317 | return -URC_FAILURE; | ||
| 319 | } | 318 | } |
| 320 | 319 | ||
| 321 | if (ctrl.vrs[PC] == 0) | 320 | if (ctrl.vrs[PC] == 0) |
| 322 | ctrl.vrs[PC] = ctrl.vrs[LR]; | 321 | ctrl.vrs[PC] = ctrl.vrs[LR]; |
| 323 | 322 | ||
| 323 | /* check for infinite loop */ | ||
| 324 | if (frame->pc == ctrl.vrs[PC]) | ||
| 325 | return -URC_FAILURE; | ||
| 326 | |||
| 324 | frame->fp = ctrl.vrs[FP]; | 327 | frame->fp = ctrl.vrs[FP]; |
| 325 | frame->sp = ctrl.vrs[SP]; | 328 | frame->sp = ctrl.vrs[SP]; |
| 326 | frame->lr = ctrl.vrs[LR]; | 329 | frame->lr = ctrl.vrs[LR]; |
| @@ -332,7 +335,6 @@ int unwind_frame(struct stackframe *frame) · 5 unmodified lines | |||
| 332 | void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) | 335 | void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) |
| 333 | { | 336 | { |
| 334 | struct stackframe frame; | 337 | struct stackframe frame; |
| 335 | unsigned long high, low; | ||
| 336 | register unsigned long current_sp asm ("sp"); | 338 | register unsigned long current_sp asm ("sp"); |
| 337 | 339 | ||
| 338 | pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); | 340 | pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); |
| @@ -362,9 +364,6 @@ void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) · 23 unmodified lines | |||
| 362 | frame.pc = thread_saved_pc(tsk); | 364 | frame.pc = thread_saved_pc(tsk); |
| 363 | } | 365 | } |
| 364 | 366 | ||
| 365 | low = frame.sp & ~(THREAD_SIZE - 1); | ||
| 366 | high = low + THREAD_SIZE; | ||
| 367 | |||
| 368 | while (1) { | 367 | while (1) { |
| 369 | int urc; | 368 | int urc; |
| 370 | unsigned long where = frame.pc; | 369 | unsigned long where = frame.pc; |
| @@ -6,6 +6,7 @@ · 5 unmodified lines | |||
| 6 | #include <asm-generic/vmlinux.lds.h> | 6 | #include <asm-generic/vmlinux.lds.h> |
| 7 | #include <asm/thread_info.h> | 7 | #include <asm/thread_info.h> |
| 8 | #include <asm/memory.h> | 8 | #include <asm/memory.h> |
| 9 | #include <asm/page.h> | ||
| 9 | 10 | ||
| 10 | OUTPUT_ARCH(arm) | 11 | OUTPUT_ARCH(arm) |
| 11 | ENTRY(stext) | 12 | ENTRY(stext) |
| @@ -63,7 +64,7 @@ SECTIONS · 51 unmodified lines | |||
| 63 | usr/built-in.o(.init.ramfs) | 64 | usr/built-in.o(.init.ramfs) |
| 64 | __initramfs_end = .; | 65 | __initramfs_end = .; |
| 65 | #endif | 66 | #endif |
| 66 | . = ALIGN(4096); | 67 | . = ALIGN(PAGE_SIZE); |
| 67 | __per_cpu_load = .; | 68 | __per_cpu_load = .; |
| 68 | __per_cpu_start = .; | 69 | __per_cpu_start = .; |
| 69 | *(.data.percpu.page_aligned) | 70 | *(.data.percpu.page_aligned) |
| @@ -73,7 +74,7 @@ SECTIONS · 3 unmodified lines | |||
| 73 | #ifndef CONFIG_XIP_KERNEL | 74 | #ifndef CONFIG_XIP_KERNEL |
| 74 | __init_begin = _stext; | 75 | __init_begin = _stext; |
| 75 | INIT_DATA | 76 | INIT_DATA |
| 76 | . = ALIGN(4096); | 77 | . = ALIGN(PAGE_SIZE); |
| 77 | __init_end = .; | 78 | __init_end = .; |
| 78 | #endif | 79 | #endif |
| 79 | } | 80 | } |
| @@ -85,6 +86,14 @@ SECTIONS · 5 unmodified lines | |||
| 85 | *(.discard) | 86 | *(.discard) |
| 86 | *(.ARM.exidx.exit.text) | 87 | *(.ARM.exidx.exit.text) |
| 87 | *(.ARM.extab.exit.text) | 88 | *(.ARM.extab.exit.text) |
| 89 | #ifndef CONFIG_HOTPLUG_CPU | ||
| 90 | *(.ARM.exidx.cpuexit.text) | ||
| 91 | *(.ARM.extab.cpuexit.text) | ||
| 92 | #endif | ||
| 93 | #ifndef CONFIG_HOTPLUG | ||
| 94 | *(.ARM.exidx.devexit.text) | ||
| 95 | *(.ARM.extab.devexit.text) | ||
| 96 | #endif | ||
| 88 | #ifndef CONFIG_MMU | 97 | #ifndef CONFIG_MMU |
| 89 | *(.fixup) | 98 | *(.fixup) |
| 90 | *(__ex_table) | 99 | *(__ex_table) |
| @@ -111,7 +120,7 @@ SECTIONS · 20 unmodified lines | |||
| 111 | *(.got) /* Global offset table */ | 120 | *(.got) /* Global offset table */ |
| 112 | } | 121 | } |
| 113 | 122 | ||
| 114 | RODATA | 123 | RO_DATA(PAGE_SIZE) |
| 115 | 124 | ||
| 116 | _etext = .; /* End of text and rodata section */ | 125 | _etext = .; /* End of text and rodata section */ |
| 117 | 126 | ||
| @@ -151,17 +160,17 @@ SECTIONS · 33 unmodified lines | |||
| 151 | *(.data.init_task) | 160 | *(.data.init_task) |
| 152 | 161 | ||
| 153 | #ifdef CONFIG_XIP_KERNEL | 162 | #ifdef CONFIG_XIP_KERNEL |
| 154 | . = ALIGN(4096); | 163 | . = ALIGN(PAGE_SIZE); |
| 155 | __init_begin = .; | 164 | __init_begin = .; |
| 156 | INIT_DATA | 165 | INIT_DATA |
| 157 | . = ALIGN(4096); | 166 | . = ALIGN(PAGE_SIZE); |
| 158 | __init_end = .; | 167 | __init_end = .; |
| 159 | #endif | 168 | #endif |
| 160 | 169 | ||
| 161 | . = ALIGN(4096); | 170 | . = ALIGN(PAGE_SIZE); |
| 162 | __nosave_begin = .; | 171 | __nosave_begin = .; |
| 163 | *(.data.nosave) | 172 | *(.data.nosave) |
| 164 | . = ALIGN(4096); | 173 | . = ALIGN(PAGE_SIZE); |
| 165 | __nosave_end = .; | 174 | __nosave_end = .; |
| 166 | 175 | ||
| 167 | /* | 176 | /* |
| @@ -24,6 +24,8 @@ · 23 unmodified lines | |||
| 24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/spi/spi.h> | 25 | #include <linux/spi/spi.h> |
| 26 | #include <linux/spi/at73c213.h> | 26 | #include <linux/spi/at73c213.h> |
| 27 | #include <linux/gpio_keys.h> | ||
| 28 | #include <linux/input.h> | ||
| 27 | #include <linux/clk.h> | 29 | #include <linux/clk.h> |
| 28 | 30 | ||
| 29 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| @@ -218,6 +220,56 @@ static struct gpio_led ek_leds[] = { · 188 unmodified lines | |||
| 218 | } | 220 | } |
| 219 | }; | 221 | }; |
| 220 | 222 | ||
| 223 | |||
| 224 | /* | ||
| 225 | * GPIO Buttons | ||
| 226 | */ | ||
| 227 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 228 | static struct gpio_keys_button ek_buttons[] = { | ||
| 229 | { | ||
| 230 | .gpio = AT91_PIN_PA30, | ||
| 231 | .code = BTN_3, | ||
| 232 | .desc = "Button 3", | ||
| 233 | .active_low = 1, | ||
| 234 | .wakeup = 1, | ||
| 235 | }, | ||
| 236 | { | ||
| 237 | .gpio = AT91_PIN_PA31, | ||
| 238 | .code = BTN_4, | ||
| 239 | .desc = "Button 4", | ||
| 240 | .active_low = 1, | ||
| 241 | .wakeup = 1, | ||
| 242 | } | ||
| 243 | }; | ||
| 244 | |||
| 245 | static struct gpio_keys_platform_data ek_button_data = { | ||
| 246 | .buttons = ek_buttons, | ||
| 247 | .nbuttons = ARRAY_SIZE(ek_buttons), | ||
| 248 | }; | ||
| 249 | |||
| 250 | static struct platform_device ek_button_device = { | ||
| 251 | .name = "gpio-keys", | ||
| 252 | .id = -1, | ||
| 253 | .num_resources = 0, | ||
| 254 | .dev = { | ||
| 255 | .platform_data = &ek_button_data, | ||
| 256 | } | ||
| 257 | }; | ||
| 258 | |||
| 259 | static void __init ek_add_device_buttons(void) | ||
| 260 | { | ||
| 261 | at91_set_gpio_input(AT91_PIN_PA30, 1); /* btn3 */ | ||
| 262 | at91_set_deglitch(AT91_PIN_PA30, 1); | ||
| 263 | at91_set_gpio_input(AT91_PIN_PA31, 1); /* btn4 */ | ||
| 264 | at91_set_deglitch(AT91_PIN_PA31, 1); | ||
| 265 | |||
| 266 | platform_device_register(&ek_button_device); | ||
| 267 | } | ||
| 268 | #else | ||
| 269 | static void __init ek_add_device_buttons(void) {} | ||
| 270 | #endif | ||
| 271 | |||
| 272 | |||
| 221 | static struct i2c_board_info __initdata ek_i2c_devices[] = { | 273 | static struct i2c_board_info __initdata ek_i2c_devices[] = { |
| 222 | { | 274 | { |
| 223 | I2C_BOARD_INFO("24c512", 0x50), | 275 | I2C_BOARD_INFO("24c512", 0x50), |
| @@ -245,6 +297,8 @@ static void __init ek_board_init(void) · 21 unmodified lines | |||
| 245 | at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); | 297 | at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); |
| 246 | /* LEDs */ | 298 | /* LEDs */ |
| 247 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); | 299 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); |
| 300 | /* Push Buttons */ | ||
| 301 | ek_add_device_buttons(); | ||
| 248 | /* PCK0 provides MCLK to the WM8731 */ | 302 | /* PCK0 provides MCLK to the WM8731 */ |
| 249 | at91_set_B_periph(AT91_PIN_PC1, 0); | 303 | at91_set_B_periph(AT91_PIN_PC1, 0); |
| 250 | /* SSC (for WM8731) */ | 304 | /* SSC (for WM8731) */ |
| @@ -186,19 +186,21 @@ static struct fb_monspecs at91fb_default_monspecs = { · 185 unmodified lines | |||
| 186 | static void at91_lcdc_power_control(int on) | 186 | static void at91_lcdc_power_control(int on) |
| 187 | { | 187 | { |
| 188 | if (on) | 188 | if (on) |
| 189 | at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ | 189 | at91_set_gpio_value(AT91_PIN_PC1, 0); /* power up */ |
| 190 | else | 190 | else |
| 191 | at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ | 191 | at91_set_gpio_value(AT91_PIN_PC1, 1); /* power down */ |
| 192 | } | 192 | } |
| 193 | 193 | ||
| 194 | /* Driver datas */ | 194 | /* Driver datas */ |
| 195 | static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | 195 | static struct atmel_lcdfb_info __initdata ek_lcdc_data = { |
| 196 | .lcdcon_is_backlight = true, | ||
| 196 | .default_bpp = 16, | 197 | .default_bpp = 16, |
| 197 | .default_dmacon = ATMEL_LCDC_DMAEN, | 198 | .default_dmacon = ATMEL_LCDC_DMAEN, |
| 198 | .default_lcdcon2 = AT91SAM9RL_DEFAULT_LCDCON2, | 199 | .default_lcdcon2 = AT91SAM9RL_DEFAULT_LCDCON2, |
| 199 | .default_monspecs = &at91fb_default_monspecs, | 200 | .default_monspecs = &at91fb_default_monspecs, |
| 200 | .atmel_lcdfb_power_control = at91_lcdc_power_control, | 201 | .atmel_lcdfb_power_control = at91_lcdc_power_control, |
| 201 | .guard_time = 1, | 202 | .guard_time = 1, |
| 203 | .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, | ||
| 202 | }; | 204 | }; |
| 203 | 205 | ||
| 204 | #else | 206 | #else |
| @@ -68,10 +68,14 @@ struct davinci_nand_pdata { /* platform_data */ · 67 unmodified lines | |||
| 68 | 68 | ||
| 69 | /* none == NAND_ECC_NONE (strongly *not* advised!!) | 69 | /* none == NAND_ECC_NONE (strongly *not* advised!!) |
| 70 | * soft == NAND_ECC_SOFT | 70 | * soft == NAND_ECC_SOFT |
| 71 | * 1-bit == NAND_ECC_HW | 71 | * else == NAND_ECC_HW, according to ecc_bits |
| 72 | * 4-bit == NAND_ECC_HW_SYNDROME (not on all chips) | 72 | * |
| 73 | * All DaVinci-family chips support 1-bit hardware ECC. | ||
| 74 | * Newer ones also support 4-bit ECC, but are awkward | ||
| 75 | * using it with large page chips. | ||
| 73 | */ | 76 | */ |
| 74 | nand_ecc_modes_t ecc_mode; | 77 | nand_ecc_modes_t ecc_mode; |
| 78 | u8 ecc_bits; | ||
| 75 | 79 | ||
| 76 | /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ | 80 | /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ |
| 77 | unsigned options; | 81 | unsigned options; |
| @@ -36,7 +36,6 @@ · 35 unmodified lines | |||
| 36 | #include <mach/hwa742.h> | 36 | #include <mach/hwa742.h> |
| 37 | #include <mach/lcd_mipid.h> | 37 | #include <mach/lcd_mipid.h> |
| 38 | #include <mach/mmc.h> | 38 | #include <mach/mmc.h> |
| 39 | #include <mach/usb.h> | ||
| 40 | #include <mach/clock.h> | 39 | #include <mach/clock.h> |
| 41 | 40 | ||
| 42 | #define ADS7846_PENDOWN_GPIO 15 | 41 | #define ADS7846_PENDOWN_GPIO 15 |
| @@ -205,9 +204,11 @@ static int nokia770_mmc_get_cover_state(struct device *dev, int slot) · 162 unmodified lines | |||
| 205 | static struct omap_mmc_platform_data nokia770_mmc2_data = { | 204 | static struct omap_mmc_platform_data nokia770_mmc2_data = { |
| 206 | .nr_slots = 1, | 205 | .nr_slots = 1, |
| 207 | .dma_mask = 0xffffffff, | 206 | .dma_mask = 0xffffffff, |
| 207 | .max_freq = 12000000, | ||
| 208 | .slots[0] = { | 208 | .slots[0] = { |
| 209 | .set_power = nokia770_mmc_set_power, | 209 | .set_power = nokia770_mmc_set_power, |
| 210 | .get_cover_state = nokia770_mmc_get_cover_state, | 210 | .get_cover_state = nokia770_mmc_get_cover_state, |
| 211 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | ||
| 211 | .name = "mmcblk", | 212 | .name = "mmcblk", |
| 212 | }, | 213 | }, |
| 213 | }; | 214 | }; |
| @@ -203,5 +203,5 @@ module_exit(omap1_mbox_exit); · 202 unmodified lines | |||
| 203 | 203 | ||
| 204 | MODULE_LICENSE("GPL v2"); | 204 | MODULE_LICENSE("GPL v2"); |
| 205 | MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions"); | 205 | MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions"); |
| 206 | MODULE_AUTHOR("Hiroshi DOYU" <Hiroshi.DOYU@nokia.com>); | 206 | MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); |
| 207 | MODULE_ALIAS("platform:omap1-mailbox"); | 207 | MODULE_ALIAS("platform:omap1-mailbox"); |
| @@ -362,6 +362,7 @@ static struct omap_onenand_platform_data board_onenand_data = { · 361 unmodified lines | |||
| 362 | .gpio_irq = 65, | 362 | .gpio_irq = 65, |
| 363 | .parts = onenand_partitions, | 363 | .parts = onenand_partitions, |
| 364 | .nr_parts = ARRAY_SIZE(onenand_partitions), | 364 | .nr_parts = ARRAY_SIZE(onenand_partitions), |
| 365 | .flags = ONENAND_SYNC_READWRITE, | ||
| 365 | }; | 366 | }; |
| 366 | 367 | ||
| 367 | static void __init board_onenand_init(void) | 368 | static void __init board_onenand_init(void) |
| @@ -302,7 +302,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) · 301 unmodified lines | |||
| 302 | udelay(1); | 302 | udelay(1); |
| 303 | } | 303 | } |
| 304 | 304 | ||
| 305 | if (i < MAX_CLOCK_ENABLE_WAIT) | 305 | if (i <= MAX_CLOCK_ENABLE_WAIT) |
| 306 | pr_debug("Clock %s stable after %d loops\n", name, i); | 306 | pr_debug("Clock %s stable after %d loops\n", name, i); |
| 307 | else | 307 | else |
| 308 | printk(KERN_ERR "Clock %s didn't enable in %d tries\n", | 308 | printk(KERN_ERR "Clock %s didn't enable in %d tries\n", |
| @@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = { · 285 unmodified lines | |||
| 286 | 286 | ||
| 287 | #define MIN_SDRC_DLL_LOCK_FREQ 83000000 | 287 | #define MIN_SDRC_DLL_LOCK_FREQ 83000000 |
| 288 | 288 | ||
| 289 | #define CYCLES_PER_MHZ 1000000 | ||
| 290 | |||
| 291 | /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ | ||
| 292 | #define SDRC_MPURATE_SCALE 8 | ||
| 293 | |||
| 294 | /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ | ||
| 295 | #define SDRC_MPURATE_BASE_SHIFT 9 | ||
| 296 | |||
| 297 | /* | ||
| 298 | * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at | ||
| 299 | * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize | ||
| 300 | */ | ||
| 301 | #define SDRC_MPURATE_LOOPS 96 | ||
| 302 | |||
| 289 | /** | 303 | /** |
| 290 | * omap3_dpll_recalc - recalculate DPLL rate | 304 | * omap3_dpll_recalc - recalculate DPLL rate |
| 291 | * @clk: DPLL struct clk | 305 | * @clk: DPLL struct clk |
| @@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) · 417 unmodified lines | |||
| 709 | { | 723 | { |
| 710 | u32 new_div = 0; | 724 | u32 new_div = 0; |
| 711 | u32 unlock_dll = 0; | 725 | u32 unlock_dll = 0; |
| 712 | unsigned long validrate, sdrcrate; | 726 | u32 c; |
| 727 | unsigned long validrate, sdrcrate, mpurate; | ||
| 713 | struct omap_sdrc_params *sp; | 728 | struct omap_sdrc_params *sp; |
| 714 | 729 | ||
| 715 | if (!clk || !rate) | 730 | if (!clk || !rate) |
| @@ -718,18 +733,15 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) · 2 unmodified lines | |||
| 718 | if (clk != &dpll3_m2_ck) | 733 | if (clk != &dpll3_m2_ck) |
| 719 | return -EINVAL; | 734 | return -EINVAL; |
| 720 | 735 | ||
| 721 | if (rate == clk->rate) | ||
| 722 | return 0; | ||
| 723 | |||
| 724 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | 736 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); |
| 725 | if (validrate != rate) | 737 | if (validrate != rate) |
| 726 | return -EINVAL; | 738 | return -EINVAL; |
| 727 | 739 | ||
| 728 | sdrcrate = sdrc_ick.rate; | 740 | sdrcrate = sdrc_ick.rate; |
| 729 | if (rate > clk->rate) | 741 | if (rate > clk->rate) |
| 730 | sdrcrate <<= ((rate / clk->rate) - 1); | 742 | sdrcrate <<= ((rate / clk->rate) >> 1); |
| 731 | else | 743 | else |
| 732 | sdrcrate >>= ((clk->rate / rate) - 1); | 744 | sdrcrate >>= ((clk->rate / rate) >> 1); |
| 733 | 745 | ||
| 734 | sp = omap2_sdrc_get_params(sdrcrate); | 746 | sp = omap2_sdrc_get_params(sdrcrate); |
| 735 | if (!sp) | 747 | if (!sp) |
| @@ -740,17 +752,25 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) · 4 unmodified lines | |||
| 740 | unlock_dll = 1; | 752 | unlock_dll = 1; |
| 741 | } | 753 | } |
| 742 | 754 | ||
| 755 | /* | ||
| 756 | * XXX This only needs to be done when the CPU frequency changes | ||
| 757 | */ | ||
| 758 | mpurate = arm_fck.rate / CYCLES_PER_MHZ; | ||
| 759 | c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; | ||
| 760 | c += 1; /* for safety */ | ||
| 761 | c *= SDRC_MPURATE_LOOPS; | ||
| 762 | c >>= SDRC_MPURATE_SCALE; | ||
| 763 | if (c == 0) | ||
| 764 | c = 1; | ||
| 765 | |||
| 743 | pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, | 766 | pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, |
| 744 | validrate); | 767 | validrate); |
| 745 | pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", | 768 | pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", |
| 746 | sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); | 769 | sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); |
| 747 | 770 | ||
| 748 | /* REVISIT: SRAM code doesn't support other M2 divisors yet */ | ||
| 749 | WARN_ON(new_div != 1 && new_div != 2); | ||
| 750 | |||
| 751 | /* REVISIT: Add SDRC_MR changing to this code also */ | ||
| 752 | omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, | 771 | omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, |
| 753 | sp->actim_ctrlb, new_div, unlock_dll); | 772 | sp->actim_ctrlb, new_div, unlock_dll, c, |
| 773 | sp->mr, rate > clk->rate); | ||
| 754 | 774 | ||
| 755 | return 0; | 775 | return 0; |
| 756 | } | 776 | } |
| @@ -31,6 +31,8 @@ static struct platform_device gpmc_onenand_device = { · 30 unmodified lines | |||
| 31 | static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) | 31 | static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) |
| 32 | { | 32 | { |
| 33 | struct gpmc_timings t; | 33 | struct gpmc_timings t; |
| 34 | u32 reg; | ||
| 35 | int err; | ||
| 34 | 36 | ||
| 35 | const int t_cer = 15; | 37 | const int t_cer = 15; |
| 36 | const int t_avdp = 12; | 38 | const int t_avdp = 12; |
| @@ -43,6 +45,11 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) · 6 unmodified lines | |||
| 43 | const int t_wpl = 40; | 45 | const int t_wpl = 40; |
| 44 | const int t_wph = 30; | 46 | const int t_wph = 30; |
| 45 | 47 | ||
| 48 | /* Ensure sync read and sync write are disabled */ | ||
| 49 | reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); | ||
| 50 | reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; | ||
| 51 | writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); | ||
| 52 | |||
| 46 | memset(&t, 0, sizeof(t)); | 53 | memset(&t, 0, sizeof(t)); |
| 47 | t.sync_clk = 0; | 54 | t.sync_clk = 0; |
| 48 | t.cs_on = 0; | 55 | t.cs_on = 0; |
| @@ -74,7 +81,16 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) · 25 unmodified lines | |||
| 74 | GPMC_CONFIG1_DEVICESIZE_16 | | 81 | GPMC_CONFIG1_DEVICESIZE_16 | |
| 75 | GPMC_CONFIG1_MUXADDDATA); | 82 | GPMC_CONFIG1_MUXADDDATA); |
| 76 | 83 | ||
| 77 | return gpmc_cs_set_timings(cs, &t); | 84 | err = gpmc_cs_set_timings(cs, &t); |
| 85 | if (err) | ||
| 86 | return err; | ||
| 87 | |||
| 88 | /* Ensure sync read and sync write are disabled */ | ||
| 89 | reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); | ||
| 90 | reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; | ||
| 91 | writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); | ||
| 92 | |||
| 93 | return 0; | ||
| 78 | } | 94 | } |
| 79 | 95 | ||
| 80 | static void set_onenand_cfg(void __iomem *onenand_base, int latency, | 96 | static void set_onenand_cfg(void __iomem *onenand_base, int latency, |
| @@ -124,7 +140,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, · 43 unmodified lines | |||
| 124 | } else if (cfg->flags & ONENAND_SYNC_READWRITE) { | 140 | } else if (cfg->flags & ONENAND_SYNC_READWRITE) { |
| 125 | sync_read = 1; | 141 | sync_read = 1; |
| 126 | sync_write = 1; | 142 | sync_write = 1; |
| 127 | } | 143 | } else |
| 144 | return omap2_onenand_set_async_mode(cs, onenand_base); | ||
| 128 | 145 | ||
| 129 | if (!freq) { | 146 | if (!freq) { |
| 130 | /* Very first call freq is not known */ | 147 | /* Very first call freq is not known */ |
| @@ -48,6 +48,28 @@ int omap_chip_is(struct omap_chip_id oci) · 47 unmodified lines | |||
| 48 | } | 48 | } |
| 49 | EXPORT_SYMBOL(omap_chip_is); | 49 | EXPORT_SYMBOL(omap_chip_is); |
| 50 | 50 | ||
| 51 | int omap_type(void) | ||
| 52 | { | ||
| 53 | u32 val = 0; | ||
| 54 | |||
| 55 | if (cpu_is_omap24xx()) | ||
| 56 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); | ||
| 57 | else if (cpu_is_omap34xx()) | ||
| 58 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); | ||
| 59 | else { | ||
| 60 | pr_err("Cannot detect omap type!\n"); | ||
| 61 | goto out; | ||
| 62 | } | ||
| 63 | |||
| 64 | val &= OMAP2_DEVICETYPE_MASK; | ||
| 65 | val >>= 8; | ||
| 66 | |||
| 67 | out: | ||
| 68 | return val; | ||
| 69 | } | ||
| 70 | EXPORT_SYMBOL(omap_type); | ||
| 71 | |||
| 72 | |||
| 51 | /*----------------------------------------------------------------------------*/ | 73 | /*----------------------------------------------------------------------------*/ |
| 52 | 74 | ||
| 53 | #define OMAP_TAP_IDCODE 0x0204 | 75 | #define OMAP_TAP_IDCODE 0x0204 |
| @@ -21,6 +21,7 @@ · 20 unmodified lines | |||
| 21 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
| 22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/clk.h> | ||
| 24 | 25 | ||
| 25 | #include <asm/tlb.h> | 26 | #include <asm/tlb.h> |
| 26 | 27 | ||
| @@ -241,6 +242,40 @@ void __init omap2_map_common_io(void) · 214 unmodified lines | |||
| 241 | omapfb_reserve_sdram(); | 242 | omapfb_reserve_sdram(); |
| 242 | } | 243 | } |
| 243 | 244 | ||
| 245 | /* | ||
| 246 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | ||
| 247 | * | ||
| 248 | * Sets the CORE DPLL3 M2 divider to the same value that it's at | ||
| 249 | * currently. This has the effect of setting the SDRC SDRAM AC timing | ||
| 250 | * registers to the values currently defined by the kernel. Currently | ||
| 251 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns | ||
| 252 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, | ||
| 253 | * or passes along the return value of clk_set_rate(). | ||
| 254 | */ | ||
| 255 | static int __init _omap2_init_reprogram_sdrc(void) | ||
| 256 | { | ||
| 257 | struct clk *dpll3_m2_ck; | ||
| 258 | int v = -EINVAL; | ||
| 259 | long rate; | ||
| 260 | |||
| 261 | if (!cpu_is_omap34xx()) | ||
| 262 | return 0; | ||
| 263 | |||
| 264 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); | ||
| 265 | if (!dpll3_m2_ck) | ||
| 266 | return -EINVAL; | ||
| 267 | |||
| 268 | rate = clk_get_rate(dpll3_m2_ck); | ||
| 269 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); | ||
| 270 | v = clk_set_rate(dpll3_m2_ck, rate); | ||
| 271 | if (v) | ||
| 272 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); | ||
| 273 | |||
| 274 | clk_put(dpll3_m2_ck); | ||
| 275 | |||
| 276 | return v; | ||
| 277 | } | ||
| 278 | |||
| 244 | void __init omap2_init_common_hw(struct omap_sdrc_params *sp) | 279 | void __init omap2_init_common_hw(struct omap_sdrc_params *sp) |
| 245 | { | 280 | { |
| 246 | omap2_mux_init(); | 281 | omap2_mux_init(); |
| @@ -249,6 +284,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp) · 2 unmodified lines | |||
| 249 | clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); | 284 | clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); |
| 250 | omap2_clk_init(); | 285 | omap2_clk_init(); |
| 251 | omap2_sdrc_init(sp); | 286 | omap2_sdrc_init(sp); |
| 287 | _omap2_init_reprogram_sdrc(); | ||
| 252 | #endif | 288 | #endif |
| 253 | gpmc_init(); | 289 | gpmc_init(); |
| 254 | } | 290 | } |
| @@ -282,12 +282,12 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) · 281 unmodified lines | |||
| 282 | return -ENOMEM; | 282 | return -ENOMEM; |
| 283 | 283 | ||
| 284 | /* DSP or IVA2 IRQ */ | 284 | /* DSP or IVA2 IRQ */ |
| 285 | mbox_dsp_info.irq = platform_get_irq(pdev, 0); | 285 | ret = platform_get_irq(pdev, 0); |
| 286 | if (mbox_dsp_info.irq < 0) { | 286 | if (ret < 0) { |
| 287 | dev_err(&pdev->dev, "invalid irq resource\n"); | 287 | dev_err(&pdev->dev, "invalid irq resource\n"); |
| 288 | ret = -ENODEV; | ||
| 289 | goto err_dsp; | 288 | goto err_dsp; |
| 290 | } | 289 | } |
| 290 | mbox_dsp_info.irq = ret; | ||
| 291 | 291 | ||
| 292 | ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info); | 292 | ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info); |
| 293 | if (ret) | 293 | if (ret) |
| @@ -263,8 +263,19 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, · 262 unmodified lines | |||
| 263 | static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int vdd) | 263 | static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int vdd) |
| 264 | { | 264 | { |
| 265 | int ret = 0; | 265 | int ret = 0; |
| 266 | struct twl_mmc_controller *c = &hsmmc[1]; | 266 | struct twl_mmc_controller *c = NULL; |
| 267 | struct omap_mmc_platform_data *mmc = dev->platform_data; | 267 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
| 268 | int i; | ||
| 269 | |||
| 270 | for (i = 1; i < ARRAY_SIZE(hsmmc); i++) { | ||
| 271 | if (mmc == hsmmc[i].mmc) { | ||
| 272 | c = &hsmmc[i]; | ||
| 273 | break; | ||
| 274 | } | ||
| 275 | } | ||
| 276 | |||
| 277 | if (c == NULL) | ||
| 278 | return -ENODEV; | ||
| 268 | 279 | ||
| 269 | /* If we don't see a Vcc regulator, assume it's a fixed | 280 | /* If we don't see a Vcc regulator, assume it's a fixed |
| 270 | * voltage always-on regulator. | 281 | * voltage always-on regulator. |
| @@ -1099,7 +1099,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm) · 1098 unmodified lines | |||
| 1099 | (c++ < PWRDM_TRANSITION_BAILOUT)) | 1099 | (c++ < PWRDM_TRANSITION_BAILOUT)) |
| 1100 | udelay(1); | 1100 | udelay(1); |
| 1101 | 1101 | ||
| 1102 | if (c >= PWRDM_TRANSITION_BAILOUT) { | 1102 | if (c > PWRDM_TRANSITION_BAILOUT) { |
| 1103 | printk(KERN_ERR "powerdomain: waited too long for " | 1103 | printk(KERN_ERR "powerdomain: waited too long for " |
| 1104 | "powerdomain %s to complete transition\n", pwrdm->name); | 1104 | "powerdomain %s to complete transition\n", pwrdm->name); |
| 1105 | return -EAGAIN; | 1105 | return -EAGAIN; |
| @@ -3,13 +3,12 @@ · 2 unmodified lines | |||
| 3 | * | 3 | * |
| 4 | * Omap3 specific functions that need to be run in internal SRAM | 4 | * Omap3 specific functions that need to be run in internal SRAM |
| 5 | * | 5 | * |
| 6 | * (C) Copyright 2007 | 6 | * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc. |
| 7 | * Texas Instruments Inc. | 7 | * Copyright (C) 2008 Nokia Corporation |
| 8 | * Rajendra Nayak <rnayak@ti.com> | ||
| 9 | * | 8 | * |
| 10 | * (C) Copyright 2004 | 9 | * Rajendra Nayak <rnayak@ti.com> |
| 11 | * Texas Instruments, <www.ti.com> | ||
| 12 | * Richard Woodruff <r-woodruff2@ti.com> | 10 | * Richard Woodruff <r-woodruff2@ti.com> |
| 11 | * Paul Walmsley | ||
| 13 | * | 12 | * |
| 14 | * This program is free software; you can redistribute it and/or | 13 | * This program is free software; you can redistribute it and/or |
| 15 | * modify it under the terms of the GNU General Public License as | 14 | * modify it under the terms of the GNU General Public License as |
| @@ -37,61 +36,112 @@ · 21 unmodified lines | |||
| 37 | 36 | ||
| 38 | .text | 37 | .text |
| 39 | 38 | ||
| 39 | /* r4 parameters */ | ||
| 40 | #define SDRC_NO_UNLOCK_DLL 0x0 | ||
| 41 | #define SDRC_UNLOCK_DLL 0x1 | ||
| 42 | |||
| 43 | /* SDRC_DLLA_CTRL bit settings */ | ||
| 44 | #define FIXEDDELAY_SHIFT 24 | ||
| 45 | #define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT) | ||
| 46 | #define DLLIDLE_MASK 0x4 | ||
| 47 | |||
| 48 | /* | ||
| 49 | * SDRC_DLLA_CTRL default values: TI hardware team indicates that | ||
| 50 | * FIXEDDELAY should be initialized to 0xf. This apparently was | ||
| 51 | * empirically determined during process testing, so no derivation | ||
| 52 | * was provided. | ||
| 53 | */ | ||
| 54 | #define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT) | ||
| 55 | |||
| 56 | /* SDRC_DLLA_STATUS bit settings */ | ||
| 57 | #define LOCKSTATUS_MASK 0x4 | ||
| 58 | |||
| 59 | /* SDRC_POWER bit settings */ | ||
| 60 | #define SRFRONIDLEREQ_MASK 0x40 | ||
| 61 | #define PWDENA_MASK 0x4 | ||
| 62 | |||
| 63 | /* CM_IDLEST1_CORE bit settings */ | ||
| 64 | #define ST_SDRC_MASK 0x2 | ||
| 65 | |||
| 66 | /* CM_ICLKEN1_CORE bit settings */ | ||
| 67 | #define EN_SDRC_MASK 0x2 | ||
| 68 | |||
| 69 | /* CM_CLKSEL1_PLL bit settings */ | ||
| 70 | #define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b | ||
| 71 | |||
| 40 | /* | 72 | /* |
| 41 | * Change frequency of core dpll | 73 | * omap3_sram_configure_core_dpll - change DPLL3 M2 divider |
| 42 | * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 | 74 | * r0 = new SDRC_RFR_CTRL register contents |
| 43 | * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for | 75 | * r1 = new SDRC_ACTIM_CTRLA register contents |
| 76 | * r2 = new SDRC_ACTIM_CTRLB register contents | ||
| 77 | * r3 = new M2 divider setting (only 1 and 2 supported right now) | ||
| 78 | * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for | ||
| 44 | * SDRC rates < 83MHz | 79 | * SDRC rates < 83MHz |
| 80 | * r5 = number of MPU cycles to wait for SDRC to stabilize after | ||
| 81 | * reprogramming the SDRC when switching to a slower MPU speed | ||
| 82 | * r6 = new SDRC_MR_0 register value | ||
| 83 | * r7 = increasing SDRC rate? (1 = yes, 0 = no) | ||
| 84 | * | ||
| 45 | */ | 85 | */ |
| 46 | ENTRY(omap3_sram_configure_core_dpll) | 86 | ENTRY(omap3_sram_configure_core_dpll) |
| 47 | stmfd sp!, {r1-r12, lr} @ store regs to stack | 87 | stmfd sp!, {r1-r12, lr} @ store regs to stack |
| 48 | ldr r4, [sp, #52] @ pull extra args off the stack | 88 | ldr r4, [sp, #52] @ pull extra args off the stack |
| 89 | ldr r5, [sp, #56] @ load extra args from the stack | ||
| 90 | ldr r6, [sp, #60] @ load extra args from the stack | ||
| 91 | ldr r7, [sp, #64] @ load extra args from the stack | ||
| 49 | dsb @ flush buffered writes to interconnect | 92 | dsb @ flush buffered writes to interconnect |
| 50 | cmp r3, #0x2 | 93 | cmp r7, #1 @ if increasing SDRC clk rate, |
| 51 | blne configure_sdrc | 94 | bleq configure_sdrc @ program the SDRC regs early (for RFR) |
| 52 | cmp r4, #0x1 | 95 | cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state |
| 53 | bleq unlock_dll | 96 | bleq unlock_dll |
| 54 | blne lock_dll | 97 | blne lock_dll |
| 55 | bl sdram_in_selfrefresh @ put the SDRAM in self refresh | 98 | bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC |
| 56 | bl configure_core_dpll | 99 | bl configure_core_dpll @ change the DPLL3 M2 divider |
| 57 | bl enable_sdrc | 100 | bl enable_sdrc @ take SDRC out of idle |
| 58 | cmp r4, #0x1 | 101 | cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change |
| 59 | bleq wait_dll_unlock | 102 | bleq wait_dll_unlock |
| 60 | blne wait_dll_lock | 103 | blne wait_dll_lock |
| 61 | cmp r3, #0x1 | 104 | cmp r7, #1 @ if increasing SDRC clk rate, |
| 62 | blne configure_sdrc | 105 | beq return_to_sdram @ return to SDRAM code, otherwise, |
| 106 | bl configure_sdrc @ reprogram SDRC regs now | ||
| 107 | mov r12, r5 | ||
| 108 | bl wait_clk_stable @ wait for SDRC to stabilize | ||
| 109 | return_to_sdram: | ||
| 63 | isb @ prevent speculative exec past here | 110 | isb @ prevent speculative exec past here |
| 64 | mov r0, #0 @ return value | 111 | mov r0, #0 @ return value |
| 65 | ldmfd sp!, {r1-r12, pc} @ restore regs and return | 112 | ldmfd sp!, {r1-r12, pc} @ restore regs and return |
| 66 | unlock_dll: | 113 | unlock_dll: |
| 67 | ldr r11, omap3_sdrc_dlla_ctrl | 114 | ldr r11, omap3_sdrc_dlla_ctrl |
| 68 | ldr r12, [r11] | 115 | ldr r12, [r11] |
| 69 | orr r12, r12, #0x4 | 116 | and r12, r12, #FIXEDDELAY_MASK |
| 117 | orr r12, r12, #FIXEDDELAY_DEFAULT | ||
| 118 | orr r12, r12, #DLLIDLE_MASK | ||
| 70 | str r12, [r11] @ (no OCP barrier needed) | 119 | str r12, [r11] @ (no OCP barrier needed) |
| 71 | bx lr | 120 | bx lr |
| 72 | lock_dll: | 121 | lock_dll: |
| 73 | ldr r11, omap3_sdrc_dlla_ctrl | 122 | ldr r11, omap3_sdrc_dlla_ctrl |
| 74 | ldr r12, [r11] | 123 | ldr r12, [r11] |
| 75 | bic r12, r12, #0x4 | 124 | bic r12, r12, #DLLIDLE_MASK |
| 76 | str r12, [r11] @ (no OCP barrier needed) | 125 | str r12, [r11] @ (no OCP barrier needed) |
| 77 | bx lr | 126 | bx lr |
| 78 | sdram_in_selfrefresh: | 127 | sdram_in_selfrefresh: |
| 79 | ldr r11, omap3_sdrc_power @ read the SDRC_POWER register | 128 | ldr r11, omap3_sdrc_power @ read the SDRC_POWER register |
| 80 | ldr r12, [r11] @ read the contents of SDRC_POWER | 129 | ldr r12, [r11] @ read the contents of SDRC_POWER |
| 81 | mov r9, r12 @ keep a copy of SDRC_POWER bits | 130 | mov r9, r12 @ keep a copy of SDRC_POWER bits |
| 82 | orr r12, r12, #0x40 @ enable self refresh on idle req | 131 | orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle |
| 83 | bic r12, r12, #0x4 @ clear PWDENA | 132 | bic r12, r12, #PWDENA_MASK @ clear PWDENA |
| 84 | str r12, [r11] @ write back to SDRC_POWER register | 133 | str r12, [r11] @ write back to SDRC_POWER register |
| 85 | ldr r12, [r11] @ posted-write barrier for SDRC | 134 | ldr r12, [r11] @ posted-write barrier for SDRC |
| 135 | idle_sdrc: | ||
| 86 | ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg | 136 | ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg |
| 87 | ldr r12, [r11] | 137 | ldr r12, [r11] |
| 88 | bic r12, r12, #0x2 @ disable iclk bit for SDRC | 138 | bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC |
| 89 | str r12, [r11] | 139 | str r12, [r11] |
| 90 | wait_sdrc_idle: | 140 | wait_sdrc_idle: |
| 91 | ldr r11, omap3_cm_idlest1_core | 141 | ldr r11, omap3_cm_idlest1_core |
| 92 | ldr r12, [r11] | 142 | ldr r12, [r11] |
| 93 | and r12, r12, #0x2 @ check for SDRC idle | 143 | and r12, r12, #ST_SDRC_MASK @ check for SDRC idle |
| 94 | cmp r12, #2 | 144 | cmp r12, #ST_SDRC_MASK |
| 95 | bne wait_sdrc_idle | 145 | bne wait_sdrc_idle |
| 96 | bx lr | 146 | bx lr |
| 97 | configure_core_dpll: | 147 | configure_core_dpll: |
| @@ -99,36 +149,23 @@ configure_core_dpll: · 1 unmodified line | |||
| 99 | ldr r12, [r11] | 149 | ldr r12, [r11] |
| 100 | ldr r10, core_m2_mask_val @ modify m2 for core dpll | 150 | ldr r10, core_m2_mask_val @ modify m2 for core dpll |
| 101 | and r12, r12, r10 | 151 | and r12, r12, r10 |
| 102 | orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val | 152 | orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT |
| 103 | str r12, [r11] | 153 | str r12, [r11] |
| 104 | ldr r12, [r11] @ posted-write barrier for CM | 154 | ldr r12, [r11] @ posted-write barrier for CM |
| 105 | mov r12, #0x800 @ wait for the clock to stabilise | ||
| 106 | cmp r3, #2 | ||
| 107 | bne wait_clk_stable | ||
| 108 | bx lr | 155 | bx lr |
| 109 | wait_clk_stable: | 156 | wait_clk_stable: |
| 110 | subs r12, r12, #1 | 157 | subs r12, r12, #1 |
| 111 | bne wait_clk_stable | 158 | bne wait_clk_stable |
| 112 | nop | ||
| 113 | nop | ||
| 114 | nop | ||
| 115 | nop | ||
| 116 | nop | ||
| 117 | nop | ||
| 118 | nop | ||
| 119 | nop | ||
| 120 | nop | ||
| 121 | nop | ||
| 122 | bx lr | 159 | bx lr |
| 123 | enable_sdrc: | 160 | enable_sdrc: |
| 124 | ldr r11, omap3_cm_iclken1_core | 161 | ldr r11, omap3_cm_iclken1_core |
| 125 | ldr r12, [r11] | 162 | ldr r12, [r11] |
| 126 | orr r12, r12, #0x2 @ enable iclk bit for SDRC | 163 | orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC |
| 127 | str r12, [r11] | 164 | str r12, [r11] |
| 128 | wait_sdrc_idle1: | 165 | wait_sdrc_idle1: |
| 129 | ldr r11, omap3_cm_idlest1_core | 166 | ldr r11, omap3_cm_idlest1_core |
| 130 | ldr r12, [r11] | 167 | ldr r12, [r11] |
| 131 | and r12, r12, #0x2 | 168 | and r12, r12, #ST_SDRC_MASK |
| 132 | cmp r12, #0 | 169 | cmp r12, #0 |
| 133 | bne wait_sdrc_idle1 | 170 | bne wait_sdrc_idle1 |
| 134 | restore_sdrc_power_val: | 171 | restore_sdrc_power_val: |
| @@ -138,14 +175,14 @@ restore_sdrc_power_val: · 3 unmodified lines | |||
| 138 | wait_dll_lock: | 175 | wait_dll_lock: |
| 139 | ldr r11, omap3_sdrc_dlla_status | 176 | ldr r11, omap3_sdrc_dlla_status |
| 140 | ldr r12, [r11] | 177 | ldr r12, [r11] |
| 141 | and r12, r12, #0x4 | 178 | and r12, r12, #LOCKSTATUS_MASK |
| 142 | cmp r12, #0x4 | 179 | cmp r12, #LOCKSTATUS_MASK |
| 143 | bne wait_dll_lock | 180 | bne wait_dll_lock |
| 144 | bx lr | 181 | bx lr |
| 145 | wait_dll_unlock: | 182 | wait_dll_unlock: |
| 146 | ldr r11, omap3_sdrc_dlla_status | 183 | ldr r11, omap3_sdrc_dlla_status |
| 147 | ldr r12, [r11] | 184 | ldr r12, [r11] |
| 148 | and r12, r12, #0x4 | 185 | and r12, r12, #LOCKSTATUS_MASK |
| 149 | cmp r12, #0x0 | 186 | cmp r12, #0x0 |
| 150 | bne wait_dll_unlock | 187 | bne wait_dll_unlock |
| 151 | bx lr | 188 | bx lr |
| @@ -156,7 +193,9 @@ configure_sdrc: · 4 unmodified lines | |||
| 156 | str r1, [r11] | 193 | str r1, [r11] |
| 157 | ldr r11, omap3_sdrc_actim_ctrlb | 194 | ldr r11, omap3_sdrc_actim_ctrlb |
| 158 | str r2, [r11] | 195 | str r2, [r11] |
| 159 | ldr r2, [r11] @ posted-write barrier for SDRC | 196 | ldr r11, omap3_sdrc_mr_0 |
| 197 | str r6, [r11] | ||
| 198 | ldr r6, [r11] @ posted-write barrier for SDRC | ||
| 160 | bx lr | 199 | bx lr |
| 161 | 200 | ||
| 162 | omap3_sdrc_power: | 201 | omap3_sdrc_power: |
| @@ -173,6 +212,8 @@ omap3_sdrc_actim_ctrla: · 10 unmodified lines | |||
| 173 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) | 212 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) |
| 174 | omap3_sdrc_actim_ctrlb: | 213 | omap3_sdrc_actim_ctrlb: |
| 175 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) | 214 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) |
| 215 | omap3_sdrc_mr_0: | ||
| 216 | .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0) | ||
| 176 | omap3_sdrc_dlla_status: | 217 | omap3_sdrc_dlla_status: |
| 177 | .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) | 218 | .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) |
| 178 | omap3_sdrc_dlla_ctrl: | 219 | omap3_sdrc_dlla_ctrl: |
| @@ -200,6 +200,6 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) · 199 unmodified lines | |||
| 200 | 200 | ||
| 201 | int __init orion5x_setup_sram_win(void) | 201 | int __init orion5x_setup_sram_win(void) |
| 202 | { | 202 | { |
| 203 | return setup_cpu_win(win_alloc_count, ORION5X_SRAM_PHYS_BASE, | 203 | return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE, |
| 204 | ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); | 204 | ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); |
| 205 | } | 205 | } |
| @@ -562,7 +562,7 @@ static struct platform_device orion5x_crypto_device = { · 561 unmodified lines | |||
| 562 | .resource = orion5x_crypto_res, | 562 | .resource = orion5x_crypto_res, |
| 563 | }; | 563 | }; |
| 564 | 564 | ||
| 565 | int __init orion5x_crypto_init(void) | 565 | static int __init orion5x_crypto_init(void) |
| 566 | { | 566 | { |
| 567 | int ret; | 567 | int ret; |
| 568 | 568 | ||
| @@ -696,6 +696,14 @@ void __init orion5x_init(void) · 127 unmodified lines | |||
| 696 | disable_hlt(); | 696 | disable_hlt(); |
| 697 | } | 697 | } |
| 698 | 698 | ||
| 699 | /* | ||
| 700 | * The 5082/5181l/5182/6082/6082l/6183 have crypto | ||
| 701 | * while 5180n/5181/5281 don't have crypto. | ||
| 702 | */ | ||
| 703 | if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || | ||
| 704 | dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) | ||
| 705 | orion5x_crypto_init(); | ||
| 706 | |||
| 699 | /* | 707 | /* |
| 700 | * Register watchdog driver | 708 | * Register watchdog driver |
| 701 | */ | 709 | */ |
| @@ -38,7 +38,6 @@ void orion5x_spi_init(void); · 37 unmodified lines | |||
| 38 | void orion5x_uart0_init(void); | 38 | void orion5x_uart0_init(void); |
| 39 | void orion5x_uart1_init(void); | 39 | void orion5x_uart1_init(void); |
| 40 | void orion5x_xor_init(void); | 40 | void orion5x_xor_init(void); |
| 41 | int orion5x_crypto_init(void); | ||
| 42 | 41 | ||
| 43 | /* | 42 | /* |
| 44 | * PCIe/PCI functions. | 43 | * PCIe/PCI functions. |
| @@ -401,6 +401,16 @@ config MACH_PALMZ72 · 400 unmodified lines | |||
| 401 | Say Y here if you intend to run this kernel on Palm Zire 72 | 401 | Say Y here if you intend to run this kernel on Palm Zire 72 |
| 402 | handheld computer. | 402 | handheld computer. |
| 403 | 403 | ||
| 404 | config MACH_TREO680 | ||
| 405 | bool "Palm Treo 680" | ||
| 406 | default y | ||
| 407 | depends on ARCH_PXA_PALM | ||
| 408 | select PXA27x | ||
| 409 | select IWMMXT | ||
| 410 | help | ||
| 411 | Say Y here if you intend to run this kernel on Palm Treo 680 | ||
| 412 | smartphone. | ||
| 413 | |||
| 404 | config MACH_PALMLD | 414 | config MACH_PALMLD |
| 405 | bool "Palm LifeDrive" | 415 | bool "Palm LifeDrive" |
| 406 | default y | 416 | default y |
| @@ -62,6 +62,7 @@ obj-$(CONFIG_MACH_PALMT5) += palmt5.o · 61 unmodified lines | |||
| 62 | obj-$(CONFIG_MACH_PALMTX) += palmtx.o | 62 | obj-$(CONFIG_MACH_PALMTX) += palmtx.o |
| 63 | obj-$(CONFIG_MACH_PALMLD) += palmld.o | 63 | obj-$(CONFIG_MACH_PALMLD) += palmld.o |
| 64 | obj-$(CONFIG_MACH_PALMZ72) += palmz72.o | 64 | obj-$(CONFIG_MACH_PALMZ72) += palmz72.o |
| 65 | obj-$(CONFIG_MACH_TREO680) += treo680.o | ||
| 65 | obj-$(CONFIG_ARCH_VIPER) += viper.o | 66 | obj-$(CONFIG_ARCH_VIPER) += viper.o |
| 66 | 67 | ||
| 67 | ifeq ($(CONFIG_MACH_ZYLONITE),y) | 68 | ifeq ($(CONFIG_MACH_ZYLONITE),y) |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | |||
| 23 | #include <linux/pm.h> | 23 | #include <linux/pm.h> |
| 24 | #include <linux/gpio.h> | 24 | #include <linux/gpio.h> |
| 25 | #include <linux/backlight.h> | 25 | #include <linux/backlight.h> |
| 26 | #include <linux/i2c.h> | ||
| 26 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 27 | #include <linux/spi/spi.h> | 28 | #include <linux/spi/spi.h> |
| 28 | #include <linux/spi/ads7846.h> | 29 | #include <linux/spi/ads7846.h> |
| @@ -600,6 +601,10 @@ static struct platform_device *devices[] __initdata = { · 571 unmodified lines | |||
| 600 | &sharpsl_rom_device, | 601 | &sharpsl_rom_device, |
| 601 | }; | 602 | }; |
| 602 | 603 | ||
| 604 | static struct i2c_board_info __initdata corgi_i2c_devices[] = { | ||
| 605 | { I2C_BOARD_INFO("wm8731", 0x1b) }, | ||
| 606 | }; | ||
| 607 | |||
| 603 | static void corgi_poweroff(void) | 608 | static void corgi_poweroff(void) |
| 604 | { | 609 | { |
| 605 | if (!machine_is_corgi()) | 610 | if (!machine_is_corgi()) |
| @@ -634,6 +639,7 @@ static void __init corgi_init(void) · 28 unmodified lines | |||
| 634 | pxa_set_mci_info(&corgi_mci_platform_data); | 639 | pxa_set_mci_info(&corgi_mci_platform_data); |
| 635 | pxa_set_ficp_info(&corgi_ficp_platform_data); | 640 | pxa_set_ficp_info(&corgi_ficp_platform_data); |
| 636 | pxa_set_i2c_info(NULL); | 641 | pxa_set_i2c_info(NULL); |
| 642 | i2c_register_board_info(0, ARRAY_AND_SIZE(corgi_i2c_devices)); | ||
| 637 | 643 | ||
| 638 | platform_scoop_config = &corgi_pcmcia_config; | 644 | platform_scoop_config = &corgi_pcmcia_config; |
| 639 | 645 | ||
| @@ -30,6 +30,7 @@ · 29 unmodified lines | |||
| 30 | #include <linux/apm-emulation.h> | 30 | #include <linux/apm-emulation.h> |
| 31 | #include <linux/i2c.h> | 31 | #include <linux/i2c.h> |
| 32 | #include <linux/i2c/pca953x.h> | 32 | #include <linux/i2c/pca953x.h> |
| 33 | #include <linux/regulator/userspace-consumer.h> | ||
| 33 | 34 | ||
| 34 | #include <media/soc_camera.h> | 35 | #include <media/soc_camera.h> |
| 35 | 36 | ||
| @@ -735,6 +736,7 @@ static struct pxa2xx_spi_chip em_x270_libertas_chip = { · 699 unmodified lines | |||
| 735 | .rx_threshold = 1, | 736 | .rx_threshold = 1, |
| 736 | .tx_threshold = 1, | 737 | .tx_threshold = 1, |
| 737 | .timeout = 1000, | 738 | .timeout = 1000, |
| 739 | .gpio_cs = 14, | ||
| 738 | }; | 740 | }; |
| 739 | 741 | ||
| 740 | static unsigned long em_x270_libertas_pin_config[] = { | 742 | static unsigned long em_x270_libertas_pin_config[] = { |
| @@ -803,7 +805,6 @@ static int em_x270_libertas_teardown(struct spi_device *spi) · 62 unmodified lines | |||
| 803 | 805 | ||
| 804 | struct libertas_spi_platform_data em_x270_libertas_pdata = { | 806 | struct libertas_spi_platform_data em_x270_libertas_pdata = { |
| 805 | .use_dummy_writes = 1, | 807 | .use_dummy_writes = 1, |
| 806 | .gpio_cs = 14, | ||
| 807 | .setup = em_x270_libertas_setup, | 808 | .setup = em_x270_libertas_setup, |
| 808 | .teardown = em_x270_libertas_teardown, | 809 | .teardown = em_x270_libertas_teardown, |
| 809 | }; | 810 | }; |
| @@ -838,10 +839,14 @@ static void __init em_x270_init_spi(void) · 28 unmodified lines | |||
| 838 | static inline void em_x270_init_spi(void) {} | 839 | static inline void em_x270_init_spi(void) {} |
| 839 | #endif | 840 | #endif |
| 840 | 841 | ||
| 841 | #if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE) | 842 | #if defined(CONFIG_SND_PXA2XX_LIB_AC97) |
| 843 | static pxa2xx_audio_ops_t em_x270_ac97_info = { | ||
| 844 | .reset_gpio = 113, | ||
| 845 | }; | ||
| 846 | |||
| 842 | static void __init em_x270_init_ac97(void) | 847 | static void __init em_x270_init_ac97(void) |
| 843 | { | 848 | { |
| 844 | pxa_set_ac97_info(NULL); | 849 | pxa_set_ac97_info(&em_x270_ac97_info); |
| 845 | } | 850 | } |
| 846 | #else | 851 | #else |
| 847 | static inline void em_x270_init_ac97(void) {} | 852 | static inline void em_x270_init_ac97(void) {} |
| @@ -1038,6 +1043,52 @@ static void __init em_x270_init_camera(void) · 190 unmodified lines | |||
| 1038 | static inline void em_x270_init_camera(void) {} | 1043 | static inline void em_x270_init_camera(void) {} |
| 1039 | #endif | 1044 | #endif |
| 1040 | 1045 | ||
| 1046 | static struct regulator_bulk_data em_x270_gps_consumer_supply = { | ||
| 1047 | .supply = "vcc gps", | ||
| 1048 | }; | ||
| 1049 | |||
| 1050 | static struct regulator_userspace_consumer_data em_x270_gps_consumer_data = { | ||
| 1051 | .name = "vcc gps", | ||
| 1052 | .num_supplies = 1, | ||
| 1053 | .supplies = &em_x270_gps_consumer_supply, | ||
| 1054 | }; | ||
| 1055 | |||
| 1056 | static struct platform_device em_x270_gps_userspace_consumer = { | ||
| 1057 | .name = "reg-userspace-consumer", | ||
| 1058 | .id = 0, | ||
| 1059 | .dev = { | ||
| 1060 | .platform_data = &em_x270_gps_consumer_data, | ||
| 1061 | }, | ||
| 1062 | }; | ||
| 1063 | |||
| 1064 | static struct regulator_bulk_data em_x270_gprs_consumer_supply = { | ||
| 1065 | .supply = "vcc gprs", | ||
| 1066 | }; | ||
| 1067 | |||
| 1068 | static struct regulator_userspace_consumer_data em_x270_gprs_consumer_data = { | ||
| 1069 | .name = "vcc gprs", | ||
| 1070 | .num_supplies = 1, | ||
| 1071 | .supplies = &em_x270_gprs_consumer_supply | ||
| 1072 | }; | ||
| 1073 | |||
| 1074 | static struct platform_device em_x270_gprs_userspace_consumer = { | ||
| 1075 | .name = "reg-userspace-consumer", | ||
| 1076 | .id = 1, | ||
| 1077 | .dev = { | ||
| 1078 | .platform_data = &em_x270_gprs_consumer_data, | ||
| 1079 | } | ||
| 1080 | }; | ||
| 1081 | |||
| 1082 | static struct platform_device *em_x270_userspace_consumers[] = { | ||
| 1083 | &em_x270_gps_userspace_consumer, | ||
| 1084 | &em_x270_gprs_userspace_consumer, | ||
| 1085 | }; | ||
| 1086 | |||
| 1087 | static void __init em_x270_userspace_consumers_init(void) | ||
| 1088 | { | ||
| 1089 | platform_add_devices(ARRAY_AND_SIZE(em_x270_userspace_consumers)); | ||
| 1090 | } | ||
| 1091 | |||
| 1041 | /* DA9030 related initializations */ | 1092 | /* DA9030 related initializations */ |
| 1042 | #define REGULATOR_CONSUMER(_name, _dev, _supply) \ | 1093 | #define REGULATOR_CONSUMER(_name, _dev, _supply) \ |
| 1043 | static struct regulator_consumer_supply _name##_consumers[] = { \ | 1094 | static struct regulator_consumer_supply _name##_consumers[] = { \ |
| @@ -1047,11 +1098,11 @@ static inline void em_x270_init_camera(void) {} · 3 unmodified lines | |||
| 1047 | }, \ | 1098 | }, \ |
| 1048 | } | 1099 | } |
| 1049 | 1100 | ||
| 1050 | REGULATOR_CONSUMER(ldo3, NULL, "vcc gps"); | 1101 | REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps"); |
| 1051 | REGULATOR_CONSUMER(ldo5, NULL, "vcc cam"); | 1102 | REGULATOR_CONSUMER(ldo5, NULL, "vcc cam"); |
| 1052 | REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio"); | 1103 | REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio"); |
| 1053 | REGULATOR_CONSUMER(ldo12, NULL, "vcc usb"); | 1104 | REGULATOR_CONSUMER(ldo12, NULL, "vcc usb"); |
| 1054 | REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs"); | 1105 | REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs"); |
| 1055 | 1106 | ||
| 1056 | #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \ | 1107 | #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \ |
| 1057 | static struct regulator_init_data _ldo##_data = { \ | 1108 | static struct regulator_init_data _ldo##_data = { \ |
| @@ -1062,6 +1113,7 @@ REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs"); · 4 unmodified lines | |||
| 1062 | .enabled = 0, \ | 1113 | .enabled = 0, \ |
| 1063 | }, \ | 1114 | }, \ |
| 1064 | .valid_ops_mask = _ops_mask, \ | 1115 | .valid_ops_mask = _ops_mask, \ |
| 1116 | .apply_uV = 1, \ | ||
| 1065 | }, \ | 1117 | }, \ |
| 1066 | .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers), \ | 1118 | .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers), \ |
| 1067 | .consumer_supplies = _ldo##_consumers, \ | 1119 | .consumer_supplies = _ldo##_consumers, \ |
| @@ -1240,6 +1292,7 @@ static void __init em_x270_init(void) · 172 unmodified lines | |||
| 1240 | em_x270_init_spi(); | 1292 | em_x270_init_spi(); |
| 1241 | em_x270_init_i2c(); | 1293 | em_x270_init_i2c(); |
| 1242 | em_x270_init_camera(); | 1294 | em_x270_init_camera(); |
| 1295 | em_x270_userspace_consumers_init(); | ||
| 1243 | } | 1296 | } |
| 1244 | 1297 | ||
| 1245 | MACHINE_START(EM_X270, "Compulab EM-X270") | 1298 | MACHINE_START(EM_X270, "Compulab EM-X270") |
| @@ -30,6 +30,7 @@ · 29 unmodified lines | |||
| 30 | #include <linux/pwm_backlight.h> | 30 | #include <linux/pwm_backlight.h> |
| 31 | #include <linux/regulator/bq24022.h> | 31 | #include <linux/regulator/bq24022.h> |
| 32 | #include <linux/regulator/machine.h> | 32 | #include <linux/regulator/machine.h> |
| 33 | #include <linux/regulator/max1586.h> | ||
| 33 | #include <linux/spi/ads7846.h> | 34 | #include <linux/spi/ads7846.h> |
| 34 | #include <linux/spi/spi.h> | 35 | #include <linux/spi/spi.h> |
| 35 | #include <linux/usb/gpio_vbus.h> | 36 | #include <linux/usb/gpio_vbus.h> |
| @@ -774,6 +775,45 @@ static struct platform_device strataflash = { · 738 unmodified lines | |||
| 774 | }, | 775 | }, |
| 775 | }; | 776 | }; |
| 776 | 777 | ||
| 778 | /* | ||
| 779 | * Maxim MAX1587A on PI2C | ||
| 780 | */ | ||
| 781 | |||
| 782 | static struct regulator_consumer_supply max1587a_consumer = { | ||
| 783 | .supply = "vcc_core", | ||
| 784 | }; | ||
| 785 | |||
| 786 | static struct regulator_init_data max1587a_v3_info = { | ||
| 787 | .constraints = { | ||
| 788 | .name = "vcc_core range", | ||
| 789 | .min_uV = 900000, | ||
| 790 | .max_uV = 1705000, | ||
| 791 | .always_on = 1, | ||
| 792 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 793 | }, | ||
| 794 | .num_consumer_supplies = 1, | ||
| 795 | .consumer_supplies = &max1587a_consumer, | ||
| 796 | }; | ||
| 797 | |||
| 798 | static struct max1586_subdev_data max1587a_subdev = { | ||
| 799 | .name = "vcc_core", | ||
| 800 | .id = MAX1586_V3, | ||
| 801 | .platform_data = &max1587a_v3_info, | ||
| 802 | }; | ||
| 803 | |||
| 804 | static struct max1586_platform_data max1587a_info = { | ||
| 805 | .num_subdevs = 1, | ||
| 806 | .subdevs = &max1587a_subdev, | ||
| 807 | .v3_gain = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */ | ||
| 808 | }; | ||
| 809 | |||
| 810 | static struct i2c_board_info __initdata pi2c_board_info[] = { | ||
| 811 | { | ||
| 812 | I2C_BOARD_INFO("max1586", 0x14), | ||
| 813 | .platform_data = &max1587a_info, | ||
| 814 | }, | ||
| 815 | }; | ||
| 816 | |||
| 777 | /* | 817 | /* |
| 778 | * PCMCIA | 818 | * PCMCIA |
| 779 | */ | 819 | */ |
| @@ -828,6 +868,7 @@ static void __init hx4700_init(void) · 48 unmodified lines | |||
| 828 | pxa_set_ficp_info(&ficp_info); | 868 | pxa_set_ficp_info(&ficp_info); |
| 829 | pxa27x_set_i2c_power_info(NULL); | 869 | pxa27x_set_i2c_power_info(NULL); |
| 830 | pxa_set_i2c_info(NULL); | 870 | pxa_set_i2c_info(NULL); |
| 871 | i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info)); | ||
| 831 | pxa2xx_set_spi_info(2, &pxa_ssp2_master_info); | 872 | pxa2xx_set_spi_info(2, &pxa_ssp2_master_info); |
| 832 | spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info)); | 873 | spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info)); |
| 833 | 874 | ||
| @@ -21,7 +21,7 @@ · 20 unmodified lines | |||
| 21 | /* SD/MMC */ | 21 | /* SD/MMC */ |
| 22 | #define GPIO_NR_PALMZ72_SD_DETECT_N 14 | 22 | #define GPIO_NR_PALMZ72_SD_DETECT_N 14 |
| 23 | #define GPIO_NR_PALMZ72_SD_POWER_N 98 | 23 | #define GPIO_NR_PALMZ72_SD_POWER_N 98 |
| 24 | #define GPIO_NR_PALMZ72_SD_RO 115 | 24 | #define GPIO_NR_PALMZ72_SD_RO 115 |
| 25 | 25 | ||
| 26 | /* Touchscreen */ | 26 | /* Touchscreen */ |
| 27 | #define GPIO_NR_PALMZ72_WM9712_IRQ 27 | 27 | #define GPIO_NR_PALMZ72_WM9712_IRQ 27 |
| @@ -31,8 +31,7 @@ · 3 unmodified lines | |||
| 31 | 31 | ||
| 32 | /* USB */ | 32 | /* USB */ |
| 33 | #define GPIO_NR_PALMZ72_USB_DETECT_N 15 | 33 | #define GPIO_NR_PALMZ72_USB_DETECT_N 15 |
| 34 | #define GPIO_NR_PALMZ72_USB_POWER 95 | 34 | #define GPIO_NR_PALMZ72_USB_PULLUP 95 |
| 35 | #define GPIO_NR_PALMZ72_USB_PULLUP 12 | ||
| 36 | 35 | ||
| 37 | /* LCD/Backlight */ | 36 | /* LCD/Backlight */ |
| 38 | #define GPIO_NR_PALMZ72_BL_POWER 20 | 37 | #define GPIO_NR_PALMZ72_BL_POWER 20 |
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * GPIOs and interrupts for Palm Treo 680 smartphone | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _INCLUDE_TREO680_H_ | ||
| 11 | #define _INCLUDE_TREO680_H_ | ||
| 12 | |||
| 13 | /* GPIOs */ | ||
| 14 | #define GPIO_NR_TREO680_POWER_DETECT 0 | ||
| 15 | #define GPIO_NR_TREO680_AMP_EN 27 | ||
| 16 | #define GPIO_NR_TREO680_KEYB_BL 24 | ||
| 17 | #define GPIO_NR_TREO680_VIBRATE_EN 44 | ||
| 18 | #define GPIO_NR_TREO680_GREEN_LED 20 | ||
| 19 | #define GPIO_NR_TREO680_RED_LED 79 | ||
| 20 | #define GPIO_NR_TREO680_SD_DETECT_N 113 | ||
| 21 | #define GPIO_NR_TREO680_SD_READONLY 33 | ||
| 22 | #define GPIO_NR_TREO680_EP_DETECT_N 116 | ||
| 23 | #define GPIO_NR_TREO680_SD_POWER 42 | ||
| 24 | #define GPIO_NR_TREO680_USB_DETECT 1 | ||
| 25 | #define GPIO_NR_TREO680_USB_PULLUP 114 | ||
| 26 | #define GPIO_NR_TREO680_GSM_POWER 40 | ||
| 27 | #define GPIO_NR_TREO680_GSM_RESET 87 | ||
| 28 | #define GPIO_NR_TREO680_GSM_WAKE 57 | ||
| 29 | #define GPIO_NR_TREO680_GSM_HOST_WAKE 14 | ||
| 30 | #define GPIO_NR_TREO680_GSM_TRIGGER 10 | ||
| 31 | #define GPIO_NR_TREO680_BT_EN 43 | ||
| 32 | #define GPIO_NR_TREO680_IR_EN 115 | ||
| 33 | #define GPIO_NR_TREO680_IR_TXD 47 | ||
| 34 | #define GPIO_NR_TREO680_BL_POWER 38 | ||
| 35 | #define GPIO_NR_TREO680_LCD_POWER 25 | ||
| 36 | |||
| 37 | /* Various addresses */ | ||
| 38 | #define TREO680_PHYS_RAM_START 0xa0000000 | ||
| 39 | #define TREO680_PHYS_IO_START 0x40000000 | ||
| 40 | #define TREO680_STR_BASE 0xa2000000 | ||
| 41 | |||
| 42 | /* BACKLIGHT */ | ||
| 43 | #define TREO680_MAX_INTENSITY 254 | ||
| 44 | #define TREO680_DEFAULT_INTENSITY 160 | ||
| 45 | #define TREO680_LIMIT_MASK 0x7F | ||
| 46 | #define TREO680_PRESCALER 63 | ||
| 47 | #define TREO680_PERIOD_NS 3500 | ||
| 48 | |||
| 49 | #endif | ||
| @@ -37,6 +37,7 @@ · 36 unmodified lines | |||
| 37 | #include <linux/wm97xx_batt.h> | 37 | #include <linux/wm97xx_batt.h> |
| 38 | #include <linux/mtd/physmap.h> | 38 | #include <linux/mtd/physmap.h> |
| 39 | #include <linux/usb/gpio_vbus.h> | 39 | #include <linux/usb/gpio_vbus.h> |
| 40 | #include <linux/regulator/max1586.h> | ||
| 40 | 41 | ||
| 41 | #include <asm/mach-types.h> | 42 | #include <asm/mach-types.h> |
| 42 | #include <asm/mach/arch.h> | 43 | #include <asm/mach/arch.h> |
| @@ -716,6 +717,38 @@ static struct wm97xx_batt_info mioa701_battery_data = { · 673 unmodified lines | |||
| 716 | .batt_name = "mioa701_battery", | 717 | .batt_name = "mioa701_battery", |
| 717 | }; | 718 | }; |
| 718 | 719 | ||
| 720 | /* | ||
| 721 | * Voltage regulation | ||
| 722 | */ | ||
| 723 | static struct regulator_consumer_supply max1586_consumers[] = { | ||
| 724 | { | ||
| 725 | .supply = "vcc_core", | ||
| 726 | } | ||
| 727 | }; | ||
| 728 | |||
| 729 | static struct regulator_init_data max1586_v3_info = { | ||
| 730 | .constraints = { | ||
| 731 | .name = "vcc_core range", | ||
| 732 | .min_uV = 1000000, | ||
| 733 | .max_uV = 1705000, | ||
| 734 | .always_on = 1, | ||
| 735 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 736 | }, | ||
| 737 | .num_consumer_supplies = ARRAY_SIZE(max1586_consumers), | ||
| 738 | .consumer_supplies = max1586_consumers, | ||
| 739 | }; | ||
| 740 | |||
| 741 | static struct max1586_subdev_data max1586_subdevs[] = { | ||
| 742 | { .name = "vcc_core", .id = MAX1586_V3, | ||
| 743 | .platform_data = &max1586_v3_info }, | ||
| 744 | }; | ||
| 745 | |||
| 746 | static struct max1586_platform_data max1586_info = { | ||
| 747 | .subdevs = max1586_subdevs, | ||
| 748 | .num_subdevs = ARRAY_SIZE(max1586_subdevs), | ||
| 749 | .v3_gain = MAX1586_GAIN_NO_R24, /* 700..1475 mV */ | ||
| 750 | }; | ||
| 751 | |||
| 719 | /* | 752 | /* |
| 720 | * Camera interface | 753 | * Camera interface |
| 721 | */ | 754 | */ |
| @@ -725,6 +758,13 @@ struct pxacamera_platform_data mioa701_pxacamera_platform_data = { · 3 unmodified lines | |||
| 725 | .mclk_10khz = 5000, | 758 | .mclk_10khz = 5000, |
| 726 | }; | 759 | }; |
| 727 | 760 | ||
| 761 | static struct i2c_board_info __initdata mioa701_pi2c_devices[] = { | ||
| 762 | { | ||
| 763 | I2C_BOARD_INFO("max1586", 0x14), | ||
| 764 | .platform_data = &max1586_info, | ||
| 765 | }, | ||
| 766 | }; | ||
| 767 | |||
| 728 | static struct soc_camera_link iclink = { | 768 | static struct soc_camera_link iclink = { |
| 729 | .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */ | 769 | .bus_id = 0, /* Must match id in pxa27x_device_camera in device.c */ |
| 730 | }; | 770 | }; |
| @@ -825,7 +865,9 @@ static void __init mioa701_machine_init(void) · 94 unmodified lines | |||
| 825 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 865 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 826 | gsm_init(); | 866 | gsm_init(); |
| 827 | 867 | ||
| 868 | i2c_register_board_info(1, ARRAY_AND_SIZE(mioa701_pi2c_devices)); | ||
| 828 | pxa_set_i2c_info(&i2c_pdata); | 869 | pxa_set_i2c_info(&i2c_pdata); |
| 870 | pxa27x_set_i2c_power_info(NULL); | ||
| 829 | pxa_set_camera_info(&mioa701_pxacamera_platform_data); | 871 | pxa_set_camera_info(&mioa701_pxacamera_platform_data); |
| 830 | i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices)); | 872 | i2c_register_board_info(0, ARRAY_AND_SIZE(mioa701_i2c_devices)); |
| 831 | } | 873 | } |
| @@ -27,7 +27,9 @@ · 26 unmodified lines | |||
| 27 | #include <linux/pda_power.h> | 27 | #include <linux/pda_power.h> |
| 28 | #include <linux/pwm_backlight.h> | 28 | #include <linux/pwm_backlight.h> |
| 29 | #include <linux/gpio.h> | 29 | #include <linux/gpio.h> |
| 30 | #include <linux/wm97xx_batt.h> | ||
| 30 | #include <linux/power_supply.h> | 31 | #include <linux/power_supply.h> |
| 32 | #include <linux/usb/gpio_vbus.h> | ||
| 31 | 33 | ||
| 32 | #include <asm/mach-types.h> | 34 | #include <asm/mach-types.h> |
| 33 | #include <asm/mach/arch.h> | 35 | #include <asm/mach/arch.h> |
| @@ -41,6 +43,8 @@ · 7 unmodified lines | |||
| 41 | #include <mach/irda.h> | 43 | #include <mach/irda.h> |
| 42 | #include <mach/pxa27x_keypad.h> | 44 | #include <mach/pxa27x_keypad.h> |
| 43 | #include <mach/udc.h> | 45 | #include <mach/udc.h> |
| 46 | #include <mach/palmasoc.h> | ||
| 47 | |||
| 44 | #include <mach/pm.h> | 48 | #include <mach/pm.h> |
| 45 | 49 | ||
| 46 | #include "generic.h" | 50 | #include "generic.h" |
| @@ -66,6 +70,8 @@ static unsigned long palmz72_pin_config[] __initdata = { · 19 unmodified lines | |||
| 66 | GPIO29_AC97_SDATA_IN_0, | 70 | GPIO29_AC97_SDATA_IN_0, |
| 67 | GPIO30_AC97_SDATA_OUT, | 71 | GPIO30_AC97_SDATA_OUT, |
| 68 | GPIO31_AC97_SYNC, | 72 | GPIO31_AC97_SYNC, |
| 73 | GPIO89_AC97_SYSCLK, | ||
| 74 | GPIO113_AC97_nRESET, | ||
| 69 | 75 | ||
| 70 | /* IrDA */ | 76 | /* IrDA */ |
| 71 | GPIO49_GPIO, /* ir disable */ | 77 | GPIO49_GPIO, /* ir disable */ |
| @@ -77,8 +83,7 @@ static unsigned long palmz72_pin_config[] __initdata = { · 5 unmodified lines | |||
| 77 | 83 | ||
| 78 | /* USB */ | 84 | /* USB */ |
| 79 | GPIO15_GPIO, /* usb detect */ | 85 | GPIO15_GPIO, /* usb detect */ |
| 80 | GPIO12_GPIO, /* usb pullup */ | 86 | GPIO95_GPIO, /* usb pullup */ |
| 81 | GPIO95_GPIO, /* usb power */ | ||
| 82 | 87 | ||
| 83 | /* Matrix keypad */ | 88 | /* Matrix keypad */ |
| 84 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | 89 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, |
| @@ -354,6 +359,22 @@ static struct platform_device palmz72_leds = { · 269 unmodified lines | |||
| 354 | } | 359 | } |
| 355 | }; | 360 | }; |
| 356 | 361 | ||
| 362 | /****************************************************************************** | ||
| 363 | * UDC | ||
| 364 | ******************************************************************************/ | ||
| 365 | static struct gpio_vbus_mach_info palmz72_udc_info = { | ||
| 366 | .gpio_vbus = GPIO_NR_PALMZ72_USB_DETECT_N, | ||
| 367 | .gpio_pullup = GPIO_NR_PALMZ72_USB_PULLUP, | ||
| 368 | }; | ||
| 369 | |||
| 370 | static struct platform_device palmz72_gpio_vbus = { | ||
| 371 | .name = "gpio-vbus", | ||
| 372 | .id = -1, | ||
| 373 | .dev = { | ||
| 374 | .platform_data = &palmz72_udc_info, | ||
| 375 | }, | ||
| 376 | }; | ||
| 377 | |||
| 357 | /****************************************************************************** | 378 | /****************************************************************************** |
| 358 | * Power supply | 379 | * Power supply |
| 359 | ******************************************************************************/ | 380 | ******************************************************************************/ |
| @@ -421,6 +442,31 @@ static struct platform_device power_supply = { · 61 unmodified lines | |||
| 421 | }, | 442 | }, |
| 422 | }; | 443 | }; |
| 423 | 444 | ||
| 445 | /****************************************************************************** | ||
| 446 | * WM97xx battery | ||
| 447 | ******************************************************************************/ | ||
| 448 | static struct wm97xx_batt_info wm97xx_batt_pdata = { | ||
| 449 | .batt_aux = WM97XX_AUX_ID3, | ||
| 450 | .temp_aux = WM97XX_AUX_ID2, | ||
| 451 | .charge_gpio = -1, | ||
| 452 | .max_voltage = PALMZ72_BAT_MAX_VOLTAGE, | ||
| 453 | .min_voltage = PALMZ72_BAT_MIN_VOLTAGE, | ||
| 454 | .batt_mult = 1000, | ||
| 455 | .batt_div = 414, | ||
| 456 | .temp_mult = 1, | ||
| 457 | .temp_div = 1, | ||
| 458 | .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, | ||
| 459 | .batt_name = "main-batt", | ||
| 460 | }; | ||
| 461 | |||
| 462 | /****************************************************************************** | ||
| 463 | * aSoC audio | ||
| 464 | ******************************************************************************/ | ||
| 465 | static struct platform_device palmz72_asoc = { | ||
| 466 | .name = "palm27x-asoc", | ||
| 467 | .id = -1, | ||
| 468 | }; | ||
| 469 | |||
| 424 | /****************************************************************************** | 470 | /****************************************************************************** |
| 425 | * Framebuffer | 471 | * Framebuffer |
| 426 | ******************************************************************************/ | 472 | ******************************************************************************/ |
| @@ -527,17 +573,32 @@ device_initcall(palmz72_pm_init); · 100 unmodified lines | |||
| 527 | static struct platform_device *devices[] __initdata = { | 573 | static struct platform_device *devices[] __initdata = { |
| 528 | &palmz72_backlight, | 574 | &palmz72_backlight, |
| 529 | &palmz72_leds, | 575 | &palmz72_leds, |
| 576 | &palmz72_asoc, | ||
| 530 | &power_supply, | 577 | &power_supply, |
| 578 | &palmz72_gpio_vbus, | ||
| 531 | }; | 579 | }; |
| 532 | 580 | ||
| 581 | /* setup udc GPIOs initial state */ | ||
| 582 | static void __init palmz72_udc_init(void) | ||
| 583 | { | ||
| 584 | if (!gpio_request(GPIO_NR_PALMZ72_USB_PULLUP, "USB Pullup")) { | ||
| 585 | gpio_direction_output(GPIO_NR_PALMZ72_USB_PULLUP, 0); | ||
| 586 | gpio_free(GPIO_NR_PALMZ72_USB_PULLUP); | ||
| 587 | } | ||
| 588 | } | ||
| 589 | |||
| 533 | static void __init palmz72_init(void) | 590 | static void __init palmz72_init(void) |
| 534 | { | 591 | { |
| 535 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config)); | 592 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config)); |
| 593 | |||
| 536 | set_pxa_fb_info(&palmz72_lcd_screen); | 594 | set_pxa_fb_info(&palmz72_lcd_screen); |
| 537 | pxa_set_mci_info(&palmz72_mci_platform_data); | 595 | pxa_set_mci_info(&palmz72_mci_platform_data); |
| 596 | palmz72_udc_init(); | ||
| 538 | pxa_set_ac97_info(NULL); | 597 | pxa_set_ac97_info(NULL); |
| 539 | pxa_set_ficp_info(&palmz72_ficp_platform_data); | 598 | pxa_set_ficp_info(&palmz72_ficp_platform_data); |
| 540 | pxa_set_keypad_info(&palmz72_keypad_platform_data); | 599 | pxa_set_keypad_info(&palmz72_keypad_platform_data); |
| 600 | wm97xx_bat_set_pdata(&wm97xx_batt_pdata); | ||
| 601 | |||
| 541 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 602 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 542 | } | 603 | } |
| 543 | 604 | ||
| @@ -22,6 +22,7 @@ · 21 unmodified lines | |||
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/mtd/physmap.h> | 23 | #include <linux/mtd/physmap.h> |
| 24 | #include <linux/gpio.h> | 24 | #include <linux/gpio.h> |
| 25 | #include <linux/i2c.h> | ||
| 25 | #include <linux/spi/spi.h> | 26 | #include <linux/spi/spi.h> |
| 26 | #include <linux/spi/ads7846.h> | 27 | #include <linux/spi/ads7846.h> |
| 27 | #include <linux/mtd/sharpsl.h> | 28 | #include <linux/mtd/sharpsl.h> |
| @@ -486,6 +487,10 @@ static struct platform_device *devices[] __initdata = { · 458 unmodified lines | |||
| 486 | &sharpsl_rom_device, | 487 | &sharpsl_rom_device, |
| 487 | }; | 488 | }; |
| 488 | 489 | ||
| 490 | static struct i2c_board_info __initdata poodle_i2c_devices[] = { | ||
| 491 | { I2C_BOARD_INFO("wm8731", 0x1b) }, | ||
| 492 | }; | ||
| 493 | |||
| 489 | static void poodle_poweroff(void) | 494 | static void poodle_poweroff(void) |
| 490 | { | 495 | { |
| 491 | arm_machine_restart('h', NULL); | 496 | arm_machine_restart('h', NULL); |
| @@ -519,6 +524,7 @@ static void __init poodle_init(void) · 27 unmodified lines | |||
| 519 | pxa_set_mci_info(&poodle_mci_platform_data); | 524 | pxa_set_mci_info(&poodle_mci_platform_data); |
| 520 | pxa_set_ficp_info(&poodle_ficp_platform_data); | 525 | pxa_set_ficp_info(&poodle_ficp_platform_data); |
| 521 | pxa_set_i2c_info(NULL); | 526 | pxa_set_i2c_info(NULL); |
| 527 | i2c_register_board_info(0, ARRAY_AND_SIZE(poodle_i2c_devices)); | ||
| 522 | poodle_init_spi(); | 528 | poodle_init_spi(); |
| 523 | } | 529 | } |
| 524 | 530 | ||
| @@ -0,0 +1,612 @@ | |||
| 1 | /* | ||
| 2 | * Hardware definitions for Palm Treo 680 | ||
| 3 | * | ||
| 4 | * Author: Tomas Cech <sleep_walker@suse.cz> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * (find more info at www.hackndev.com) | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/platform_device.h> | ||
| 15 | #include <linux/delay.h> | ||
| 16 | #include <linux/irq.h> | ||
| 17 | #include <linux/gpio_keys.h> | ||
| 18 | #include <linux/input.h> | ||
| 19 | #include <linux/pda_power.h> | ||
| 20 | #include <linux/pwm_backlight.h> | ||
| 21 | #include <linux/gpio.h> | ||
| 22 | #include <linux/wm97xx_batt.h> | ||
| 23 | #include <linux/power_supply.h> | ||
| 24 | #include <linux/sysdev.h> | ||
| 25 | #include <linux/w1-gpio.h> | ||
| 26 | |||
| 27 | #include <asm/mach-types.h> | ||
| 28 | #include <asm/mach/arch.h> | ||
| 29 | #include <asm/mach/map.h> | ||
| 30 | |||
| 31 | #include <mach/pxa27x.h> | ||
| 32 | #include <mach/pxa27x-udc.h> | ||
| 33 | #include <mach/audio.h> | ||
| 34 | #include <mach/treo680.h> | ||
| 35 | #include <mach/mmc.h> | ||
| 36 | #include <mach/pxafb.h> | ||
| 37 | #include <mach/irda.h> | ||
| 38 | #include <mach/pxa27x_keypad.h> | ||
| 39 | #include <mach/udc.h> | ||
| 40 | #include <mach/ohci.h> | ||
| 41 | #include <mach/pxa2xx-regs.h> | ||
| 42 | #include <mach/palmasoc.h> | ||
| 43 | #include <mach/camera.h> | ||
| 44 | |||
| 45 | #include <sound/pxa2xx-lib.h> | ||
| 46 | |||
| 47 | #include "generic.h" | ||
| 48 | #include "devices.h" | ||
| 49 | |||
| 50 | /****************************************************************************** | ||
| 51 | * Pin configuration | ||
| 52 | ******************************************************************************/ | ||
| 53 | static unsigned long treo680_pin_config[] __initdata = { | ||
| 54 | /* MMC */ | ||
| 55 | GPIO32_MMC_CLK, | ||
| 56 | GPIO92_MMC_DAT_0, | ||
| 57 | GPIO109_MMC_DAT_1, | ||
| 58 | GPIO110_MMC_DAT_2, | ||
| 59 | GPIO111_MMC_DAT_3, | ||
| 60 | GPIO112_MMC_CMD, | ||
| 61 | GPIO33_GPIO, /* SD read only */ | ||
| 62 | GPIO113_GPIO, /* SD detect */ | ||
| 63 | |||
| 64 | /* AC97 */ | ||
| 65 | GPIO28_AC97_BITCLK, | ||
| 66 | GPIO29_AC97_SDATA_IN_0, | ||
| 67 | GPIO30_AC97_SDATA_OUT, | ||
| 68 | GPIO31_AC97_SYNC, | ||
| 69 | GPIO89_AC97_SYSCLK, | ||
| 70 | GPIO95_AC97_nRESET, | ||
| 71 | |||
| 72 | /* IrDA */ | ||
| 73 | GPIO46_FICP_RXD, | ||
| 74 | GPIO47_FICP_TXD, | ||
| 75 | |||
| 76 | /* PWM */ | ||
| 77 | GPIO16_PWM0_OUT, | ||
| 78 | |||
| 79 | /* USB */ | ||
| 80 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* usb detect */ | ||
| 81 | |||
| 82 | /* MATRIX KEYPAD */ | ||
| 83 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
| 84 | GPIO101_KP_MKIN_1, | ||
| 85 | GPIO102_KP_MKIN_2, | ||
| 86 | GPIO97_KP_MKIN_3, | ||
| 87 | GPIO98_KP_MKIN_4, | ||
| 88 | GPIO99_KP_MKIN_5, | ||
| 89 | GPIO91_KP_MKIN_6, | ||
| 90 | GPIO13_KP_MKIN_7, | ||
| 91 | GPIO103_KP_MKOUT_0 | MFP_LPM_DRIVE_HIGH, | ||
| 92 | GPIO104_KP_MKOUT_1, | ||
| 93 | GPIO105_KP_MKOUT_2, | ||
| 94 | GPIO106_KP_MKOUT_3, | ||
| 95 | GPIO107_KP_MKOUT_4, | ||
| 96 | GPIO108_KP_MKOUT_5, | ||
| 97 | GPIO96_KP_MKOUT_6, | ||
| 98 | GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, /* Hotsync button */ | ||
| 99 | |||
| 100 | /* LCD */ | ||
| 101 | GPIO58_LCD_LDD_0, | ||
| 102 | GPIO59_LCD_LDD_1, | ||
| 103 | GPIO60_LCD_LDD_2, | ||
| 104 | GPIO61_LCD_LDD_3, | ||
| 105 | GPIO62_LCD_LDD_4, | ||
| 106 | GPIO63_LCD_LDD_5, | ||
| 107 | GPIO64_LCD_LDD_6, | ||
| 108 | GPIO65_LCD_LDD_7, | ||
| 109 | GPIO66_LCD_LDD_8, | ||
| 110 | GPIO67_LCD_LDD_9, | ||
| 111 | GPIO68_LCD_LDD_10, | ||
| 112 | GPIO69_LCD_LDD_11, | ||
| 113 | GPIO70_LCD_LDD_12, | ||
| 114 | GPIO71_LCD_LDD_13, | ||
| 115 | GPIO72_LCD_LDD_14, | ||
| 116 | GPIO73_LCD_LDD_15, | ||
| 117 | GPIO74_LCD_FCLK, | ||
| 118 | GPIO75_LCD_LCLK, | ||
| 119 | GPIO76_LCD_PCLK, | ||
| 120 | |||
| 121 | /* Quick Capture Interface */ | ||
| 122 | GPIO84_CIF_FV, | ||
| 123 | GPIO85_CIF_LV, | ||
| 124 | GPIO53_CIF_MCLK, | ||
| 125 | GPIO54_CIF_PCLK, | ||
| 126 | GPIO81_CIF_DD_0, | ||
| 127 | GPIO55_CIF_DD_1, | ||
| 128 | GPIO51_CIF_DD_2, | ||
| 129 | GPIO50_CIF_DD_3, | ||
| 130 | GPIO52_CIF_DD_4, | ||
| 131 | GPIO48_CIF_DD_5, | ||
| 132 | GPIO17_CIF_DD_6, | ||
| 133 | GPIO12_CIF_DD_7, | ||
| 134 | |||
| 135 | /* I2C */ | ||
| 136 | GPIO117_I2C_SCL, | ||
| 137 | GPIO118_I2C_SDA, | ||
| 138 | |||
| 139 | /* GSM */ | ||
| 140 | GPIO14_GPIO | WAKEUP_ON_EDGE_BOTH, /* GSM host wake up */ | ||
| 141 | GPIO34_FFUART_RXD, | ||
| 142 | GPIO35_FFUART_CTS, | ||
| 143 | GPIO39_FFUART_TXD, | ||
| 144 | GPIO41_FFUART_RTS, | ||
| 145 | |||
| 146 | /* MISC. */ | ||
| 147 | GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* external power detect */ | ||
| 148 | GPIO15_GPIO | WAKEUP_ON_EDGE_BOTH, /* silent switch */ | ||
| 149 | GPIO116_GPIO, /* headphone detect */ | ||
| 150 | GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* bluetooth host wake up */ | ||
| 151 | }; | ||
| 152 | |||
| 153 | /****************************************************************************** | ||
| 154 | * SD/MMC card controller | ||
| 155 | ******************************************************************************/ | ||
| 156 | static int treo680_mci_init(struct device *dev, | ||
| 157 | irq_handler_t treo680_detect_int, void *data) | ||
| 158 | { | ||
| 159 | int err = 0; | ||
| 160 | |||
| 161 | /* Setup an interrupt for detecting card insert/remove events */ | ||
| 162 | err = gpio_request(GPIO_NR_TREO680_SD_DETECT_N, "SD IRQ"); | ||
| 163 | |||
| 164 | if (err) | ||
| 165 | goto err; | ||
| 166 | |||
| 167 | err = gpio_direction_input(GPIO_NR_TREO680_SD_DETECT_N); | ||
| 168 | if (err) | ||
| 169 | goto err2; | ||
| 170 | |||
| 171 | err = request_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), | ||
| 172 | treo680_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | | ||
| 173 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | ||
| 174 | "SD/MMC card detect", data); | ||
| 175 | |||
| 176 | if (err) { | ||
| 177 | dev_err(dev, "%s: cannot request SD/MMC card detect IRQ\n", | ||
| 178 | __func__); | ||
| 179 | goto err2; | ||
| 180 | } | ||
| 181 | |||
| 182 | err = gpio_request(GPIO_NR_TREO680_SD_POWER, "SD_POWER"); | ||
| 183 | if (err) | ||
| 184 | goto err3; | ||
| 185 | |||
| 186 | err = gpio_direction_output(GPIO_NR_TREO680_SD_POWER, 1); | ||
| 187 | if (err) | ||
| 188 | goto err4; | ||
| 189 | |||
| 190 | err = gpio_request(GPIO_NR_TREO680_SD_READONLY, "SD_READONLY"); | ||
| 191 | if (err) | ||
| 192 | goto err4; | ||
| 193 | |||
| 194 | err = gpio_direction_input(GPIO_NR_TREO680_SD_READONLY); | ||
| 195 | if (err) | ||
| 196 | goto err5; | ||
| 197 | |||
| 198 | return 0; | ||
| 199 | |||
| 200 | err5: | ||
| 201 | gpio_free(GPIO_NR_TREO680_SD_READONLY); | ||
| 202 | err4: | ||
| 203 | gpio_free(GPIO_NR_TREO680_SD_POWER); | ||
| 204 | err3: | ||
| 205 | free_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), data); | ||
| 206 | err2: | ||
| 207 | gpio_free(GPIO_NR_TREO680_SD_DETECT_N); | ||
| 208 | err: | ||
| 209 | return err; | ||
| 210 | } | ||
| 211 | |||
| 212 | static void treo680_mci_exit(struct device *dev, void *data) | ||
| 213 | { | ||
| 214 | gpio_free(GPIO_NR_TREO680_SD_READONLY); | ||
| 215 | gpio_free(GPIO_NR_TREO680_SD_POWER); | ||
| 216 | free_irq(gpio_to_irq(GPIO_NR_TREO680_SD_DETECT_N), data); | ||
| 217 | gpio_free(GPIO_NR_TREO680_SD_DETECT_N); | ||
| 218 | } | ||
| 219 | |||
| 220 | static void treo680_mci_power(struct device *dev, unsigned int vdd) | ||
| 221 | { | ||
| 222 | struct pxamci_platform_data *p_d = dev->platform_data; | ||
| 223 | gpio_set_value(GPIO_NR_TREO680_SD_POWER, p_d->ocr_mask & (1 << vdd)); | ||
| 224 | } | ||
| 225 | |||
| 226 | static int treo680_mci_get_ro(struct device *dev) | ||
| 227 | { | ||
| 228 | return gpio_get_value(GPIO_NR_TREO680_SD_READONLY); | ||
| 229 | } | ||
| 230 | |||
| 231 | static struct pxamci_platform_data treo680_mci_platform_data = { | ||
| 232 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 233 | .setpower = treo680_mci_power, | ||
| 234 | .get_ro = treo680_mci_get_ro, | ||
| 235 | .init = treo680_mci_init, | ||
| 236 | .exit = treo680_mci_exit, | ||
| 237 | }; | ||
| 238 | |||
| 239 | /****************************************************************************** | ||
| 240 | * GPIO keyboard | ||
| 241 | ******************************************************************************/ | ||
| 242 | static unsigned int treo680_matrix_keys[] = { | ||
| 243 | KEY(0, 0, KEY_F8), /* Red/Off/Power */ | ||
| 244 | KEY(0, 1, KEY_LEFT), | ||
| 245 | KEY(0, 2, KEY_LEFTCTRL), /* Alternate */ | ||
| 246 | KEY(0, 3, KEY_L), | ||
| 247 | KEY(0, 4, KEY_A), | ||
| 248 | KEY(0, 5, KEY_Q), | ||
| 249 | KEY(0, 6, KEY_P), | ||
| 250 | |||
| 251 | KEY(1, 0, KEY_RIGHTCTRL), /* Menu */ | ||
| 252 | KEY(1, 1, KEY_RIGHT), | ||
| 253 | KEY(1, 2, KEY_LEFTSHIFT), /* Left shift */ | ||
| 254 | KEY(1, 3, KEY_Z), | ||
| 255 | KEY(1, 4, KEY_S), | ||
| 256 | KEY(1, 5, KEY_W), | ||
| 257 | |||
| 258 | KEY(2, 0, KEY_F1), /* Phone */ | ||
| 259 | KEY(2, 1, KEY_UP), | ||
| 260 | KEY(2, 2, KEY_0), | ||
| 261 | KEY(2, 3, KEY_X), | ||
| 262 | KEY(2, 4, KEY_D), | ||
| 263 | KEY(2, 5, KEY_E), | ||
| 264 | |||
| 265 | KEY(3, 0, KEY_F10), /* Calendar */ | ||
| 266 | KEY(3, 1, KEY_DOWN), | ||
| 267 | KEY(3, 2, KEY_SPACE), | ||
| 268 | KEY(3, 3, KEY_C), | ||
| 269 | KEY(3, 4, KEY_F), | ||
| 270 | KEY(3, 5, KEY_R), | ||
| 271 | |||
| 272 | KEY(4, 0, KEY_F12), /* Mail */ | ||
| 273 | KEY(4, 1, KEY_KPENTER), | ||
| 274 | KEY(4, 2, KEY_RIGHTALT), /* Alt */ | ||
| 275 | KEY(4, 3, KEY_V), | ||
| 276 | KEY(4, 4, KEY_G), | ||
| 277 | KEY(4, 5, KEY_T), | ||
| 278 | |||
| 279 | KEY(5, 0, KEY_F9), /* Home */ | ||
| 280 | KEY(5, 1, KEY_PAGEUP), /* Side up */ | ||
| 281 | KEY(5, 2, KEY_DOT), | ||
| 282 | KEY(5, 3, KEY_B), | ||
| 283 | KEY(5, 4, KEY_H), | ||
| 284 | KEY(5, 5, KEY_Y), | ||
| 285 | |||
| 286 | KEY(6, 0, KEY_TAB), /* Side Activate */ | ||
| 287 | KEY(6, 1, KEY_PAGEDOWN), /* Side down */ | ||
| 288 | KEY(6, 2, KEY_ENTER), | ||
| 289 | KEY(6, 3, KEY_N), | ||
| 290 | KEY(6, 4, KEY_J), | ||
| 291 | KEY(6, 5, KEY_U), | ||
| 292 | |||
| 293 | KEY(7, 0, KEY_F6), /* Green/Call */ | ||
| 294 | KEY(7, 1, KEY_O), | ||
| 295 | KEY(7, 2, KEY_BACKSPACE), | ||
| 296 | KEY(7, 3, KEY_M), | ||
| 297 | KEY(7, 4, KEY_K), | ||
| 298 | KEY(7, 5, KEY_I), | ||
| 299 | }; | ||
| 300 | |||
| 301 | static struct pxa27x_keypad_platform_data treo680_keypad_platform_data = { | ||
| 302 | .matrix_key_rows = 8, | ||
| 303 | .matrix_key_cols = 7, | ||
| 304 | .matrix_key_map = treo680_matrix_keys, | ||
| 305 | .matrix_key_map_size = ARRAY_SIZE(treo680_matrix_keys), | ||
| 306 | .direct_key_map = { KEY_CONNECT }, | ||
| 307 | .direct_key_num = 1, | ||
| 308 | |||
| 309 | .debounce_interval = 30, | ||
| 310 | }; | ||
| 311 | |||
| 312 | /****************************************************************************** | ||
| 313 | * aSoC audio | ||
| 314 | ******************************************************************************/ | ||
| 315 | |||
| 316 | static pxa2xx_audio_ops_t treo680_ac97_pdata = { | ||
| 317 | .reset_gpio = 95, | ||
| 318 | }; | ||
| 319 | |||
| 320 | /****************************************************************************** | ||
| 321 | * Backlight | ||
| 322 | ******************************************************************************/ | ||
| 323 | static int treo680_backlight_init(struct device *dev) | ||
| 324 | { | ||
| 325 | int ret; | ||
| 326 | |||
| 327 | ret = gpio_request(GPIO_NR_TREO680_BL_POWER, "BL POWER"); | ||
| 328 | if (ret) | ||
| 329 | goto err; | ||
| 330 | ret = gpio_direction_output(GPIO_NR_TREO680_BL_POWER, 0); | ||
| 331 | if (ret) | ||
| 332 | goto err2; | ||
| 333 | ret = gpio_request(GPIO_NR_TREO680_LCD_POWER, "LCD POWER"); | ||
| 334 | if (ret) | ||
| 335 | goto err2; | ||
| 336 | ret = gpio_direction_output(GPIO_NR_TREO680_LCD_POWER, 0); | ||
| 337 | if (ret) | ||
| 338 | goto err3; | ||
| 339 | |||
| 340 | return 0; | ||
| 341 | err3: | ||
| 342 | gpio_free(GPIO_NR_TREO680_LCD_POWER); | ||
| 343 | err2: | ||
| 344 | gpio_free(GPIO_NR_TREO680_BL_POWER); | ||
| 345 | err: | ||
| 346 | return ret; | ||
| 347 | } | ||
| 348 | |||
| 349 | static int treo680_backlight_notify(int brightness) | ||
| 350 | { | ||
| 351 | gpio_set_value(GPIO_NR_TREO680_BL_POWER, brightness); | ||
| 352 | return TREO680_MAX_INTENSITY - brightness; | ||
| 353 | }; | ||
| 354 | |||
| 355 | static void treo680_backlight_exit(struct device *dev) | ||
| 356 | { | ||
| 357 | gpio_free(GPIO_NR_TREO680_BL_POWER); | ||
| 358 | gpio_free(GPIO_NR_TREO680_LCD_POWER); | ||
| 359 | } | ||
| 360 | |||
| 361 | static struct platform_pwm_backlight_data treo680_backlight_data = { | ||
| 362 | .pwm_id = 0, | ||
| 363 | .max_brightness = TREO680_MAX_INTENSITY, | ||
| 364 | .dft_brightness = TREO680_DEFAULT_INTENSITY, | ||
| 365 | .pwm_period_ns = TREO680_PERIOD_NS, | ||
| 366 | .init = treo680_backlight_init, | ||
| 367 | .notify = treo680_backlight_notify, | ||
| 368 | .exit = treo680_backlight_exit, | ||
| 369 | }; | ||
| 370 | |||
| 371 | static struct platform_device treo680_backlight = { | ||
| 372 | .name = "pwm-backlight", | ||
| 373 | .dev = { | ||
| 374 | .parent = &pxa27x_device_pwm0.dev, | ||
| 375 | .platform_data = &treo680_backlight_data, | ||
| 376 | }, | ||
| 377 | }; | ||
| 378 | |||
| 379 | /****************************************************************************** | ||
| 380 | * IrDA | ||
| 381 | ******************************************************************************/ | ||
| 382 | static void treo680_transceiver_mode(struct device *dev, int mode) | ||
| 383 | { | ||
| 384 | gpio_set_value(GPIO_NR_TREO680_IR_EN, mode & IR_OFF); | ||
| 385 | pxa2xx_transceiver_mode(dev, mode); | ||
| 386 | } | ||
| 387 | |||
| 388 | static int treo680_irda_startup(struct device *dev) | ||
| 389 | { | ||
| 390 | int err; | ||
| 391 | |||
| 392 | err = gpio_request(GPIO_NR_TREO680_IR_EN, "Ir port disable"); | ||
| 393 | if (err) | ||
| 394 | goto err1; | ||
| 395 | |||
| 396 | err = gpio_direction_output(GPIO_NR_TREO680_IR_EN, 1); | ||
| 397 | if (err) | ||
| 398 | goto err2; | ||
| 399 | |||
| 400 | return 0; | ||
| 401 | |||
| 402 | err2: | ||
| 403 | dev_err(dev, "treo680_irda: cannot change IR gpio direction\n"); | ||
| 404 | gpio_free(GPIO_NR_TREO680_IR_EN); | ||
| 405 | err1: | ||
| 406 | dev_err(dev, "treo680_irda: cannot allocate IR gpio\n"); | ||
| 407 | return err; | ||
| 408 | } | ||
| 409 | |||
| 410 | static void treo680_irda_shutdown(struct device *dev) | ||
| 411 | { | ||
| 412 | gpio_free(GPIO_NR_TREO680_AMP_EN); | ||
| 413 | } | ||
| 414 | |||
| 415 | static struct pxaficp_platform_data treo680_ficp_info = { | ||
| 416 | .transceiver_cap = IR_FIRMODE | IR_SIRMODE | IR_OFF, | ||
| 417 | .startup = treo680_irda_startup, | ||
| 418 | .shutdown = treo680_irda_shutdown, | ||
| 419 | .transceiver_mode = treo680_transceiver_mode, | ||
| 420 | }; | ||
| 421 | |||
| 422 | /****************************************************************************** | ||
| 423 | * UDC | ||
| 424 | ******************************************************************************/ | ||
| 425 | static struct pxa2xx_udc_mach_info treo680_udc_info __initdata = { | ||
| 426 | .gpio_vbus = GPIO_NR_TREO680_USB_DETECT, | ||
| 427 | .gpio_vbus_inverted = 1, | ||
| 428 | .gpio_pullup = GPIO_NR_TREO680_USB_PULLUP, | ||
| 429 | }; | ||
| 430 | |||
| 431 | |||
| 432 | /****************************************************************************** | ||
| 433 | * USB host | ||
| 434 | ******************************************************************************/ | ||
| 435 | static struct pxaohci_platform_data treo680_ohci_info = { | ||
| 436 | .port_mode = PMM_PERPORT_MODE, | ||
| 437 | .flags = ENABLE_PORT1 | ENABLE_PORT3, | ||
| 438 | .power_budget = 0, | ||
| 439 | }; | ||
| 440 | |||
| 441 | /****************************************************************************** | ||
| 442 | * Power supply | ||
| 443 | ******************************************************************************/ | ||
| 444 | static int power_supply_init(struct device *dev) | ||
| 445 | { | ||
| 446 | int ret; | ||
| 447 | |||
| 448 | ret = gpio_request(GPIO_NR_TREO680_POWER_DETECT, "CABLE_STATE_AC"); | ||
| 449 | if (ret) | ||
| 450 | goto err1; | ||
| 451 | ret = gpio_direction_input(GPIO_NR_TREO680_POWER_DETECT); | ||
| 452 | if (ret) | ||
| 453 | goto err2; | ||
| 454 | |||
| 455 | return 0; | ||
| 456 | |||
| 457 | err2: | ||
| 458 | gpio_free(GPIO_NR_TREO680_POWER_DETECT); | ||
| 459 | err1: | ||
| 460 | return ret; | ||
| 461 | } | ||
| 462 | |||
| 463 | static int treo680_is_ac_online(void) | ||
| 464 | { | ||
| 465 | return gpio_get_value(GPIO_NR_TREO680_POWER_DETECT); | ||
| 466 | } | ||
| 467 | |||
| 468 | static void power_supply_exit(struct device *dev) | ||
| 469 | { | ||
| 470 | gpio_free(GPIO_NR_TREO680_POWER_DETECT); | ||
| 471 | } | ||
| 472 | |||
| 473 | static char *treo680_supplicants[] = { | ||
| 474 | "main-battery", | ||
| 475 | }; | ||
| 476 | |||
| 477 | static struct pda_power_pdata power_supply_info = { | ||
| 478 | .init = power_supply_init, | ||
| 479 | .is_ac_online = treo680_is_ac_online, | ||
| 480 | .exit = power_supply_exit, | ||
| 481 | .supplied_to = treo680_supplicants, | ||
| 482 | .num_supplicants = ARRAY_SIZE(treo680_supplicants), | ||
| 483 | }; | ||
| 484 | |||
| 485 | static struct platform_device power_supply = { | ||
| 486 | .name = "pda-power", | ||
| 487 | .id = -1, | ||
| 488 | .dev = { | ||
| 489 | .platform_data = &power_supply_info, | ||
| 490 | }, | ||
| 491 | }; | ||
| 492 | |||
| 493 | /****************************************************************************** | ||
| 494 | * Vibra and LEDs | ||
| 495 | ******************************************************************************/ | ||
| 496 | static struct gpio_led gpio_leds[] = { | ||
| 497 | { | ||
| 498 | .name = "treo680:vibra:vibra", | ||
| 499 | .default_trigger = "none", | ||
| 500 | .gpio = GPIO_NR_TREO680_VIBRATE_EN, | ||
| 501 | }, | ||
| 502 | { | ||
| 503 | .name = "treo680:green:led", | ||
| 504 | .default_trigger = "mmc0", | ||
| 505 | .gpio = GPIO_NR_TREO680_GREEN_LED, | ||
| 506 | }, | ||
| 507 | { | ||
| 508 | .name = "treo680:keybbl:keybbl", | ||
| 509 | .default_trigger = "none", | ||
| 510 | .gpio = GPIO_NR_TREO680_KEYB_BL, | ||
| 511 | }, | ||
| 512 | }; | ||
| 513 | |||
| 514 | static struct gpio_led_platform_data gpio_led_info = { | ||
| 515 | .leds = gpio_leds, | ||
| 516 | .num_leds = ARRAY_SIZE(gpio_leds), | ||
| 517 | }; | ||
| 518 | |||
| 519 | static struct platform_device treo680_leds = { | ||
| 520 | .name = "leds-gpio", | ||
| 521 | .id = -1, | ||
| 522 | .dev = { | ||
| 523 | .platform_data = &gpio_led_info, | ||
| 524 | } | ||
| 525 | }; | ||
| 526 | |||
| 527 | |||
| 528 | /****************************************************************************** | ||
| 529 | * Framebuffer | ||
| 530 | ******************************************************************************/ | ||
| 531 | /* TODO: add support for 324x324 */ | ||
| 532 | static struct pxafb_mode_info treo680_lcd_modes[] = { | ||
| 533 | { | ||
| 534 | .pixclock = 86538, | ||
| 535 | .xres = 320, | ||
| 536 | .yres = 320, | ||
| 537 | .bpp = 16, | ||
| 538 | |||
| 539 | .left_margin = 20, | ||
| 540 | .right_margin = 8, | ||
| 541 | .upper_margin = 8, | ||
| 542 | .lower_margin = 5, | ||
| 543 | |||
| 544 | .hsync_len = 4, | ||
| 545 | .vsync_len = 1, | ||
| 546 | }, | ||
| 547 | }; | ||
| 548 | |||
| 549 | static struct pxafb_mach_info treo680_lcd_screen = { | ||
| 550 | .modes = treo680_lcd_modes, | ||
| 551 | .num_modes = ARRAY_SIZE(treo680_lcd_modes), | ||
| 552 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | ||
| 553 | }; | ||
| 554 | |||
| 555 | /****************************************************************************** | ||
| 556 | * Power management - standby | ||
| 557 | ******************************************************************************/ | ||
| 558 | static void __init treo680_pm_init(void) | ||
| 559 | { | ||
| 560 | static u32 resume[] = { | ||
| 561 | 0xe3a00101, /* mov r0, #0x40000000 */ | ||
| 562 | 0xe380060f, /* orr r0, r0, #0x00f00000 */ | ||
| 563 | 0xe590f008, /* ldr pc, [r0, #0x08] */ | ||
| 564 | }; | ||
| 565 | |||
| 566 | /* this is where the bootloader jumps */ | ||
| 567 | memcpy(phys_to_virt(TREO680_STR_BASE), resume, sizeof(resume)); | ||
| 568 | } | ||
| 569 | |||
| 570 | /****************************************************************************** | ||
| 571 | * Machine init | ||
| 572 | ******************************************************************************/ | ||
| 573 | static struct platform_device *devices[] __initdata = { | ||
| 574 | &treo680_backlight, | ||
| 575 | &treo680_leds, | ||
| 576 | &power_supply, | ||
| 577 | }; | ||
| 578 | |||
| 579 | /* setup udc GPIOs initial state */ | ||
| 580 | static void __init treo680_udc_init(void) | ||
| 581 | { | ||
| 582 | if (!gpio_request(GPIO_NR_TREO680_USB_PULLUP, "UDC Vbus")) { | ||
| 583 | gpio_direction_output(GPIO_NR_TREO680_USB_PULLUP, 1); | ||
| 584 | gpio_free(GPIO_NR_TREO680_USB_PULLUP); | ||
| 585 | } | ||
| 586 | } | ||
| 587 | |||
| 588 | static void __init treo680_init(void) | ||
| 589 | { | ||
| 590 | treo680_pm_init(); | ||
| 591 | pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config)); | ||
| 592 | pxa_set_keypad_info(&treo680_keypad_platform_data); | ||
| 593 | set_pxa_fb_info(&treo680_lcd_screen); | ||
| 594 | pxa_set_mci_info(&treo680_mci_platform_data); | ||
| 595 | treo680_udc_init(); | ||
| 596 | pxa_set_udc_info(&treo680_udc_info); | ||
| 597 | pxa_set_ac97_info(&treo680_ac97_pdata); | ||
| 598 | pxa_set_ficp_info(&treo680_ficp_info); | ||
| 599 | pxa_set_ohci_info(&treo680_ohci_info); | ||
| 600 | |||
| 601 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 602 | } | ||
| 603 | |||
| 604 | MACHINE_START(TREO680, "Palm Treo 680") | ||
| 605 | .phys_io = TREO680_PHYS_IO_START, | ||
| 606 | .io_pg_offst = io_p2v(0x40000000), | ||
| 607 | .boot_params = 0xa0000100, | ||
| 608 | .map_io = pxa_map_io, | ||
| 609 | .init_irq = pxa27x_init_irq, | ||
| 610 | .timer = &pxa_timer, | ||
| 611 | .init_machine = treo680_init, | ||
| 612 | MACHINE_END | ||
| @@ -27,6 +27,7 @@ · 26 unmodified lines | |||
| 27 | #include <asm/irq.h> | 27 | #include <asm/irq.h> |
| 28 | #include <asm/leds.h> | 28 | #include <asm/leds.h> |
| 29 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
| 30 | #include <asm/smp_twd.h> | ||
| 30 | #include <asm/hardware/gic.h> | 31 | #include <asm/hardware/gic.h> |
| 31 | #include <asm/hardware/cache-l2x0.h> | 32 | #include <asm/hardware/cache-l2x0.h> |
| 32 | 33 | ||
| @@ -22,7 +22,6 @@ · 21 unmodified lines | |||
| 22 | #include <linux/timer.h> | 22 | #include <linux/timer.h> |
| 23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| 24 | #include <linux/device.h> | 24 | #include <linux/device.h> |
| 25 | #include <linux/gpio.h> | ||
| 26 | #include <linux/io.h> | 25 | #include <linux/io.h> |
| 27 | 26 | ||
| 28 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| @@ -84,5 +84,15 @@ config MACH_AT2440EVB · 83 unmodified lines | |||
| 84 | help | 84 | help |
| 85 | Say Y here if you are using the AT2440EVB development board | 85 | Say Y here if you are using the AT2440EVB development board |
| 86 | 86 | ||
| 87 | config MACH_MINI2440 | ||
| 88 | bool "MINI2440 development board" | ||
| 89 | select CPU_S3C2440 | ||
| 90 | select EEPROM_AT24 | ||
| 91 | select LEDS_TRIGGER_BACKLIGHT | ||
| 92 | select SND_S3C24XX_SOC_S3C24XX_UDA134X | ||
| 93 | help | ||
| 94 | Say Y here to select support for the MINI2440. Is a 10cm x 10cm board | ||
| 95 | available via various sources. It can come with a 3.5" or 7" touch LCD. | ||
| 96 | |||
| 87 | endmenu | 97 | endmenu |
| 88 | 98 | ||
| @@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o · 21 unmodified lines | |||
| 22 | obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o | 22 | obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o |
| 23 | obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o | 23 | obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o |
| 24 | obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o | 24 | obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o |
| 25 | obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o | ||
| @@ -0,0 +1,702 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2440/mach-mini2440.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com> | ||
| 4 | * Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * and modifications by SBZ <sbz@spgui.org> and | ||
| 6 | * Weibing <http://weibing.blogbus.com> and | ||
| 7 | * Michel Pollet <buserror@gmail.com> | ||
| 8 | * | ||
| 9 | * For product information, visit http://code.google.com/p/mini2440/ | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/types.h> | ||
| 18 | #include <linux/interrupt.h> | ||
| 19 | #include <linux/list.h> | ||
| 20 | #include <linux/timer.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/gpio.h> | ||
| 23 | #include <linux/input.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | #include <linux/serial_core.h> | ||
| 26 | #include <linux/dm9000.h> | ||
| 27 | #include <linux/i2c/at24.h> | ||
| 28 | #include <linux/platform_device.h> | ||
| 29 | #include <linux/gpio_keys.h> | ||
| 30 | #include <linux/i2c.h> | ||
| 31 | #include <linux/mmc/host.h> | ||
| 32 | |||
| 33 | #include <asm/mach/arch.h> | ||
| 34 | #include <asm/mach/map.h> | ||
| 35 | |||
| 36 | #include <mach/hardware.h> | ||
| 37 | #include <mach/fb.h> | ||
| 38 | #include <asm/mach-types.h> | ||
| 39 | |||
| 40 | #include <plat/regs-serial.h> | ||
| 41 | #include <mach/regs-gpio.h> | ||
| 42 | #include <mach/leds-gpio.h> | ||
| 43 | #include <mach/regs-mem.h> | ||
| 44 | #include <mach/regs-lcd.h> | ||
| 45 | #include <mach/irqs.h> | ||
| 46 | #include <plat/nand.h> | ||
| 47 | #include <plat/iic.h> | ||
| 48 | #include <plat/mci.h> | ||
| 49 | #include <plat/udc.h> | ||
| 50 | |||
| 51 | #include <linux/mtd/mtd.h> | ||
| 52 | #include <linux/mtd/nand.h> | ||
| 53 | #include <linux/mtd/nand_ecc.h> | ||
| 54 | #include <linux/mtd/partitions.h> | ||
| 55 | |||
| 56 | #include <plat/clock.h> | ||
| 57 | #include <plat/devs.h> | ||
| 58 | #include <plat/cpu.h> | ||
| 59 | |||
| 60 | #include <sound/s3c24xx_uda134x.h> | ||
| 61 | |||
| 62 | #define MACH_MINI2440_DM9K_BASE (S3C2410_CS4 + 0x300) | ||
| 63 | |||
| 64 | static struct map_desc mini2440_iodesc[] __initdata = { | ||
| 65 | /* nothing to declare, move along */ | ||
| 66 | }; | ||
| 67 | |||
| 68 | #define UCON S3C2410_UCON_DEFAULT | ||
| 69 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | ||
| 70 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | ||
| 71 | |||
| 72 | |||
| 73 | static struct s3c2410_uartcfg mini2440_uartcfgs[] __initdata = { | ||
| 74 | [0] = { | ||
| 75 | .hwport = 0, | ||
| 76 | .flags = 0, | ||
| 77 | .ucon = UCON, | ||
| 78 | .ulcon = ULCON, | ||
| 79 | .ufcon = UFCON, | ||
| 80 | }, | ||
| 81 | [1] = { | ||
| 82 | .hwport = 1, | ||
| 83 | .flags = 0, | ||
| 84 | .ucon = UCON, | ||
| 85 | .ulcon = ULCON, | ||
| 86 | .ufcon = UFCON, | ||
| 87 | }, | ||
| 88 | [2] = { | ||
| 89 | .hwport = 2, | ||
| 90 | .flags = 0, | ||
| 91 | .ucon = UCON, | ||
| 92 | .ulcon = ULCON, | ||
| 93 | .ufcon = UFCON, | ||
| 94 | }, | ||
| 95 | }; | ||
| 96 | |||
| 97 | /* USB device UDC support */ | ||
| 98 | |||
| 99 | static void mini2440_udc_pullup(enum s3c2410_udc_cmd_e cmd) | ||
| 100 | { | ||
| 101 | pr_debug("udc: pullup(%d)\n", cmd); | ||
| 102 | |||
| 103 | switch (cmd) { | ||
| 104 | case S3C2410_UDC_P_ENABLE : | ||
| 105 | s3c2410_gpio_setpin(S3C2410_GPC(5), 1); | ||
| 106 | break; | ||
| 107 | case S3C2410_UDC_P_DISABLE : | ||
| 108 | s3c2410_gpio_setpin(S3C2410_GPC(5), 0); | ||
| 109 | break; | ||
| 110 | case S3C2410_UDC_P_RESET : | ||
| 111 | break; | ||
| 112 | default: | ||
| 113 | break; | ||
| 114 | } | ||
| 115 | } | ||
| 116 | |||
| 117 | static struct s3c2410_udc_mach_info mini2440_udc_cfg __initdata = { | ||
| 118 | .udc_command = mini2440_udc_pullup, | ||
| 119 | }; | ||
| 120 | |||
| 121 | |||
| 122 | /* LCD timing and setup */ | ||
| 123 | |||
| 124 | /* | ||
| 125 | * This macro simplifies the table bellow | ||
| 126 | */ | ||
| 127 | #define _LCD_DECLARE(_clock,_xres,margin_left,margin_right,hsync, \ | ||
| 128 | _yres,margin_top,margin_bottom,vsync, refresh) \ | ||
| 129 | .width = _xres, \ | ||
| 130 | .xres = _xres, \ | ||
| 131 | .height = _yres, \ | ||
| 132 | .yres = _yres, \ | ||
| 133 | .left_margin = margin_left, \ | ||
| 134 | .right_margin = margin_right, \ | ||
| 135 | .upper_margin = margin_top, \ | ||
| 136 | .lower_margin = margin_bottom, \ | ||
| 137 | .hsync_len = hsync, \ | ||
| 138 | .vsync_len = vsync, \ | ||
| 139 | .pixclock = ((_clock*100000000000LL) / \ | ||
| 140 | ((refresh) * \ | ||
| 141 | (hsync + margin_left + _xres + margin_right) * \ | ||
| 142 | (vsync + margin_top + _yres + margin_bottom))), \ | ||
| 143 | .bpp = 16,\ | ||
| 144 | .type = (S3C2410_LCDCON1_TFT16BPP |\ | ||
| 145 | S3C2410_LCDCON1_TFT) | ||
| 146 | |||
| 147 | struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = { | ||
| 148 | [0] = { /* mini2440 + 3.5" TFT + touchscreen */ | ||
| 149 | _LCD_DECLARE( | ||
| 150 | 7, /* The 3.5 is quite fast */ | ||
| 151 | 240, 21, 38, 6, /* x timing */ | ||
| 152 | 320, 4, 4, 2, /* y timing */ | ||
| 153 | 60), /* refresh rate */ | ||
| 154 | .lcdcon5 = (S3C2410_LCDCON5_FRM565 | | ||
| 155 | S3C2410_LCDCON5_INVVLINE | | ||
| 156 | S3C2410_LCDCON5_INVVFRAME | | ||
| 157 | S3C2410_LCDCON5_INVVDEN | | ||
| 158 | S3C2410_LCDCON5_PWREN), | ||
| 159 | }, | ||
| 160 | [1] = { /* mini2440 + 7" TFT + touchscreen */ | ||
| 161 | _LCD_DECLARE( | ||
| 162 | 10, /* the 7" runs slower */ | ||
| 163 | 800, 40, 40, 48, /* x timing */ | ||
| 164 | 480, 29, 3, 3, /* y timing */ | ||
| 165 | 50), /* refresh rate */ | ||
| 166 | .lcdcon5 = (S3C2410_LCDCON5_FRM565 | | ||
| 167 | S3C2410_LCDCON5_INVVLINE | | ||
| 168 | S3C2410_LCDCON5_INVVFRAME | | ||
| 169 | S3C2410_LCDCON5_PWREN), | ||
| 170 | }, | ||
| 171 | /* The VGA shield can outout at several resolutions. All share | ||
| 172 | * the same timings, however, anything smaller than 1024x768 | ||
| 173 | * will only be displayed in the top left corner of a 1024x768 | ||
| 174 | * XGA output unless you add optional dip switches to the shield. | ||
| 175 | * Therefore timings for other resolutions have been ommited here. | ||
| 176 | */ | ||
| 177 | [2] = { | ||
| 178 | _LCD_DECLARE( | ||
| 179 | 10, | ||
| 180 | 1024, 1, 2, 2, /* y timing */ | ||
| 181 | 768, 200, 16, 16, /* x timing */ | ||
| 182 | 24), /* refresh rate, maximum stable, | ||
| 183 | tested with the FPGA shield */ | ||
| 184 | .lcdcon5 = (S3C2410_LCDCON5_FRM565 | | ||
| 185 | S3C2410_LCDCON5_HWSWP), | ||
| 186 | }, | ||
| 187 | }; | ||
| 188 | |||
| 189 | /* todo - put into gpio header */ | ||
| 190 | |||
| 191 | #define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2)) | ||
| 192 | #define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2)) | ||
| 193 | |||
| 194 | struct s3c2410fb_mach_info mini2440_fb_info __initdata = { | ||
| 195 | .displays = &mini2440_lcd_cfg[0], /* not constant! see init */ | ||
| 196 | .num_displays = 1, | ||
| 197 | .default_display = 0, | ||
| 198 | |||
| 199 | /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN | ||
| 200 | * and disable the pull down resistors on pins we are using for LCD | ||
| 201 | * data. */ | ||
| 202 | |||
| 203 | .gpcup = (0xf << 1) | (0x3f << 10), | ||
| 204 | |||
| 205 | .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE | | ||
| 206 | S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM | | ||
| 207 | S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 | | ||
| 208 | S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 | | ||
| 209 | S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7), | ||
| 210 | |||
| 211 | .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) | | ||
| 212 | S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) | | ||
| 213 | S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) | | ||
| 214 | S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) | | ||
| 215 | S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)), | ||
| 216 | |||
| 217 | .gpdup = (0x3f << 2) | (0x3f << 10), | ||
| 218 | |||
| 219 | .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 | | ||
| 220 | S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 | | ||
| 221 | S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 | | ||
| 222 | S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 | | ||
| 223 | S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 | | ||
| 224 | S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23), | ||
| 225 | |||
| 226 | .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) | | ||
| 227 | S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) | | ||
| 228 | S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) | | ||
| 229 | S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)| | ||
| 230 | S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)| | ||
| 231 | S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)), | ||
| 232 | }; | ||
| 233 | |||
| 234 | /* MMC/SD */ | ||
| 235 | |||
| 236 | static struct s3c24xx_mci_pdata mini2440_mmc_cfg __initdata = { | ||
| 237 | .gpio_detect = S3C2410_GPG(8), | ||
| 238 | .gpio_wprotect = S3C2410_GPH(8), | ||
| 239 | .set_power = NULL, | ||
| 240 | .ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34, | ||
| 241 | }; | ||
| 242 | |||
| 243 | /* NAND Flash on MINI2440 board */ | ||
| 244 | |||
| 245 | static struct mtd_partition mini2440_default_nand_part[] __initdata = { | ||
| 246 | [0] = { | ||
| 247 | .name = "u-boot", | ||
| 248 | .size = SZ_256K, | ||
| 249 | .offset = 0, | ||
| 250 | }, | ||
| 251 | [1] = { | ||
| 252 | .name = "u-boot-env", | ||
| 253 | .size = SZ_128K, | ||
| 254 | .offset = SZ_256K, | ||
| 255 | }, | ||
| 256 | [2] = { | ||
| 257 | .name = "kernel", | ||
| 258 | /* 5 megabytes, for a kernel with no modules | ||
| 259 | * or a uImage with a ramdisk attached */ | ||
| 260 | .size = 0x00500000, | ||
| 261 | .offset = SZ_256K + SZ_128K, | ||
| 262 | }, | ||
| 263 | [3] = { | ||
| 264 | .name = "root", | ||
| 265 | .offset = SZ_256K + SZ_128K + 0x00500000, | ||
| 266 | .size = MTDPART_SIZ_FULL, | ||
| 267 | }, | ||
| 268 | }; | ||
| 269 | |||
| 270 | static struct s3c2410_nand_set mini2440_nand_sets[] __initdata = { | ||
| 271 | [0] = { | ||
| 272 | .name = "nand", | ||
| 273 | .nr_chips = 1, | ||
| 274 | .nr_partitions = ARRAY_SIZE(mini2440_default_nand_part), | ||
| 275 | .partitions = mini2440_default_nand_part, | ||
| 276 | .flash_bbt = 1, /* we use u-boot to create a BBT */ | ||
| 277 | }, | ||
| 278 | }; | ||
| 279 | |||
| 280 | static struct s3c2410_platform_nand mini2440_nand_info __initdata = { | ||
| 281 | .tacls = 0, | ||
| 282 | .twrph0 = 25, | ||
| 283 | .twrph1 = 15, | ||
| 284 | .nr_sets = ARRAY_SIZE(mini2440_nand_sets), | ||
| 285 | .sets = mini2440_nand_sets, | ||
| 286 | .ignore_unset_ecc = 1, | ||
| 287 | }; | ||
| 288 | |||
| 289 | /* DM9000AEP 10/100 ethernet controller */ | ||
| 290 | |||
| 291 | static struct resource mini2440_dm9k_resource[] __initdata = { | ||
| 292 | [0] = { | ||
| 293 | .start = MACH_MINI2440_DM9K_BASE, | ||
| 294 | .end = MACH_MINI2440_DM9K_BASE + 3, | ||
| 295 | .flags = IORESOURCE_MEM | ||
| 296 | }, | ||
| 297 | [1] = { | ||
| 298 | .start = MACH_MINI2440_DM9K_BASE + 4, | ||
| 299 | .end = MACH_MINI2440_DM9K_BASE + 7, | ||
| 300 | .flags = IORESOURCE_MEM | ||
| 301 | }, | ||
| 302 | [2] = { | ||
| 303 | .start = IRQ_EINT7, | ||
| 304 | .end = IRQ_EINT7, | ||
| 305 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
| 306 | } | ||
| 307 | }; | ||
| 308 | |||
| 309 | /* | ||
| 310 | * The DM9000 has no eeprom, and it's MAC address is set by | ||
| 311 | * the bootloader before starting the kernel. | ||
| 312 | */ | ||
| 313 | static struct dm9000_plat_data mini2440_dm9k_pdata __initdata = { | ||
| 314 | .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), | ||
| 315 | }; | ||
| 316 | |||
| 317 | static struct platform_device mini2440_device_eth __initdata = { | ||
| 318 | .name = "dm9000", | ||
| 319 | .id = -1, | ||
| 320 | .num_resources = ARRAY_SIZE(mini2440_dm9k_resource), | ||
| 321 | .resource = mini2440_dm9k_resource, | ||
| 322 | .dev = { | ||
| 323 | .platform_data = &mini2440_dm9k_pdata, | ||
| 324 | }, | ||
| 325 | }; | ||
| 326 | |||
| 327 | /* CON5 | ||
| 328 | * +--+ /-----\ | ||
| 329 | * | | | | | ||
| 330 | * | | | BAT | | ||
| 331 | * | | \_____/ | ||
| 332 | * | | | ||
| 333 | * | | +----+ +----+ | ||
| 334 | * | | | K5 | | K1 | | ||
| 335 | * | | +----+ +----+ | ||
| 336 | * | | +----+ +----+ | ||
| 337 | * | | | K4 | | K2 | | ||
| 338 | * | | +----+ +----+ | ||
| 339 | * | | +----+ +----+ | ||
| 340 | * | | | K6 | | K3 | | ||
| 341 | * | | +----+ +----+ | ||
| 342 | * ..... | ||
| 343 | */ | ||
| 344 | static struct gpio_keys_button mini2440_buttons[] __initdata = { | ||
| 345 | { | ||
| 346 | .gpio = S3C2410_GPG(0), /* K1 */ | ||
| 347 | .code = KEY_F1, | ||
| 348 | .desc = "Button 1", | ||
| 349 | .active_low = 1, | ||
| 350 | }, | ||
| 351 | { | ||
| 352 | .gpio = S3C2410_GPG(3), /* K2 */ | ||
| 353 | .code = KEY_F2, | ||
| 354 | .desc = "Button 2", | ||
| 355 | .active_low = 1, | ||
| 356 | }, | ||
| 357 | { | ||
| 358 | .gpio = S3C2410_GPG(5), /* K3 */ | ||
| 359 | .code = KEY_F3, | ||
| 360 | .desc = "Button 3", | ||
| 361 | .active_low = 1, | ||
| 362 | }, | ||
| 363 | { | ||
| 364 | .gpio = S3C2410_GPG(6), /* K4 */ | ||
| 365 | .code = KEY_POWER, | ||
| 366 | .desc = "Power", | ||
| 367 | .active_low = 1, | ||
| 368 | }, | ||
| 369 | { | ||
| 370 | .gpio = S3C2410_GPG(7), /* K5 */ | ||
| 371 | .code = KEY_F5, | ||
| 372 | .desc = "Button 5", | ||
| 373 | .active_low = 1, | ||
| 374 | }, | ||
| 375 | #if 0 | ||
| 376 | /* this pin is also known as TCLK1 and seems to already | ||
| 377 | * marked as "in use" somehow in the kernel -- possibly wrongly */ | ||
| 378 | { | ||
| 379 | .gpio = S3C2410_GPG(11), /* K6 */ | ||
| 380 | .code = KEY_F6, | ||
| 381 | .desc = "Button 6", | ||
| 382 | .active_low = 1, | ||
| 383 | }, | ||
| 384 | #endif | ||
| 385 | }; | ||
| 386 | |||
| 387 | static struct gpio_keys_platform_data mini2440_button_data __initdata = { | ||
| 388 | .buttons = mini2440_buttons, | ||
| 389 | .nbuttons = ARRAY_SIZE(mini2440_buttons), | ||
| 390 | }; | ||
| 391 | |||
| 392 | static struct platform_device mini2440_button_device __initdata = { | ||
| 393 | .name = "gpio-keys", | ||
| 394 | .id = -1, | ||
| 395 | .dev = { | ||
| 396 | .platform_data = &mini2440_button_data, | ||
| 397 | } | ||
| 398 | }; | ||
| 399 | |||
| 400 | /* LEDS */ | ||
| 401 | |||
| 402 | static struct s3c24xx_led_platdata mini2440_led1_pdata __initdata = { | ||
| 403 | .name = "led1", | ||
| 404 | .gpio = S3C2410_GPB(5), | ||
| 405 | .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, | ||
| 406 | .def_trigger = "heartbeat", | ||
| 407 | }; | ||
| 408 | |||
| 409 | static struct s3c24xx_led_platdata mini2440_led2_pdata __initdata = { | ||
| 410 | .name = "led2", | ||
| 411 | .gpio = S3C2410_GPB(6), | ||
| 412 | .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, | ||
| 413 | .def_trigger = "nand-disk", | ||
| 414 | }; | ||
| 415 | |||
| 416 | static struct s3c24xx_led_platdata mini2440_led3_pdata __initdata = { | ||
| 417 | .name = "led3", | ||
| 418 | .gpio = S3C2410_GPB(7), | ||
| 419 | .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, | ||
| 420 | .def_trigger = "mmc0", | ||
| 421 | }; | ||
| 422 | |||
| 423 | static struct s3c24xx_led_platdata mini2440_led4_pdata __initdata = { | ||
| 424 | .name = "led4", | ||
| 425 | .gpio = S3C2410_GPB(8), | ||
| 426 | .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, | ||
| 427 | .def_trigger = "", | ||
| 428 | }; | ||
| 429 | |||
| 430 | static struct s3c24xx_led_platdata mini2440_led_backlight_pdata __initdata = { | ||
| 431 | .name = "backlight", | ||
| 432 | .gpio = S3C2410_GPG(4), | ||
| 433 | .def_trigger = "backlight", | ||
| 434 | }; | ||
| 435 | |||
| 436 | static struct platform_device mini2440_led1 __initdata = { | ||
| 437 | .name = "s3c24xx_led", | ||
| 438 | .id = 1, | ||
| 439 | .dev = { | ||
| 440 | .platform_data = &mini2440_led1_pdata, | ||
| 441 | }, | ||
| 442 | }; | ||
| 443 | |||
| 444 | static struct platform_device mini2440_led2 __initdata = { | ||
| 445 | .name = "s3c24xx_led", | ||
| 446 | .id = 2, | ||
| 447 | .dev = { | ||
| 448 | .platform_data = &mini2440_led2_pdata, | ||
| 449 | }, | ||
| 450 | }; | ||
| 451 | |||
| 452 | static struct platform_device mini2440_led3 __initdata = { | ||
| 453 | .name = "s3c24xx_led", | ||
| 454 | .id = 3, | ||
| 455 | .dev = { | ||
| 456 | .platform_data = &mini2440_led3_pdata, | ||
| 457 | }, | ||
| 458 | }; | ||
| 459 | |||
| 460 | static struct platform_device mini2440_led4 __initdata = { | ||
| 461 | .name = "s3c24xx_led", | ||
| 462 | .id = 4, | ||
| 463 | .dev = { | ||
| 464 | .platform_data = &mini2440_led4_pdata, | ||
| 465 | }, | ||
| 466 | }; | ||
| 467 | |||
| 468 | static struct platform_device mini2440_led_backlight __initdata = { | ||
| 469 | .name = "s3c24xx_led", | ||
| 470 | .id = 5, | ||
| 471 | .dev = { | ||
| 472 | .platform_data = &mini2440_led_backlight_pdata, | ||
| 473 | }, | ||
| 474 | }; | ||
| 475 | |||
| 476 | /* AUDIO */ | ||
| 477 | |||
| 478 | static struct s3c24xx_uda134x_platform_data mini2440_audio_pins __initdata = { | ||
| 479 | .l3_clk = S3C2410_GPB(4), | ||
| 480 | .l3_mode = S3C2410_GPB(2), | ||
| 481 | .l3_data = S3C2410_GPB(3), | ||
| 482 | .model = UDA134X_UDA1341 | ||
| 483 | }; | ||
| 484 | |||
| 485 | static struct platform_device mini2440_audio __initdata = { | ||
| 486 | .name = "s3c24xx_uda134x", | ||
| 487 | .id = 0, | ||
| 488 | .dev = { | ||
| 489 | .platform_data = &mini2440_audio_pins, | ||
| 490 | }, | ||
| 491 | }; | ||
| 492 | |||
| 493 | /* | ||
| 494 | * I2C devices | ||
| 495 | */ | ||
| 496 | static struct at24_platform_data at24c08 = { | ||
| 497 | .byte_len = SZ_8K / 8, | ||
| 498 | .page_size = 16, | ||
| 499 | }; | ||
| 500 | |||
| 501 | static struct i2c_board_info mini2440_i2c_devs[] __initdata = { | ||
| 502 | { | ||
| 503 | I2C_BOARD_INFO("24c08", 0x50), | ||
| 504 | .platform_data = &at24c08, | ||
| 505 | }, | ||
| 506 | }; | ||
| 507 | |||
| 508 | static struct platform_device *mini2440_devices[] __initdata = { | ||
| 509 | &s3c_device_usb, | ||
| 510 | &s3c_device_wdt, | ||
| 511 | /* &s3c_device_adc,*/ /* ADC doesn't like living with touchscreen ! */ | ||
| 512 | &s3c_device_i2c0, | ||
| 513 | &s3c_device_rtc, | ||
| 514 | &s3c_device_usbgadget, | ||
| 515 | &mini2440_device_eth, | ||
| 516 | &mini2440_led1, | ||
| 517 | &mini2440_led2, | ||
| 518 | &mini2440_led3, | ||
| 519 | &mini2440_led4, | ||
| 520 | &mini2440_button_device, | ||
| 521 | &s3c_device_nand, | ||
| 522 | &s3c_device_sdi, | ||
| 523 | &s3c_device_iis, | ||
| 524 | &mini2440_audio, | ||
| 525 | /* &s3c_device_timer[0],*/ /* buzzer pwm, no API for it */ | ||
| 526 | /* remaining devices are optional */ | ||
| 527 | }; | ||
| 528 | |||
| 529 | static void __init mini2440_map_io(void) | ||
| 530 | { | ||
| 531 | s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); | ||
| 532 | s3c24xx_init_clocks(12000000); | ||
| 533 | s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); | ||
| 534 | |||
| 535 | s3c_device_nand.dev.platform_data = &mini2440_nand_info; | ||
| 536 | s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg; | ||
| 537 | } | ||
| 538 | |||
| 539 | /* | ||
| 540 | * mini2440_features string | ||
| 541 | * | ||
| 542 | * t = Touchscreen present | ||
| 543 | * b = backlight control | ||
| 544 | * c = camera [TODO] | ||
| 545 | * 0-9 LCD configuration | ||
| 546 | * | ||
| 547 | */ | ||
| 548 | static char mini2440_features_str[12] __initdata = "0tb"; | ||
| 549 | |||
| 550 | static int __init mini2440_features_setup(char *str) | ||
| 551 | { | ||
| 552 | if (str) | ||
| 553 | strlcpy(mini2440_features_str, str, sizeof(mini2440_features_str)); | ||
| 554 | return 1; | ||
| 555 | } | ||
| 556 | |||
| 557 | __setup("mini2440=", mini2440_features_setup); | ||
| 558 | |||
| 559 | #define FEATURE_SCREEN (1 << 0) | ||
| 560 | #define FEATURE_BACKLIGHT (1 << 1) | ||
| 561 | #define FEATURE_TOUCH (1 << 2) | ||
| 562 | #define FEATURE_CAMERA (1 << 3) | ||
| 563 | |||
| 564 | struct mini2440_features_t { | ||
| 565 | int count; | ||
| 566 | int done; | ||
| 567 | int lcd_index; | ||
| 568 | struct platform_device *optional[8]; | ||
| 569 | }; | ||
| 570 | |||
| 571 | static void mini2440_parse_features( | ||
| 572 | struct mini2440_features_t * features, | ||
| 573 | const char * features_str ) | ||
| 574 | { | ||
| 575 | const char * fp = features_str; | ||
| 576 | |||
| 577 | features->count = 0; | ||
| 578 | features->done = 0; | ||
| 579 | features->lcd_index = -1; | ||
| 580 | |||
| 581 | while (*fp) { | ||
| 582 | char f = *fp++; | ||
| 583 | |||
| 584 | switch (f) { | ||
| 585 | case '0'...'9': /* tft screen */ | ||
| 586 | if (features->done & FEATURE_SCREEN) { | ||
| 587 | printk(KERN_INFO "MINI2440: '%c' ignored, " | ||
| 588 | "screen type already set\n", f); | ||
| 589 | } else { | ||
| 590 | int li = f - '0'; | ||
| 591 | if (li >= ARRAY_SIZE(mini2440_lcd_cfg)) | ||
| 592 | printk(KERN_INFO "MINI2440: " | ||
| 593 | "'%c' out of range LCD mode\n", f); | ||
| 594 | else { | ||
| 595 | features->optional[features->count++] = | ||
| 596 | &s3c_device_lcd; | ||
| 597 | features->lcd_index = li; | ||
| 598 | } | ||
| 599 | } | ||
| 600 | features->done |= FEATURE_SCREEN; | ||
| 601 | break; | ||
| 602 | case 'b': | ||
| 603 | if (features->done & FEATURE_BACKLIGHT) | ||
| 604 | printk(KERN_INFO "MINI2440: '%c' ignored, " | ||
| 605 | "backlight already set\n", f); | ||
| 606 | else { | ||
| 607 | features->optional[features->count++] = | ||
| 608 | &mini2440_led_backlight; | ||
| 609 | } | ||
| 610 | features->done |= FEATURE_BACKLIGHT; | ||
| 611 | break; | ||
| 612 | case 't': | ||
| 613 | printk(KERN_INFO "MINI2440: '%c' ignored, " | ||
| 614 | "touchscreen not compiled in\n", f); | ||
| 615 | break; | ||
| 616 | case 'c': | ||
| 617 | if (features->done & FEATURE_CAMERA) | ||
| 618 | printk(KERN_INFO "MINI2440: '%c' ignored, " | ||
| 619 | "camera already registered\n", f); | ||
| 620 | else | ||
| 621 | features->optional[features->count++] = | ||
| 622 | &s3c_device_camif; | ||
| 623 | features->done |= FEATURE_CAMERA; | ||
| 624 | break; | ||
| 625 | } | ||
| 626 | } | ||
| 627 | } | ||
| 628 | |||
| 629 | static void __init mini2440_init(void) | ||
| 630 | { | ||
| 631 | struct mini2440_features_t features = { 0 }; | ||
| 632 | int i; | ||
| 633 | |||
| 634 | printk(KERN_INFO "MINI2440: Option string mini2440=%s\n", | ||
| 635 | mini2440_features_str); | ||
| 636 | |||
| 637 | /* Parse the feature string */ | ||
| 638 | mini2440_parse_features(&features, mini2440_features_str); | ||
| 639 | |||
| 640 | /* turn LCD on */ | ||
| 641 | s3c2410_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND); | ||
| 642 | |||
| 643 | /* Turn the backlight early on */ | ||
| 644 | s3c2410_gpio_setpin(S3C2410_GPG(4), 1); | ||
| 645 | s3c2410_gpio_cfgpin(S3C2410_GPG(4), S3C2410_GPIO_OUTPUT); | ||
| 646 | |||
| 647 | /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */ | ||
| 648 | s3c2410_gpio_pullup(S3C2410_GPB(1), 0); | ||
| 649 | s3c2410_gpio_setpin(S3C2410_GPB(1), 0); | ||
| 650 | s3c2410_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT); | ||
| 651 | |||
| 652 | /* Make sure the D+ pullup pin is output */ | ||
| 653 | s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT); | ||
| 654 | |||
| 655 | /* mark the key as input, without pullups (there is one on the board) */ | ||
| 656 | for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) { | ||
| 657 | s3c2410_gpio_pullup(mini2440_buttons[i].gpio, 0); | ||
| 658 | s3c2410_gpio_cfgpin(mini2440_buttons[i].gpio, | ||
| 659 | S3C2410_GPIO_INPUT); | ||
| 660 | } | ||
| 661 | if (features.lcd_index != -1) { | ||
| 662 | int li; | ||
| 663 | |||
| 664 | mini2440_fb_info.displays = | ||
| 665 | &mini2440_lcd_cfg[features.lcd_index]; | ||
| 666 | |||
| 667 | printk(KERN_INFO "MINI2440: LCD"); | ||
| 668 | for (li = 0; li < ARRAY_SIZE(mini2440_lcd_cfg); li++) | ||
| 669 | if (li == features.lcd_index) | ||
| 670 | printk(" [%d:%dx%d]", li, | ||
| 671 | mini2440_lcd_cfg[li].width, | ||
| 672 | mini2440_lcd_cfg[li].height); | ||
| 673 | else | ||
| 674 | printk(" %d:%dx%d", li, | ||
| 675 | mini2440_lcd_cfg[li].width, | ||
| 676 | mini2440_lcd_cfg[li].height); | ||
| 677 | printk("\n"); | ||
| 678 | s3c24xx_fb_set_platdata(&mini2440_fb_info); | ||
| 679 | } | ||
| 680 | s3c24xx_udc_set_platdata(&mini2440_udc_cfg); | ||
| 681 | s3c_i2c0_set_platdata(NULL); | ||
| 682 | i2c_register_board_info(0, mini2440_i2c_devs, | ||
| 683 | ARRAY_SIZE(mini2440_i2c_devs)); | ||
| 684 | |||
| 685 | platform_add_devices(mini2440_devices, ARRAY_SIZE(mini2440_devices)); | ||
| 686 | |||
| 687 | if (features.count) /* the optional features */ | ||
| 688 | platform_add_devices(features.optional, features.count); | ||
| 689 | |||
| 690 | } | ||
| 691 | |||
| 692 | |||
| 693 | MACHINE_START(MINI2440, "MINI2440") | ||
| 694 | /* Maintainer: Michel Pollet <buserror@gmail.com> */ | ||
| 695 | .phys_io = S3C2410_PA_UART, | ||
| 696 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | ||
| 697 | .boot_params = S3C2410_SDRAM_PA + 0x100, | ||
| 698 | .map_io = mini2440_map_io, | ||
| 699 | .init_machine = mini2440_init, | ||
| 700 | .init_irq = s3c24xx_init_irq, | ||
| 701 | .timer = &s3c24xx_timer, | ||
| 702 | MACHINE_END | ||
| @@ -24,6 +24,18 @@ config SMDK2440_CPU2442 · 23 unmodified lines | |||
| 24 | depends on ARCH_S3C2440 | 24 | depends on ARCH_S3C2440 |
| 25 | select CPU_S3C2442 | 25 | select CPU_S3C2442 |
| 26 | 26 | ||
| 27 | config MACH_NEO1973_GTA02 | ||
| 28 | bool "Openmoko GTA02 / Freerunner phone" | ||
| 29 | select CPU_S3C2442 | ||
| 30 | select MFD_PCF50633 | ||
| 31 | select PCF50633_GPIO | ||
| 32 | select I2C | ||
| 33 | select POWER_SUPPLY | ||
| 34 | select MACH_NEO1973 | ||
| 35 | select S3C2410_PWM | ||
| 36 | help | ||
| 37 | Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone | ||
| 38 | |||
| 27 | 39 | ||
| 28 | endmenu | 40 | endmenu |
| 29 | 41 | ||
| @@ -12,5 +12,7 @@ obj- := · 11 unmodified lines | |||
| 12 | obj-$(CONFIG_CPU_S3C2442) += s3c2442.o | 12 | obj-$(CONFIG_CPU_S3C2442) += s3c2442.o |
| 13 | obj-$(CONFIG_CPU_S3C2442) += clock.o | 13 | obj-$(CONFIG_CPU_S3C2442) += clock.o |
| 14 | 14 | ||
| 15 | obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o | ||
| 16 | |||
| 15 | # Machine support | 17 | # Machine support |
| 16 | 18 | ||
| @@ -0,0 +1,84 @@ | |||
| 1 | #ifndef _GTA02_H | ||
| 2 | #define _GTA02_H | ||
| 3 | |||
| 4 | #include <mach/regs-gpio.h> | ||
| 5 | |||
| 6 | /* Different hardware revisions, passed in ATAG_REVISION by u-boot */ | ||
| 7 | #define GTA02v1_SYSTEM_REV 0x00000310 | ||
| 8 | #define GTA02v2_SYSTEM_REV 0x00000320 | ||
| 9 | #define GTA02v3_SYSTEM_REV 0x00000330 | ||
| 10 | #define GTA02v4_SYSTEM_REV 0x00000340 | ||
| 11 | #define GTA02v5_SYSTEM_REV 0x00000350 | ||
| 12 | /* since A7 is basically same as A6, we use A6 PCB ID */ | ||
| 13 | #define GTA02v6_SYSTEM_REV 0x00000360 | ||
| 14 | |||
| 15 | #define GTA02_GPIO_n3DL_GSM S3C2410_GPA(13) /* v1 + v2 + v3 only */ | ||
| 16 | |||
| 17 | #define GTA02_GPIO_PWR_LED1 S3C2410_GPB(0) | ||
| 18 | #define GTA02_GPIO_PWR_LED2 S3C2410_GPB(1) | ||
| 19 | #define GTA02_GPIO_AUX_LED S3C2410_GPB(2) | ||
| 20 | #define GTA02_GPIO_VIBRATOR_ON S3C2410_GPB(3) | ||
| 21 | #define GTA02_GPIO_MODEM_RST S3C2410_GPB(5) | ||
| 22 | #define GTA02_GPIO_BT_EN S3C2410_GPB(6) | ||
| 23 | #define GTA02_GPIO_MODEM_ON S3C2410_GPB(7) | ||
| 24 | #define GTA02_GPIO_EXTINT8 S3C2410_GPB(8) | ||
| 25 | #define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9) | ||
| 26 | |||
| 27 | #define GTA02_GPIO_PIO5 S3C2410_GPC(5) /* v3 + v4 only */ | ||
| 28 | |||
| 29 | #define GTA02v3_GPIO_nG1_CS S3C2410_GPD(12) /* v3 + v4 only */ | ||
| 30 | #define GTA02v3_GPIO_nG2_CS S3C2410_GPD(13) /* v3 + v4 only */ | ||
| 31 | #define GTA02v5_GPIO_HDQ S3C2410_GPD(14) /* v5 + */ | ||
| 32 | |||
| 33 | #define GTA02_GPIO_nG1_INT S3C2410_GPF(0) | ||
| 34 | #define GTA02_GPIO_IO1 S3C2410_GPF(1) | ||
| 35 | #define GTA02_GPIO_PIO_2 S3C2410_GPF(2) /* v2 + v3 + v4 only */ | ||
| 36 | #define GTA02_GPIO_JACK_INSERT S3C2410_GPF(4) | ||
| 37 | #define GTA02_GPIO_WLAN_GPIO1 S3C2410_GPF(5) /* v2 + v3 + v4 only */ | ||
| 38 | #define GTA02_GPIO_AUX_KEY S3C2410_GPF(6) | ||
| 39 | #define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7) | ||
| 40 | |||
| 41 | #define GTA02_GPIO_3D_IRQ S3C2410_GPG(4) | ||
| 42 | #define GTA02v2_GPIO_nG2_INT S3C2410_GPG(8) /* v2 + v3 + v4 only */ | ||
| 43 | #define GTA02v3_GPIO_nUSB_OC S3C2410_GPG(9) /* v3 + v4 only */ | ||
| 44 | #define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG(10) /* v3 + v4 only */ | ||
| 45 | #define GTA02v3_GPIO_nGSM_OC S3C2410_GPG(11) /* v3 + v4 only */ | ||
| 46 | |||
| 47 | #define GTA02_GPIO_AMP_SHUT S3C2440_GPJ1 /* v2 + v3 + v4 only */ | ||
| 48 | #define GTA02v1_GPIO_WLAN_GPIO10 S3C2440_GPJ2 | ||
| 49 | #define GTA02_GPIO_HP_IN S3C2440_GPJ2 /* v2 + v3 + v4 only */ | ||
| 50 | #define GTA02_GPIO_INT0 S3C2440_GPJ3 /* v2 + v3 + v4 only */ | ||
| 51 | #define GTA02_GPIO_nGSM_EN S3C2440_GPJ4 | ||
| 52 | #define GTA02_GPIO_3D_RESET S3C2440_GPJ5 | ||
| 53 | #define GTA02_GPIO_nDL_GSM S3C2440_GPJ6 /* v4 + v5 only */ | ||
| 54 | #define GTA02_GPIO_WLAN_GPIO0 S3C2440_GPJ7 | ||
| 55 | #define GTA02v1_GPIO_BAT_ID S3C2440_GPJ8 | ||
| 56 | #define GTA02_GPIO_KEEPACT S3C2440_GPJ8 | ||
| 57 | #define GTA02v1_GPIO_HP_IN S3C2440_GPJ10 | ||
| 58 | #define GTA02_CHIP_PWD S3C2440_GPJ11 /* v2 + v3 + v4 only */ | ||
| 59 | #define GTA02_GPIO_nWLAN_RESET S3C2440_GPJ12 /* v2 + v3 + v4 only */ | ||
| 60 | |||
| 61 | #define GTA02_IRQ_GSENSOR_1 IRQ_EINT0 | ||
| 62 | #define GTA02_IRQ_MODEM IRQ_EINT1 | ||
| 63 | #define GTA02_IRQ_PIO_2 IRQ_EINT2 /* v2 + v3 + v4 only */ | ||
| 64 | #define GTA02_IRQ_nJACK_INSERT IRQ_EINT4 | ||
| 65 | #define GTA02_IRQ_WLAN_GPIO1 IRQ_EINT5 | ||
| 66 | #define GTA02_IRQ_AUX IRQ_EINT6 | ||
| 67 | #define GTA02_IRQ_nHOLD IRQ_EINT7 | ||
| 68 | #define GTA02_IRQ_PCF50633 IRQ_EINT9 | ||
| 69 | #define GTA02_IRQ_3D IRQ_EINT12 | ||
| 70 | #define GTA02_IRQ_GSENSOR_2 IRQ_EINT16 /* v2 + v3 + v4 only */ | ||
| 71 | #define GTA02v3_IRQ_nUSB_OC IRQ_EINT17 /* v3 + v4 only */ | ||
| 72 | #define GTA02v3_IRQ_nUSB_FLT IRQ_EINT18 /* v3 + v4 only */ | ||
| 73 | #define GTA02v3_IRQ_nGSM_OC IRQ_EINT19 /* v3 + v4 only */ | ||
| 74 | |||
| 75 | /* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */ | ||
| 76 | #define GTA02_PCB_ID1_0 S3C2410_GPC(13) | ||
| 77 | #define GTA02_PCB_ID1_1 S3C2410_GPC(15) | ||
| 78 | #define GTA02_PCB_ID1_2 S3C2410_GPD(0) | ||
| 79 | #define GTA02_PCB_ID2_0 S3C2410_GPD(3) | ||
| 80 | #define GTA02_PCB_ID2_1 S3C2410_GPD(4) | ||
| 81 | |||
| 82 | int gta02_get_pcb_revision(void); | ||
| 83 | |||
| 84 | #endif /* _GTA02_H */ | ||
| @@ -0,0 +1,645 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-s3c2442/mach-gta02.c | ||
| 3 | * | ||
| 4 | * S3C2442 Machine Support for Openmoko GTA02 / FreeRunner. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2006-2009 by Openmoko, Inc. | ||
| 7 | * Authors: Harald Welte <laforge@openmoko.org> | ||
| 8 | * Andy Green <andy@openmoko.org> | ||
| 9 | * Werner Almesberger <werner@openmoko.org> | ||
| 10 | * All rights reserved. | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or | ||
| 13 | * modify it under the terms of the GNU General Public License as | ||
| 14 | * published by the Free Software Foundation; either version 2 of | ||
| 15 | * the License, or (at your option) any later version. | ||
| 16 | * | ||
| 17 | * This program is distributed in the hope that it will be useful, | ||
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 20 | * GNU General Public License for more details. | ||
| 21 | * | ||
| 22 | * You should have received a copy of the GNU General Public License | ||
| 23 | * along with this program; if not, write to the Free Software | ||
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 25 | * MA 02111-1307 USA | ||
| 26 | * | ||
| 27 | */ | ||
| 28 | |||
| 29 | #include <linux/kernel.h> | ||
| 30 | #include <linux/types.h> | ||
| 31 | #include <linux/interrupt.h> | ||
| 32 | #include <linux/list.h> | ||
| 33 | #include <linux/delay.h> | ||
| 34 | #include <linux/timer.h> | ||
| 35 | #include <linux/init.h> | ||
| 36 | #include <linux/gpio.h> | ||
| 37 | #include <linux/workqueue.h> | ||
| 38 | #include <linux/platform_device.h> | ||
| 39 | #include <linux/serial_core.h> | ||
| 40 | #include <linux/spi/spi.h> | ||
| 41 | |||
| 42 | #include <linux/mmc/host.h> | ||
| 43 | |||
| 44 | #include <linux/mtd/mtd.h> | ||
| 45 | #include <linux/mtd/nand.h> | ||
| 46 | #include <linux/mtd/nand_ecc.h> | ||
| 47 | #include <linux/mtd/partitions.h> | ||
| 48 | #include <linux/mtd/physmap.h> | ||
| 49 | #include <linux/io.h> | ||
| 50 | |||
| 51 | #include <linux/i2c.h> | ||
| 52 | #include <linux/backlight.h> | ||
| 53 | #include <linux/regulator/machine.h> | ||
| 54 | |||
| 55 | #include <linux/mfd/pcf50633/core.h> | ||
| 56 | #include <linux/mfd/pcf50633/mbc.h> | ||
| 57 | #include <linux/mfd/pcf50633/adc.h> | ||
| 58 | #include <linux/mfd/pcf50633/gpio.h> | ||
| 59 | #include <linux/mfd/pcf50633/pmic.h> | ||
| 60 | |||
| 61 | #include <asm/mach/arch.h> | ||
| 62 | #include <asm/mach/map.h> | ||
| 63 | #include <asm/mach/irq.h> | ||
| 64 | |||
| 65 | #include <asm/irq.h> | ||
| 66 | #include <asm/mach-types.h> | ||
| 67 | |||
| 68 | #include <mach/regs-irq.h> | ||
| 69 | #include <mach/regs-gpio.h> | ||
| 70 | #include <mach/regs-gpioj.h> | ||
| 71 | #include <mach/fb.h> | ||
| 72 | |||
| 73 | #include <mach/spi.h> | ||
| 74 | #include <mach/spi-gpio.h> | ||
| 75 | #include <plat/usb-control.h> | ||
| 76 | #include <mach/regs-mem.h> | ||
| 77 | #include <mach/hardware.h> | ||
| 78 | |||
| 79 | #include <mach/gta02.h> | ||
| 80 | |||
| 81 | #include <plat/regs-serial.h> | ||
| 82 | #include <plat/nand.h> | ||
| 83 | #include <plat/devs.h> | ||
| 84 | #include <plat/cpu.h> | ||
| 85 | #include <plat/pm.h> | ||
| 86 | #include <plat/udc.h> | ||
| 87 | #include <plat/gpio-cfg.h> | ||
| 88 | #include <plat/iic.h> | ||
| 89 | |||
| 90 | static struct pcf50633 *gta02_pcf; | ||
| 91 | |||
| 92 | /* | ||
| 93 | * This gets called every 1ms when we paniced. | ||
| 94 | */ | ||
| 95 | |||
| 96 | static long gta02_panic_blink(long count) | ||
| 97 | { | ||
| 98 | long delay = 0; | ||
| 99 | static long last_blink; | ||
| 100 | static char led; | ||
| 101 | |||
| 102 | /* Fast blink: 200ms period. */ | ||
| 103 | if (count - last_blink < 100) | ||
| 104 | return 0; | ||
| 105 | |||
| 106 | led ^= 1; | ||
| 107 | gpio_direction_output(GTA02_GPIO_AUX_LED, led); | ||
| 108 | |||
| 109 | last_blink = count; | ||
| 110 | |||
| 111 | return delay; | ||
| 112 | } | ||
| 113 | |||
| 114 | |||
| 115 | static struct map_desc gta02_iodesc[] __initdata = { | ||
| 116 | { | ||
| 117 | .virtual = 0xe0000000, | ||
| 118 | .pfn = __phys_to_pfn(S3C2410_CS3 + 0x01000000), | ||
| 119 | .length = SZ_1M, | ||
| 120 | .type = MT_DEVICE | ||
| 121 | }, | ||
| 122 | }; | ||
| 123 | |||
| 124 | #define UCON (S3C2410_UCON_DEFAULT | S3C2443_UCON_RXERR_IRQEN) | ||
| 125 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) | ||
| 126 | #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) | ||
| 127 | |||
| 128 | static struct s3c2410_uartcfg gta02_uartcfgs[] = { | ||
| 129 | [0] = { | ||
| 130 | .hwport = 0, | ||
| 131 | .flags = 0, | ||
| 132 | .ucon = UCON, | ||
| 133 | .ulcon = ULCON, | ||
| 134 | .ufcon = UFCON, | ||
| 135 | }, | ||
| 136 | [1] = { | ||
| 137 | .hwport = 1, | ||
| 138 | .flags = 0, | ||
| 139 | .ucon = UCON, | ||
| 140 | .ulcon = ULCON, | ||
| 141 | .ufcon = UFCON, | ||
| 142 | }, | ||
| 143 | [2] = { | ||
| 144 | .hwport = 2, | ||
| 145 | .flags = 0, | ||
| 146 | .ucon = UCON, | ||
| 147 | .ulcon = ULCON, | ||
| 148 | .ufcon = UFCON, | ||
| 149 | }, | ||
| 150 | }; | ||
| 151 | |||
| 152 | #ifdef CONFIG_CHARGER_PCF50633 | ||
| 153 | /* | ||
| 154 | * On GTA02 the 1A charger features a 48K resistor to 0V on the ID pin. | ||
| 155 | * We use this to recognize that we can pull 1A from the USB socket. | ||
| 156 | * | ||
| 157 | * These constants are the measured pcf50633 ADC levels with the 1A | ||
| 158 | * charger / 48K resistor, and with no pulldown resistor. | ||
| 159 | */ | ||
| 160 | |||
| 161 | #define ADC_NOM_CHG_DETECT_1A 6 | ||
| 162 | #define ADC_NOM_CHG_DETECT_USB 43 | ||
| 163 | |||
| 164 | static void | ||
| 165 | gta02_configure_pmu_for_charger(struct pcf50633 *pcf, void *unused, int res) | ||
| 166 | { | ||
| 167 | int ma; | ||
| 168 | |||
| 169 | /* Interpret charger type */ | ||
| 170 | if (res < ((ADC_NOM_CHG_DETECT_USB + ADC_NOM_CHG_DETECT_1A) / 2)) { | ||
| 171 | |||
| 172 | /* | ||
| 173 | * Sanity - stop GPO driving out now that we have a 1A charger | ||
| 174 | * GPO controls USB Host power generation on GTA02 | ||
| 175 | */ | ||
| 176 | pcf50633_gpio_set(pcf, PCF50633_GPO, 0); | ||
| 177 | |||
| 178 | ma = 1000; | ||
| 179 | } else | ||
| 180 | ma = 100; | ||
| 181 | |||
| 182 | pcf50633_mbc_usb_curlim_set(pcf, ma); | ||
| 183 | } | ||
| 184 | |||
| 185 | static struct delayed_work gta02_charger_work; | ||
| 186 | static int gta02_usb_vbus_draw; | ||
| 187 | |||
| 188 | static void gta02_charger_worker(struct work_struct *work) | ||
| 189 | { | ||
| 190 | if (gta02_usb_vbus_draw) { | ||
| 191 | pcf50633_mbc_usb_curlim_set(gta02_pcf, gta02_usb_vbus_draw); | ||
| 192 | return; | ||
| 193 | } | ||
| 194 | |||
| 195 | #ifdef CONFIG_PCF50633_ADC | ||
| 196 | pcf50633_adc_async_read(gta02_pcf, | ||
| 197 | PCF50633_ADCC1_MUX_ADCIN1, | ||
| 198 | PCF50633_ADCC1_AVERAGE_16, | ||
| 199 | gta02_configure_pmu_for_charger, | ||
| 200 | NULL); | ||
| 201 | #else | ||
| 202 | /* | ||
| 203 | * If the PCF50633 ADC is disabled we fallback to a | ||
| 204 | * 100mA limit for safety. | ||
| 205 | */ | ||
| 206 | pcf50633_mbc_usb_curlim_set(pcf, 100); | ||
| 207 | #endif | ||
| 208 | } | ||
| 209 | |||
| 210 | #define GTA02_CHARGER_CONFIGURE_TIMEOUT ((3000 * HZ) / 1000) | ||
| 211 | |||
| 212 | static void gta02_pmu_event_callback(struct pcf50633 *pcf, int irq) | ||
| 213 | { | ||
| 214 | if (irq == PCF50633_IRQ_USBINS) { | ||
| 215 | schedule_delayed_work(>a02_charger_work, | ||
| 216 | GTA02_CHARGER_CONFIGURE_TIMEOUT); | ||
| 217 | |||
| 218 | return; | ||
| 219 | } | ||
| 220 | |||
| 221 | if (irq == PCF50633_IRQ_USBREM) { | ||
| 222 | cancel_delayed_work_sync(>a02_charger_work); | ||
| 223 | gta02_usb_vbus_draw = 0; | ||
| 224 | } | ||
| 225 | } | ||
| 226 | |||
| 227 | static void gta02_udc_vbus_draw(unsigned int ma) | ||
| 228 | { | ||
| 229 | if (!gta02_pcf) | ||
| 230 | return; | ||
| 231 | |||
| 232 | gta02_usb_vbus_draw = ma; | ||
| 233 | |||
| 234 | schedule_delayed_work(>a02_charger_work, | ||
| 235 | GTA02_CHARGER_CONFIGURE_TIMEOUT); | ||
| 236 | } | ||
| 237 | #else /* !CONFIG_CHARGER_PCF50633 */ | ||
| 238 | #define gta02_pmu_event_callback NULL | ||
| 239 | #define gta02_udc_vbus_draw NULL | ||
| 240 | #endif | ||
| 241 | |||
| 242 | /* | ||
| 243 | * This is called when pc50633 is probed, unfortunately quite late in the | ||
| 244 | * day since it is an I2C bus device. Here we can belatedly define some | ||
| 245 | * platform devices with the advantage that we can mark the pcf50633 as the | ||
| 246 | * parent. This makes them get suspended and resumed with their parent | ||
| 247 | * the pcf50633 still around. | ||
| 248 | */ | ||
| 249 | |||
| 250 | static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf); | ||
| 251 | |||
| 252 | |||
| 253 | static char *gta02_batteries[] = { | ||
| 254 | "battery", | ||
| 255 | }; | ||
| 256 | |||
| 257 | struct pcf50633_platform_data gta02_pcf_pdata = { | ||
| 258 | .resumers = { | ||
| 259 | [0] = PCF50633_INT1_USBINS | | ||
| 260 | PCF50633_INT1_USBREM | | ||
| 261 | PCF50633_INT1_ALARM, | ||
| 262 | [1] = PCF50633_INT2_ONKEYF, | ||
| 263 | [2] = PCF50633_INT3_ONKEY1S, | ||
| 264 | [3] = PCF50633_INT4_LOWSYS | | ||
| 265 | PCF50633_INT4_LOWBAT | | ||
| 266 | PCF50633_INT4_HIGHTMP, | ||
| 267 | }, | ||
| 268 | |||
| 269 | .batteries = gta02_batteries, | ||
| 270 | .num_batteries = ARRAY_SIZE(gta02_batteries), | ||
| 271 | .reg_init_data = { | ||
| 272 | [PCF50633_REGULATOR_AUTO] = { | ||
| 273 | .constraints = { | ||
| 274 | .min_uV = 3300000, | ||
| 275 | .max_uV = 3300000, | ||
| 276 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 277 | .always_on = 1, | ||
| 278 | .apply_uV = 1, | ||
| 279 | .state_mem = { | ||
| 280 | .enabled = 1, | ||
| 281 | }, | ||
| 282 | }, | ||
| 283 | }, | ||
| 284 | [PCF50633_REGULATOR_DOWN1] = { | ||
| 285 | .constraints = { | ||
| 286 | .min_uV = 1300000, | ||
| 287 | .max_uV = 1600000, | ||
| 288 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 289 | .always_on = 1, | ||
| 290 | .apply_uV = 1, | ||
| 291 | }, | ||
| 292 | }, | ||
| 293 | [PCF50633_REGULATOR_DOWN2] = { | ||
| 294 | .constraints = { | ||
| 295 | .min_uV = 1800000, | ||
| 296 | .max_uV = 1800000, | ||
| 297 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 298 | .apply_uV = 1, | ||
| 299 | .always_on = 1, | ||
| 300 | .state_mem = { | ||
| 301 | .enabled = 1, | ||
| 302 | }, | ||
| 303 | }, | ||
| 304 | }, | ||
| 305 | [PCF50633_REGULATOR_HCLDO] = { | ||
| 306 | .constraints = { | ||
| 307 | .min_uV = 2000000, | ||
| 308 | .max_uV = 3300000, | ||
| 309 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 310 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 311 | .always_on = 1, | ||
| 312 | }, | ||
| 313 | }, | ||
| 314 | [PCF50633_REGULATOR_LDO1] = { | ||
| 315 | .constraints = { | ||
| 316 | .min_uV = 3300000, | ||
| 317 | .max_uV = 3300000, | ||
| 318 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 319 | .apply_uV = 1, | ||
| 320 | .state_mem = { | ||
| 321 | .enabled = 0, | ||
| 322 | }, | ||
| 323 | }, | ||
| 324 | }, | ||
| 325 | [PCF50633_REGULATOR_LDO2] = { | ||
| 326 | .constraints = { | ||
| 327 | .min_uV = 3300000, | ||
| 328 | .max_uV = 3300000, | ||
| 329 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 330 | .apply_uV = 1, | ||
| 331 | }, | ||
| 332 | }, | ||
| 333 | [PCF50633_REGULATOR_LDO3] = { | ||
| 334 | .constraints = { | ||
| 335 | .min_uV = 3000000, | ||
| 336 | .max_uV = 3000000, | ||
| 337 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 338 | .apply_uV = 1, | ||
| 339 | }, | ||
| 340 | }, | ||
| 341 | [PCF50633_REGULATOR_LDO4] = { | ||
| 342 | .constraints = { | ||
| 343 | .min_uV = 3200000, | ||
| 344 | .max_uV = 3200000, | ||
| 345 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 346 | .apply_uV = 1, | ||
| 347 | }, | ||
| 348 | }, | ||
| 349 | [PCF50633_REGULATOR_LDO5] = { | ||
| 350 | .constraints = { | ||
| 351 | .min_uV = 3000000, | ||
| 352 | .max_uV = 3000000, | ||
| 353 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 354 | .apply_uV = 1, | ||
| 355 | .state_mem = { | ||
| 356 | .enabled = 1, | ||
| 357 | }, | ||
| 358 | }, | ||
| 359 | }, | ||
| 360 | [PCF50633_REGULATOR_LDO6] = { | ||
| 361 | .constraints = { | ||
| 362 | .min_uV = 3000000, | ||
| 363 | .max_uV = 3000000, | ||
| 364 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 365 | }, | ||
| 366 | }, | ||
| 367 | [PCF50633_REGULATOR_MEMLDO] = { | ||
| 368 | .constraints = { | ||
| 369 | .min_uV = 1800000, | ||
| 370 | .max_uV = 1800000, | ||
| 371 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 372 | .state_mem = { | ||
| 373 | .enabled = 1, | ||
| 374 | }, | ||
| 375 | }, | ||
| 376 | }, | ||
| 377 | |||
| 378 | }, | ||
| 379 | .probe_done = gta02_pmu_attach_child_devices, | ||
| 380 | .mbc_event_callback = gta02_pmu_event_callback, | ||
| 381 | }; | ||
| 382 | |||
| 383 | |||
| 384 | /* NOR Flash. */ | ||
| 385 | |||
| 386 | #define GTA02_FLASH_BASE 0x18000000 /* GCS3 */ | ||
| 387 | #define GTA02_FLASH_SIZE 0x200000 /* 2MBytes */ | ||
| 388 | |||
| 389 | static struct physmap_flash_data gta02_nor_flash_data = { | ||
| 390 | .width = 2, | ||
| 391 | }; | ||
| 392 | |||
| 393 | static struct resource gta02_nor_flash_resource = { | ||
| 394 | .start = GTA02_FLASH_BASE, | ||
| 395 | .end = GTA02_FLASH_BASE + GTA02_FLASH_SIZE - 1, | ||
| 396 | .flags = IORESOURCE_MEM, | ||
| 397 | }; | ||
| 398 | |||
| 399 | static struct platform_device gta02_nor_flash = { | ||
| 400 | .name = "physmap-flash", | ||
| 401 | .id = 0, | ||
| 402 | .dev = { | ||
| 403 | .platform_data = >a02_nor_flash_data, | ||
| 404 | }, | ||
| 405 | .resource = >a02_nor_flash_resource, | ||
| 406 | .num_resources = 1, | ||
| 407 | }; | ||
| 408 | |||
| 409 | |||
| 410 | struct platform_device s3c24xx_pwm_device = { | ||
| 411 | .name = "s3c24xx_pwm", | ||
| 412 | .num_resources = 0, | ||
| 413 | }; | ||
| 414 | |||
| 415 | static struct i2c_board_info gta02_i2c_devs[] __initdata = { | ||
| 416 | { | ||
| 417 | I2C_BOARD_INFO("pcf50633", 0x73), | ||
| 418 | .irq = GTA02_IRQ_PCF50633, | ||
| 419 | .platform_data = >a02_pcf_pdata, | ||
| 420 | }, | ||
| 421 | { | ||
| 422 | I2C_BOARD_INFO("wm8753", 0x1a), | ||
| 423 | }, | ||
| 424 | }; | ||
| 425 | |||
| 426 | static struct s3c2410_nand_set gta02_nand_sets[] = { | ||
| 427 | [0] = { | ||
| 428 | /* | ||
| 429 | * This name is also hard-coded in the boot loaders, so | ||
| 430 | * changing it would would require all users to upgrade | ||
| 431 | * their boot loaders, some of which are stored in a NOR | ||
| 432 | * that is considered to be immutable. | ||
| 433 | */ | ||
| 434 | .name = "neo1973-nand", | ||
| 435 | .nr_chips = 1, | ||
| 436 | .flash_bbt = 1, | ||
| 437 | }, | ||
| 438 | }; | ||
| 439 | |||
| 440 | /* | ||
| 441 | * Choose a set of timings derived from S3C@2442B MCP54 | ||
| 442 | * data sheet (K5D2G13ACM-D075 MCP Memory). | ||
| 443 | */ | ||
| 444 | |||
| 445 | static struct s3c2410_platform_nand gta02_nand_info = { | ||
| 446 | .tacls = 0, | ||
| 447 | .twrph0 = 25, | ||
| 448 | .twrph1 = 15, | ||
| 449 | .nr_sets = ARRAY_SIZE(gta02_nand_sets), | ||
| 450 | .sets = gta02_nand_sets, | ||
| 451 | }; | ||
| 452 | |||
| 453 | |||
| 454 | static void gta02_udc_command(enum s3c2410_udc_cmd_e cmd) | ||
| 455 | { | ||
| 456 | switch (cmd) { | ||
| 457 | case S3C2410_UDC_P_ENABLE: | ||
| 458 | pr_debug("%s S3C2410_UDC_P_ENABLE\n", __func__); | ||
| 459 | gpio_direction_output(GTA02_GPIO_USB_PULLUP, 1); | ||
| 460 | break; | ||
| 461 | case S3C2410_UDC_P_DISABLE: | ||
| 462 | pr_debug("%s S3C2410_UDC_P_DISABLE\n", __func__); | ||
| 463 | gpio_direction_output(GTA02_GPIO_USB_PULLUP, 0); | ||
| 464 | break; | ||
| 465 | case S3C2410_UDC_P_RESET: | ||
| 466 | pr_debug("%s S3C2410_UDC_P_RESET\n", __func__); | ||
| 467 | /* FIXME: Do something here. */ | ||
| 468 | } | ||
| 469 | } | ||
| 470 | |||
| 471 | /* Get PMU to set USB current limit accordingly. */ | ||
| 472 | static struct s3c2410_udc_mach_info gta02_udc_cfg = { | ||
| 473 | .vbus_draw = gta02_udc_vbus_draw, | ||
| 474 | .udc_command = gta02_udc_command, | ||
| 475 | |||
| 476 | }; | ||
| 477 | |||
| 478 | |||
| 479 | |||
| 480 | static void gta02_bl_set_intensity(int intensity) | ||
| 481 | { | ||
| 482 | struct pcf50633 *pcf = gta02_pcf; | ||
| 483 | int old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT); | ||
| 484 | |||
| 485 | /* We map 8-bit intensity to 6-bit intensity in hardware. */ | ||
| 486 | intensity >>= 2; | ||
| 487 | |||
| 488 | /* | ||
| 489 | * This can happen during, eg, print of panic on blanked console, | ||
| 490 | * but we can't service i2c without interrupts active, so abort. | ||
| 491 | */ | ||
| 492 | if (in_atomic()) { | ||
| 493 | printk(KERN_ERR "gta02_bl_set_intensity called while atomic\n"); | ||
| 494 | return; | ||
| 495 | } | ||
| 496 | |||
| 497 | old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT); | ||
| 498 | if (intensity == old_intensity) | ||
| 499 | return; | ||
| 500 | |||
| 501 | /* We can't do this anywhere else. */ | ||
| 502 | pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 5); | ||
| 503 | |||
| 504 | if (!(pcf50633_reg_read(pcf, PCF50633_REG_LEDENA) & 3)) | ||
| 505 | old_intensity = 0; | ||
| 506 | |||
| 507 | /* | ||
| 508 | * The PCF50633 cannot handle LEDOUT = 0 (datasheet p60) | ||
| 509 | * if seen, you have to re-enable the LED unit. | ||
| 510 | */ | ||
| 511 | if (!intensity || !old_intensity) | ||
| 512 | pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0); | ||
| 513 | |||
| 514 | /* Illegal to set LEDOUT to 0. */ | ||
| 515 | if (!intensity) | ||
| 516 | pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f, 2); | ||
| 517 | else | ||
| 518 | pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f, | ||
| 519 | intensity); | ||
| 520 | |||
| 521 | if (intensity) | ||
| 522 | pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 2); | ||
| 523 | |||
| 524 | } | ||
| 525 | |||
| 526 | static struct generic_bl_info gta02_bl_info = { | ||
| 527 | .name = "gta02-bl", | ||
| 528 | .max_intensity = 0xff, | ||
| 529 | .default_intensity = 0xff, | ||
| 530 | .set_bl_intensity = gta02_bl_set_intensity, | ||
| 531 | }; | ||
| 532 | |||
| 533 | static struct platform_device gta02_bl_dev = { | ||
| 534 | .name = "generic-bl", | ||
| 535 | .id = 1, | ||
| 536 | .dev = { | ||
| 537 | .platform_data = >a02_bl_info, | ||
| 538 | }, | ||
| 539 | }; | ||
| 540 | |||
| 541 | |||
| 542 | |||
| 543 | /* USB */ | ||
| 544 | static struct s3c2410_hcd_info gta02_usb_info = { | ||
| 545 | .port[0] = { | ||
| 546 | .flags = S3C_HCDFLG_USED, | ||
| 547 | }, | ||
| 548 | .port[1] = { | ||
| 549 | .flags = 0, | ||
| 550 | }, | ||
| 551 | }; | ||
| 552 | |||
| 553 | |||
| 554 | static void __init gta02_map_io(void) | ||
| 555 | { | ||
| 556 | s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc)); | ||
| 557 | s3c24xx_init_clocks(12000000); | ||
| 558 | s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs)); | ||
| 559 | } | ||
| 560 | |||
| 561 | |||
| 562 | /* These are the guys that don't need to be children of PMU. */ | ||
| 563 | |||
| 564 | static struct platform_device *gta02_devices[] __initdata = { | ||
| 565 | &s3c_device_usb, | ||
| 566 | &s3c_device_wdt, | ||
| 567 | &s3c_device_sdi, | ||
| 568 | &s3c_device_usbgadget, | ||
| 569 | &s3c_device_nand, | ||
| 570 | >a02_nor_flash, | ||
| 571 | &s3c24xx_pwm_device, | ||
| 572 | &s3c_device_iis, | ||
| 573 | &s3c_device_i2c0, | ||
| 574 | }; | ||
| 575 | |||
| 576 | /* These guys DO need to be children of PMU. */ | ||
| 577 | |||
| 578 | static struct platform_device *gta02_devices_pmu_children[] = { | ||
| 579 | >a02_bl_dev, | ||
| 580 | }; | ||
| 581 | |||
| 582 | |||
| 583 | /* | ||
| 584 | * This is called when pc50633 is probed, quite late in the day since it is an | ||
| 585 | * I2C bus device. Here we can define platform devices with the advantage that | ||
| 586 | * we can mark the pcf50633 as the parent. This makes them get suspended and | ||
| 587 | * resumed with their parent the pcf50633 still around. All devices whose | ||
| 588 | * operation depends on something from pcf50633 must have this relationship | ||
| 589 | * made explicit like this, or suspend and resume will become an unreliable | ||
| 590 | * hellworld. | ||
| 591 | */ | ||
| 592 | |||
| 593 | static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf) | ||
| 594 | { | ||
| 595 | int n; | ||
| 596 | |||
| 597 | /* Grab a copy of the now probed PMU pointer. */ | ||
| 598 | gta02_pcf = pcf; | ||
| 599 | |||
| 600 | for (n = 0; n < ARRAY_SIZE(gta02_devices_pmu_children); n++) | ||
| 601 | gta02_devices_pmu_children[n]->dev.parent = pcf->dev; | ||
| 602 | |||
| 603 | platform_add_devices(gta02_devices_pmu_children, | ||
| 604 | ARRAY_SIZE(gta02_devices_pmu_children)); | ||
| 605 | } | ||
| 606 | |||
| 607 | static void gta02_poweroff(void) | ||
| 608 | { | ||
| 609 | pcf50633_reg_set_bit_mask(gta02_pcf, PCF50633_REG_OOCSHDWN, 1, 1); | ||
| 610 | } | ||
| 611 | |||
| 612 | static void __init gta02_machine_init(void) | ||
| 613 | { | ||
| 614 | /* Set the panic callback to make AUX LED blink at ~5Hz. */ | ||
| 615 | panic_blink = gta02_panic_blink; | ||
| 616 | |||
| 617 | s3c_pm_init(); | ||
| 618 | |||
| 619 | #ifdef CONFIG_CHARGER_PCF50633 | ||
| 620 | INIT_DELAYED_WORK(>a02_charger_work, gta02_charger_worker); | ||
| 621 | #endif | ||
| 622 | |||
| 623 | s3c_device_usb.dev.platform_data = >a02_usb_info; | ||
| 624 | s3c_device_nand.dev.platform_data = >a02_nand_info; | ||
| 625 | |||
| 626 | s3c24xx_udc_set_platdata(>a02_udc_cfg); | ||
| 627 | s3c_i2c0_set_platdata(NULL); | ||
| 628 | |||
| 629 | i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs)); | ||
| 630 | |||
| 631 | platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices)); | ||
| 632 | pm_power_off = gta02_poweroff; | ||
| 633 | } | ||
| 634 | |||
| 635 | |||
| 636 | MACHINE_START(NEO1973_GTA02, "GTA02") | ||
| 637 | /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */ | ||
| 638 | .phys_io = S3C2410_PA_UART, | ||
| 639 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | ||
| 640 | .boot_params = S3C2410_SDRAM_PA + 0x100, | ||
| 641 | .map_io = gta02_map_io, | ||
| 642 | .init_irq = s3c24xx_init_irq, | ||
| 643 | .init_machine = gta02_machine_init, | ||
| 644 | .timer = &s3c24xx_timer, | ||
| 645 | MACHINE_END | ||
| @@ -62,6 +62,12 @@ · 61 unmodified lines | |||
| 62 | #define SHIFT_ASR 0x40 | 62 | #define SHIFT_ASR 0x40 |
| 63 | #define SHIFT_RORRRX 0x60 | 63 | #define SHIFT_RORRRX 0x60 |
| 64 | 64 | ||
| 65 | #define BAD_INSTR 0xdeadc0de | ||
| 66 | |||
| 67 | /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */ | ||
| 68 | #define IS_T32(hi16) \ | ||
| 69 | (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800)) | ||
| 70 | |||
| 65 | static unsigned long ai_user; | 71 | static unsigned long ai_user; |
| 66 | static unsigned long ai_sys; | 72 | static unsigned long ai_sys; |
| 67 | static unsigned long ai_skipped; | 73 | static unsigned long ai_skipped; |
| @@ -332,38 +338,48 @@ do_alignment_ldrdstrd(unsigned long addr, unsigned long instr, · 264 unmodified lines | |||
| 332 | struct pt_regs *regs) | 338 | struct pt_regs *regs) |
| 333 | { | 339 | { |
| 334 | unsigned int rd = RD_BITS(instr); | 340 | unsigned int rd = RD_BITS(instr); |
| 335 | 341 | unsigned int rd2; | |
| 336 | if (((rd & 1) == 1) || (rd == 14)) | 342 | int load; |
| 343 | |||
| 344 | if ((instr & 0xfe000000) == 0xe8000000) { | ||
| 345 | /* ARMv7 Thumb-2 32-bit LDRD/STRD */ | ||
| 346 | rd2 = (instr >> 8) & 0xf; | ||
| 347 | load = !!(LDST_L_BIT(instr)); | ||
| 348 | } else if (((rd & 1) == 1) || (rd == 14)) | ||
| 337 | goto bad; | 349 | goto bad; |
| 350 | else { | ||
| 351 | load = ((instr & 0xf0) == 0xd0); | ||
| 352 | rd2 = rd + 1; | ||
| 353 | } | ||
| 338 | 354 | ||
| 339 | ai_dword += 1; | 355 | ai_dword += 1; |
| 340 | 356 | ||
| 341 | if (user_mode(regs)) | 357 | if (user_mode(regs)) |
| 342 | goto user; | 358 | goto user; |
| 343 | 359 | ||
| 344 | if ((instr & 0xf0) == 0xd0) { | 360 | if (load) { |
| 345 | unsigned long val; | 361 | unsigned long val; |
| 346 | get32_unaligned_check(val, addr); | 362 | get32_unaligned_check(val, addr); |
| 347 | regs->uregs[rd] = val; | 363 | regs->uregs[rd] = val; |
| 348 | get32_unaligned_check(val, addr + 4); | 364 | get32_unaligned_check(val, addr + 4); |
| 349 | regs->uregs[rd + 1] = val; | 365 | regs->uregs[rd2] = val; |
| 350 | } else { | 366 | } else { |
| 351 | put32_unaligned_check(regs->uregs[rd], addr); | 367 | put32_unaligned_check(regs->uregs[rd], addr); |
| 352 | put32_unaligned_check(regs->uregs[rd + 1], addr + 4); | 368 | put32_unaligned_check(regs->uregs[rd2], addr + 4); |
| 353 | } | 369 | } |
| 354 | 370 | ||
| 355 | return TYPE_LDST; | 371 | return TYPE_LDST; |
| 356 | 372 | ||
| 357 | user: | 373 | user: |
| 358 | if ((instr & 0xf0) == 0xd0) { | 374 | if (load) { |
| 359 | unsigned long val; | 375 | unsigned long val; |
| 360 | get32t_unaligned_check(val, addr); | 376 | get32t_unaligned_check(val, addr); |
| 361 | regs->uregs[rd] = val; | 377 | regs->uregs[rd] = val; |
| 362 | get32t_unaligned_check(val, addr + 4); | 378 | get32t_unaligned_check(val, addr + 4); |
| 363 | regs->uregs[rd + 1] = val; | 379 | regs->uregs[rd2] = val; |
| 364 | } else { | 380 | } else { |
| 365 | put32t_unaligned_check(regs->uregs[rd], addr); | 381 | put32t_unaligned_check(regs->uregs[rd], addr); |
| 366 | put32t_unaligned_check(regs->uregs[rd + 1], addr + 4); | 382 | put32t_unaligned_check(regs->uregs[rd2], addr + 4); |
| 367 | } | 383 | } |
| 368 | 384 | ||
| 369 | return TYPE_LDST; | 385 | return TYPE_LDST; |
| @@ -616,8 +632,72 @@ thumb2arm(u16 tinstr) · 246 unmodified lines | |||
| 616 | /* Else fall through for illegal instruction case */ | 632 | /* Else fall through for illegal instruction case */ |
| 617 | 633 | ||
| 618 | default: | 634 | default: |
| 619 | return 0xdeadc0de; | 635 | return BAD_INSTR; |
| 636 | } | ||
| 637 | } | ||
| 638 | |||
| 639 | /* | ||
| 640 | * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction | ||
| 641 | * handlable by ARM alignment handler, also find the corresponding handler, | ||
| 642 | * so that we can reuse ARM userland alignment fault fixups for Thumb. | ||
| 643 | * | ||
| 644 | * @pinstr: original Thumb-2 instruction; returns new handlable instruction | ||
| 645 | * @regs: register context. | ||
| 646 | * @poffset: return offset from faulted addr for later writeback | ||
| 647 | * | ||
| 648 | * NOTES: | ||
| 649 | * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections. | ||
| 650 | * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt) | ||
| 651 | */ | ||
| 652 | static void * | ||
| 653 | do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs, | ||
| 654 | union offset_union *poffset) | ||
| 655 | { | ||
| 656 | unsigned long instr = *pinstr; | ||
| 657 | u16 tinst1 = (instr >> 16) & 0xffff; | ||
| 658 | u16 tinst2 = instr & 0xffff; | ||
| 659 | poffset->un = 0; | ||
| 660 | |||
| 661 | switch (tinst1 & 0xffe0) { | ||
| 662 | /* A6.3.5 Load/Store multiple */ | ||
| 663 | case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */ | ||
| 664 | case 0xe8a0: /* ...above writeback version */ | ||
| 665 | case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */ | ||
| 666 | case 0xe920: /* ...above writeback version */ | ||
| 667 | /* no need offset decision since handler calculates it */ | ||
| 668 | return do_alignment_ldmstm; | ||
| 669 | |||
| 670 | case 0xf840: /* POP/PUSH T3 (single register) */ | ||
| 671 | if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) { | ||
| 672 | u32 L = !!(LDST_L_BIT(instr)); | ||
| 673 | const u32 subset[2] = { | ||
| 674 | 0xe92d0000, /* STMDB sp!,{registers} */ | ||
| 675 | 0xe8bd0000, /* LDMIA sp!,{registers} */ | ||
| 676 | }; | ||
| 677 | *pinstr = subset[L] | (1<<RD_BITS(instr)); | ||
| 678 | return do_alignment_ldmstm; | ||
| 679 | } | ||
| 680 | /* Else fall through for illegal instruction case */ | ||
| 681 | break; | ||
| 682 | |||
| 683 | /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */ | ||
| 684 | case 0xe860: | ||
| 685 | case 0xe960: | ||
| 686 | case 0xe8e0: | ||
| 687 | case 0xe9e0: | ||
| 688 | poffset->un = (tinst2 & 0xff) << 2; | ||
| 689 | case 0xe940: | ||
| 690 | case 0xe9c0: | ||
| 691 | return do_alignment_ldrdstrd; | ||
| 692 | |||
| 693 | /* | ||
| 694 | * No need to handle load/store instructions up to word size | ||
| 695 | * since ARMv6 and later CPUs can perform unaligned accesses. | ||
| 696 | */ | ||
| 697 | default: | ||
| 698 | break; | ||
| 620 | } | 699 | } |
| 700 | return NULL; | ||
| 621 | } | 701 | } |
| 622 | 702 | ||
| 623 | static int | 703 | static int |
| @@ -630,6 +710,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) · 6 unmodified lines | |||
| 630 | mm_segment_t fs; | 710 | mm_segment_t fs; |
| 631 | unsigned int fault; | 711 | unsigned int fault; |
| 632 | u16 tinstr = 0; | 712 | u16 tinstr = 0; |
| 713 | int isize = 4; | ||
| 714 | int thumb2_32b = 0; | ||
| 633 | 715 | ||
| 634 | instrptr = instruction_pointer(regs); | 716 | instrptr = instruction_pointer(regs); |
| 635 | 717 | ||
| @@ -637,8 +719,19 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) · 1 unmodified line | |||
| 637 | set_fs(KERNEL_DS); | 719 | set_fs(KERNEL_DS); |
| 638 | if (thumb_mode(regs)) { | 720 | if (thumb_mode(regs)) { |
| 639 | fault = __get_user(tinstr, (u16 *)(instrptr & ~1)); | 721 | fault = __get_user(tinstr, (u16 *)(instrptr & ~1)); |
| 640 | if (!(fault)) | 722 | if (!fault) { |
| 641 | instr = thumb2arm(tinstr); | 723 | if (cpu_architecture() >= CPU_ARCH_ARMv7 && |
| 724 | IS_T32(tinstr)) { | ||
| 725 | /* Thumb-2 32-bit */ | ||
| 726 | u16 tinst2 = 0; | ||
| 727 | fault = __get_user(tinst2, (u16 *)(instrptr+2)); | ||
| 728 | instr = (tinstr << 16) | tinst2; | ||
| 729 | thumb2_32b = 1; | ||
| 730 | } else { | ||
| 731 | isize = 2; | ||
| 732 | instr = thumb2arm(tinstr); | ||
| 733 | } | ||
| 734 | } | ||
| 642 | } else | 735 | } else |
| 643 | fault = __get_user(instr, (u32 *)instrptr); | 736 | fault = __get_user(instr, (u32 *)instrptr); |
| 644 | set_fs(fs); | 737 | set_fs(fs); |
| @@ -655,7 +748,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) · 10 unmodified lines | |||
| 655 | 748 | ||
| 656 | fixup: | 749 | fixup: |
| 657 | 750 | ||
| 658 | regs->ARM_pc += thumb_mode(regs) ? 2 : 4; | 751 | regs->ARM_pc += isize; |
| 659 | 752 | ||
| 660 | switch (CODING_BITS(instr)) { | 753 | switch (CODING_BITS(instr)) { |
| 661 | case 0x00000000: /* 3.13.4 load/store instruction extensions */ | 754 | case 0x00000000: /* 3.13.4 load/store instruction extensions */ |
| @@ -714,18 +807,25 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) · 52 unmodified lines | |||
| 714 | handler = do_alignment_ldrstr; | 807 | handler = do_alignment_ldrstr; |
| 715 | break; | 808 | break; |
| 716 | 809 | ||
| 717 | case 0x08000000: /* ldm or stm */ | 810 | case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */ |
| 718 | handler = do_alignment_ldmstm; | 811 | if (thumb2_32b) |
| 812 | handler = do_alignment_t32_to_handler(&instr, regs, &offset); | ||
| 813 | else | ||
| 814 | handler = do_alignment_ldmstm; | ||
| 719 | break; | 815 | break; |
| 720 | 816 | ||
| 721 | default: | 817 | default: |
| 722 | goto bad; | 818 | goto bad; |
| 723 | } | 819 | } |
| 724 | 820 | ||
| 821 | if (!handler) | ||
| 822 | goto bad; | ||
| 725 | type = handler(addr, instr, regs); | 823 | type = handler(addr, instr, regs); |
| 726 | 824 | ||
| 727 | if (type == TYPE_ERROR || type == TYPE_FAULT) | 825 | if (type == TYPE_ERROR || type == TYPE_FAULT) { |
| 826 | regs->ARM_pc -= isize; | ||
| 728 | goto bad_or_fault; | 827 | goto bad_or_fault; |
| 828 | } | ||
| 729 | 829 | ||
| 730 | if (type == TYPE_LDST) | 830 | if (type == TYPE_LDST) |
| 731 | do_alignment_finish_ldst(addr, instr, regs, offset); | 831 | do_alignment_finish_ldst(addr, instr, regs, offset); |
| @@ -735,7 +835,6 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) · 3 unmodified lines | |||
| 735 | bad_or_fault: | 835 | bad_or_fault: |
| 736 | if (type == TYPE_ERROR) | 836 | if (type == TYPE_ERROR) |
| 737 | goto bad; | 837 | goto bad; |
| 738 | regs->ARM_pc -= thumb_mode(regs) ? 2 : 4; | ||
| 739 | /* | 838 | /* |
| 740 | * We got a fault - fix it up, or die. | 839 | * We got a fault - fix it up, or die. |
| 741 | */ | 840 | */ |
| @@ -751,8 +850,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) · 9 unmodified lines | |||
| 751 | */ | 850 | */ |
| 752 | printk(KERN_ERR "Alignment trap: not handling instruction " | 851 | printk(KERN_ERR "Alignment trap: not handling instruction " |
| 753 | "%0*lx at [<%08lx>]\n", | 852 | "%0*lx at [<%08lx>]\n", |
| 754 | thumb_mode(regs) ? 4 : 8, | 853 | isize << 1, |
| 755 | thumb_mode(regs) ? tinstr : instr, instrptr); | 854 | isize == 2 ? tinstr : instr, instrptr); |
| 756 | ai_skipped += 1; | 855 | ai_skipped += 1; |
| 757 | return 1; | 856 | return 1; |
| 758 | 857 | ||
| @@ -763,8 +862,8 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) · 4 unmodified lines | |||
| 763 | printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx " | 862 | printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx " |
| 764 | "Address=0x%08lx FSR 0x%03x\n", current->comm, | 863 | "Address=0x%08lx FSR 0x%03x\n", current->comm, |
| 765 | task_pid_nr(current), instrptr, | 864 | task_pid_nr(current), instrptr, |
| 766 | thumb_mode(regs) ? 4 : 8, | 865 | isize << 1, |
| 767 | thumb_mode(regs) ? tinstr : instr, | 866 | isize == 2 ? tinstr : instr, |
| 768 | addr, fsr); | 867 | addr, fsr); |
| 769 | 868 | ||
| 770 | if (ai_usermode & UM_FIXUP) | 869 | if (ai_usermode & UM_FIXUP) |
| @@ -836,6 +836,13 @@ void __init reserve_node_zero(pg_data_t *pgdat) · 835 unmodified lines | |||
| 836 | BOOTMEM_EXCLUSIVE); | 836 | BOOTMEM_EXCLUSIVE); |
| 837 | } | 837 | } |
| 838 | 838 | ||
| 839 | if (machine_is_treo680()) { | ||
| 840 | reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, | ||
| 841 | BOOTMEM_EXCLUSIVE); | ||
| 842 | reserve_bootmem_node(pgdat, 0xa2000000, 0x1000, | ||
| 843 | BOOTMEM_EXCLUSIVE); | ||
| 844 | } | ||
| 845 | |||
| 839 | if (machine_is_palmt5()) | 846 | if (machine_is_palmt5()) |
| 840 | reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, | 847 | reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, |
| 841 | BOOTMEM_EXCLUSIVE); | 848 | BOOTMEM_EXCLUSIVE); |
| @@ -2457,6 +2457,19 @@ static int __init omap_init_dma(void) · 2456 unmodified lines | |||
| 2457 | setup_irq(irq, &omap24xx_dma_irq); | 2457 | setup_irq(irq, &omap24xx_dma_irq); |
| 2458 | } | 2458 | } |
| 2459 | 2459 | ||
| 2460 | /* Enable smartidle idlemodes and autoidle */ | ||
| 2461 | if (cpu_is_omap34xx()) { | ||
| 2462 | u32 v = dma_read(OCP_SYSCONFIG); | ||
| 2463 | v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK | | ||
| 2464 | DMA_SYSCONFIG_SIDLEMODE_MASK | | ||
| 2465 | DMA_SYSCONFIG_AUTOIDLE); | ||
| 2466 | v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | | ||
| 2467 | DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | | ||
| 2468 | DMA_SYSCONFIG_AUTOIDLE); | ||
| 2469 | dma_write(v , OCP_SYSCONFIG); | ||
| 2470 | } | ||
| 2471 | |||
| 2472 | |||
| 2460 | /* FIXME: Update LCD DMA to work on 24xx */ | 2473 | /* FIXME: Update LCD DMA to work on 24xx */ |
| 2461 | if (cpu_class_is_omap1()) { | 2474 | if (cpu_class_is_omap1()) { |
| 2462 | r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, | 2475 | r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, |
| @@ -1585,6 +1585,7 @@ static int __init _omap_gpio_init(void) · 1584 unmodified lines | |||
| 1585 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); | 1585 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); |
| 1586 | __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); | 1586 | __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); |
| 1587 | __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); | 1587 | __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); |
| 1588 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN); | ||
| 1588 | 1589 | ||
| 1589 | /* Initialize interface clock ungated, module enabled */ | 1590 | /* Initialize interface clock ungated, module enabled */ |
| 1590 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | 1591 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); |
| @@ -30,6 +30,17 @@ · 29 unmodified lines | |||
| 30 | #ifndef __ASM_ARCH_OMAP_CPU_H | 30 | #ifndef __ASM_ARCH_OMAP_CPU_H |
| 31 | #define __ASM_ARCH_OMAP_CPU_H | 31 | #define __ASM_ARCH_OMAP_CPU_H |
| 32 | 32 | ||
| 33 | /* | ||
| 34 | * Omap device type i.e. EMU/HS/TST/GP/BAD | ||
| 35 | */ | ||
| 36 | #define OMAP2_DEVICE_TYPE_TEST 0 | ||
| 37 | #define OMAP2_DEVICE_TYPE_EMU 1 | ||
| 38 | #define OMAP2_DEVICE_TYPE_SEC 2 | ||
| 39 | #define OMAP2_DEVICE_TYPE_GP 3 | ||
| 40 | #define OMAP2_DEVICE_TYPE_BAD 4 | ||
| 41 | |||
| 42 | int omap_type(void); | ||
| 43 | |||
| 33 | struct omap_chip_id { | 44 | struct omap_chip_id { |
| 34 | u8 oc; | 45 | u8 oc; |
| 35 | u8 type; | 46 | u8 type; |
| @@ -424,17 +435,6 @@ IS_OMAP_TYPE(3430, 0x3430) · 388 unmodified lines | |||
| 424 | 435 | ||
| 425 | 436 | ||
| 426 | int omap_chip_is(struct omap_chip_id oci); | 437 | int omap_chip_is(struct omap_chip_id oci); |
| 427 | int omap_type(void); | ||
| 428 | |||
| 429 | /* | ||
| 430 | * Macro to detect device type i.e. EMU/HS/TST/GP/BAD | ||
| 431 | */ | ||
| 432 | #define OMAP2_DEVICE_TYPE_TEST 0 | ||
| 433 | #define OMAP2_DEVICE_TYPE_EMU 1 | ||
| 434 | #define OMAP2_DEVICE_TYPE_SEC 2 | ||
| 435 | #define OMAP2_DEVICE_TYPE_GP 3 | ||
| 436 | #define OMAP2_DEVICE_TYPE_BAD 4 | ||
| 437 | |||
| 438 | void omap2_check_revision(void); | 438 | void omap2_check_revision(void); |
| 439 | 439 | ||
| 440 | #endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */ | 440 | #endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */ |
| @@ -389,6 +389,21 @@ · 388 unmodified lines | |||
| 389 | #define DMA_THREAD_FIFO_25 (0x02 << 14) | 389 | #define DMA_THREAD_FIFO_25 (0x02 << 14) |
| 390 | #define DMA_THREAD_FIFO_50 (0x03 << 14) | 390 | #define DMA_THREAD_FIFO_50 (0x03 << 14) |
| 391 | 391 | ||
| 392 | /* DMA4_OCP_SYSCONFIG bits */ | ||
| 393 | #define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12) | ||
| 394 | #define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8) | ||
| 395 | #define DMA_SYSCONFIG_EMUFREE (1 << 5) | ||
| 396 | #define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3) | ||
| 397 | #define DMA_SYSCONFIG_SOFTRESET (1 << 2) | ||
| 398 | #define DMA_SYSCONFIG_AUTOIDLE (1 << 0) | ||
| 399 | |||
| 400 | #define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12) | ||
| 401 | #define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3) | ||
| 402 | |||
| 403 | #define DMA_IDLEMODE_SMARTIDLE 0x2 | ||
| 404 | #define DMA_IDLEMODE_NO_IDLE 0x1 | ||
| 405 | #define DMA_IDLEMODE_FORCE_IDLE 0x0 | ||
| 406 | |||
| 392 | /* Chaining modes*/ | 407 | /* Chaining modes*/ |
| 393 | #ifndef CONFIG_ARCH_OMAP1 | 408 | #ifndef CONFIG_ARCH_OMAP1 |
| 394 | #define OMAP_DMA_STATIC_CHAIN 0x1 | 409 | #define OMAP_DMA_STATIC_CHAIN 0x1 |
| @@ -201,7 +201,7 @@ · 200 unmodified lines | |||
| 201 | #define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa)) | 201 | #define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa)) |
| 202 | 202 | ||
| 203 | #ifdef __ASSEMBLER__ | 203 | #ifdef __ASSEMBLER__ |
| 204 | #define IOMEM(x) x | 204 | #define IOMEM(x) (x) |
| 205 | #else | 205 | #else |
| 206 | #define IOMEM(x) ((void __force __iomem *)(x)) | 206 | #define IOMEM(x) ((void __force __iomem *)(x)) |
| 207 | 207 | ||
| @@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); · 23 unmodified lines | |||
| 24 | extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, | 24 | extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, |
| 25 | u32 sdrc_actim_ctrla, | 25 | u32 sdrc_actim_ctrla, |
| 26 | u32 sdrc_actim_ctrlb, u32 m2, | 26 | u32 sdrc_actim_ctrlb, u32 m2, |
| 27 | u32 unlock_dll); | 27 | u32 unlock_dll, u32 f, u32 sdrc_mr, |
| 28 | u32 inc); | ||
| 28 | 29 | ||
| 29 | /* Do not use these */ | 30 | /* Do not use these */ |
| 30 | extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); | 31 | extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); |
| @@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; · 31 unmodified lines | |||
| 62 | extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, | 63 | extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, |
| 63 | u32 sdrc_actim_ctrla, | 64 | u32 sdrc_actim_ctrla, |
| 64 | u32 sdrc_actim_ctrlb, u32 m2, | 65 | u32 sdrc_actim_ctrlb, u32 m2, |
| 65 | u32 unlock_dll); | 66 | u32 unlock_dll, u32 f, u32 sdrc_mr, |
| 67 | u32 inc); | ||
| 66 | extern unsigned long omap3_sram_configure_core_dpll_sz; | 68 | extern unsigned long omap3_sram_configure_core_dpll_sz; |
| 67 | 69 | ||
| 68 | #endif | 70 | #endif |
| @@ -298,7 +298,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da) · 297 unmodified lines | |||
| 298 | if ((start <= da) && (da < start + bytes)) { | 298 | if ((start <= da) && (da < start + bytes)) { |
| 299 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | 299 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", |
| 300 | __func__, start, da, bytes); | 300 | __func__, start, da, bytes); |
| 301 | 301 | iotlb_load_cr(obj, &cr); | |
| 302 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | 302 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
| 303 | } | 303 | } |
| 304 | } | 304 | } |
| @@ -133,7 +133,12 @@ void __init omap_detect_sram(void) · 132 unmodified lines | |||
| 133 | if (cpu_is_omap34xx()) { | 133 | if (cpu_is_omap34xx()) { |
| 134 | omap_sram_base = OMAP3_SRAM_PUB_VA; | 134 | omap_sram_base = OMAP3_SRAM_PUB_VA; |
| 135 | omap_sram_start = OMAP3_SRAM_PUB_PA; | 135 | omap_sram_start = OMAP3_SRAM_PUB_PA; |
| 136 | omap_sram_size = 0x8000; /* 32K */ | 136 | if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || |
| 137 | (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { | ||
| 138 | omap_sram_size = 0x7000; /* 28K */ | ||
| 139 | } else { | ||
| 140 | omap_sram_size = 0x8000; /* 32K */ | ||
| 141 | } | ||
| 137 | } else { | 142 | } else { |
| 138 | omap_sram_base = OMAP2_SRAM_PUB_VA; | 143 | omap_sram_base = OMAP2_SRAM_PUB_VA; |
| 139 | omap_sram_start = OMAP2_SRAM_PUB_PA; | 144 | omap_sram_start = OMAP2_SRAM_PUB_PA; |
| @@ -371,15 +376,17 @@ static inline int omap243x_sram_init(void) · 231 unmodified lines | |||
| 371 | static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, | 376 | static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, |
| 372 | u32 sdrc_actim_ctrla, | 377 | u32 sdrc_actim_ctrla, |
| 373 | u32 sdrc_actim_ctrlb, | 378 | u32 sdrc_actim_ctrlb, |
| 374 | u32 m2, u32 unlock_dll); | 379 | u32 m2, u32 unlock_dll, |
| 380 | u32 f, u32 sdrc_mr, u32 inc); | ||
| 375 | u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, | 381 | u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, |
| 376 | u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll) | 382 | u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, |
| 383 | u32 f, u32 sdrc_mr, u32 inc) | ||
| 377 | { | 384 | { |
| 378 | BUG_ON(!_omap3_sram_configure_core_dpll); | 385 | BUG_ON(!_omap3_sram_configure_core_dpll); |
| 379 | return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, | 386 | return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, |
| 380 | sdrc_actim_ctrla, | 387 | sdrc_actim_ctrla, |
| 381 | sdrc_actim_ctrlb, m2, | 388 | sdrc_actim_ctrlb, m2, |
| 382 | unlock_dll); | 389 | unlock_dll, f, sdrc_mr, inc); |
| 383 | } | 390 | } |
| 384 | 391 | ||
| 385 | /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ | 392 | /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ |
| @@ -34,6 +34,7 @@ obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o · 33 unmodified lines | |||
| 34 | obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o | 34 | obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o |
| 35 | obj-y += dev-i2c0.o | 35 | obj-y += dev-i2c0.o |
| 36 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o | 36 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o |
| 37 | obj-$(CONFIG_SND_S3C64XX_SOC_I2S) += dev-audio.o | ||
| 37 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o | 38 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o |
| 38 | obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o | 39 | obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o |
| 39 | obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o | 40 | obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o |
| @@ -0,0 +1,68 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/dev-audio.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Wolfson Microelectronics | ||
| 4 | * Mark Brown <broonie@opensource.wolfsonmicro.com> | ||
| 5 | * | ||
| 6 | |||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/string.h> | ||
| 14 | #include <linux/platform_device.h> | ||
| 15 | |||
| 16 | #include <mach/irqs.h> | ||
| 17 | #include <mach/map.h> | ||
| 18 | |||
| 19 | #include <plat/devs.h> | ||
| 20 | |||
| 21 | |||
| 22 | static struct resource s3c64xx_iis0_resource[] = { | ||
| 23 | [0] = { | ||
| 24 | .start = S3C64XX_PA_IIS0, | ||
| 25 | .end = S3C64XX_PA_IIS0 + 0x100 - 1, | ||
| 26 | .flags = IORESOURCE_MEM, | ||
| 27 | }, | ||
| 28 | }; | ||
| 29 | |||
| 30 | struct platform_device s3c64xx_device_iis0 = { | ||
| 31 | .name = "s3c64xx-iis", | ||
| 32 | .id = 0, | ||
| 33 | .num_resources = ARRAY_SIZE(s3c64xx_iis0_resource), | ||
| 34 | .resource = s3c64xx_iis0_resource, | ||
| 35 | }; | ||
| 36 | EXPORT_SYMBOL(s3c64xx_device_iis0); | ||
| 37 | |||
| 38 | static struct resource s3c64xx_iis1_resource[] = { | ||
| 39 | [0] = { | ||
| 40 | .start = S3C64XX_PA_IIS1, | ||
| 41 | .end = S3C64XX_PA_IIS1 + 0x100 - 1, | ||
| 42 | .flags = IORESOURCE_MEM, | ||
| 43 | }, | ||
| 44 | }; | ||
| 45 | |||
| 46 | struct platform_device s3c64xx_device_iis1 = { | ||
| 47 | .name = "s3c64xx-iis", | ||
| 48 | .id = 1, | ||
| 49 | .num_resources = ARRAY_SIZE(s3c64xx_iis1_resource), | ||
| 50 | .resource = s3c64xx_iis1_resource, | ||
| 51 | }; | ||
| 52 | EXPORT_SYMBOL(s3c64xx_device_iis1); | ||
| 53 | |||
| 54 | static struct resource s3c64xx_iisv4_resource[] = { | ||
| 55 | [0] = { | ||
| 56 | .start = S3C64XX_PA_IISV4, | ||
| 57 | .end = S3C64XX_PA_IISV4 + 0x100 - 1, | ||
| 58 | .flags = IORESOURCE_MEM, | ||
| 59 | }, | ||
| 60 | }; | ||
| 61 | |||
| 62 | struct platform_device s3c64xx_device_iisv4 = { | ||
| 63 | .name = "s3c64xx-iis-v4", | ||
| 64 | .id = -1, | ||
| 65 | .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource), | ||
| 66 | .resource = s3c64xx_iisv4_resource, | ||
| 67 | }; | ||
| 68 | EXPORT_SYMBOL(s3c64xx_device_iisv4); | ||
| @@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, · 118 unmodified lines | |||
| 119 | unsigned int shift = (off & 7) * 4; | 119 | unsigned int shift = (off & 7) * 4; |
| 120 | u32 con; | 120 | u32 con; |
| 121 | 121 | ||
| 122 | if (off < 8 && chip->chip.ngpio >= 8) | 122 | if (off < 8 && chip->chip.ngpio > 8) |
| 123 | reg -= 4; | 123 | reg -= 4; |
| 124 | 124 | ||
| 125 | if (s3c_gpio_is_cfg_special(cfg)) { | 125 | if (s3c_gpio_is_cfg_special(cfg)) { |
| @@ -24,16 +24,20 @@ extern struct platform_device *s3c24xx_uart_src[]; · 23 unmodified lines | |||
| 24 | 24 | ||
| 25 | extern struct platform_device s3c_device_timer[]; | 25 | extern struct platform_device s3c_device_timer[]; |
| 26 | 26 | ||
| 27 | extern struct platform_device s3c64xx_device_iis0; | ||
| 28 | extern struct platform_device s3c64xx_device_iis1; | ||
| 29 | extern struct platform_device s3c64xx_device_iisv4; | ||
| 30 | |||
| 27 | extern struct platform_device s3c_device_fb; | 31 | extern struct platform_device s3c_device_fb; |
| 28 | extern struct platform_device s3c_device_usb; | 32 | extern struct platform_device s3c_device_usb; |
| 29 | extern struct platform_device s3c_device_lcd; | 33 | extern struct platform_device s3c_device_lcd; |
| 30 | extern struct platform_device s3c_device_wdt; | 34 | extern struct platform_device s3c_device_wdt; |
| 31 | extern struct platform_device s3c_device_i2c0; | 35 | extern struct platform_device s3c_device_i2c0; |
| 32 | extern struct platform_device s3c_device_i2c1; | 36 | extern struct platform_device s3c_device_i2c1; |
| 33 | extern struct platform_device s3c_device_iis; | ||
| 34 | extern struct platform_device s3c_device_rtc; | 37 | extern struct platform_device s3c_device_rtc; |
| 35 | extern struct platform_device s3c_device_adc; | 38 | extern struct platform_device s3c_device_adc; |
| 36 | extern struct platform_device s3c_device_sdi; | 39 | extern struct platform_device s3c_device_sdi; |
| 40 | extern struct platform_device s3c_device_iis; | ||
| 37 | extern struct platform_device s3c_device_hwmon; | 41 | extern struct platform_device s3c_device_hwmon; |
| 38 | extern struct platform_device s3c_device_hsmmc0; | 42 | extern struct platform_device s3c_device_hsmmc0; |
| 39 | extern struct platform_device s3c_device_hsmmc1; | 43 | extern struct platform_device s3c_device_hsmmc1; |
| @@ -10,19 +10,26 @@ · 9 unmodified lines | |||
| 10 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /* struct s3c2410_nand_set | 13 | /** |
| 14 | * struct s3c2410_nand_set - define a set of one or more nand chips | ||
| 15 | * @disable_ecc: Entirely disable ECC - Dangerous | ||
| 16 | * @flash_bbt: Openmoko u-boot can create a Bad Block Table | ||
| 17 | * Setting this flag will allow the kernel to | ||
| 18 | * look for it at boot time and also skip the NAND | ||
| 19 | * scan. | ||
| 20 | * @nr_chips: Number of chips in this set | ||
| 21 | * @nr_partitions: Number of partitions pointed to by @partitions | ||
| 22 | * @name: Name of set (optional) | ||
| 23 | * @nr_map: Map for low-layer logical to physical chip numbers (option) | ||
| 24 | * @partitions: The mtd partition list | ||
| 14 | * | 25 | * |
| 15 | * define an set of one or more nand chips registered with an unique mtd | 26 | * define a set of one or more nand chips registered with an unique mtd. Also |
| 16 | * | 27 | * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger |
| 17 | * nr_chips = number of chips in this set | 28 | * a warning at boot time. |
| 18 | * nr_partitions = number of partitions pointed to be partitoons (or zero) | 29 | */ |
| 19 | * name = name of set (optional) | ||
| 20 | * nr_map = map for low-layer logical to physical chip numbers (option) | ||
| 21 | * partitions = mtd partition list | ||
| 22 | */ | ||
| 23 | |||
| 24 | struct s3c2410_nand_set { | 30 | struct s3c2410_nand_set { |
| 25 | unsigned int disable_ecc : 1; | 31 | unsigned int disable_ecc:1; |
| 32 | unsigned int flash_bbt:1; | ||
| 26 | 33 | ||
| 27 | int nr_chips; | 34 | int nr_chips; |
| 28 | int nr_partitions; | 35 | int nr_partitions; |
| @@ -39,7 +46,7 @@ struct s3c2410_platform_nand { · 10 unmodified lines | |||
| 39 | int twrph0; /* active time for nWE/nOE */ | 46 | int twrph0; /* active time for nWE/nOE */ |
| 40 | int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ | 47 | int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ |
| 41 | 48 | ||
| 42 | unsigned int ignore_unset_ecc : 1; | 49 | unsigned int ignore_unset_ecc:1; |
| 43 | 50 | ||
| 44 | int nr_sets; | 51 | int nr_sets; |
| 45 | struct s3c2410_nand_set *sets; | 52 | struct s3c2410_nand_set *sets; |
| @@ -29,7 +29,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o · 28 unmodified lines | |||
| 29 | obj-$(CONFIG_PM) += pm.o | 29 | obj-$(CONFIG_PM) += pm.o |
| 30 | obj-$(CONFIG_PM) += irq-pm.o | 30 | obj-$(CONFIG_PM) += irq-pm.o |
| 31 | obj-$(CONFIG_PM) += sleep.o | 31 | obj-$(CONFIG_PM) += sleep.o |
| 32 | obj-$(CONFIG_HAVE_PWM) += pwm.o | 32 | obj-$(CONFIG_S3C24XX_PWM) += pwm.o |
| 33 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o | 33 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o |
| 34 | obj-$(CONFIG_S3C2410_DMA) += dma.o | 34 | obj-$(CONFIG_S3C2410_DMA) += dma.o |
| 35 | obj-$(CONFIG_S3C24XX_ADC) += adc.o | 35 | obj-$(CONFIG_S3C24XX_ADC) += adc.o |
| @@ -12,8 +12,7 @@ · 11 unmodified lines | |||
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 15 | 15 | #include <linux/gpio.h> | |
| 16 | #include <mach/hardware.h> | ||
| 17 | 16 | ||
| 18 | #include <mach/spi.h> | 17 | #include <mach/spi.h> |
| 19 | #include <mach/regs-gpio.h> | 18 | #include <mach/regs-gpio.h> |
| @@ -12,8 +12,7 @@ · 11 unmodified lines | |||
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 15 | 15 | #include <linux/gpio.h> | |
| 16 | #include <mach/hardware.h> | ||
| 17 | 16 | ||
| 18 | #include <mach/spi.h> | 17 | #include <mach/spi.h> |
| 19 | #include <mach/regs-gpio.h> | 18 | #include <mach/regs-gpio.h> |
| @@ -23,6 +23,7 @@ obj-y += gpiolib.o · 22 unmodified lines | |||
| 23 | 23 | ||
| 24 | obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o | 24 | obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o |
| 25 | obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o | 25 | obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o |
| 26 | obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o | ||
| 26 | 27 | ||
| 27 | # PM support | 28 | # PM support |
| 28 | 29 | ||
| @@ -191,7 +191,7 @@ static struct clk init_clocks[] = { · 190 unmodified lines | |||
| 191 | .id = -1, | 191 | .id = -1, |
| 192 | .parent = &clk_h, | 192 | .parent = &clk_h, |
| 193 | .enable = s3c64xx_hclk_ctrl, | 193 | .enable = s3c64xx_hclk_ctrl, |
| 194 | .ctrlbit = S3C_CLKCON_SCLK_UHOST, | 194 | .ctrlbit = S3C_CLKCON_HCLK_UHOST, |
| 195 | }, { | 195 | }, { |
| 196 | .name = "hsmmc", | 196 | .name = "hsmmc", |
| 197 | .id = 0, | 197 | .id = 0, |
| @@ -0,0 +1,262 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c64xx/cpufreq.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Wolfson Microelectronics plc | ||
| 4 | * | ||
| 5 | * S3C64xx CPUfreq Support | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/types.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/cpufreq.h> | ||
| 16 | #include <linux/clk.h> | ||
| 17 | #include <linux/err.h> | ||
| 18 | #include <linux/regulator/consumer.h> | ||
| 19 | |||
| 20 | static struct clk *armclk; | ||
| 21 | static struct regulator *vddarm; | ||
| 22 | |||
| 23 | #ifdef CONFIG_CPU_S3C6410 | ||
| 24 | struct s3c64xx_dvfs { | ||
| 25 | unsigned int vddarm_min; | ||
| 26 | unsigned int vddarm_max; | ||
| 27 | }; | ||
| 28 | |||
| 29 | static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { | ||
| 30 | [0] = { 1000000, 1000000 }, | ||
| 31 | [1] = { 1000000, 1050000 }, | ||
| 32 | [2] = { 1050000, 1100000 }, | ||
| 33 | [3] = { 1050000, 1150000 }, | ||
| 34 | [4] = { 1250000, 1350000 }, | ||
| 35 | }; | ||
| 36 | |||
| 37 | static struct cpufreq_frequency_table s3c64xx_freq_table[] = { | ||
| 38 | { 0, 66000 }, | ||
| 39 | { 0, 133000 }, | ||
| 40 | { 1, 222000 }, | ||
| 41 | { 1, 266000 }, | ||
| 42 | { 2, 333000 }, | ||
| 43 | { 2, 400000 }, | ||
| 44 | { 3, 532000 }, | ||
| 45 | { 3, 533000 }, | ||
| 46 | { 4, 667000 }, | ||
| 47 | { 0, CPUFREQ_TABLE_END }, | ||
| 48 | }; | ||
| 49 | #endif | ||
| 50 | |||
| 51 | static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy) | ||
| 52 | { | ||
| 53 | if (policy->cpu != 0) | ||
| 54 | return -EINVAL; | ||
| 55 | |||
| 56 | return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table); | ||
| 57 | } | ||
| 58 | |||
| 59 | static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu) | ||
| 60 | { | ||
| 61 | if (cpu != 0) | ||
| 62 | return 0; | ||
| 63 | |||
| 64 | return clk_get_rate(armclk) / 1000; | ||
| 65 | } | ||
| 66 | |||
| 67 | static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, | ||
| 68 | unsigned int target_freq, | ||
| 69 | unsigned int relation) | ||
| 70 | { | ||
| 71 | int ret; | ||
| 72 | unsigned int i; | ||
| 73 | struct cpufreq_freqs freqs; | ||
| 74 | struct s3c64xx_dvfs *dvfs; | ||
| 75 | |||
| 76 | ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table, | ||
| 77 | target_freq, relation, &i); | ||
| 78 | if (ret != 0) | ||
| 79 | return ret; | ||
| 80 | |||
| 81 | freqs.cpu = 0; | ||
| 82 | freqs.old = clk_get_rate(armclk) / 1000; | ||
| 83 | freqs.new = s3c64xx_freq_table[i].frequency; | ||
| 84 | freqs.flags = 0; | ||
| 85 | dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index]; | ||
| 86 | |||
| 87 | if (freqs.old == freqs.new) | ||
| 88 | return 0; | ||
| 89 | |||
| 90 | pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new); | ||
| 91 | |||
| 92 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | ||
| 93 | |||
| 94 | #ifdef CONFIG_REGULATOR | ||
| 95 | if (vddarm && freqs.new > freqs.old) { | ||
| 96 | ret = regulator_set_voltage(vddarm, | ||
| 97 | dvfs->vddarm_min, | ||
| 98 | dvfs->vddarm_max); | ||
| 99 | if (ret != 0) { | ||
| 100 | pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", | ||
| 101 | freqs.new, ret); | ||
| 102 | goto err; | ||
| 103 | } | ||
| 104 | } | ||
| 105 | #endif | ||
| 106 | |||
| 107 | ret = clk_set_rate(armclk, freqs.new * 1000); | ||
| 108 | if (ret < 0) { | ||
| 109 | pr_err("cpufreq: Failed to set rate %dkHz: %d\n", | ||
| 110 | freqs.new, ret); | ||
| 111 | goto err; | ||
| 112 | } | ||
| 113 | |||
| 114 | #ifdef CONFIG_REGULATOR | ||
| 115 | if (vddarm && freqs.new < freqs.old) { | ||
| 116 | ret = regulator_set_voltage(vddarm, | ||
| 117 | dvfs->vddarm_min, | ||
| 118 | dvfs->vddarm_max); | ||
| 119 | if (ret != 0) { | ||
| 120 | pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n", | ||
| 121 | freqs.new, ret); | ||
| 122 | goto err_clk; | ||
| 123 | } | ||
| 124 | } | ||
| 125 | #endif | ||
| 126 | |||
| 127 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | ||
| 128 | |||
| 129 | pr_debug("cpufreq: Set actual frequency %lukHz\n", | ||
| 130 | clk_get_rate(armclk) / 1000); | ||
| 131 | |||
| 132 | return 0; | ||
| 133 | |||
| 134 | err_clk: | ||
| 135 | if (clk_set_rate(armclk, freqs.old * 1000) < 0) | ||
| 136 | pr_err("Failed to restore original clock rate\n"); | ||
| 137 | err: | ||
| 138 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | ||
| 139 | |||
| 140 | return ret; | ||
| 141 | } | ||
| 142 | |||
| 143 | #ifdef CONFIG_REGULATOR | ||
| 144 | static void __init s3c64xx_cpufreq_constrain_voltages(void) | ||
| 145 | { | ||
| 146 | int count, v, i, found; | ||
| 147 | struct cpufreq_frequency_table *freq; | ||
| 148 | struct s3c64xx_dvfs *dvfs; | ||
| 149 | |||
| 150 | count = regulator_count_voltages(vddarm); | ||
| 151 | if (count < 0) { | ||
| 152 | pr_err("cpufreq: Unable to check supported voltages\n"); | ||
| 153 | return; | ||
| 154 | } | ||
| 155 | |||
| 156 | freq = s3c64xx_freq_table; | ||
| 157 | while (freq->frequency != CPUFREQ_TABLE_END) { | ||
| 158 | if (freq->frequency == CPUFREQ_ENTRY_INVALID) | ||
| 159 | continue; | ||
| 160 | |||
| 161 | dvfs = &s3c64xx_dvfs_table[freq->index]; | ||
| 162 | found = 0; | ||
| 163 | |||
| 164 | for (i = 0; i < count; i++) { | ||
| 165 | v = regulator_list_voltage(vddarm, i); | ||
| 166 | if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) | ||
| 167 | found = 1; | ||
| 168 | } | ||
| 169 | |||
| 170 | if (!found) { | ||
| 171 | pr_debug("cpufreq: %dkHz unsupported by regulator\n", | ||
| 172 | freq->frequency); | ||
| 173 | freq->frequency = CPUFREQ_ENTRY_INVALID; | ||
| 174 | } | ||
| 175 | |||
| 176 | freq++; | ||
| 177 | } | ||
| 178 | } | ||
| 179 | #endif | ||
| 180 | |||
| 181 | static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) | ||
| 182 | { | ||
| 183 | int ret; | ||
| 184 | struct cpufreq_frequency_table *freq; | ||
| 185 | |||
| 186 | if (policy->cpu != 0) | ||
| 187 | return -EINVAL; | ||
| 188 | |||
| 189 | if (s3c64xx_freq_table == NULL) { | ||
| 190 | pr_err("cpufreq: No frequency information for this CPU\n"); | ||
| 191 | return -ENODEV; | ||
| 192 | } | ||
| 193 | |||
| 194 | armclk = clk_get(NULL, "armclk"); | ||
| 195 | if (IS_ERR(armclk)) { | ||
| 196 | pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n", | ||
| 197 | PTR_ERR(armclk)); | ||
| 198 | return PTR_ERR(armclk); | ||
| 199 | } | ||
| 200 | |||
| 201 | #ifdef CONFIG_REGULATOR | ||
| 202 | vddarm = regulator_get(NULL, "vddarm"); | ||
| 203 | if (IS_ERR(vddarm)) { | ||
| 204 | ret = PTR_ERR(vddarm); | ||
| 205 | pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret); | ||
| 206 | pr_err("cpufreq: Only frequency scaling available\n"); | ||
| 207 | vddarm = NULL; | ||
| 208 | } else { | ||
| 209 | s3c64xx_cpufreq_constrain_voltages(); | ||
| 210 | } | ||
| 211 | #endif | ||
| 212 | |||
| 213 | freq = s3c64xx_freq_table; | ||
| 214 | while (freq->frequency != CPUFREQ_TABLE_END) { | ||
| 215 | unsigned long r; | ||
| 216 | |||
| 217 | /* Check for frequencies we can generate */ | ||
| 218 | r = clk_round_rate(armclk, freq->frequency * 1000); | ||
| 219 | r /= 1000; | ||
| 220 | if (r != freq->frequency) | ||
| 221 | freq->frequency = CPUFREQ_ENTRY_INVALID; | ||
| 222 | |||
| 223 | /* If we have no regulator then assume startup | ||
| 224 | * frequency is the maximum we can support. */ | ||
| 225 | if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0)) | ||
| 226 | freq->frequency = CPUFREQ_ENTRY_INVALID; | ||
| 227 | |||
| 228 | freq++; | ||
| 229 | } | ||
| 230 | |||
| 231 | policy->cur = clk_get_rate(armclk) / 1000; | ||
| 232 | |||
| 233 | /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI | ||
| 234 | * write plus clock reprogramming. */ | ||
| 235 | policy->cpuinfo.transition_latency = 2 * 1000 * 1000; | ||
| 236 | |||
| 237 | ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table); | ||
| 238 | if (ret != 0) { | ||
| 239 | pr_err("cpufreq: Failed to configure frequency table: %d\n", | ||
| 240 | ret); | ||
| 241 | regulator_put(vddarm); | ||
| 242 | clk_put(armclk); | ||
| 243 | } | ||
| 244 | |||
| 245 | return ret; | ||
| 246 | } | ||
| 247 | |||
| 248 | static struct cpufreq_driver s3c64xx_cpufreq_driver = { | ||
| 249 | .owner = THIS_MODULE, | ||
| 250 | .flags = 0, | ||
| 251 | .verify = s3c64xx_cpufreq_verify_speed, | ||
| 252 | .target = s3c64xx_cpufreq_set_target, | ||
| 253 | .get = s3c64xx_cpufreq_get_speed, | ||
| 254 | .init = s3c64xx_cpufreq_driver_init, | ||
| 255 | .name = "s3c", | ||
| 256 | }; | ||
| 257 | |||
| 258 | static int __init s3c64xx_cpufreq_init(void) | ||
| 259 | { | ||
| 260 | return cpufreq_register_driver(&s3c64xx_cpufreq_driver); | ||
| 261 | } | ||
| 262 | module_init(s3c64xx_cpufreq_init); | ||
| @@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { · 320 unmodified lines | |||
| 321 | .get_pull = s3c_gpio_getpull_updown, | 321 | .get_pull = s3c_gpio_getpull_updown, |
| 322 | }; | 322 | }; |
| 323 | 323 | ||
| 324 | int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin) | ||
| 325 | { | ||
| 326 | return IRQ_EINT(0) + pin; | ||
| 327 | } | ||
| 328 | |||
| 324 | static struct s3c_gpio_chip gpio_2bit[] = { | 329 | static struct s3c_gpio_chip gpio_2bit[] = { |
| 325 | { | 330 | { |
| 326 | .base = S3C64XX_GPF_BASE, | 331 | .base = S3C64XX_GPF_BASE, |
| @@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = { · 26 unmodified lines | |||
| 353 | .base = S3C64XX_GPN(0), | 358 | .base = S3C64XX_GPN(0), |
| 354 | .ngpio = S3C64XX_GPIO_N_NR, | 359 | .ngpio = S3C64XX_GPIO_N_NR, |
| 355 | .label = "GPN", | 360 | .label = "GPN", |
| 361 | .to_irq = s3c64xx_gpio2int_gpn, | ||
| 356 | }, | 362 | }, |
| 357 | }, { | 363 | }, { |
| 358 | .base = S3C64XX_GPO_BASE, | 364 | .base = S3C64XX_GPO_BASE, |
| @@ -88,11 +88,11 @@ · 87 unmodified lines | |||
| 88 | #define S3C6400_CLKDIV2_SPI0_SHIFT (0) | 88 | #define S3C6400_CLKDIV2_SPI0_SHIFT (0) |
| 89 | 89 | ||
| 90 | /* HCLK GATE Registers */ | 90 | /* HCLK GATE Registers */ |
| 91 | #define S3C_CLKCON_HCLK_BUS (1<<30) | 91 | #define S3C_CLKCON_HCLK_3DSE (1<<31) |
| 92 | #define S3C_CLKCON_HCLK_SECUR (1<<29) | 92 | #define S3C_CLKCON_HCLK_UHOST (1<<29) |
| 93 | #define S3C_CLKCON_HCLK_SDMA1 (1<<28) | 93 | #define S3C_CLKCON_HCLK_SECUR (1<<28) |
| 94 | #define S3C_CLKCON_HCLK_SDMA2 (1<<27) | 94 | #define S3C_CLKCON_HCLK_SDMA1 (1<<27) |
| 95 | #define S3C_CLKCON_HCLK_UHOST (1<<26) | 95 | #define S3C_CLKCON_HCLK_SDMA0 (1<<26) |
| 96 | #define S3C_CLKCON_HCLK_IROM (1<<25) | 96 | #define S3C_CLKCON_HCLK_IROM (1<<25) |
| 97 | #define S3C_CLKCON_HCLK_DDR1 (1<<24) | 97 | #define S3C_CLKCON_HCLK_DDR1 (1<<24) |
| 98 | #define S3C_CLKCON_HCLK_DDR0 (1<<23) | 98 | #define S3C_CLKCON_HCLK_DDR0 (1<<23) |
| @@ -12,7 +12,7 @@ · 11 unmodified lines | |||
| 12 | # | 12 | # |
| 13 | # http://www.arm.linux.org.uk/developer/machines/?action=new | 13 | # http://www.arm.linux.org.uk/developer/machines/?action=new |
| 14 | # | 14 | # |
| 15 | # Last update: Fri May 29 10:14:20 2009 | 15 | # Last update: Sat Jun 20 22:28:39 2009 |
| 16 | # | 16 | # |
| 17 | # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number | 17 | # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number |
| 18 | # | 18 | # |
| @@ -1455,7 +1455,7 @@ gba MACH_GBA GBA 1457 · 1436 unmodified lines | |||
| 1455 | h6044 MACH_H6044 H6044 1458 | 1455 | h6044 MACH_H6044 H6044 1458 |
| 1456 | app MACH_APP APP 1459 | 1456 | app MACH_APP APP 1459 |
| 1457 | tct_hammer MACH_TCT_HAMMER TCT_HAMMER 1460 | 1457 | tct_hammer MACH_TCT_HAMMER TCT_HAMMER 1460 |
| 1458 | herald MACH_HERMES HERMES 1461 | 1458 | herald MACH_HERALD HERALD 1461 |
| 1459 | artemis MACH_ARTEMIS ARTEMIS 1462 | 1459 | artemis MACH_ARTEMIS ARTEMIS 1462 |
| 1460 | htctitan MACH_HTCTITAN HTCTITAN 1463 | 1460 | htctitan MACH_HTCTITAN HTCTITAN 1463 |
| 1461 | qranium MACH_QRANIUM QRANIUM 1464 | 1461 | qranium MACH_QRANIUM QRANIUM 1464 |
| @@ -2245,3 +2245,38 @@ str9 MACH_STR9 STR9 2257 · 783 unmodified lines | |||
| 2245 | omap3_wl_ff MACH_OMAP3_WL_FF OMAP3_WL_FF 2258 | 2245 | omap3_wl_ff MACH_OMAP3_WL_FF OMAP3_WL_FF 2258 |
| 2246 | simcom MACH_SIMCOM SIMCOM 2259 | 2246 | simcom MACH_SIMCOM SIMCOM 2259 |
| 2247 | mcwebio MACH_MCWEBIO MCWEBIO 2260 | 2247 | mcwebio MACH_MCWEBIO MCWEBIO 2260 |
| 2248 | omap3_phrazer MACH_OMAP3_PHRAZER OMAP3_PHRAZER 2261 | ||
| 2249 | darwin MACH_DARWIN DARWIN 2262 | ||
| 2250 | oratiscomu MACH_ORATISCOMU ORATISCOMU 2263 | ||
| 2251 | rtsbc20 MACH_RTSBC20 RTSBC20 2264 | ||
| 2252 | i780 MACH_I780 I780 2265 | ||
| 2253 | gemini324 MACH_GEMINI324 GEMINI324 2266 | ||
| 2254 | oratislan MACH_ORATISLAN ORATISLAN 2267 | ||
| 2255 | oratisalog MACH_ORATISALOG ORATISALOG 2268 | ||
| 2256 | oratismadi MACH_ORATISMADI ORATISMADI 2269 | ||
| 2257 | oratisot16 MACH_ORATISOT16 ORATISOT16 2270 | ||
| 2258 | oratisdesk MACH_ORATISDESK ORATISDESK 2271 | ||
| 2259 | v2p_ca9 MACH_V2P_CA9 V2P_CA9 2272 | ||
| 2260 | sintexo MACH_SINTEXO SINTEXO 2273 | ||
| 2261 | cm3389 MACH_CM3389 CM3389 2274 | ||
| 2262 | omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275 | ||
| 2263 | sgh_i900 MACH_SGH_I900 SGH_I900 2276 | ||
| 2264 | bst100 MACH_BST100 BST100 2277 | ||
| 2265 | passion MACH_PASSION PASSION 2278 | ||
| 2266 | indesign_at91sam MACH_INDESIGN_AT91SAM INDESIGN_AT91SAM 2279 | ||
| 2267 | c4_badger MACH_C4_BADGER C4_BADGER 2280 | ||
| 2268 | c4_viper MACH_C4_VIPER C4_VIPER 2281 | ||
| 2269 | d2net MACH_D2NET D2NET 2282 | ||
| 2270 | bigdisk MACH_BIGDISK BIGDISK 2283 | ||
| 2271 | notalvision MACH_NOTALVISION NOTALVISION 2284 | ||
| 2272 | omap3_kboc MACH_OMAP3_KBOC OMAP3_KBOC 2285 | ||
| 2273 | cyclone MACH_CYCLONE CYCLONE 2286 | ||
| 2274 | ninja MACH_NINJA NINJA 2287 | ||
| 2275 | at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288 | ||
| 2276 | bcmring MACH_BCMRING BCMRING 2289 | ||
| 2277 | resol_dl2 MACH_RESOL_DL2 RESOL_DL2 2290 | ||
| 2278 | ifosw MACH_IFOSW IFOSW 2291 | ||
| 2279 | htcrhodium MACH_HTCRHODIUM HTCRHODIUM 2292 | ||
| 2280 | htctopaz MACH_HTCTOPAZ HTCTOPAZ 2293 | ||
| 2281 | matrix504 MACH_MATRIX504 MATRIX504 2294 | ||
| 2282 | mrfsa MACH_MRFSA MRFSA 2295 | ||
| @@ -274,7 +274,7 @@ config BF_REV_0_0 · 273 unmodified lines | |||
| 274 | 274 | ||
| 275 | config BF_REV_0_1 | 275 | config BF_REV_0_1 |
| 276 | bool "0.1" | 276 | bool "0.1" |
| 277 | depends on (BF52x || (BF54x && !BF54xM)) | 277 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
| 278 | 278 | ||
| 279 | config BF_REV_0_2 | 279 | config BF_REV_0_2 |
| 280 | bool "0.2" | 280 | bool "0.2" |
| @@ -358,7 +358,7 @@ config MEM_MT48LC8M32B2B5_7 · 77 unmodified lines | |||
| 358 | 358 | ||
| 359 | config MEM_MT48LC32M16A2TG_75 | 359 | config MEM_MT48LC32M16A2TG_75 |
| 360 | bool | 360 | bool |
| 361 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) | 361 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP) |
| 362 | default y | 362 | default y |
| 363 | 363 | ||
| 364 | config MEM_MT48LC32M8A2_75 | 364 | config MEM_MT48LC32M8A2_75 |
| @@ -366,6 +366,11 @@ config MEM_MT48LC32M8A2_75 · 1 unmodified line | |||
| 366 | depends on (BFIN518F_EZBRD) | 366 | depends on (BFIN518F_EZBRD) |
| 367 | default y | 367 | default y |
| 368 | 368 | ||
| 369 | config MEM_MT48H32M16LFCJ_75 | ||
| 370 | bool | ||
| 371 | depends on (BFIN526_EZBRD) | ||
| 372 | default y | ||
| 373 | |||
| 369 | source "arch/blackfin/mach-bf518/Kconfig" | 374 | source "arch/blackfin/mach-bf518/Kconfig" |
| 370 | source "arch/blackfin/mach-bf527/Kconfig" | 375 | source "arch/blackfin/mach-bf527/Kconfig" |
| 371 | source "arch/blackfin/mach-bf533/Kconfig" | 376 | source "arch/blackfin/mach-bf533/Kconfig" |
| @@ -623,7 +628,6 @@ choice · 251 unmodified lines | |||
| 623 | config TICKSOURCE_GPTMR0 | 628 | config TICKSOURCE_GPTMR0 |
| 624 | bool "Gptimer0 (SCLK domain)" | 629 | bool "Gptimer0 (SCLK domain)" |
| 625 | select BFIN_GPTIMERS | 630 | select BFIN_GPTIMERS |
| 626 | depends on !IPIPE | ||
| 627 | 631 | ||
| 628 | config TICKSOURCE_CORETMR | 632 | config TICKSOURCE_CORETMR |
| 629 | bool "Core timer (CCLK domain)" | 633 | bool "Core timer (CCLK domain)" |
| @@ -644,6 +648,7 @@ config CYCLES_CLOCKSOURCE · 14 unmodified lines | |||
| 644 | 648 | ||
| 645 | config GPTMR0_CLOCKSOURCE | 649 | config GPTMR0_CLOCKSOURCE |
| 646 | bool "Use GPTimer0 as a clocksource (higher rating)" | 650 | bool "Use GPTimer0 as a clocksource (higher rating)" |
| 651 | select BFIN_GPTIMERS | ||
| 647 | depends on GENERIC_CLOCKEVENTS | 652 | depends on GENERIC_CLOCKEVENTS |
| 648 | depends on !TICKSOURCE_GPTMR0 | 653 | depends on !TICKSOURCE_GPTMR0 |
| 649 | 654 | ||
| @@ -908,23 +913,41 @@ endchoice · 258 unmodified lines | |||
| 908 | 913 | ||
| 909 | 914 | ||
| 910 | comment "Cache Support" | 915 | comment "Cache Support" |
| 916 | |||
| 911 | config BFIN_ICACHE | 917 | config BFIN_ICACHE |
| 912 | bool "Enable ICACHE" | 918 | bool "Enable ICACHE" |
| 919 | default y | ||
| 920 | config BFIN_ICACHE_LOCK | ||
| 921 | bool "Enable Instruction Cache Locking" | ||
| 922 | depends on BFIN_ICACHE | ||
| 923 | default n | ||
| 924 | config BFIN_EXTMEM_ICACHEABLE | ||
| 925 | bool "Enable ICACHE for external memory" | ||
| 926 | depends on BFIN_ICACHE | ||
| 927 | default y | ||
| 928 | config BFIN_L2_ICACHEABLE | ||
| 929 | bool "Enable ICACHE for L2 SRAM" | ||
| 930 | depends on BFIN_ICACHE | ||
| 931 | depends on BF54x || BF561 | ||
| 932 | default n | ||
| 933 | |||
| 913 | config BFIN_DCACHE | 934 | config BFIN_DCACHE |
| 914 | bool "Enable DCACHE" | 935 | bool "Enable DCACHE" |
| 936 | default y | ||
| 915 | config BFIN_DCACHE_BANKA | 937 | config BFIN_DCACHE_BANKA |
| 916 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" | 938 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
| 917 | depends on BFIN_DCACHE && !BF531 | 939 | depends on BFIN_DCACHE && !BF531 |
| 918 | default n | 940 | default n |
| 919 | config BFIN_ICACHE_LOCK | 941 | config BFIN_EXTMEM_DCACHEABLE |
| 920 | bool "Enable Instruction Cache Locking" | 942 | bool "Enable DCACHE for external memory" |
| 921 | |||
| 922 | choice | ||
| 923 | prompt "External memory cache policy" | ||
| 924 | depends on BFIN_DCACHE | 943 | depends on BFIN_DCACHE |
| 925 | default BFIN_WB if !SMP | 944 | default y |
| 926 | default BFIN_WT if SMP | 945 | choice |
| 927 | config BFIN_WB | 946 | prompt "External memory DCACHE policy" |
| 947 | depends on BFIN_EXTMEM_DCACHEABLE | ||
| 948 | default BFIN_EXTMEM_WRITEBACK if !SMP | ||
| 949 | default BFIN_EXTMEM_WRITETHROUGH if SMP | ||
| 950 | config BFIN_EXTMEM_WRITEBACK | ||
| 928 | bool "Write back" | 951 | bool "Write back" |
| 929 | depends on !SMP | 952 | depends on !SMP |
| 930 | help | 953 | help |
| @@ -942,7 +965,7 @@ config BFIN_WB · 11 unmodified lines | |||
| 942 | If you are unsure of the options and you want to be safe, | 965 | If you are unsure of the options and you want to be safe, |
| 943 | then go with Write Through. | 966 | then go with Write Through. |
| 944 | 967 | ||
| 945 | config BFIN_WT | 968 | config BFIN_EXTMEM_WRITETHROUGH |
| 946 | bool "Write through" | 969 | bool "Write through" |
| 947 | help | 970 | help |
| 948 | Write Back Policy: | 971 | Write Back Policy: |
| @@ -961,23 +984,26 @@ config BFIN_WT · 12 unmodified lines | |||
| 961 | 984 | ||
| 962 | endchoice | 985 | endchoice |
| 963 | 986 | ||
| 987 | config BFIN_L2_DCACHEABLE | ||
| 988 | bool "Enable DCACHE for L2 SRAM" | ||
| 989 | depends on BFIN_DCACHE | ||
| 990 | depends on BF54x || BF561 | ||
| 991 | default n | ||
| 964 | choice | 992 | choice |
| 965 | prompt "L2 SRAM cache policy" | 993 | prompt "L2 SRAM DCACHE policy" |
| 966 | depends on (BF54x || BF561) | 994 | depends on BFIN_L2_DCACHEABLE |
| 967 | default BFIN_L2_WT | 995 | default BFIN_L2_WRITEBACK |
| 968 | config BFIN_L2_WB | 996 | config BFIN_L2_WRITEBACK |
| 969 | bool "Write back" | 997 | bool "Write back" |
| 970 | depends on !SMP | 998 | depends on !SMP |
| 971 | 999 | ||
| 972 | config BFIN_L2_WT | 1000 | config BFIN_L2_WRITETHROUGH |
| 973 | bool "Write through" | 1001 | bool "Write through" |
| 974 | depends on !SMP | 1002 | depends on !SMP |
| 975 | |||
| 976 | config BFIN_L2_NOT_CACHED | ||
| 977 | bool "Not cached" | ||
| 978 | |||
| 979 | endchoice | 1003 | endchoice |
| 980 | 1004 | ||
| 1005 | |||
| 1006 | comment "Memory Protection Unit" | ||
| 981 | config MPU | 1007 | config MPU |
| 982 | bool "Enable the memory protection unit (EXPERIMENTAL)" | 1008 | bool "Enable the memory protection unit (EXPERIMENTAL)" |
| 983 | default n | 1009 | default n |
| @@ -13,7 +13,7 @@ extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma · 12 unmodified lines | |||
| 13 | 13 | ||
| 14 | quiet_cmd_uimage = UIMAGE $@ | 14 | quiet_cmd_uimage = UIMAGE $@ |
| 15 | cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ | 15 | cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ |
| 16 | -C $(2) -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \ | 16 | -C $(2) -n '$(MACHINE)-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \ |
| 17 | -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \ | 17 | -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \ |
| 18 | -d $< $@ | 18 | -d $< $@ |
| 19 | 19 | ||
| @@ -326,11 +326,17 @@ CONFIG_DMA_UNCACHED_1M=y · 325 unmodified lines | |||
| 326 | # Cache Support | 326 | # Cache Support |
| 327 | # | 327 | # |
| 328 | CONFIG_BFIN_ICACHE=y | 328 | CONFIG_BFIN_ICACHE=y |
| 329 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 329 | CONFIG_BFIN_DCACHE=y | 330 | CONFIG_BFIN_DCACHE=y |
| 330 | # CONFIG_BFIN_DCACHE_BANKA is not set | 331 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 331 | # CONFIG_BFIN_ICACHE_LOCK is not set | 332 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 332 | CONFIG_BFIN_WB=y | 333 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 333 | # CONFIG_BFIN_WT is not set | 334 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 335 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set | ||
| 336 | |||
| 337 | # | ||
| 338 | # Memory Protection Unit | ||
| 339 | # | ||
| 334 | # CONFIG_MPU is not set | 340 | # CONFIG_MPU is not set |
| 335 | 341 | ||
| 336 | # | 342 | # |
| @@ -413,11 +419,11 @@ CONFIG_IP_PNP=y · 76 unmodified lines | |||
| 413 | # CONFIG_INET_IPCOMP is not set | 419 | # CONFIG_INET_IPCOMP is not set |
| 414 | # CONFIG_INET_XFRM_TUNNEL is not set | 420 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 415 | # CONFIG_INET_TUNNEL is not set | 421 | # CONFIG_INET_TUNNEL is not set |
| 416 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 422 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 417 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 423 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 418 | CONFIG_INET_XFRM_MODE_BEET=y | 424 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 419 | # CONFIG_INET_LRO is not set | 425 | # CONFIG_INET_LRO is not set |
| 420 | CONFIG_INET_DIAG=y | 426 | # CONFIG_INET_DIAG is not set |
| 421 | CONFIG_INET_TCP_DIAG=y | 427 | CONFIG_INET_TCP_DIAG=y |
| 422 | # CONFIG_TCP_CONG_ADVANCED is not set | 428 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 423 | CONFIG_TCP_CONG_CUBIC=y | 429 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -916,7 +922,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y · 492 unmodified lines | |||
| 916 | # CONFIG_MMC_SDHCI is not set | 922 | # CONFIG_MMC_SDHCI is not set |
| 917 | CONFIG_SDH_BFIN=m | 923 | CONFIG_SDH_BFIN=m |
| 918 | CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y | 924 | CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y |
| 919 | CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ=y | 925 | # CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ is not set |
| 920 | # CONFIG_MMC_SPI is not set | 926 | # CONFIG_MMC_SPI is not set |
| 921 | # CONFIG_MEMSTICK is not set | 927 | # CONFIG_MEMSTICK is not set |
| 922 | # CONFIG_NEW_LEDS is not set | 928 | # CONFIG_NEW_LEDS is not set |
| @@ -1147,7 +1153,7 @@ CONFIG_SCHED_DEBUG=y · 224 unmodified lines | |||
| 1147 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1153 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1148 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1154 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1149 | # CONFIG_DEBUG_KOBJECT is not set | 1155 | # CONFIG_DEBUG_KOBJECT is not set |
| 1150 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1156 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1151 | CONFIG_DEBUG_INFO=y | 1157 | CONFIG_DEBUG_INFO=y |
| 1152 | # CONFIG_DEBUG_VM is not set | 1158 | # CONFIG_DEBUG_VM is not set |
| 1153 | # CONFIG_DEBUG_WRITECOUNT is not set | 1159 | # CONFIG_DEBUG_WRITECOUNT is not set |
| @@ -331,16 +331,18 @@ CONFIG_DMA_UNCACHED_1M=y · 330 unmodified lines | |||
| 331 | # Cache Support | 331 | # Cache Support |
| 332 | # | 332 | # |
| 333 | CONFIG_BFIN_ICACHE=y | 333 | CONFIG_BFIN_ICACHE=y |
| 334 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 334 | CONFIG_BFIN_DCACHE=y | 335 | CONFIG_BFIN_DCACHE=y |
| 335 | # CONFIG_BFIN_DCACHE_BANKA is not set | 336 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 336 | # CONFIG_BFIN_ICACHE_LOCK is not set | 337 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 337 | CONFIG_BFIN_WB=y | 338 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 338 | # CONFIG_BFIN_WT is not set | 339 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 339 | # CONFIG_MPU is not set | 340 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set |
| 340 | 341 | ||
| 341 | # | 342 | # |
| 342 | # Asynchonous Memory Configuration | 343 | # Memory Protection Unit |
| 343 | # | 344 | # |
| 345 | # CONFIG_MPU is not set | ||
| 344 | 346 | ||
| 345 | # | 347 | # |
| 346 | # EBIU_AMGCTL Global Control | 348 | # EBIU_AMGCTL Global Control |
| @@ -418,11 +420,11 @@ CONFIG_IP_PNP=y · 71 unmodified lines | |||
| 418 | # CONFIG_INET_IPCOMP is not set | 420 | # CONFIG_INET_IPCOMP is not set |
| 419 | # CONFIG_INET_XFRM_TUNNEL is not set | 421 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 420 | # CONFIG_INET_TUNNEL is not set | 422 | # CONFIG_INET_TUNNEL is not set |
| 421 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 423 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 422 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 424 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 423 | CONFIG_INET_XFRM_MODE_BEET=y | 425 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 424 | # CONFIG_INET_LRO is not set | 426 | # CONFIG_INET_LRO is not set |
| 425 | CONFIG_INET_DIAG=y | 427 | # CONFIG_INET_DIAG is not set |
| 426 | CONFIG_INET_TCP_DIAG=y | 428 | CONFIG_INET_TCP_DIAG=y |
| 427 | # CONFIG_TCP_CONG_ADVANCED is not set | 429 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 428 | CONFIG_TCP_CONG_CUBIC=y | 430 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -1424,7 +1426,7 @@ CONFIG_SCHED_DEBUG=y · 995 unmodified lines | |||
| 1424 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1426 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1425 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1427 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1426 | # CONFIG_DEBUG_KOBJECT is not set | 1428 | # CONFIG_DEBUG_KOBJECT is not set |
| 1427 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1429 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1428 | CONFIG_DEBUG_INFO=y | 1430 | CONFIG_DEBUG_INFO=y |
| 1429 | # CONFIG_DEBUG_VM is not set | 1431 | # CONFIG_DEBUG_VM is not set |
| 1430 | # CONFIG_DEBUG_WRITECOUNT is not set | 1432 | # CONFIG_DEBUG_WRITECOUNT is not set |
| @@ -331,11 +331,17 @@ CONFIG_DMA_UNCACHED_1M=y · 330 unmodified lines | |||
| 331 | # Cache Support | 331 | # Cache Support |
| 332 | # | 332 | # |
| 333 | CONFIG_BFIN_ICACHE=y | 333 | CONFIG_BFIN_ICACHE=y |
| 334 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 334 | CONFIG_BFIN_DCACHE=y | 335 | CONFIG_BFIN_DCACHE=y |
| 335 | # CONFIG_BFIN_DCACHE_BANKA is not set | 336 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 336 | # CONFIG_BFIN_ICACHE_LOCK is not set | 337 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 337 | CONFIG_BFIN_WB=y | 338 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 338 | # CONFIG_BFIN_WT is not set | 339 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 340 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set | ||
| 341 | |||
| 342 | # | ||
| 343 | # Memory Protection Unit | ||
| 344 | # | ||
| 339 | # CONFIG_MPU is not set | 345 | # CONFIG_MPU is not set |
| 340 | 346 | ||
| 341 | # | 347 | # |
| @@ -418,11 +424,11 @@ CONFIG_IP_PNP=y · 76 unmodified lines | |||
| 418 | # CONFIG_INET_IPCOMP is not set | 424 | # CONFIG_INET_IPCOMP is not set |
| 419 | # CONFIG_INET_XFRM_TUNNEL is not set | 425 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 420 | # CONFIG_INET_TUNNEL is not set | 426 | # CONFIG_INET_TUNNEL is not set |
| 421 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 427 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 422 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 428 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 423 | CONFIG_INET_XFRM_MODE_BEET=y | 429 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 424 | # CONFIG_INET_LRO is not set | 430 | # CONFIG_INET_LRO is not set |
| 425 | CONFIG_INET_DIAG=y | 431 | # CONFIG_INET_DIAG is not set |
| 426 | CONFIG_INET_TCP_DIAG=y | 432 | CONFIG_INET_TCP_DIAG=y |
| 427 | # CONFIG_TCP_CONG_ADVANCED is not set | 433 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 428 | CONFIG_TCP_CONG_CUBIC=y | 434 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -1505,7 +1511,7 @@ CONFIG_SCHED_DEBUG=y · 1076 unmodified lines | |||
| 1505 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1511 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1506 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1512 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1507 | # CONFIG_DEBUG_KOBJECT is not set | 1513 | # CONFIG_DEBUG_KOBJECT is not set |
| 1508 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1514 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1509 | CONFIG_DEBUG_INFO=y | 1515 | CONFIG_DEBUG_INFO=y |
| 1510 | # CONFIG_DEBUG_VM is not set | 1516 | # CONFIG_DEBUG_VM is not set |
| 1511 | # CONFIG_DEBUG_WRITECOUNT is not set | 1517 | # CONFIG_DEBUG_WRITECOUNT is not set |
| @@ -289,15 +289,24 @@ CONFIG_BFIN_GPTIMERS=m · 288 unmodified lines | |||
| 289 | CONFIG_DMA_UNCACHED_1M=y | 289 | CONFIG_DMA_UNCACHED_1M=y |
| 290 | # CONFIG_DMA_UNCACHED_NONE is not set | 290 | # CONFIG_DMA_UNCACHED_NONE is not set |
| 291 | 291 | ||
| 292 | # | ||
| 293 | # Cache Support | ||
| 294 | # | ||
| 292 | # | 295 | # |
| 293 | # Cache Support | 296 | # Cache Support |
| 294 | # | 297 | # |
| 295 | CONFIG_BFIN_ICACHE=y | 298 | CONFIG_BFIN_ICACHE=y |
| 299 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 296 | CONFIG_BFIN_DCACHE=y | 300 | CONFIG_BFIN_DCACHE=y |
| 297 | # CONFIG_BFIN_DCACHE_BANKA is not set | 301 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 298 | # CONFIG_BFIN_ICACHE_LOCK is not set | 302 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 299 | CONFIG_BFIN_WB=y | 303 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 300 | # CONFIG_BFIN_WT is not set | 304 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 305 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set | ||
| 306 | |||
| 307 | # | ||
| 308 | # Memory Protection Unit | ||
| 309 | # | ||
| 301 | # CONFIG_MPU is not set | 310 | # CONFIG_MPU is not set |
| 302 | 311 | ||
| 303 | # | 312 | # |
| @@ -391,11 +400,11 @@ CONFIG_IP_PNP=y · 87 unmodified lines | |||
| 391 | # CONFIG_INET_IPCOMP is not set | 400 | # CONFIG_INET_IPCOMP is not set |
| 392 | # CONFIG_INET_XFRM_TUNNEL is not set | 401 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 393 | # CONFIG_INET_TUNNEL is not set | 402 | # CONFIG_INET_TUNNEL is not set |
| 394 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 403 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 395 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 404 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 396 | CONFIG_INET_XFRM_MODE_BEET=y | 405 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 397 | # CONFIG_INET_LRO is not set | 406 | # CONFIG_INET_LRO is not set |
| 398 | CONFIG_INET_DIAG=y | 407 | # CONFIG_INET_DIAG is not set |
| 399 | CONFIG_INET_TCP_DIAG=y | 408 | CONFIG_INET_TCP_DIAG=y |
| 400 | # CONFIG_TCP_CONG_ADVANCED is not set | 409 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 401 | CONFIG_TCP_CONG_CUBIC=y | 410 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -1052,7 +1061,7 @@ CONFIG_SCHED_DEBUG=y · 650 unmodified lines | |||
| 1052 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1061 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1053 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1062 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1054 | # CONFIG_DEBUG_KOBJECT is not set | 1063 | # CONFIG_DEBUG_KOBJECT is not set |
| 1055 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1064 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1056 | CONFIG_DEBUG_INFO=y | 1065 | CONFIG_DEBUG_INFO=y |
| 1057 | # CONFIG_DEBUG_VM is not set | 1066 | # CONFIG_DEBUG_VM is not set |
| 1058 | # CONFIG_DEBUG_WRITECOUNT is not set | 1067 | # CONFIG_DEBUG_WRITECOUNT is not set |
| @@ -293,11 +293,17 @@ CONFIG_DMA_UNCACHED_1M=y · 292 unmodified lines | |||
| 293 | # Cache Support | 293 | # Cache Support |
| 294 | # | 294 | # |
| 295 | CONFIG_BFIN_ICACHE=y | 295 | CONFIG_BFIN_ICACHE=y |
| 296 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 296 | CONFIG_BFIN_DCACHE=y | 297 | CONFIG_BFIN_DCACHE=y |
| 297 | # CONFIG_BFIN_DCACHE_BANKA is not set | 298 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 298 | # CONFIG_BFIN_ICACHE_LOCK is not set | 299 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 299 | CONFIG_BFIN_WB=y | 300 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 300 | # CONFIG_BFIN_WT is not set | 301 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 302 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set | ||
| 303 | |||
| 304 | # | ||
| 305 | # Memory Protection Unit | ||
| 306 | # | ||
| 301 | # CONFIG_MPU is not set | 307 | # CONFIG_MPU is not set |
| 302 | 308 | ||
| 303 | # | 309 | # |
| @@ -391,11 +397,11 @@ CONFIG_IP_PNP=y · 87 unmodified lines | |||
| 391 | # CONFIG_INET_IPCOMP is not set | 397 | # CONFIG_INET_IPCOMP is not set |
| 392 | # CONFIG_INET_XFRM_TUNNEL is not set | 398 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 393 | # CONFIG_INET_TUNNEL is not set | 399 | # CONFIG_INET_TUNNEL is not set |
| 394 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 400 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 395 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 401 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 396 | CONFIG_INET_XFRM_MODE_BEET=y | 402 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 397 | # CONFIG_INET_LRO is not set | 403 | # CONFIG_INET_LRO is not set |
| 398 | CONFIG_INET_DIAG=y | 404 | # CONFIG_INET_DIAG is not set |
| 399 | CONFIG_INET_TCP_DIAG=y | 405 | CONFIG_INET_TCP_DIAG=y |
| 400 | # CONFIG_TCP_CONG_ADVANCED is not set | 406 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 401 | CONFIG_TCP_CONG_CUBIC=y | 407 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -1216,7 +1222,7 @@ CONFIG_SCHED_DEBUG=y · 814 unmodified lines | |||
| 1216 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1222 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1217 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1223 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1218 | # CONFIG_DEBUG_KOBJECT is not set | 1224 | # CONFIG_DEBUG_KOBJECT is not set |
| 1219 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1225 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1220 | CONFIG_DEBUG_INFO=y | 1226 | CONFIG_DEBUG_INFO=y |
| 1221 | # CONFIG_DEBUG_VM is not set | 1227 | # CONFIG_DEBUG_VM is not set |
| 1222 | # CONFIG_DEBUG_WRITECOUNT is not set | 1228 | # CONFIG_DEBUG_WRITECOUNT is not set |
| @@ -300,11 +300,17 @@ CONFIG_DMA_UNCACHED_1M=y · 299 unmodified lines | |||
| 300 | # Cache Support | 300 | # Cache Support |
| 301 | # | 301 | # |
| 302 | CONFIG_BFIN_ICACHE=y | 302 | CONFIG_BFIN_ICACHE=y |
| 303 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 303 | CONFIG_BFIN_DCACHE=y | 304 | CONFIG_BFIN_DCACHE=y |
| 304 | # CONFIG_BFIN_DCACHE_BANKA is not set | 305 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 305 | # CONFIG_BFIN_ICACHE_LOCK is not set | 306 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 306 | CONFIG_BFIN_WB=y | 307 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 307 | # CONFIG_BFIN_WT is not set | 308 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 309 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set | ||
| 310 | |||
| 311 | # | ||
| 312 | # Memory Protection Unit | ||
| 313 | # | ||
| 308 | # CONFIG_MPU is not set | 314 | # CONFIG_MPU is not set |
| 309 | 315 | ||
| 310 | # | 316 | # |
| @@ -399,11 +405,11 @@ CONFIG_IP_PNP=y · 88 unmodified lines | |||
| 399 | # CONFIG_INET_IPCOMP is not set | 405 | # CONFIG_INET_IPCOMP is not set |
| 400 | # CONFIG_INET_XFRM_TUNNEL is not set | 406 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 401 | # CONFIG_INET_TUNNEL is not set | 407 | # CONFIG_INET_TUNNEL is not set |
| 402 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 408 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 403 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 409 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 404 | CONFIG_INET_XFRM_MODE_BEET=y | 410 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 405 | # CONFIG_INET_LRO is not set | 411 | # CONFIG_INET_LRO is not set |
| 406 | CONFIG_INET_DIAG=y | 412 | # CONFIG_INET_DIAG is not set |
| 407 | CONFIG_INET_TCP_DIAG=y | 413 | CONFIG_INET_TCP_DIAG=y |
| 408 | # CONFIG_TCP_CONG_ADVANCED is not set | 414 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 409 | CONFIG_TCP_CONG_CUBIC=y | 415 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -1269,7 +1275,7 @@ CONFIG_SCHED_DEBUG=y · 859 unmodified lines | |||
| 1269 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1275 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1270 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1276 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1271 | # CONFIG_DEBUG_KOBJECT is not set | 1277 | # CONFIG_DEBUG_KOBJECT is not set |
| 1272 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1278 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1273 | CONFIG_DEBUG_INFO=y | 1279 | CONFIG_DEBUG_INFO=y |
| 1274 | # CONFIG_DEBUG_VM is not set | 1280 | # CONFIG_DEBUG_VM is not set |
| 1275 | # CONFIG_DEBUG_WRITECOUNT is not set | 1281 | # CONFIG_DEBUG_WRITECOUNT is not set |
| @@ -311,11 +311,17 @@ CONFIG_DMA_UNCACHED_1M=y · 310 unmodified lines | |||
| 311 | # Cache Support | 311 | # Cache Support |
| 312 | # | 312 | # |
| 313 | CONFIG_BFIN_ICACHE=y | 313 | CONFIG_BFIN_ICACHE=y |
| 314 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 314 | CONFIG_BFIN_DCACHE=y | 315 | CONFIG_BFIN_DCACHE=y |
| 315 | # CONFIG_BFIN_DCACHE_BANKA is not set | 316 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 316 | # CONFIG_BFIN_ICACHE_LOCK is not set | 317 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 317 | CONFIG_BFIN_WB=y | 318 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 318 | # CONFIG_BFIN_WT is not set | 319 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 320 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set | ||
| 321 | |||
| 322 | # | ||
| 323 | # Memory Protection Unit | ||
| 324 | # | ||
| 319 | # CONFIG_MPU is not set | 325 | # CONFIG_MPU is not set |
| 320 | 326 | ||
| 321 | # | 327 | # |
| @@ -398,11 +404,11 @@ CONFIG_IP_PNP=y · 76 unmodified lines | |||
| 398 | # CONFIG_INET_IPCOMP is not set | 404 | # CONFIG_INET_IPCOMP is not set |
| 399 | # CONFIG_INET_XFRM_TUNNEL is not set | 405 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 400 | # CONFIG_INET_TUNNEL is not set | 406 | # CONFIG_INET_TUNNEL is not set |
| 401 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 407 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 402 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 408 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 403 | CONFIG_INET_XFRM_MODE_BEET=y | 409 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 404 | # CONFIG_INET_LRO is not set | 410 | # CONFIG_INET_LRO is not set |
| 405 | CONFIG_INET_DIAG=y | 411 | # CONFIG_INET_DIAG is not set |
| 406 | CONFIG_INET_TCP_DIAG=y | 412 | CONFIG_INET_TCP_DIAG=y |
| 407 | # CONFIG_TCP_CONG_ADVANCED is not set | 413 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 408 | CONFIG_TCP_CONG_CUBIC=y | 414 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -1203,7 +1209,7 @@ CONFIG_SCHED_DEBUG=y · 794 unmodified lines | |||
| 1203 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1209 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1204 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1210 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1205 | # CONFIG_DEBUG_KOBJECT is not set | 1211 | # CONFIG_DEBUG_KOBJECT is not set |
| 1206 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1212 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1207 | CONFIG_DEBUG_INFO=y | 1213 | CONFIG_DEBUG_INFO=y |
| 1208 | # CONFIG_DEBUG_VM is not set | 1214 | # CONFIG_DEBUG_VM is not set |
| 1209 | # CONFIG_DEBUG_WRITECOUNT is not set | 1215 | # CONFIG_DEBUG_WRITECOUNT is not set |
| @@ -366,14 +366,19 @@ CONFIG_DMA_UNCACHED_2M=y · 365 unmodified lines | |||
| 366 | # Cache Support | 366 | # Cache Support |
| 367 | # | 367 | # |
| 368 | CONFIG_BFIN_ICACHE=y | 368 | CONFIG_BFIN_ICACHE=y |
| 369 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 369 | CONFIG_BFIN_DCACHE=y | 370 | CONFIG_BFIN_DCACHE=y |
| 370 | # CONFIG_BFIN_DCACHE_BANKA is not set | 371 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 371 | # CONFIG_BFIN_ICACHE_LOCK is not set | 372 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 372 | CONFIG_BFIN_WB=y | 373 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 373 | # CONFIG_BFIN_WT is not set | 374 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 374 | # CONFIG_BFIN_L2_WB is not set | 375 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set |
| 375 | CONFIG_BFIN_L2_WT=y | 376 | # CONFIG_BFIN_L2_ICACHEABLE is not set |
| 376 | # CONFIG_BFIN_L2_NOT_CACHED is not set | 377 | # CONFIG_BFIN_L2_DCACHEABLE is not set |
| 378 | |||
| 379 | # | ||
| 380 | # Memory Protection Unit | ||
| 381 | # | ||
| 377 | # CONFIG_MPU is not set | 382 | # CONFIG_MPU is not set |
| 378 | 383 | ||
| 379 | # | 384 | # |
| @@ -459,11 +464,11 @@ CONFIG_IP_PNP=y · 79 unmodified lines | |||
| 459 | # CONFIG_INET_IPCOMP is not set | 464 | # CONFIG_INET_IPCOMP is not set |
| 460 | # CONFIG_INET_XFRM_TUNNEL is not set | 465 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 461 | # CONFIG_INET_TUNNEL is not set | 466 | # CONFIG_INET_TUNNEL is not set |
| 462 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 467 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 463 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 468 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 464 | CONFIG_INET_XFRM_MODE_BEET=y | 469 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 465 | # CONFIG_INET_LRO is not set | 470 | # CONFIG_INET_LRO is not set |
| 466 | CONFIG_INET_DIAG=y | 471 | # CONFIG_INET_DIAG is not set |
| 467 | CONFIG_INET_TCP_DIAG=y | 472 | CONFIG_INET_TCP_DIAG=y |
| 468 | # CONFIG_TCP_CONG_ADVANCED is not set | 473 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 469 | CONFIG_TCP_CONG_CUBIC=y | 474 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -1606,7 +1611,7 @@ CONFIG_SCHED_DEBUG=y · 1136 unmodified lines | |||
| 1606 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1611 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1607 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1612 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1608 | # CONFIG_DEBUG_KOBJECT is not set | 1613 | # CONFIG_DEBUG_KOBJECT is not set |
| 1609 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1614 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1610 | CONFIG_DEBUG_INFO=y | 1615 | CONFIG_DEBUG_INFO=y |
| 1611 | # CONFIG_DEBUG_VM is not set | 1616 | # CONFIG_DEBUG_VM is not set |
| 1612 | # CONFIG_DEBUG_WRITECOUNT is not set | 1617 | # CONFIG_DEBUG_WRITECOUNT is not set |
| @@ -331,14 +331,19 @@ CONFIG_DMA_UNCACHED_1M=y · 330 unmodified lines | |||
| 331 | # Cache Support | 331 | # Cache Support |
| 332 | # | 332 | # |
| 333 | CONFIG_BFIN_ICACHE=y | 333 | CONFIG_BFIN_ICACHE=y |
| 334 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 334 | CONFIG_BFIN_DCACHE=y | 335 | CONFIG_BFIN_DCACHE=y |
| 335 | # CONFIG_BFIN_DCACHE_BANKA is not set | 336 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 336 | # CONFIG_BFIN_ICACHE_LOCK is not set | 337 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 337 | CONFIG_BFIN_WB=y | 338 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 338 | # CONFIG_BFIN_WT is not set | 339 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 339 | # CONFIG_BFIN_L2_WB is not set | 340 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set |
| 340 | CONFIG_BFIN_L2_WT=y | 341 | # CONFIG_BFIN_L2_ICACHEABLE is not set |
| 341 | # CONFIG_BFIN_L2_NOT_CACHED is not set | 342 | # CONFIG_BFIN_L2_DCACHEABLE is not set |
| 343 | |||
| 344 | # | ||
| 345 | # Memory Protection Unit | ||
| 346 | # | ||
| 342 | # CONFIG_MPU is not set | 347 | # CONFIG_MPU is not set |
| 343 | 348 | ||
| 344 | # | 349 | # |
| @@ -425,11 +430,11 @@ CONFIG_IP_PNP=y · 80 unmodified lines | |||
| 425 | # CONFIG_INET_IPCOMP is not set | 430 | # CONFIG_INET_IPCOMP is not set |
| 426 | # CONFIG_INET_XFRM_TUNNEL is not set | 431 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 427 | # CONFIG_INET_TUNNEL is not set | 432 | # CONFIG_INET_TUNNEL is not set |
| 428 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 433 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 429 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 434 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 430 | CONFIG_INET_XFRM_MODE_BEET=y | 435 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 431 | # CONFIG_INET_LRO is not set | 436 | # CONFIG_INET_LRO is not set |
| 432 | CONFIG_INET_DIAG=y | 437 | # CONFIG_INET_DIAG is not set |
| 433 | CONFIG_INET_TCP_DIAG=y | 438 | CONFIG_INET_TCP_DIAG=y |
| 434 | # CONFIG_TCP_CONG_ADVANCED is not set | 439 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 435 | CONFIG_TCP_CONG_CUBIC=y | 440 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -1044,7 +1049,7 @@ CONFIG_SCHED_DEBUG=y · 608 unmodified lines | |||
| 1044 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1049 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1045 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1050 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1046 | # CONFIG_DEBUG_KOBJECT is not set | 1051 | # CONFIG_DEBUG_KOBJECT is not set |
| 1047 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1052 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1048 | CONFIG_DEBUG_INFO=y | 1053 | CONFIG_DEBUG_INFO=y |
| 1049 | # CONFIG_DEBUG_VM is not set | 1054 | # CONFIG_DEBUG_VM is not set |
| 1050 | # CONFIG_DEBUG_WRITECOUNT is not set | 1055 | # CONFIG_DEBUG_WRITECOUNT is not set |
| @@ -285,11 +285,17 @@ CONFIG_DMA_UNCACHED_1M=y · 284 unmodified lines | |||
| 285 | # Cache Support | 285 | # Cache Support |
| 286 | # | 286 | # |
| 287 | CONFIG_BFIN_ICACHE=y | 287 | CONFIG_BFIN_ICACHE=y |
| 288 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 288 | CONFIG_BFIN_DCACHE=y | 289 | CONFIG_BFIN_DCACHE=y |
| 289 | # CONFIG_BFIN_DCACHE_BANKA is not set | 290 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 290 | # CONFIG_BFIN_ICACHE_LOCK is not set | 291 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 291 | CONFIG_BFIN_WB=y | 292 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 292 | # CONFIG_BFIN_WT is not set | 293 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 294 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set | ||
| 295 | |||
| 296 | # | ||
| 297 | # Memory Protection Unit | ||
| 298 | # | ||
| 293 | # CONFIG_MPU is not set | 299 | # CONFIG_MPU is not set |
| 294 | 300 | ||
| 295 | # | 301 | # |
| @@ -329,11 +329,17 @@ CONFIG_DMA_UNCACHED_1M=y · 328 unmodified lines | |||
| 329 | # Cache Support | 329 | # Cache Support |
| 330 | # | 330 | # |
| 331 | CONFIG_BFIN_ICACHE=y | 331 | CONFIG_BFIN_ICACHE=y |
| 332 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 332 | CONFIG_BFIN_DCACHE=y | 333 | CONFIG_BFIN_DCACHE=y |
| 333 | # CONFIG_BFIN_DCACHE_BANKA is not set | 334 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 334 | # CONFIG_BFIN_ICACHE_LOCK is not set | 335 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 335 | CONFIG_BFIN_WB=y | 336 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 336 | # CONFIG_BFIN_WT is not set | 337 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 338 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set | ||
| 339 | |||
| 340 | # | ||
| 341 | # Memory Protection Unit | ||
| 342 | # | ||
| 337 | # CONFIG_MPU is not set | 343 | # CONFIG_MPU is not set |
| 338 | 344 | ||
| 339 | # | 345 | # |
| @@ -417,11 +423,11 @@ CONFIG_IP_PNP=y · 77 unmodified lines | |||
| 417 | # CONFIG_INET_IPCOMP is not set | 423 | # CONFIG_INET_IPCOMP is not set |
| 418 | # CONFIG_INET_XFRM_TUNNEL is not set | 424 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 419 | # CONFIG_INET_TUNNEL is not set | 425 | # CONFIG_INET_TUNNEL is not set |
| 420 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 426 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 421 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 427 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 422 | CONFIG_INET_XFRM_MODE_BEET=y | 428 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 423 | # CONFIG_INET_LRO is not set | 429 | # CONFIG_INET_LRO is not set |
| 424 | CONFIG_INET_DIAG=y | 430 | # CONFIG_INET_DIAG is not set |
| 425 | CONFIG_INET_TCP_DIAG=y | 431 | CONFIG_INET_TCP_DIAG=y |
| 426 | # CONFIG_TCP_CONG_ADVANCED is not set | 432 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 427 | CONFIG_TCP_CONG_CUBIC=y | 433 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -1246,7 +1252,7 @@ CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 · 818 unmodified lines | |||
| 1246 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1252 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1247 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1253 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1248 | # CONFIG_DEBUG_KOBJECT is not set | 1254 | # CONFIG_DEBUG_KOBJECT is not set |
| 1249 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1255 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1250 | # CONFIG_DEBUG_INFO is not set | 1256 | # CONFIG_DEBUG_INFO is not set |
| 1251 | # CONFIG_DEBUG_VM is not set | 1257 | # CONFIG_DEBUG_VM is not set |
| 1252 | # CONFIG_DEBUG_WRITECOUNT is not set | 1258 | # CONFIG_DEBUG_WRITECOUNT is not set |
| @@ -262,12 +262,17 @@ CONFIG_DMA_UNCACHED_1M=y · 261 unmodified lines | |||
| 262 | # Cache Support | 262 | # Cache Support |
| 263 | # | 263 | # |
| 264 | CONFIG_BFIN_ICACHE=y | 264 | CONFIG_BFIN_ICACHE=y |
| 265 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 265 | CONFIG_BFIN_DCACHE=y | 266 | CONFIG_BFIN_DCACHE=y |
| 266 | # CONFIG_BFIN_DCACHE_BANKA is not set | 267 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 267 | # CONFIG_BFIN_ICACHE_LOCK is not set | 268 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 268 | CONFIG_BFIN_WB=y | 269 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 269 | # CONFIG_BFIN_WT is not set | 270 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 270 | CONFIG_L1_MAX_PIECE=16 | 271 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set |
| 272 | |||
| 273 | # | ||
| 274 | # Memory Protection Unit | ||
| 275 | # | ||
| 271 | # CONFIG_MPU is not set | 276 | # CONFIG_MPU is not set |
| 272 | 277 | ||
| 273 | # | 278 | # |
| @@ -353,10 +358,10 @@ CONFIG_IP_FIB_HASH=y · 79 unmodified lines | |||
| 353 | # CONFIG_INET_IPCOMP is not set | 358 | # CONFIG_INET_IPCOMP is not set |
| 354 | # CONFIG_INET_XFRM_TUNNEL is not set | 359 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 355 | # CONFIG_INET_TUNNEL is not set | 360 | # CONFIG_INET_TUNNEL is not set |
| 356 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 361 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 357 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 362 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 358 | CONFIG_INET_XFRM_MODE_BEET=y | 363 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 359 | CONFIG_INET_DIAG=y | 364 | # CONFIG_INET_DIAG is not set |
| 360 | CONFIG_INET_TCP_DIAG=y | 365 | CONFIG_INET_TCP_DIAG=y |
| 361 | # CONFIG_TCP_CONG_ADVANCED is not set | 366 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 362 | CONFIG_TCP_CONG_CUBIC=y | 367 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -873,7 +878,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 510 unmodified lines | |||
| 873 | CONFIG_DEBUG_FS=y | 878 | CONFIG_DEBUG_FS=y |
| 874 | # CONFIG_HEADERS_CHECK is not set | 879 | # CONFIG_HEADERS_CHECK is not set |
| 875 | # CONFIG_DEBUG_KERNEL is not set | 880 | # CONFIG_DEBUG_KERNEL is not set |
| 876 | # CONFIG_DEBUG_BUGVERBOSE is not set | 881 | CONFIG_DEBUG_BUGVERBOSE=y |
| 877 | CONFIG_DEBUG_MMRS=y | 882 | CONFIG_DEBUG_MMRS=y |
| 878 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 883 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 879 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 884 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| @@ -297,11 +297,17 @@ CONFIG_DMA_UNCACHED_1M=y · 296 unmodified lines | |||
| 297 | # Cache Support | 297 | # Cache Support |
| 298 | # | 298 | # |
| 299 | CONFIG_BFIN_ICACHE=y | 299 | CONFIG_BFIN_ICACHE=y |
| 300 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 300 | CONFIG_BFIN_DCACHE=y | 301 | CONFIG_BFIN_DCACHE=y |
| 301 | # CONFIG_BFIN_DCACHE_BANKA is not set | 302 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 302 | # CONFIG_BFIN_ICACHE_LOCK is not set | 303 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 303 | CONFIG_BFIN_WB=y | 304 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 304 | # CONFIG_BFIN_WT is not set | 305 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 306 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set | ||
| 307 | |||
| 308 | # | ||
| 309 | # Memory Protection Unit | ||
| 310 | # | ||
| 305 | # CONFIG_MPU is not set | 311 | # CONFIG_MPU is not set |
| 306 | 312 | ||
| 307 | # | 313 | # |
| @@ -383,11 +389,11 @@ CONFIG_IP_PNP=y · 75 unmodified lines | |||
| 383 | # CONFIG_INET_IPCOMP is not set | 389 | # CONFIG_INET_IPCOMP is not set |
| 384 | # CONFIG_INET_XFRM_TUNNEL is not set | 390 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 385 | # CONFIG_INET_TUNNEL is not set | 391 | # CONFIG_INET_TUNNEL is not set |
| 386 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 392 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 387 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 393 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 388 | CONFIG_INET_XFRM_MODE_BEET=y | 394 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 389 | # CONFIG_INET_LRO is not set | 395 | # CONFIG_INET_LRO is not set |
| 390 | CONFIG_INET_DIAG=y | 396 | # CONFIG_INET_DIAG is not set |
| 391 | CONFIG_INET_TCP_DIAG=y | 397 | CONFIG_INET_TCP_DIAG=y |
| 392 | # CONFIG_TCP_CONG_ADVANCED is not set | 398 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 393 | CONFIG_TCP_CONG_CUBIC=y | 399 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -861,7 +867,7 @@ CONFIG_DEBUG_FS=y · 467 unmodified lines | |||
| 861 | # CONFIG_HEADERS_CHECK is not set | 867 | # CONFIG_HEADERS_CHECK is not set |
| 862 | CONFIG_DEBUG_SECTION_MISMATCH=y | 868 | CONFIG_DEBUG_SECTION_MISMATCH=y |
| 863 | # CONFIG_DEBUG_KERNEL is not set | 869 | # CONFIG_DEBUG_KERNEL is not set |
| 864 | # CONFIG_DEBUG_BUGVERBOSE is not set | 870 | CONFIG_DEBUG_BUGVERBOSE=y |
| 865 | # CONFIG_DEBUG_MEMORY_INIT is not set | 871 | # CONFIG_DEBUG_MEMORY_INIT is not set |
| 866 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 872 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 867 | 873 | ||
| @@ -270,12 +270,17 @@ CONFIG_DMA_UNCACHED_1M=y · 269 unmodified lines | |||
| 270 | # Cache Support | 270 | # Cache Support |
| 271 | # | 271 | # |
| 272 | CONFIG_BFIN_ICACHE=y | 272 | CONFIG_BFIN_ICACHE=y |
| 273 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 273 | CONFIG_BFIN_DCACHE=y | 274 | CONFIG_BFIN_DCACHE=y |
| 274 | # CONFIG_BFIN_DCACHE_BANKA is not set | 275 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 275 | # CONFIG_BFIN_ICACHE_LOCK is not set | 276 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 276 | CONFIG_BFIN_WB=y | 277 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 277 | # CONFIG_BFIN_WT is not set | 278 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 278 | CONFIG_L1_MAX_PIECE=16 | 279 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set |
| 280 | |||
| 281 | # | ||
| 282 | # Memory Protection Unit | ||
| 283 | # | ||
| 279 | # CONFIG_MPU is not set | 284 | # CONFIG_MPU is not set |
| 280 | 285 | ||
| 281 | # | 286 | # |
| @@ -361,10 +366,10 @@ CONFIG_IP_FIB_HASH=y · 79 unmodified lines | |||
| 361 | # CONFIG_INET_IPCOMP is not set | 366 | # CONFIG_INET_IPCOMP is not set |
| 362 | # CONFIG_INET_XFRM_TUNNEL is not set | 367 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 363 | # CONFIG_INET_TUNNEL is not set | 368 | # CONFIG_INET_TUNNEL is not set |
| 364 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 369 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 365 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 370 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 366 | CONFIG_INET_XFRM_MODE_BEET=y | 371 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 367 | CONFIG_INET_DIAG=y | 372 | # CONFIG_INET_DIAG is not set |
| 368 | CONFIG_INET_TCP_DIAG=y | 373 | CONFIG_INET_TCP_DIAG=y |
| 369 | # CONFIG_TCP_CONG_ADVANCED is not set | 374 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 370 | CONFIG_TCP_CONG_CUBIC=y | 375 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -901,7 +906,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 530 unmodified lines | |||
| 901 | CONFIG_DEBUG_FS=y | 906 | CONFIG_DEBUG_FS=y |
| 902 | # CONFIG_HEADERS_CHECK is not set | 907 | # CONFIG_HEADERS_CHECK is not set |
| 903 | # CONFIG_DEBUG_KERNEL is not set | 908 | # CONFIG_DEBUG_KERNEL is not set |
| 904 | # CONFIG_DEBUG_BUGVERBOSE is not set | 909 | CONFIG_DEBUG_BUGVERBOSE=y |
| 905 | CONFIG_DEBUG_MMRS=y | 910 | CONFIG_DEBUG_MMRS=y |
| 906 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 911 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| 907 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y | 912 | CONFIG_DEBUG_BFIN_HWTRACE_ON=y |
| @@ -333,12 +333,19 @@ CONFIG_DMA_UNCACHED_1M=y · 332 unmodified lines | |||
| 333 | # Cache Support | 333 | # Cache Support |
| 334 | # | 334 | # |
| 335 | CONFIG_BFIN_ICACHE=y | 335 | CONFIG_BFIN_ICACHE=y |
| 336 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 336 | CONFIG_BFIN_DCACHE=y | 337 | CONFIG_BFIN_DCACHE=y |
| 337 | # CONFIG_BFIN_DCACHE_BANKA is not set | 338 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 338 | # CONFIG_BFIN_ICACHE_LOCK is not set | 339 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 339 | CONFIG_BFIN_WB=y | 340 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 340 | # CONFIG_BFIN_WT is not set | 341 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 341 | CONFIG_L1_MAX_PIECE=16 | 342 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set |
| 343 | # CONFIG_BFIN_L2_ICACHEABLE is not set | ||
| 344 | # CONFIG_BFIN_L2_DCACHEABLE is not set | ||
| 345 | |||
| 346 | # | ||
| 347 | # Memory Protection Unit | ||
| 348 | # | ||
| 342 | # CONFIG_MPU is not set | 349 | # CONFIG_MPU is not set |
| 343 | 350 | ||
| 344 | # | 351 | # |
| @@ -428,11 +435,11 @@ CONFIG_IP_PNP=y · 83 unmodified lines | |||
| 428 | # CONFIG_INET_IPCOMP is not set | 435 | # CONFIG_INET_IPCOMP is not set |
| 429 | # CONFIG_INET_XFRM_TUNNEL is not set | 436 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 430 | # CONFIG_INET_TUNNEL is not set | 437 | # CONFIG_INET_TUNNEL is not set |
| 431 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 438 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 432 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 439 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 433 | CONFIG_INET_XFRM_MODE_BEET=y | 440 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 434 | # CONFIG_INET_LRO is not set | 441 | # CONFIG_INET_LRO is not set |
| 435 | CONFIG_INET_DIAG=y | 442 | # CONFIG_INET_DIAG is not set |
| 436 | CONFIG_INET_TCP_DIAG=y | 443 | CONFIG_INET_TCP_DIAG=y |
| 437 | # CONFIG_TCP_CONG_ADVANCED is not set | 444 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 438 | CONFIG_TCP_CONG_CUBIC=y | 445 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -1334,7 +1341,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 895 unmodified lines | |||
| 1334 | CONFIG_DEBUG_FS=y | 1341 | CONFIG_DEBUG_FS=y |
| 1335 | # CONFIG_HEADERS_CHECK is not set | 1342 | # CONFIG_HEADERS_CHECK is not set |
| 1336 | # CONFIG_DEBUG_KERNEL is not set | 1343 | # CONFIG_DEBUG_KERNEL is not set |
| 1337 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1344 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1338 | # CONFIG_SAMPLES is not set | 1345 | # CONFIG_SAMPLES is not set |
| 1339 | CONFIG_DEBUG_MMRS=y | 1346 | CONFIG_DEBUG_MMRS=y |
| 1340 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 1347 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| @@ -308,12 +308,19 @@ CONFIG_DMA_UNCACHED_1M=y · 307 unmodified lines | |||
| 308 | # Cache Support | 308 | # Cache Support |
| 309 | # | 309 | # |
| 310 | CONFIG_BFIN_ICACHE=y | 310 | CONFIG_BFIN_ICACHE=y |
| 311 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 311 | CONFIG_BFIN_DCACHE=y | 312 | CONFIG_BFIN_DCACHE=y |
| 312 | # CONFIG_BFIN_DCACHE_BANKA is not set | 313 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 313 | # CONFIG_BFIN_ICACHE_LOCK is not set | 314 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 314 | CONFIG_BFIN_WB=y | 315 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 315 | # CONFIG_BFIN_WT is not set | 316 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 316 | CONFIG_L1_MAX_PIECE=16 | 317 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set |
| 318 | # CONFIG_BFIN_L2_ICACHEABLE is not set | ||
| 319 | # CONFIG_BFIN_L2_DCACHEABLE is not set | ||
| 320 | |||
| 321 | # | ||
| 322 | # Memory Protection Unit | ||
| 323 | # | ||
| 317 | # CONFIG_MPU is not set | 324 | # CONFIG_MPU is not set |
| 318 | 325 | ||
| 319 | # | 326 | # |
| @@ -395,11 +402,11 @@ CONFIG_IP_FIB_HASH=y · 75 unmodified lines | |||
| 395 | # CONFIG_INET_IPCOMP is not set | 402 | # CONFIG_INET_IPCOMP is not set |
| 396 | # CONFIG_INET_XFRM_TUNNEL is not set | 403 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 397 | # CONFIG_INET_TUNNEL is not set | 404 | # CONFIG_INET_TUNNEL is not set |
| 398 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 405 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 399 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 406 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 400 | CONFIG_INET_XFRM_MODE_BEET=y | 407 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 401 | # CONFIG_INET_LRO is not set | 408 | # CONFIG_INET_LRO is not set |
| 402 | CONFIG_INET_DIAG=y | 409 | # CONFIG_INET_DIAG is not set |
| 403 | CONFIG_INET_TCP_DIAG=y | 410 | CONFIG_INET_TCP_DIAG=y |
| 404 | # CONFIG_TCP_CONG_ADVANCED is not set | 411 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 405 | CONFIG_TCP_CONG_CUBIC=y | 412 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -837,7 +844,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 431 unmodified lines | |||
| 837 | CONFIG_DEBUG_FS=y | 844 | CONFIG_DEBUG_FS=y |
| 838 | # CONFIG_HEADERS_CHECK is not set | 845 | # CONFIG_HEADERS_CHECK is not set |
| 839 | # CONFIG_DEBUG_KERNEL is not set | 846 | # CONFIG_DEBUG_KERNEL is not set |
| 840 | # CONFIG_DEBUG_BUGVERBOSE is not set | 847 | CONFIG_DEBUG_BUGVERBOSE=y |
| 841 | # CONFIG_SAMPLES is not set | 848 | # CONFIG_SAMPLES is not set |
| 842 | CONFIG_DEBUG_MMRS=y | 849 | CONFIG_DEBUG_MMRS=y |
| 843 | CONFIG_DEBUG_HUNT_FOR_ZERO=y | 850 | CONFIG_DEBUG_HUNT_FOR_ZERO=y |
| @@ -258,12 +258,18 @@ CONFIG_DMA_UNCACHED_1M=y · 257 unmodified lines | |||
| 258 | # Cache Support | 258 | # Cache Support |
| 259 | # | 259 | # |
| 260 | CONFIG_BFIN_ICACHE=y | 260 | CONFIG_BFIN_ICACHE=y |
| 261 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 261 | CONFIG_BFIN_DCACHE=y | 262 | CONFIG_BFIN_DCACHE=y |
| 262 | # CONFIG_BFIN_DCACHE_BANKA is not set | 263 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 263 | CONFIG_BFIN_ICACHE_LOCK=y | 264 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 264 | CONFIG_BFIN_WB=y | 265 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 265 | # CONFIG_BFIN_WT is not set | 266 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 266 | CONFIG_L1_MAX_PIECE=16 | 267 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set |
| 268 | |||
| 269 | # | ||
| 270 | # Memory Protection Unit | ||
| 271 | # | ||
| 272 | # CONFIG_MPU is not set | ||
| 267 | 273 | ||
| 268 | # | 274 | # |
| 269 | # Asynchonous Memory Configuration | 275 | # Asynchonous Memory Configuration |
| @@ -295,11 +295,17 @@ CONFIG_DMA_UNCACHED_1M=y · 294 unmodified lines | |||
| 295 | # Cache Support | 295 | # Cache Support |
| 296 | # | 296 | # |
| 297 | CONFIG_BFIN_ICACHE=y | 297 | CONFIG_BFIN_ICACHE=y |
| 298 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 298 | CONFIG_BFIN_DCACHE=y | 299 | CONFIG_BFIN_DCACHE=y |
| 299 | # CONFIG_BFIN_DCACHE_BANKA is not set | 300 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 300 | # CONFIG_BFIN_ICACHE_LOCK is not set | 301 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 301 | CONFIG_BFIN_WB=y | 302 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 302 | # CONFIG_BFIN_WT is not set | 303 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 304 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set | ||
| 305 | |||
| 306 | # | ||
| 307 | # Memory Protection Unit | ||
| 308 | # | ||
| 303 | # CONFIG_MPU is not set | 309 | # CONFIG_MPU is not set |
| 304 | 310 | ||
| 305 | # | 311 | # |
| @@ -382,11 +388,11 @@ CONFIG_IP_PNP=y · 76 unmodified lines | |||
| 382 | # CONFIG_INET_IPCOMP is not set | 388 | # CONFIG_INET_IPCOMP is not set |
| 383 | # CONFIG_INET_XFRM_TUNNEL is not set | 389 | # CONFIG_INET_XFRM_TUNNEL is not set |
| 384 | # CONFIG_INET_TUNNEL is not set | 390 | # CONFIG_INET_TUNNEL is not set |
| 385 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | 391 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set |
| 386 | CONFIG_INET_XFRM_MODE_TUNNEL=y | 392 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set |
| 387 | CONFIG_INET_XFRM_MODE_BEET=y | 393 | # CONFIG_INET_XFRM_MODE_BEET is not set |
| 388 | # CONFIG_INET_LRO is not set | 394 | # CONFIG_INET_LRO is not set |
| 389 | CONFIG_INET_DIAG=y | 395 | # CONFIG_INET_DIAG is not set |
| 390 | CONFIG_INET_TCP_DIAG=y | 396 | CONFIG_INET_TCP_DIAG=y |
| 391 | # CONFIG_TCP_CONG_ADVANCED is not set | 397 | # CONFIG_TCP_CONG_ADVANCED is not set |
| 392 | CONFIG_TCP_CONG_CUBIC=y | 398 | CONFIG_TCP_CONG_CUBIC=y |
| @@ -279,12 +279,18 @@ CONFIG_DMA_UNCACHED_2M=y · 278 unmodified lines | |||
| 279 | # Cache Support | 279 | # Cache Support |
| 280 | # | 280 | # |
| 281 | CONFIG_BFIN_ICACHE=y | 281 | CONFIG_BFIN_ICACHE=y |
| 282 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 282 | CONFIG_BFIN_DCACHE=y | 283 | CONFIG_BFIN_DCACHE=y |
| 283 | # CONFIG_BFIN_DCACHE_BANKA is not set | 284 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 284 | # CONFIG_BFIN_ICACHE_LOCK is not set | 285 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 285 | CONFIG_BFIN_WB=y | 286 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 286 | # CONFIG_BFIN_WT is not set | 287 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 287 | CONFIG_L1_MAX_PIECE=16 | 288 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set |
| 289 | |||
| 290 | # | ||
| 291 | # Memory Protection Unit | ||
| 292 | # | ||
| 293 | # CONFIG_MPU is not set | ||
| 288 | 294 | ||
| 289 | # | 295 | # |
| 290 | # Asynchonous Memory Configuration | 296 | # Asynchonous Memory Configuration |
| @@ -287,11 +287,17 @@ CONFIG_DMA_UNCACHED_1M=y · 286 unmodified lines | |||
| 287 | # Cache Support | 287 | # Cache Support |
| 288 | # | 288 | # |
| 289 | CONFIG_BFIN_ICACHE=y | 289 | CONFIG_BFIN_ICACHE=y |
| 290 | # CONFIG_BFIN_ICACHE_LOCK is not set | ||
| 290 | CONFIG_BFIN_DCACHE=y | 291 | CONFIG_BFIN_DCACHE=y |
| 291 | # CONFIG_BFIN_DCACHE_BANKA is not set | 292 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 292 | # CONFIG_BFIN_ICACHE_LOCK is not set | 293 | CONFIG_BFIN_EXTMEM_ICACHEABLE=y |
| 293 | CONFIG_BFIN_WB=y | 294 | CONFIG_BFIN_EXTMEM_DCACHEABLE=y |
| 294 | # CONFIG_BFIN_WT is not set | 295 | CONFIG_BFIN_EXTMEM_WRITEBACK=y |
| 296 | # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set | ||
| 297 | |||
| 298 | # | ||
| 299 | # Memory Protection Unit | ||
| 300 | # | ||
| 295 | # CONFIG_MPU is not set | 301 | # CONFIG_MPU is not set |
| 296 | 302 | ||
| 297 | # | 303 | # |
| @@ -709,7 +715,7 @@ CONFIG_FRAME_WARN=1024 · 411 unmodified lines | |||
| 709 | CONFIG_DEBUG_FS=y | 715 | CONFIG_DEBUG_FS=y |
| 710 | # CONFIG_HEADERS_CHECK is not set | 716 | # CONFIG_HEADERS_CHECK is not set |
| 711 | # CONFIG_DEBUG_KERNEL is not set | 717 | # CONFIG_DEBUG_KERNEL is not set |
| 712 | # CONFIG_DEBUG_BUGVERBOSE is not set | 718 | CONFIG_DEBUG_BUGVERBOSE=y |
| 713 | # CONFIG_DEBUG_MEMORY_INIT is not set | 719 | # CONFIG_DEBUG_MEMORY_INIT is not set |
| 714 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 720 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 715 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | 721 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set |
| @@ -86,6 +86,7 @@ static inline void CSYNC(void) · 85 unmodified lines | |||
| 86 | 86 | ||
| 87 | #endif /* __ASSEMBLY__ */ | 87 | #endif /* __ASSEMBLY__ */ |
| 88 | 88 | ||
| 89 | #include <asm/mem_map.h> | ||
| 89 | #include <mach/blackfin.h> | 90 | #include <mach/blackfin.h> |
| 90 | #include <asm/bfin-global.h> | 91 | #include <asm/bfin-global.h> |
| 91 | 92 | ||
| @@ -35,10 +35,10 @@ · 34 unmodified lines | |||
| 35 | 35 | ||
| 36 | #if defined(CONFIG_SMP) && \ | 36 | #if defined(CONFIG_SMP) && \ |
| 37 | !defined(CONFIG_BFIN_CACHE_COHERENT) | 37 | !defined(CONFIG_BFIN_CACHE_COHERENT) |
| 38 | # if defined(CONFIG_BFIN_ICACHE) | 38 | # if defined(CONFIG_BFIN_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE) |
| 39 | # define __ARCH_SYNC_CORE_ICACHE | 39 | # define __ARCH_SYNC_CORE_ICACHE |
| 40 | # endif | 40 | # endif |
| 41 | # if defined(CONFIG_BFIN_DCACHE) | 41 | # if defined(CONFIG_BFIN_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE) |
| 42 | # define __ARCH_SYNC_CORE_DCACHE | 42 | # define __ARCH_SYNC_CORE_DCACHE |
| 43 | # endif | 43 | # endif |
| 44 | #ifndef __ASSEMBLY__ | 44 | #ifndef __ASSEMBLY__ |
| @@ -56,7 +56,7 @@ extern void blackfin_invalidate_entire_icache(void); · 55 unmodified lines | |||
| 56 | 56 | ||
| 57 | static inline void flush_icache_range(unsigned start, unsigned end) | 57 | static inline void flush_icache_range(unsigned start, unsigned end) |
| 58 | { | 58 | { |
| 59 | #if defined(CONFIG_BFIN_WB) | 59 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
| 60 | blackfin_dcache_flush_range(start, end); | 60 | blackfin_dcache_flush_range(start, end); |
| 61 | #endif | 61 | #endif |
| 62 | 62 | ||
| @@ -87,9 +87,9 @@ do { memcpy(dst, src, len); \ · 24 unmodified lines | |||
| 87 | #else | 87 | #else |
| 88 | # define invalidate_dcache_range(start,end) do { } while (0) | 88 | # define invalidate_dcache_range(start,end) do { } while (0) |
| 89 | #endif | 89 | #endif |
| 90 | #if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB) | 90 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
| 91 | # define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) | 91 | # define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) |
| 92 | # define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) | 92 | # define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) |
| 93 | #else | 93 | #else |
| 94 | # define flush_dcache_range(start,end) do { } while (0) | 94 | # define flush_dcache_range(start,end) do { } while (0) |
| 95 | # define flush_dcache_page(page) do { } while (0) | 95 | # define flush_dcache_page(page) do { } while (0) |
| @@ -100,7 +100,7 @@ extern unsigned long reserved_mem_icache_on; · 4 unmodified lines | |||
| 100 | 100 | ||
| 101 | static inline int bfin_addr_dcacheable(unsigned long addr) | 101 | static inline int bfin_addr_dcacheable(unsigned long addr) |
| 102 | { | 102 | { |
| 103 | #ifdef CONFIG_BFIN_DCACHE | 103 | #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE |
| 104 | if (addr < (_ramend - DMA_UNCACHED_REGION)) | 104 | if (addr < (_ramend - DMA_UNCACHED_REGION)) |
| 105 | return 1; | 105 | return 1; |
| 106 | #endif | 106 | #endif |
| @@ -109,7 +109,7 @@ static inline int bfin_addr_dcacheable(unsigned long addr) · 2 unmodified lines | |||
| 109 | addr >= _ramend && addr < physical_mem_end) | 109 | addr >= _ramend && addr < physical_mem_end) |
| 110 | return 1; | 110 | return 1; |
| 111 | 111 | ||
| 112 | #ifndef CONFIG_BFIN_L2_NOT_CACHED | 112 | #ifdef CONFIG_BFIN_L2_DCACHEABLE |
| 113 | if (addr >= L2_START && addr < L2_START + L2_LENGTH) | 113 | if (addr >= L2_START && addr < L2_START + L2_LENGTH) |
| 114 | return 1; | 114 | return 1; |
| 115 | #endif | 115 | #endif |
| @@ -37,8 +37,6 @@ · 36 unmodified lines | |||
| 37 | #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) | 37 | #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) |
| 38 | #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) | 38 | #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) |
| 39 | 39 | ||
| 40 | /*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/ | ||
| 41 | |||
| 42 | #if ANOMALY_05000158 | 40 | #if ANOMALY_05000158 |
| 43 | #define ANOMALY_05000158_WORKAROUND 0x200 | 41 | #define ANOMALY_05000158_WORKAROUND 0x200 |
| 44 | #else | 42 | #else |
| @@ -47,10 +45,12 @@ · 2 unmodified lines | |||
| 47 | 45 | ||
| 48 | #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) | 46 | #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) |
| 49 | 47 | ||
| 50 | #ifdef CONFIG_BFIN_WB /*Write Back Policy */ | 48 | #ifdef CONFIG_BFIN_EXTMEM_WRITEBACK |
| 51 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) | 49 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) |
| 52 | #else /*Write Through */ | 50 | #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) |
| 53 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) | 51 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) |
| 52 | #else | ||
| 53 | #define SDRAM_DGENERIC (CPLB_COMMON) | ||
| 54 | #endif | 54 | #endif |
| 55 | 55 | ||
| 56 | #define SDRAM_DNON_CHBL (CPLB_COMMON) | 56 | #define SDRAM_DNON_CHBL (CPLB_COMMON) |
| @@ -61,21 +61,23 @@ · 4 unmodified lines | |||
| 61 | 61 | ||
| 62 | #ifdef CONFIG_SMP | 62 | #ifdef CONFIG_SMP |
| 63 | #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) | 63 | #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) |
| 64 | #define L2_IMEMORY (CPLB_COMMON) | 64 | #define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) |
| 65 | #define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON) | 65 | #define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB) |
| 66 | 66 | ||
| 67 | #else | 67 | #else |
| 68 | #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) | 68 | #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) |
| 69 | #define L2_IMEMORY (SDRAM_IGENERIC) | 69 | # if defined(CONFIG_BFIN_L2_ICACHEABLE) |
| 70 | 70 | # define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) | |
| 71 | # if defined(CONFIG_BFIN_L2_WB) | 71 | # else |
| 72 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON) | 72 | # define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) |
| 73 | # elif defined(CONFIG_BFIN_L2_WT) | 73 | # endif |
| 74 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) | 74 | |
| 75 | # elif defined(CONFIG_BFIN_L2_NOT_CACHED) | 75 | # if defined(CONFIG_BFIN_L2_WRITEBACK) |
| 76 | # define L2_DMEMORY (CPLB_COMMON) | 76 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB) |
| 77 | # elif defined(CONFIG_BFIN_L2_WRITETHROUGH) | ||
| 78 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB) | ||
| 77 | # else | 79 | # else |
| 78 | # define L2_DMEMORY (0) | 80 | # define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) |
| 79 | # endif | 81 | # endif |
| 80 | #endif /* CONFIG_SMP */ | 82 | #endif /* CONFIG_SMP */ |
| 81 | 83 | ||
| @@ -95,4 +95,17 @@ static inline void dma_sync_single_for_device(struct device *dev, · 94 unmodified lines | |||
| 95 | enum dma_data_direction dir) | 95 | enum dma_data_direction dir) |
| 96 | { | 96 | { |
| 97 | } | 97 | } |
| 98 | |||
| 99 | static inline void dma_sync_sg_for_cpu(struct device *dev, | ||
| 100 | struct scatterlist *sg, | ||
| 101 | int nents, enum dma_data_direction dir) | ||
| 102 | { | ||
| 103 | } | ||
| 104 | |||
| 105 | static inline void dma_sync_sg_for_device(struct device *dev, | ||
| 106 | struct scatterlist *sg, | ||
| 107 | int nents, enum dma_data_direction dir) | ||
| 108 | { | ||
| 109 | } | ||
| 110 | |||
| 98 | #endif /* _BLACKFIN_DMA_MAPPING_H */ | 111 | #endif /* _BLACKFIN_DMA_MAPPING_H */ |
| @@ -35,9 +35,9 @@ · 34 unmodified lines | |||
| 35 | #include <asm/atomic.h> | 35 | #include <asm/atomic.h> |
| 36 | #include <asm/traps.h> | 36 | #include <asm/traps.h> |
| 37 | 37 | ||
| 38 | #define IPIPE_ARCH_STRING "1.10-00" | 38 | #define IPIPE_ARCH_STRING "1.11-00" |
| 39 | #define IPIPE_MAJOR_NUMBER 1 | 39 | #define IPIPE_MAJOR_NUMBER 1 |
| 40 | #define IPIPE_MINOR_NUMBER 10 | 40 | #define IPIPE_MINOR_NUMBER 11 |
| 41 | #define IPIPE_PATCH_NUMBER 0 | 41 | #define IPIPE_PATCH_NUMBER 0 |
| 42 | 42 | ||
| 43 | #ifdef CONFIG_SMP | 43 | #ifdef CONFIG_SMP |
| @@ -207,7 +207,7 @@ void ipipe_init_irq_threads(void); · 163 unmodified lines | |||
| 207 | 207 | ||
| 208 | int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); | 208 | int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); |
| 209 | 209 | ||
| 210 | #ifdef CONFIG_GENERIC_CLOCKEVENTS | 210 | #ifdef CONFIG_TICKSOURCE_CORETMR |
| 211 | #define IRQ_SYSTMR IRQ_CORETMR | 211 | #define IRQ_SYSTMR IRQ_CORETMR |
| 212 | #define IRQ_PRIOTMR IRQ_CORETMR | 212 | #define IRQ_PRIOTMR IRQ_CORETMR |
| 213 | #else | 213 | #else |
| @@ -240,8 +240,13 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); · 26 unmodified lines | |||
| 240 | #define ipipe_init_irq_threads() do { } while (0) | 240 | #define ipipe_init_irq_threads() do { } while (0) |
| 241 | #define ipipe_start_irq_thread(irq, desc) 0 | 241 | #define ipipe_start_irq_thread(irq, desc) 0 |
| 242 | 242 | ||
| 243 | #ifndef CONFIG_TICKSOURCE_GPTMR0 | ||
| 243 | #define IRQ_SYSTMR IRQ_CORETMR | 244 | #define IRQ_SYSTMR IRQ_CORETMR |
| 244 | #define IRQ_PRIOTMR IRQ_CORETMR | 245 | #define IRQ_PRIOTMR IRQ_CORETMR |
| 246 | #else | ||
| 247 | #define IRQ_SYSTMR IRQ_TIMER0 | ||
| 248 | #define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 | ||
| 249 | #endif | ||
| 245 | 250 | ||
| 246 | #define __ipipe_root_tick_p(regs) 1 | 251 | #define __ipipe_root_tick_p(regs) 1 |
| 247 | 252 | ||
| @@ -51,23 +51,23 @@ · 50 unmodified lines | |||
| 51 | 51 | ||
| 52 | extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ | 52 | extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ |
| 53 | 53 | ||
| 54 | static inline void __ipipe_stall_root(void) | 54 | #define __ipipe_stall_root() \ |
| 55 | { | 55 | do { \ |
| 56 | volatile unsigned long *p = &__ipipe_root_status; | 56 | volatile unsigned long *p = &__ipipe_root_status; \ |
| 57 | set_bit(0, p); | 57 | set_bit(0, p); \ |
| 58 | } | 58 | } while (0) |
| 59 | 59 | ||
| 60 | static inline unsigned long __ipipe_test_and_stall_root(void) | 60 | #define __ipipe_test_and_stall_root() \ |
| 61 | { | 61 | ({ \ |
| 62 | volatile unsigned long *p = &__ipipe_root_status; | 62 | volatile unsigned long *p = &__ipipe_root_status; \ |
| 63 | return test_and_set_bit(0, p); | 63 | test_and_set_bit(0, p); \ |
| 64 | } | 64 | }) |
| 65 | 65 | ||
| 66 | static inline unsigned long __ipipe_test_root(void) | 66 | #define __ipipe_test_root() \ |
| 67 | { | 67 | ({ \ |
| 68 | const unsigned long *p = &__ipipe_root_status; | 68 | const unsigned long *p = &__ipipe_root_status; \ |
| 69 | return test_bit(0, p); | 69 | test_bit(0, p); \ |
| 70 | } | 70 | }) |
| 71 | 71 | ||
| 72 | #endif /* !__ASSEMBLY__ */ | 72 | #endif /* !__ASSEMBLY__ */ |
| 73 | 73 | ||
| @@ -22,13 +22,6 @@ · 21 unmodified lines | |||
| 22 | /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ | 22 | /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ |
| 23 | #include <mach/irq.h> | 23 | #include <mach/irq.h> |
| 24 | 24 | ||
| 25 | /* Xenomai IPIPE helpers */ | ||
| 26 | #define local_irq_restore_hw(x) local_irq_restore(x) | ||
| 27 | #define local_irq_save_hw(x) local_irq_save(x) | ||
| 28 | #define local_irq_enable_hw(x) local_irq_enable(x) | ||
| 29 | #define local_irq_disable_hw(x) local_irq_disable(x) | ||
| 30 | #define irqs_disabled_hw(x) irqs_disabled(x) | ||
| 31 | |||
| 32 | #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) | 25 | #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) |
| 33 | # define NOP_PAD_ANOMALY_05000244 "nop; nop;" | 26 | # define NOP_PAD_ANOMALY_05000244 "nop; nop;" |
| 34 | #else | 27 | #else |
| @@ -31,6 +31,150 @@ static inline unsigned long bfin_cli(void) · 30 unmodified lines | |||
| 31 | return flags; | 31 | return flags; |
| 32 | } | 32 | } |
| 33 | 33 | ||
| 34 | #ifdef CONFIG_IPIPE | ||
| 35 | |||
| 36 | #include <linux/ipipe_base.h> | ||
| 37 | #include <linux/ipipe_trace.h> | ||
| 38 | |||
| 39 | #ifdef CONFIG_DEBUG_HWERR | ||
| 40 | # define bfin_no_irqs 0x3f | ||
| 41 | #else | ||
| 42 | # define bfin_no_irqs 0x1f | ||
| 43 | #endif | ||
| 44 | |||
| 45 | #define raw_local_irq_disable() \ | ||
| 46 | do { \ | ||
| 47 | ipipe_check_context(ipipe_root_domain); \ | ||
| 48 | __ipipe_stall_root(); \ | ||
| 49 | barrier(); \ | ||
| 50 | } while (0) | ||
| 51 | |||
| 52 | static inline void raw_local_irq_enable(void) | ||
| 53 | { | ||
| 54 | barrier(); | ||
| 55 | ipipe_check_context(ipipe_root_domain); | ||
| 56 | __ipipe_unstall_root(); | ||
| 57 | } | ||
| 58 | |||
| 59 | #define raw_local_save_flags_ptr(x) \ | ||
| 60 | do { \ | ||
| 61 | *(x) = __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; \ | ||
| 62 | } while (0) | ||
| 63 | |||
| 64 | #define raw_local_save_flags(x) raw_local_save_flags_ptr(&(x)) | ||
| 65 | |||
| 66 | #define raw_irqs_disabled_flags(x) ((x) == bfin_no_irqs) | ||
| 67 | |||
| 68 | #define raw_local_irq_save_ptr(x) \ | ||
| 69 | do { \ | ||
| 70 | *(x) = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; \ | ||
| 71 | barrier(); \ | ||
| 72 | } while (0) | ||
| 73 | |||
| 74 | #define raw_local_irq_save(x) \ | ||
| 75 | do { \ | ||
| 76 | ipipe_check_context(ipipe_root_domain); \ | ||
| 77 | raw_local_irq_save_ptr(&(x)); \ | ||
| 78 | } while (0) | ||
| 79 | |||
| 80 | static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real) | ||
| 81 | { | ||
| 82 | /* | ||
| 83 | * Merge virtual and real interrupt mask bits into a single | ||
| 84 | * 32bit word. | ||
| 85 | */ | ||
| 86 | return (real & ~(1 << 31)) | ((virt != 0) << 31); | ||
| 87 | } | ||
| 88 | |||
| 89 | static inline int raw_demangle_irq_bits(unsigned long *x) | ||
| 90 | { | ||
| 91 | int virt = (*x & (1 << 31)) != 0; | ||
| 92 | *x &= ~(1L << 31); | ||
| 93 | return virt; | ||
| 94 | } | ||
| 95 | |||
| 96 | static inline void local_irq_disable_hw_notrace(void) | ||
| 97 | { | ||
| 98 | bfin_cli(); | ||
| 99 | } | ||
| 100 | |||
| 101 | static inline void local_irq_enable_hw_notrace(void) | ||
| 102 | { | ||
| 103 | bfin_sti(bfin_irq_flags); | ||
| 104 | } | ||
| 105 | |||
| 106 | #define local_save_flags_hw(flags) \ | ||
| 107 | do { \ | ||
| 108 | (flags) = bfin_read_IMASK(); \ | ||
| 109 | } while (0) | ||
| 110 | |||
| 111 | #define irqs_disabled_flags_hw(flags) (((flags) & ~0x3f) == 0) | ||
| 112 | |||
| 113 | #define irqs_disabled_hw() \ | ||
| 114 | ({ \ | ||
| 115 | unsigned long flags; \ | ||
| 116 | local_save_flags_hw(flags); \ | ||
| 117 | irqs_disabled_flags_hw(flags); \ | ||
| 118 | }) | ||
| 119 | |||
| 120 | static inline void local_irq_save_ptr_hw(unsigned long *flags) | ||
| 121 | { | ||
| 122 | *flags = bfin_cli(); | ||
| 123 | #ifdef CONFIG_DEBUG_HWERR | ||
| 124 | bfin_sti(0x3f); | ||
| 125 | #endif | ||
| 126 | } | ||
| 127 | |||
| 128 | #define local_irq_save_hw_notrace(flags) \ | ||
| 129 | do { \ | ||
| 130 | local_irq_save_ptr_hw(&(flags)); \ | ||
| 131 | } while (0) | ||
| 132 | |||
| 133 | static inline void local_irq_restore_hw_notrace(unsigned long flags) | ||
| 134 | { | ||
| 135 | if (!irqs_disabled_flags_hw(flags)) | ||
| 136 | local_irq_enable_hw_notrace(); | ||
| 137 | } | ||
| 138 | |||
| 139 | #ifdef CONFIG_IPIPE_TRACE_IRQSOFF | ||
| 140 | # define local_irq_disable_hw() \ | ||
| 141 | do { \ | ||
| 142 | if (!irqs_disabled_hw()) { \ | ||
| 143 | local_irq_disable_hw_notrace(); \ | ||
| 144 | ipipe_trace_begin(0x80000000); \ | ||
| 145 | } \ | ||
| 146 | } while (0) | ||
| 147 | # define local_irq_enable_hw() \ | ||
| 148 | do { \ | ||
| 149 | if (irqs_disabled_hw()) { \ | ||
| 150 | ipipe_trace_end(0x80000000); \ | ||
| 151 | local_irq_enable_hw_notrace(); \ | ||
| 152 | } \ | ||
| 153 | } while (0) | ||
| 154 | # define local_irq_save_hw(flags) \ | ||
| 155 | do { \ | ||
| 156 | local_save_flags_hw(flags); \ | ||
| 157 | if (!irqs_disabled_flags_hw(flags)) { \ | ||
| 158 | local_irq_disable_hw_notrace(); \ | ||
| 159 | ipipe_trace_begin(0x80000001); \ | ||
| 160 | } \ | ||
| 161 | } while (0) | ||
| 162 | # define local_irq_restore_hw(flags) \ | ||
| 163 | do { \ | ||
| 164 | if (!irqs_disabled_flags_hw(flags)) { \ | ||
| 165 | ipipe_trace_end(0x80000001); \ | ||
| 166 | local_irq_enable_hw_notrace(); \ | ||
| 167 | } \ | ||
| 168 | } while (0) | ||
| 169 | #else /* !CONFIG_IPIPE_TRACE_IRQSOFF */ | ||
| 170 | # define local_irq_disable_hw() local_irq_disable_hw_notrace() | ||
| 171 | # define local_irq_enable_hw() local_irq_enable_hw_notrace() | ||
| 172 | # define local_irq_save_hw(flags) local_irq_save_hw_notrace(flags) | ||
| 173 | # define local_irq_restore_hw(flags) local_irq_restore_hw_notrace(flags) | ||
| 174 | #endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */ | ||
| 175 | |||
| 176 | #else /* CONFIG_IPIPE */ | ||
| 177 | |||
| 34 | static inline void raw_local_irq_disable(void) | 178 | static inline void raw_local_irq_disable(void) |
| 35 | { | 179 | { |
| 36 | bfin_cli(); | 180 | bfin_cli(); |
| @@ -44,12 +188,6 @@ static inline void raw_local_irq_enable(void) · 7 unmodified lines | |||
| 44 | 188 | ||
| 45 | #define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0) | 189 | #define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0) |
| 46 | 190 | ||
| 47 | static inline void raw_local_irq_restore(unsigned long flags) | ||
| 48 | { | ||
| 49 | if (!raw_irqs_disabled_flags(flags)) | ||
| 50 | raw_local_irq_enable(); | ||
| 51 | } | ||
| 52 | |||
| 53 | static inline unsigned long __raw_local_irq_save(void) | 191 | static inline unsigned long __raw_local_irq_save(void) |
| 54 | { | 192 | { |
| 55 | unsigned long flags = bfin_cli(); | 193 | unsigned long flags = bfin_cli(); |
| @@ -60,4 +198,18 @@ static inline unsigned long __raw_local_irq_save(void) · 4 unmodified lines | |||
| 60 | } | 198 | } |
| 61 | #define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0) | 199 | #define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0) |
| 62 | 200 | ||
| 201 | #define local_irq_save_hw(flags) raw_local_irq_save(flags) | ||
| 202 | #define local_irq_restore_hw(flags) raw_local_irq_restore(flags) | ||
| 203 | #define local_irq_enable_hw() raw_local_irq_enable() | ||
| 204 | #define local_irq_disable_hw() raw_local_irq_disable() | ||
| 205 | #define irqs_disabled_hw() irqs_disabled() | ||
| 206 | |||
| 207 | #endif /* !CONFIG_IPIPE */ | ||
| 208 | |||
| 209 | static inline void raw_local_irq_restore(unsigned long flags) | ||
| 210 | { | ||
| 211 | if (!raw_irqs_disabled_flags(flags)) | ||
| 212 | raw_local_irq_enable(); | ||
| 213 | } | ||
| 214 | |||
| 63 | #endif | 215 | #endif |
| @@ -59,7 +59,7 @@ · 58 unmodified lines | |||
| 59 | #define SDRAM_tRP TRP_1 | 59 | #define SDRAM_tRP TRP_1 |
| 60 | #define SDRAM_tRP_num 1 | 60 | #define SDRAM_tRP_num 1 |
| 61 | #define SDRAM_tRAS TRAS_4 | 61 | #define SDRAM_tRAS TRAS_4 |
| 62 | #define SDRAM_tRAS_num 3 | 62 | #define SDRAM_tRAS_num 4 |
| 63 | #define SDRAM_tRCD TRCD_1 | 63 | #define SDRAM_tRCD TRCD_1 |
| 64 | #define SDRAM_tWR TWR_2 | 64 | #define SDRAM_tWR TWR_2 |
| 65 | #endif | 65 | #endif |
| @@ -89,6 +89,85 @@ · 23 unmodified lines | |||
| 89 | #endif | 89 | #endif |
| 90 | #endif | 90 | #endif |
| 91 | 91 | ||
| 92 | /* | ||
| 93 | * The BF526-EZ-Board changed SDRAM chips between revisions, | ||
| 94 | * so we use below timings to accommodate both. | ||
| 95 | */ | ||
| 96 | #if defined(CONFIG_MEM_MT48H32M16LFCJ_75) | ||
| 97 | #if (CONFIG_SCLK_HZ > 119402985) | ||
| 98 | #define SDRAM_tRP TRP_2 | ||
| 99 | #define SDRAM_tRP_num 2 | ||
| 100 | #define SDRAM_tRAS TRAS_8 | ||
| 101 | #define SDRAM_tRAS_num 8 | ||
| 102 | #define SDRAM_tRCD TRCD_2 | ||
| 103 | #define SDRAM_tWR TWR_2 | ||
| 104 | #endif | ||
| 105 | #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) | ||
| 106 | #define SDRAM_tRP TRP_2 | ||
| 107 | #define SDRAM_tRP_num 2 | ||
| 108 | #define SDRAM_tRAS TRAS_7 | ||
| 109 | #define SDRAM_tRAS_num 7 | ||
| 110 | #define SDRAM_tRCD TRCD_2 | ||
| 111 | #define SDRAM_tWR TWR_2 | ||
| 112 | #endif | ||
| 113 | #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) | ||
| 114 | #define SDRAM_tRP TRP_2 | ||
| 115 | #define SDRAM_tRP_num 2 | ||
| 116 | #define SDRAM_tRAS TRAS_6 | ||
| 117 | #define SDRAM_tRAS_num 6 | ||
| 118 | #define SDRAM_tRCD TRCD_2 | ||
| 119 | #define SDRAM_tWR TWR_2 | ||
| 120 | #endif | ||
| 121 | #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) | ||
| 122 | #define SDRAM_tRP TRP_2 | ||
| 123 | #define SDRAM_tRP_num 2 | ||
| 124 | #define SDRAM_tRAS TRAS_5 | ||
| 125 | #define SDRAM_tRAS_num 5 | ||
| 126 | #define SDRAM_tRCD TRCD_2 | ||
| 127 | #define SDRAM_tWR TWR_2 | ||
| 128 | #endif | ||
| 129 | #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) | ||
| 130 | #define SDRAM_tRP TRP_2 | ||
| 131 | #define SDRAM_tRP_num 2 | ||
| 132 | #define SDRAM_tRAS TRAS_4 | ||
| 133 | #define SDRAM_tRAS_num 4 | ||
| 134 | #define SDRAM_tRCD TRCD_2 | ||
| 135 | #define SDRAM_tWR TWR_2 | ||
| 136 | #endif | ||
| 137 | #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) | ||
| 138 | #define SDRAM_tRP TRP_2 | ||
| 139 | #define SDRAM_tRP_num 2 | ||
| 140 | #define SDRAM_tRAS TRAS_4 | ||
| 141 | #define SDRAM_tRAS_num 4 | ||
| 142 | #define SDRAM_tRCD TRCD_1 | ||
| 143 | #define SDRAM_tWR TWR_2 | ||
| 144 | #endif | ||
| 145 | #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) | ||
| 146 | #define SDRAM_tRP TRP_2 | ||
| 147 | #define SDRAM_tRP_num 2 | ||
| 148 | #define SDRAM_tRAS TRAS_3 | ||
| 149 | #define SDRAM_tRAS_num 3 | ||
| 150 | #define SDRAM_tRCD TRCD_1 | ||
| 151 | #define SDRAM_tWR TWR_2 | ||
| 152 | #endif | ||
| 153 | #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) | ||
| 154 | #define SDRAM_tRP TRP_1 | ||
| 155 | #define SDRAM_tRP_num 1 | ||
| 156 | #define SDRAM_tRAS TRAS_3 | ||
| 157 | #define SDRAM_tRAS_num 3 | ||
| 158 | #define SDRAM_tRCD TRCD_1 | ||
| 159 | #define SDRAM_tWR TWR_2 | ||
| 160 | #endif | ||
| 161 | #if (CONFIG_SCLK_HZ <= 29850746) | ||
| 162 | #define SDRAM_tRP TRP_1 | ||
| 163 | #define SDRAM_tRP_num 1 | ||
| 164 | #define SDRAM_tRAS TRAS_2 | ||
| 165 | #define SDRAM_tRAS_num 2 | ||
| 166 | #define SDRAM_tRCD TRCD_1 | ||
| 167 | #define SDRAM_tWR TWR_2 | ||
| 168 | #endif | ||
| 169 | #endif | ||
| 170 | |||
| 92 | #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ | 171 | #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ |
| 93 | defined(CONFIG_MEM_MT48LC8M32B2B5_7) | 172 | defined(CONFIG_MEM_MT48LC8M32B2B5_7) |
| 94 | /*SDRAM INFORMATION: */ | 173 | /*SDRAM INFORMATION: */ |
| @@ -109,6 +188,13 @@ · 14 unmodified lines | |||
| 109 | #define SDRAM_CL CL_3 | 188 | #define SDRAM_CL CL_3 |
| 110 | #endif | 189 | #endif |
| 111 | 190 | ||
| 191 | #if defined(CONFIG_MEM_MT48H32M16LFCJ_75) | ||
| 192 | /*SDRAM INFORMATION: */ | ||
| 193 | #define SDRAM_Tref 64 /* Refresh period in milliseconds */ | ||
| 194 | #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ | ||
| 195 | #define SDRAM_CL CL_2 | ||
| 196 | #endif | ||
| 197 | |||
| 112 | 198 | ||
| 113 | #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC | 199 | #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC |
| 114 | /* Equation from section 17 (p17-46) of BF533 HRM */ | 200 | /* Equation from section 17 (p17-46) of BF533 HRM */ |
| @@ -1,87 +1,84 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * mem_map.h | 2 | * Common Blackfin memory map |
| 3 | * Common header file for blackfin family of processors. | ||
| 4 | * | 3 | * |
| 4 | * Copyright 2004-2009 Analog Devices Inc. | ||
| 5 | * Licensed under the GPL-2 or later. | ||
| 5 | */ | 6 | */ |
| 6 | 7 | ||
| 7 | #ifndef _MEM_MAP_H_ | 8 | #ifndef __BFIN_MEM_MAP_H__ |
| 8 | #define _MEM_MAP_H_ | 9 | #define __BFIN_MEM_MAP_H__ |
| 9 | 10 | ||
| 10 | #include <mach/mem_map.h> | 11 | #include <mach/mem_map.h> |
| 11 | 12 | ||
| 12 | #ifndef __ASSEMBLY__ | 13 | /* Every Blackfin so far has MMRs like this */ |
| 14 | #ifndef COREMMR_BASE | ||
| 15 | # define COREMMR_BASE 0xFFE00000 | ||
| 16 | #endif | ||
| 17 | #ifndef SYSMMR_BASE | ||
| 18 | # define SYSMMR_BASE 0xFFC00000 | ||
| 19 | #endif | ||
| 13 | 20 | ||
| 14 | #ifdef CONFIG_SMP | 21 | /* Every Blackfin so far has on-chip Scratch Pad SRAM like this */ |
| 15 | static inline ulong get_l1_scratch_start_cpu(int cpu) | 22 | #ifndef L1_SCRATCH_START |
| 16 | { | 23 | # define L1_SCRATCH_START 0xFFB00000 |
| 17 | return (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; | 24 | # define L1_SCRATCH_LENGTH 0x1000 |
| 18 | } | 25 | #endif |
| 19 | static inline ulong get_l1_code_start_cpu(int cpu) | ||
| 20 | { | ||
| 21 | return (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START; | ||
| 22 | } | ||
| 23 | static inline ulong get_l1_data_a_start_cpu(int cpu) | ||
| 24 | { | ||
| 25 | return (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; | ||
| 26 | } | ||
| 27 | static inline ulong get_l1_data_b_start_cpu(int cpu) | ||
| 28 | { | ||
| 29 | return (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; | ||
| 30 | } | ||
| 31 | 26 | ||
| 32 | static inline ulong get_l1_scratch_start(void) | 27 | /* Most parts lack on-chip L2 SRAM */ |
| 33 | { | 28 | #ifndef L2_START |
| 34 | return get_l1_scratch_start_cpu(blackfin_core_id()); | 29 | # define L2_START 0 |
| 35 | } | 30 | # define L2_LENGTH 0 |
| 36 | static inline ulong get_l1_code_start(void) | 31 | #endif |
| 37 | { | 32 | |
| 38 | return get_l1_code_start_cpu(blackfin_core_id()); | 33 | /* Most parts lack on-chip L1 ROM */ |
| 39 | } | 34 | #ifndef L1_ROM_START |
| 40 | static inline ulong get_l1_data_a_start(void) | 35 | # define L1_ROM_START 0 |
| 41 | { | 36 | # define L1_ROM_LENGTH 0 |
| 42 | return get_l1_data_a_start_cpu(blackfin_core_id()); | 37 | #endif |
| 43 | } | 38 | |
| 44 | static inline ulong get_l1_data_b_start(void) | 39 | /* Allow wonky SMP ports to override this */ |
| 45 | { | 40 | #ifndef GET_PDA_SAFE |
| 46 | return get_l1_data_b_start_cpu(blackfin_core_id()); | 41 | # define GET_PDA_SAFE(preg) \ |
| 47 | } | 42 | preg.l = _cpu_pda; \ |
| 43 | preg.h = _cpu_pda; | ||
| 44 | # define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 48 | 45 | ||
| 49 | #else /* !CONFIG_SMP */ | 46 | # ifndef __ASSEMBLY__ |
| 50 | 47 | ||
| 51 | static inline ulong get_l1_scratch_start_cpu(int cpu) | 48 | static inline unsigned long get_l1_scratch_start_cpu(int cpu) |
| 52 | { | 49 | { |
| 53 | return L1_SCRATCH_START; | 50 | return L1_SCRATCH_START; |
| 54 | } | 51 | } |
| 55 | static inline ulong get_l1_code_start_cpu(int cpu) | 52 | static inline unsigned long get_l1_code_start_cpu(int cpu) |
| 56 | { | 53 | { |
| 57 | return L1_CODE_START; | 54 | return L1_CODE_START; |
| 58 | } | 55 | } |
| 59 | static inline ulong get_l1_data_a_start_cpu(int cpu) | 56 | static inline unsigned long get_l1_data_a_start_cpu(int cpu) |
| 60 | { | 57 | { |
| 61 | return L1_DATA_A_START; | 58 | return L1_DATA_A_START; |
| 62 | } | 59 | } |
| 63 | static inline ulong get_l1_data_b_start_cpu(int cpu) | 60 | static inline unsigned long get_l1_data_b_start_cpu(int cpu) |
| 64 | { | 61 | { |
| 65 | return L1_DATA_B_START; | 62 | return L1_DATA_B_START; |
| 66 | } | 63 | } |
| 67 | static inline ulong get_l1_scratch_start(void) | 64 | static inline unsigned long get_l1_scratch_start(void) |
| 68 | { | 65 | { |
| 69 | return get_l1_scratch_start_cpu(0); | 66 | return get_l1_scratch_start_cpu(0); |
| 70 | } | 67 | } |
| 71 | static inline ulong get_l1_code_start(void) | 68 | static inline unsigned long get_l1_code_start(void) |
| 72 | { | 69 | { |
| 73 | return get_l1_code_start_cpu(0); | 70 | return get_l1_code_start_cpu(0); |
| 74 | } | 71 | } |
| 75 | static inline ulong get_l1_data_a_start(void) | 72 | static inline unsigned long get_l1_data_a_start(void) |
| 76 | { | 73 | { |
| 77 | return get_l1_data_a_start_cpu(0); | 74 | return get_l1_data_a_start_cpu(0); |
| 78 | } | 75 | } |
| 79 | static inline ulong get_l1_data_b_start(void) | 76 | static inline unsigned long get_l1_data_b_start(void) |
| 80 | { | 77 | { |
| 81 | return get_l1_data_b_start_cpu(0); | 78 | return get_l1_data_b_start_cpu(0); |
| 82 | } | 79 | } |
| 83 | 80 | ||
| 84 | #endif /* CONFIG_SMP */ | 81 | # endif /* __ASSEMBLY__ */ |
| 85 | #endif /* __ASSEMBLY__ */ | 82 | #endif /* !GET_PDA_SAFE */ |
| 86 | 83 | ||
| 87 | #endif /* _MEM_MAP_H_ */ | 84 | #endif |
| @@ -135,11 +135,13 @@ struct __xchg_dummy { · 134 unmodified lines | |||
| 135 | }; | 135 | }; |
| 136 | #define __xg(x) ((volatile struct __xchg_dummy *)(x)) | 136 | #define __xg(x) ((volatile struct __xchg_dummy *)(x)) |
| 137 | 137 | ||
| 138 | #include <mach/blackfin.h> | ||
| 139 | |||
| 138 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, | 140 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, |
| 139 | int size) | 141 | int size) |
| 140 | { | 142 | { |
| 141 | unsigned long tmp = 0; | 143 | unsigned long tmp = 0; |
| 142 | unsigned long flags = 0; | 144 | unsigned long flags; |
| 143 | 145 | ||
| 144 | local_irq_save_hw(flags); | 146 | local_irq_save_hw(flags); |
| 145 | 147 | ||
| @@ -111,9 +111,7 @@ · 110 unmodified lines | |||
| 111 | level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" | 111 | level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" |
| 112 | #define EXC_0x2A(level) \ | 112 | #define EXC_0x2A(level) \ |
| 113 | "Instruction fetch misaligned address violation\n" \ | 113 | "Instruction fetch misaligned address violation\n" \ |
| 114 | level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ | 114 | level " - Attempted misaligned instruction cache fetch.\n" |
| 115 | level " exception, the return address provided in RETX is the destination address which is\n" \ | ||
| 116 | level " misaligned, rather than the address of the offending instruction.\n" | ||
| 117 | #define EXC_0x2B(level) \ | 115 | #define EXC_0x2B(level) \ |
| 118 | "CPLB protection violation\n" \ | 116 | "CPLB protection violation\n" \ |
| 119 | level " - Illegal instruction fetch access (memory protection violation).\n" | 117 | level " - Illegal instruction fetch access (memory protection violation).\n" |
| @@ -265,4 +265,26 @@ __clear_user(void *to, unsigned long n) · 264 unmodified lines | |||
| 265 | 265 | ||
| 266 | #define clear_user(to, n) __clear_user(to, n) | 266 | #define clear_user(to, n) __clear_user(to, n) |
| 267 | 267 | ||
| 268 | /* How to interpret these return values: | ||
| 269 | * CORE: can be accessed by core load or dma memcpy | ||
| 270 | * CORE_ONLY: can only be accessed by core load | ||
| 271 | * DMA: can only be accessed by dma memcpy | ||
| 272 | * IDMA: can only be accessed by interprocessor dma memcpy (BF561) | ||
| 273 | * ITEST: can be accessed by isram memcpy or dma memcpy | ||
| 274 | */ | ||
| 275 | enum { | ||
| 276 | BFIN_MEM_ACCESS_CORE = 0, | ||
| 277 | BFIN_MEM_ACCESS_CORE_ONLY, | ||
| 278 | BFIN_MEM_ACCESS_DMA, | ||
| 279 | BFIN_MEM_ACCESS_IDMA, | ||
| 280 | BFIN_MEM_ACCESS_ITEST, | ||
| 281 | }; | ||
| 282 | /** | ||
| 283 | * bfin_mem_access_type() - what kind of memory access is required | ||
| 284 | * @addr: the address to check | ||
| 285 | * @size: number of bytes needed | ||
| 286 | * @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above) | ||
| 287 | */ | ||
| 288 | int bfin_mem_access_type(unsigned long addr, unsigned long size); | ||
| 289 | |||
| 268 | #endif /* _BLACKFIN_UACCESS_H */ | 290 | #endif /* _BLACKFIN_UACCESS_H */ |
| @@ -381,8 +381,9 @@ · 380 unmodified lines | |||
| 381 | #define __NR_preadv 366 | 381 | #define __NR_preadv 366 |
| 382 | #define __NR_pwritev 367 | 382 | #define __NR_pwritev 367 |
| 383 | #define __NR_rt_tgsigqueueinfo 368 | 383 | #define __NR_rt_tgsigqueueinfo 368 |
| 384 | #define __NR_perf_counter_open 369 | ||
| 384 | 385 | ||
| 385 | #define __NR_syscall 369 | 386 | #define __NR_syscall 370 |
| 386 | #define NR_syscalls __NR_syscall | 387 | #define NR_syscalls __NR_syscall |
| 387 | 388 | ||
| 388 | /* Old optional stuff no one actually uses */ | 389 | /* Old optional stuff no one actually uses */ |
| @@ -20,7 +20,6 @@ obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o · 19 unmodified lines | |||
| 20 | CFLAGS_REMOVE_ftrace.o = -pg | 20 | CFLAGS_REMOVE_ftrace.o = -pg |
| 21 | 21 | ||
| 22 | obj-$(CONFIG_IPIPE) += ipipe.o | 22 | obj-$(CONFIG_IPIPE) += ipipe.o |
| 23 | obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o | ||
| 24 | obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o | 23 | obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o |
| 25 | obj-$(CONFIG_CPLB_INFO) += cplbinfo.o | 24 | obj-$(CONFIG_CPLB_INFO) += cplbinfo.o |
| 26 | obj-$(CONFIG_MODULES) += module.o | 25 | obj-$(CONFIG_MODULES) += module.o |
| @@ -46,13 +46,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) · 45 unmodified lines | |||
| 46 | 46 | ||
| 47 | printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n"); | 47 | printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n"); |
| 48 | 48 | ||
| 49 | #ifdef CONFIG_BFIN_ICACHE | 49 | #ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE |
| 50 | i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; | 50 | i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; |
| 51 | #endif | 51 | #endif |
| 52 | 52 | ||
| 53 | #ifdef CONFIG_BFIN_DCACHE | 53 | #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE |
| 54 | d_cache = CPLB_L1_CHBL; | 54 | d_cache = CPLB_L1_CHBL; |
| 55 | #ifdef CONFIG_BFIN_WT | 55 | #ifdef CONFIG_BFIN_EXTMEM_WRITETROUGH |
| 56 | d_cache |= CPLB_L1_AOW | CPLB_WT; | 56 | d_cache |= CPLB_L1_AOW | CPLB_WT; |
| 57 | #endif | 57 | #endif |
| 58 | #endif | 58 | #endif |
| @@ -91,9 +91,9 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) · 32 unmodified lines | |||
| 91 | /* Cover L2 memory */ | 91 | /* Cover L2 memory */ |
| 92 | #if L2_LENGTH > 0 | 92 | #if L2_LENGTH > 0 |
| 93 | dcplb_tbl[cpu][i_d].addr = L2_START; | 93 | dcplb_tbl[cpu][i_d].addr = L2_START; |
| 94 | dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB; | 94 | dcplb_tbl[cpu][i_d++].data = L2_DMEMORY; |
| 95 | icplb_tbl[cpu][i_i].addr = L2_START; | 95 | icplb_tbl[cpu][i_i].addr = L2_START; |
| 96 | icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB; | 96 | icplb_tbl[cpu][i_i++].data = L2_IMEMORY; |
| 97 | #endif | 97 | #endif |
| 98 | 98 | ||
| 99 | first_mask_dcplb = i_d; | 99 | first_mask_dcplb = i_d; |
| @@ -150,15 +150,19 @@ static noinline int dcplb_miss(unsigned int cpu) · 149 unmodified lines | |||
| 150 | nr_dcplb_miss[cpu]++; | 150 | nr_dcplb_miss[cpu]++; |
| 151 | 151 | ||
| 152 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; | 152 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; |
| 153 | #ifdef CONFIG_BFIN_DCACHE | 153 | #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE |
| 154 | if (bfin_addr_dcacheable(addr)) { | 154 | if (bfin_addr_dcacheable(addr)) { |
| 155 | d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; | 155 | d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; |
| 156 | #ifdef CONFIG_BFIN_WT | 156 | # ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH |
| 157 | d_data |= CPLB_L1_AOW | CPLB_WT; | 157 | d_data |= CPLB_L1_AOW | CPLB_WT; |
| 158 | #endif | 158 | # endif |
| 159 | } | 159 | } |
| 160 | #endif | 160 | #endif |
| 161 | if (addr >= physical_mem_end) { | 161 | |
| 162 | if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { | ||
| 163 | addr = L2_START; | ||
| 164 | d_data = L2_DMEMORY; | ||
| 165 | } else if (addr >= physical_mem_end) { | ||
| 162 | if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE | 166 | if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE |
| 163 | && (status & FAULT_USERSUPV)) { | 167 | && (status & FAULT_USERSUPV)) { |
| 164 | addr &= ~0x3fffff; | 168 | addr &= ~0x3fffff; |
| @@ -235,7 +239,7 @@ static noinline int icplb_miss(unsigned int cpu) · 70 unmodified lines | |||
| 235 | 239 | ||
| 236 | i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; | 240 | i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; |
| 237 | 241 | ||
| 238 | #ifdef CONFIG_BFIN_ICACHE | 242 | #ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE |
| 239 | /* | 243 | /* |
| 240 | * Normal RAM, and possibly the reserved memory area, are | 244 | * Normal RAM, and possibly the reserved memory area, are |
| 241 | * cacheable. | 245 | * cacheable. |
| @@ -245,7 +249,10 @@ static noinline int icplb_miss(unsigned int cpu) · 3 unmodified lines | |||
| 245 | i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; | 249 | i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; |
| 246 | #endif | 250 | #endif |
| 247 | 251 | ||
| 248 | if (addr >= physical_mem_end) { | 252 | if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { |
| 253 | addr = L2_START; | ||
| 254 | i_data = L2_IMEMORY; | ||
| 255 | } else if (addr >= physical_mem_end) { | ||
| 249 | if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH | 256 | if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH |
| 250 | && (status & FAULT_USERSUPV)) { | 257 | && (status & FAULT_USERSUPV)) { |
| 251 | addr &= ~(1 * 1024 * 1024 - 1); | 258 | addr &= ~(1 * 1024 * 1024 - 1); |
| @@ -365,13 +372,18 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu) · 113 unmodified lines | |||
| 365 | local_irq_save_hw(flags); | 372 | local_irq_save_hw(flags); |
| 366 | current_rwx_mask[cpu] = masks; | 373 | current_rwx_mask[cpu] = masks; |
| 367 | 374 | ||
| 368 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; | 375 | if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) { |
| 369 | #ifdef CONFIG_BFIN_DCACHE | 376 | addr = L2_START; |
| 370 | d_data |= CPLB_L1_CHBL; | 377 | d_data = L2_DMEMORY; |
| 371 | #ifdef CONFIG_BFIN_WT | 378 | } else { |
| 372 | d_data |= CPLB_L1_AOW | CPLB_WT; | 379 | d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; |
| 373 | #endif | 380 | #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE |
| 381 | d_data |= CPLB_L1_CHBL; | ||
| 382 | # ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH | ||
| 383 | d_data |= CPLB_L1_AOW | CPLB_WT; | ||
| 384 | # endif | ||
| 374 | #endif | 385 | #endif |
| 386 | } | ||
| 375 | 387 | ||
| 376 | disable_dcplb(); | 388 | disable_dcplb(); |
| 377 | for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { | 389 | for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { |
| @@ -52,7 +52,7 @@ EXPORT_SYMBOL(__ipipe_freq_scale); · 51 unmodified lines | |||
| 52 | 52 | ||
| 53 | atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; | 53 | atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; |
| 54 | 54 | ||
| 55 | unsigned long __ipipe_irq_lvmask = __all_masked_irq_flags; | 55 | unsigned long __ipipe_irq_lvmask = bfin_no_irqs; |
| 56 | EXPORT_SYMBOL(__ipipe_irq_lvmask); | 56 | EXPORT_SYMBOL(__ipipe_irq_lvmask); |
| 57 | 57 | ||
| 58 | static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc) | 58 | static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc) |
| @@ -342,8 +342,3 @@ void ___ipipe_sync_pipeline(unsigned long syncmask) · 283 unmodified lines | |||
| 342 | } | 342 | } |
| 343 | 343 | ||
| 344 | EXPORT_SYMBOL(show_stack); | 344 | EXPORT_SYMBOL(show_stack); |
| 345 | |||
| 346 | #ifdef CONFIG_IPIPE_TRACE_MCOUNT | ||
| 347 | void notrace _mcount(void); | ||
| 348 | EXPORT_SYMBOL(_mcount); | ||
| 349 | #endif /* CONFIG_IPIPE_TRACE_MCOUNT */ | ||
| @@ -38,38 +38,15 @@ · 37 unmodified lines | |||
| 38 | #include <asm/pda.h> | 38 | #include <asm/pda.h> |
| 39 | 39 | ||
| 40 | static atomic_t irq_err_count; | 40 | static atomic_t irq_err_count; |
| 41 | static spinlock_t irq_controller_lock; | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Dummy mask/unmask handler | ||
| 45 | */ | ||
| 46 | void dummy_mask_unmask_irq(unsigned int irq) | ||
| 47 | { | ||
| 48 | } | ||
| 49 | |||
| 50 | void ack_bad_irq(unsigned int irq) | 41 | void ack_bad_irq(unsigned int irq) |
| 51 | { | 42 | { |
| 52 | atomic_inc(&irq_err_count); | 43 | atomic_inc(&irq_err_count); |
| 53 | printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq); | 44 | printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq); |
| 54 | } | 45 | } |
| 55 | 46 | ||
| 56 | static struct irq_chip bad_chip = { | ||
| 57 | .ack = dummy_mask_unmask_irq, | ||
| 58 | .mask = dummy_mask_unmask_irq, | ||
| 59 | .unmask = dummy_mask_unmask_irq, | ||
| 60 | }; | ||
| 61 | |||
| 62 | static int bad_stats; | ||
| 63 | static struct irq_desc bad_irq_desc = { | 47 | static struct irq_desc bad_irq_desc = { |
| 64 | .status = IRQ_DISABLED, | ||
| 65 | .chip = &bad_chip, | ||
| 66 | .handle_irq = handle_bad_irq, | 48 | .handle_irq = handle_bad_irq, |
| 67 | .depth = 1, | ||
| 68 | .lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock), | 49 | .lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock), |
| 69 | .kstat_irqs = &bad_stats, | ||
| 70 | #ifdef CONFIG_SMP | ||
| 71 | .affinity = CPU_MASK_ALL | ||
| 72 | #endif | ||
| 73 | }; | 50 | }; |
| 74 | 51 | ||
| 75 | #ifdef CONFIG_CPUMASK_OFFSTACK | 52 | #ifdef CONFIG_CPUMASK_OFFSTACK |
| @@ -77,6 +54,7 @@ static struct irq_desc bad_irq_desc = { · 1 unmodified line | |||
| 77 | #error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK." | 54 | #error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK." |
| 78 | #endif | 55 | #endif |
| 79 | 56 | ||
| 57 | #ifdef CONFIG_PROC_FS | ||
| 80 | int show_interrupts(struct seq_file *p, void *v) | 58 | int show_interrupts(struct seq_file *p, void *v) |
| 81 | { | 59 | { |
| 82 | int i = *(loff_t *) v, j; | 60 | int i = *(loff_t *) v, j; |
| @@ -108,50 +86,29 @@ int show_interrupts(struct seq_file *p, void *v) · 25 unmodified lines | |||
| 108 | } | 86 | } |
| 109 | return 0; | 87 | return 0; |
| 110 | } | 88 | } |
| 111 | |||
| 112 | /* | ||
| 113 | * do_IRQ handles all hardware IRQs. Decoded IRQs should not | ||
| 114 | * come via this function. Instead, they should provide their | ||
| 115 | * own 'handler' | ||
| 116 | */ | ||
| 117 | #ifdef CONFIG_DO_IRQ_L1 | ||
| 118 | __attribute__((l1_text)) | ||
| 119 | #endif | ||
| 120 | asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | ||
| 121 | { | ||
| 122 | struct pt_regs *old_regs; | ||
| 123 | struct irq_desc *desc = irq_desc + irq; | ||
| 124 | #ifndef CONFIG_IPIPE | ||
| 125 | unsigned short pending, other_ints; | ||
| 126 | #endif | 89 | #endif |
| 127 | old_regs = set_irq_regs(regs); | ||
| 128 | 90 | ||
| 129 | /* | ||
| 130 | * Some hardware gives randomly wrong interrupts. Rather | ||
| 131 | * than crashing, do something sensible. | ||
| 132 | */ | ||
| 133 | if (irq >= NR_IRQS) | ||
| 134 | desc = &bad_irq_desc; | ||
| 135 | |||
| 136 | irq_enter(); | ||
| 137 | #ifdef CONFIG_DEBUG_STACKOVERFLOW | 91 | #ifdef CONFIG_DEBUG_STACKOVERFLOW |
| 92 | static void check_stack_overflow(int irq) | ||
| 93 | { | ||
| 138 | /* Debugging check for stack overflow: is there less than STACK_WARN free? */ | 94 | /* Debugging check for stack overflow: is there less than STACK_WARN free? */ |
| 139 | { | 95 | long sp = __get_SP() & (THREAD_SIZE - 1); |
| 140 | long sp; | ||
| 141 | |||
| 142 | sp = __get_SP() & (THREAD_SIZE-1); | ||
| 143 | 96 | ||
| 144 | if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { | 97 | if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { |
| 145 | dump_stack(); | 98 | dump_stack(); |
| 146 | printk(KERN_EMERG "%s: possible stack overflow while handling irq %i " | 99 | pr_emerg("irq%i: possible stack overflow only %ld bytes free\n", |
| 147 | " only %ld bytes free\n", | 100 | irq, sp - sizeof(struct thread_info)); |
| 148 | __func__, irq, sp - sizeof(struct thread_info)); | ||
| 149 | } | ||
| 150 | } | 101 | } |
| 102 | } | ||
| 103 | #else | ||
| 104 | static inline void check_stack_overflow(int irq) { } | ||
| 151 | #endif | 105 | #endif |
| 152 | generic_handle_irq(irq); | ||
| 153 | 106 | ||
| 154 | #ifndef CONFIG_IPIPE | 107 | #ifndef CONFIG_IPIPE |
| 108 | static void maybe_lower_to_irq14(void) | ||
| 109 | { | ||
| 110 | unsigned short pending, other_ints; | ||
| 111 | |||
| 155 | /* | 112 | /* |
| 156 | * If we're the only interrupt running (ignoring IRQ15 which | 113 | * If we're the only interrupt running (ignoring IRQ15 which |
| 157 | * is for syscalls), lower our priority to IRQ14 so that | 114 | * is for syscalls), lower our priority to IRQ14 so that |
| @@ -165,7 +122,38 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) · 7 unmodified lines | |||
| 165 | other_ints = pending & (pending - 1); | 122 | other_ints = pending & (pending - 1); |
| 166 | if (other_ints == 0) | 123 | if (other_ints == 0) |
| 167 | lower_to_irq14(); | 124 | lower_to_irq14(); |
| 168 | #endif /* !CONFIG_IPIPE */ | 125 | } |
| 126 | #else | ||
| 127 | static inline void maybe_lower_to_irq14(void) { } | ||
| 128 | #endif | ||
| 129 | |||
| 130 | /* | ||
| 131 | * do_IRQ handles all hardware IRQs. Decoded IRQs should not | ||
| 132 | * come via this function. Instead, they should provide their | ||
| 133 | * own 'handler' | ||
| 134 | */ | ||
| 135 | #ifdef CONFIG_DO_IRQ_L1 | ||
| 136 | __attribute__((l1_text)) | ||
| 137 | #endif | ||
| 138 | asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | ||
| 139 | { | ||
| 140 | struct pt_regs *old_regs = set_irq_regs(regs); | ||
| 141 | |||
| 142 | irq_enter(); | ||
| 143 | |||
| 144 | check_stack_overflow(irq); | ||
| 145 | |||
| 146 | /* | ||
| 147 | * Some hardware gives randomly wrong interrupts. Rather | ||
| 148 | * than crashing, do something sensible. | ||
| 149 | */ | ||
| 150 | if (irq >= NR_IRQS) | ||
| 151 | handle_bad_irq(irq, &bad_irq_desc); | ||
| 152 | else | ||
| 153 | generic_handle_irq(irq); | ||
| 154 | |||
| 155 | maybe_lower_to_irq14(); | ||
| 156 | |||
| 169 | irq_exit(); | 157 | irq_exit(); |
| 170 | 158 | ||
| 171 | set_irq_regs(old_regs); | 159 | set_irq_regs(old_regs); |
| @@ -173,14 +161,6 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) · 1 unmodified line | |||
| 173 | 161 | ||
| 174 | void __init init_IRQ(void) | 162 | void __init init_IRQ(void) |
| 175 | { | 163 | { |
| 176 | struct irq_desc *desc; | ||
| 177 | int irq; | ||
| 178 | |||
| 179 | spin_lock_init(&irq_controller_lock); | ||
| 180 | for (irq = 0, desc = irq_desc; irq < NR_IRQS; irq++, desc++) { | ||
| 181 | *desc = bad_irq_desc; | ||
| 182 | } | ||
| 183 | |||
| 184 | init_arch_irq(); | 164 | init_arch_irq(); |
| 185 | 165 | ||
| 186 | #ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND | 166 | #ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND |
| @@ -34,15 +34,6 @@ int gdb_bfin_vector = -1; · 33 unmodified lines | |||
| 34 | #error change the definition of slavecpulocks | 34 | #error change the definition of slavecpulocks |
| 35 | #endif | 35 | #endif |
| 36 | 36 | ||
| 37 | #define IN_MEM(addr, size, l1_addr, l1_size) \ | ||
| 38 | ({ \ | ||
| 39 | unsigned long __addr = (unsigned long)(addr); \ | ||
| 40 | (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \ | ||
| 41 | }) | ||
| 42 | #define ASYNC_BANK_SIZE \ | ||
| 43 | (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ | ||
| 44 | ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) | ||
| 45 | |||
| 46 | void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) | 37 | void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) |
| 47 | { | 38 | { |
| 48 | gdb_regs[BFIN_R0] = regs->r0; | 39 | gdb_regs[BFIN_R0] = regs->r0; |
| @@ -463,41 +454,88 @@ static int hex(char ch) · 414 unmodified lines | |||
| 463 | 454 | ||
| 464 | static int validate_memory_access_address(unsigned long addr, int size) | 455 | static int validate_memory_access_address(unsigned long addr, int size) |
| 465 | { | 456 | { |
| 466 | int cpu = raw_smp_processor_id(); | 457 | if (size < 0 || addr == 0) |
| 467 | |||
| 468 | if (size < 0) | ||
| 469 | return -EFAULT; | 458 | return -EFAULT; |
| 470 | if (addr >= 0x1000 && (addr + size) <= physical_mem_end) | 459 | return bfin_mem_access_type(addr, size); |
| 471 | return 0; | 460 | } |
| 472 | if (addr >= SYSMMR_BASE) | 461 | |
| 473 | return 0; | 462 | static int bfin_probe_kernel_read(char *dst, char *src, int size) |
| 474 | if (IN_MEM(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE)) | 463 | { |
| 475 | return 0; | 464 | unsigned long lsrc = (unsigned long)src; |
| 476 | if (cpu == 0) { | 465 | int mem_type; |
| 477 | if (IN_MEM(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH)) | 466 | |
| 478 | return 0; | 467 | mem_type = validate_memory_access_address(lsrc, size); |
| 479 | if (IN_MEM(addr, size, L1_CODE_START, L1_CODE_LENGTH)) | 468 | if (mem_type < 0) |
| 480 | return 0; | 469 | return mem_type; |
| 481 | if (IN_MEM(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH)) | 470 | |
| 482 | return 0; | 471 | if (lsrc >= SYSMMR_BASE) { |
| 483 | if (IN_MEM(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) | 472 | if (size == 2 && lsrc % 2 == 0) { |
| 484 | return 0; | 473 | u16 mmr = bfin_read16(src); |
| 485 | #ifdef CONFIG_SMP | 474 | memcpy(dst, &mmr, sizeof(mmr)); |
| 486 | } else if (cpu == 1) { | ||
| 487 | if (IN_MEM(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) | ||
| 488 | return 0; | 475 | return 0; |
| 489 | if (IN_MEM(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) | 476 | } else if (size == 4 && lsrc % 4 == 0) { |
| 477 | u32 mmr = bfin_read32(src); | ||
| 478 | memcpy(dst, &mmr, sizeof(mmr)); | ||
| 490 | return 0; | 479 | return 0; |
| 491 | if (IN_MEM(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) | 480 | } |
| 481 | } else { | ||
| 482 | switch (mem_type) { | ||
| 483 | case BFIN_MEM_ACCESS_CORE: | ||
| 484 | case BFIN_MEM_ACCESS_CORE_ONLY: | ||
| 485 | return probe_kernel_read(dst, src, size); | ||
| 486 | /* XXX: should support IDMA here with SMP */ | ||
| 487 | case BFIN_MEM_ACCESS_DMA: | ||
| 488 | if (dma_memcpy(dst, src, size)) | ||
| 489 | return 0; | ||
| 490 | break; | ||
| 491 | case BFIN_MEM_ACCESS_ITEST: | ||
| 492 | if (isram_memcpy(dst, src, size)) | ||
| 493 | return 0; | ||
| 494 | break; | ||
| 495 | } | ||
| 496 | } | ||
| 497 | |||
| 498 | return -EFAULT; | ||
| 499 | } | ||
| 500 | |||
| 501 | static int bfin_probe_kernel_write(char *dst, char *src, int size) | ||
| 502 | { | ||
| 503 | unsigned long ldst = (unsigned long)dst; | ||
| 504 | int mem_type; | ||
| 505 | |||
| 506 | mem_type = validate_memory_access_address(ldst, size); | ||
| 507 | if (mem_type < 0) | ||
| 508 | return mem_type; | ||
| 509 | |||
| 510 | if (ldst >= SYSMMR_BASE) { | ||
| 511 | if (size == 2 && ldst % 2 == 0) { | ||
| 512 | u16 mmr; | ||
| 513 | memcpy(&mmr, src, sizeof(mmr)); | ||
| 514 | bfin_write16(dst, mmr); | ||
| 492 | return 0; | 515 | return 0; |
| 493 | if (IN_MEM(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) | 516 | } else if (size == 4 && ldst % 4 == 0) { |
| 517 | u32 mmr; | ||
| 518 | memcpy(&mmr, src, sizeof(mmr)); | ||
| 519 | bfin_write32(dst, mmr); | ||
| 494 | return 0; | 520 | return 0; |
| 495 | #endif | 521 | } |
| 522 | } else { | ||
| 523 | switch (mem_type) { | ||
| 524 | case BFIN_MEM_ACCESS_CORE: | ||
| 525 | case BFIN_MEM_ACCESS_CORE_ONLY: | ||
| 526 | return probe_kernel_write(dst, src, size); | ||
| 527 | /* XXX: should support IDMA here with SMP */ | ||
| 528 | case BFIN_MEM_ACCESS_DMA: | ||
| 529 | if (dma_memcpy(dst, src, size)) | ||
| 530 | return 0; | ||
| 531 | break; | ||
| 532 | case BFIN_MEM_ACCESS_ITEST: | ||
| 533 | if (isram_memcpy(dst, src, size)) | ||
| 534 | return 0; | ||
| 535 | break; | ||
| 536 | } | ||
| 496 | } | 537 | } |
| 497 | 538 | ||
| 498 | if (IN_MEM(addr, size, L2_START, L2_LENGTH)) | ||
| 499 | return 0; | ||
| 500 | |||
| 501 | return -EFAULT; | 539 | return -EFAULT; |
| 502 | } | 540 | } |
| 503 | 541 | ||
| @@ -509,14 +547,6 @@ int kgdb_mem2hex(char *mem, char *buf, int count) · 5 unmodified lines | |||
| 509 | { | 547 | { |
| 510 | char *tmp; | 548 | char *tmp; |
| 511 | int err; | 549 | int err; |
| 512 | unsigned char *pch; | ||
| 513 | unsigned short mmr16; | ||
| 514 | unsigned long mmr32; | ||
| 515 | int cpu = raw_smp_processor_id(); | ||
| 516 | |||
| 517 | err = validate_memory_access_address((unsigned long)mem, count); | ||
| 518 | if (err) | ||
| 519 | return err; | ||
| 520 | 550 | ||
| 521 | /* | 551 | /* |
| 522 | * We use the upper half of buf as an intermediate buffer for the | 552 | * We use the upper half of buf as an intermediate buffer for the |
| @@ -524,44 +554,7 @@ int kgdb_mem2hex(char *mem, char *buf, int count) · 1 unmodified line | |||
| 524 | */ | 554 | */ |
| 525 | tmp = buf + count; | 555 | tmp = buf + count; |
| 526 | 556 | ||
| 527 | if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ | 557 | err = bfin_probe_kernel_read(tmp, mem, count); |
| 528 | switch (count) { | ||
| 529 | case 2: | ||
| 530 | if ((unsigned int)mem % 2 == 0) { | ||
| 531 | mmr16 = *(unsigned short *)mem; | ||
| 532 | pch = (unsigned char *)&mmr16; | ||
| 533 | *tmp++ = *pch++; | ||
| 534 | *tmp++ = *pch++; | ||
| 535 | tmp -= 2; | ||
| 536 | } else | ||
| 537 | err = -EFAULT; | ||
| 538 | break; | ||
| 539 | case 4: | ||
| 540 | if ((unsigned int)mem % 4 == 0) { | ||
| 541 | mmr32 = *(unsigned long *)mem; | ||
| 542 | pch = (unsigned char *)&mmr32; | ||
| 543 | *tmp++ = *pch++; | ||
| 544 | *tmp++ = *pch++; | ||
| 545 | *tmp++ = *pch++; | ||
| 546 | *tmp++ = *pch++; | ||
| 547 | tmp -= 4; | ||
| 548 | } else | ||
| 549 | err = -EFAULT; | ||
| 550 | break; | ||
| 551 | default: | ||
| 552 | err = -EFAULT; | ||
| 553 | } | ||
| 554 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) | ||
| 555 | #ifdef CONFIG_SMP | ||
| 556 | || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) | ||
| 557 | #endif | ||
| 558 | ) { | ||
| 559 | /* access L1 instruction SRAM*/ | ||
| 560 | if (dma_memcpy(tmp, mem, count) == NULL) | ||
| 561 | err = -EFAULT; | ||
| 562 | } else | ||
| 563 | err = probe_kernel_read(tmp, mem, count); | ||
| 564 | |||
| 565 | if (!err) { | 558 | if (!err) { |
| 566 | while (count > 0) { | 559 | while (count > 0) { |
| 567 | buf = pack_hex_byte(buf, *tmp); | 560 | buf = pack_hex_byte(buf, *tmp); |
| @@ -582,13 +575,8 @@ int kgdb_mem2hex(char *mem, char *buf, int count) · 14 unmodified lines | |||
| 582 | */ | 575 | */ |
| 583 | int kgdb_ebin2mem(char *buf, char *mem, int count) | 576 | int kgdb_ebin2mem(char *buf, char *mem, int count) |
| 584 | { | 577 | { |
| 585 | char *tmp_old; | 578 | char *tmp_old, *tmp_new; |
| 586 | char *tmp_new; | ||
| 587 | unsigned short *mmr16; | ||
| 588 | unsigned long *mmr32; | ||
| 589 | int err; | ||
| 590 | int size; | 579 | int size; |
| 591 | int cpu = raw_smp_processor_id(); | ||
| 592 | 580 | ||
| 593 | tmp_old = tmp_new = buf; | 581 | tmp_old = tmp_new = buf; |
| 594 | 582 | ||
| @@ -601,41 +589,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count) · 6 unmodified lines | |||
| 601 | tmp_old++; | 589 | tmp_old++; |
| 602 | } | 590 | } |
| 603 | 591 | ||
| 604 | err = validate_memory_access_address((unsigned long)mem, size); | 592 | return bfin_probe_kernel_write(mem, buf, count); |
| 605 | if (err) | ||
| 606 | return err; | ||
| 607 | |||
| 608 | if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ | ||
| 609 | switch (size) { | ||
| 610 | case 2: | ||
| 611 | if ((unsigned int)mem % 2 == 0) { | ||
| 612 | mmr16 = (unsigned short *)buf; | ||
| 613 | *(unsigned short *)mem = *mmr16; | ||
| 614 | } else | ||
| 615 | err = -EFAULT; | ||
| 616 | break; | ||
| 617 | case 4: | ||
| 618 | if ((unsigned int)mem % 4 == 0) { | ||
| 619 | mmr32 = (unsigned long *)buf; | ||
| 620 | *(unsigned long *)mem = *mmr32; | ||
| 621 | } else | ||
| 622 | err = -EFAULT; | ||
| 623 | break; | ||
| 624 | default: | ||
| 625 | err = -EFAULT; | ||
| 626 | } | ||
| 627 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) | ||
| 628 | #ifdef CONFIG_SMP | ||
| 629 | || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) | ||
| 630 | #endif | ||
| 631 | ) { | ||
| 632 | /* access L1 instruction SRAM */ | ||
| 633 | if (dma_memcpy(mem, buf, size) == NULL) | ||
| 634 | err = -EFAULT; | ||
| 635 | } else | ||
| 636 | err = probe_kernel_write(mem, buf, size); | ||
| 637 | |||
| 638 | return err; | ||
| 639 | } | 593 | } |
| 640 | 594 | ||
| 641 | /* | 595 | /* |
| @@ -645,16 +599,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count) · 3 unmodified lines | |||
| 645 | */ | 599 | */ |
| 646 | int kgdb_hex2mem(char *buf, char *mem, int count) | 600 | int kgdb_hex2mem(char *buf, char *mem, int count) |
| 647 | { | 601 | { |
| 648 | char *tmp_raw; | 602 | char *tmp_raw, *tmp_hex; |
| 649 | char *tmp_hex; | ||
| 650 | unsigned short *mmr16; | ||
| 651 | unsigned long *mmr32; | ||
| 652 | int err; | ||
| 653 | int cpu = raw_smp_processor_id(); | ||
| 654 | |||
| 655 | err = validate_memory_access_address((unsigned long)mem, count); | ||
| 656 | if (err) | ||
| 657 | return err; | ||
| 658 | 603 | ||
| 659 | /* | 604 | /* |
| 660 | * We use the upper half of buf as an intermediate buffer for the | 605 | * We use the upper half of buf as an intermediate buffer for the |
| @@ -669,39 +614,18 @@ int kgdb_hex2mem(char *buf, char *mem, int count) · 8 unmodified lines | |||
| 669 | *tmp_raw |= hex(*tmp_hex--) << 4; | 614 | *tmp_raw |= hex(*tmp_hex--) << 4; |
| 670 | } | 615 | } |
| 671 | 616 | ||
| 672 | if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ | 617 | return bfin_probe_kernel_write(mem, tmp_raw, count); |
| 673 | switch (count) { | ||
| 674 | case 2: | ||
| 675 | if ((unsigned int)mem % 2 == 0) { | ||
| 676 | mmr16 = (unsigned short *)tmp_raw; | ||
| 677 | *(unsigned short *)mem = *mmr16; | ||
| 678 | } else | ||
| 679 | err = -EFAULT; | ||
| 680 | break; | ||
| 681 | case 4: | ||
| 682 | if ((unsigned int)mem % 4 == 0) { | ||
| 683 | mmr32 = (unsigned long *)tmp_raw; | ||
| 684 | *(unsigned long *)mem = *mmr32; | ||
| 685 | } else | ||
| 686 | err = -EFAULT; | ||
| 687 | break; | ||
| 688 | default: | ||
| 689 | err = -EFAULT; | ||
| 690 | } | ||
| 691 | } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH)) | ||
| 692 | #ifdef CONFIG_SMP | ||
| 693 | || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH)) | ||
| 694 | #endif | ||
| 695 | ) { | ||
| 696 | /* access L1 instruction SRAM */ | ||
| 697 | if (dma_memcpy(mem, tmp_raw, count) == NULL) | ||
| 698 | err = -EFAULT; | ||
| 699 | } else | ||
| 700 | err = probe_kernel_write(mem, tmp_raw, count); | ||
| 701 | |||
| 702 | return err; | ||
| 703 | } | 618 | } |
| 704 | 619 | ||
| 620 | #define IN_MEM(addr, size, l1_addr, l1_size) \ | ||
| 621 | ({ \ | ||
| 622 | unsigned long __addr = (unsigned long)(addr); \ | ||
| 623 | (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \ | ||
| 624 | }) | ||
| 625 | #define ASYNC_BANK_SIZE \ | ||
| 626 | (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ | ||
| 627 | ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) | ||
| 628 | |||
| 705 | int kgdb_validate_break_address(unsigned long addr) | 629 | int kgdb_validate_break_address(unsigned long addr) |
| 706 | { | 630 | { |
| 707 | int cpu = raw_smp_processor_id(); | 631 | int cpu = raw_smp_processor_id(); |
| @@ -724,46 +648,17 @@ int kgdb_validate_break_address(unsigned long addr) · 16 unmodified lines | |||
| 724 | 648 | ||
| 725 | int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr) | 649 | int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr) |
| 726 | { | 650 | { |
| 727 | int err; | 651 | int err = bfin_probe_kernel_read(saved_instr, (char *)addr, |
| 728 | int cpu = raw_smp_processor_id(); | 652 | BREAK_INSTR_SIZE); |
| 729 | 653 | if (err) | |
| 730 | if ((cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) | 654 | return err; |
| 731 | #ifdef CONFIG_SMP | 655 | return bfin_probe_kernel_write((char *)addr, arch_kgdb_ops.gdb_bpt_instr, |
| 732 | || (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH)) | 656 | BREAK_INSTR_SIZE); |
| 733 | #endif | ||
| 734 | ) { | ||
| 735 | /* access L1 instruction SRAM */ | ||
| 736 | if (dma_memcpy(saved_instr, (void *)addr, BREAK_INSTR_SIZE) | ||
| 737 | == NULL) | ||
| 738 | return -EFAULT; | ||
| 739 | |||
| 740 | if (dma_memcpy((void *)addr, arch_kgdb_ops.gdb_bpt_instr, | ||
| 741 | BREAK_INSTR_SIZE) == NULL) | ||
| 742 | return -EFAULT; | ||
| 743 | |||
| 744 | return 0; | ||
| 745 | } else { | ||
| 746 | err = probe_kernel_read(saved_instr, (char *)addr, | ||
| 747 | BREAK_INSTR_SIZE); | ||
| 748 | if (err) | ||
| 749 | return err; | ||
| 750 | |||
| 751 | return probe_kernel_write((char *)addr, | ||
| 752 | arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE); | ||
| 753 | } | ||
| 754 | } | 657 | } |
| 755 | 658 | ||
| 756 | int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle) | 659 | int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle) |
| 757 | { | 660 | { |
| 758 | if (IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) { | 661 | return bfin_probe_kernel_write((char *)addr, bundle, BREAK_INSTR_SIZE); |
| 759 | /* access L1 instruction SRAM */ | ||
| 760 | if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL) | ||
| 761 | return -EFAULT; | ||
| 762 | |||
| 763 | return 0; | ||
| 764 | } else | ||
| 765 | return probe_kernel_write((char *)addr, | ||
| 766 | (char *)bundle, BREAK_INSTR_SIZE); | ||
| 767 | } | 662 | } |
| 768 | 663 | ||
| 769 | int kgdb_arch_init(void) | 664 | int kgdb_arch_init(void) |
| @@ -1,70 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/blackfin/mcount.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Analog Devices Inc. | ||
| 5 | * | ||
| 6 | * 2007/04/12 Save index, length, modify and base registers. --rpm | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/linkage.h> | ||
| 10 | #include <asm/blackfin.h> | ||
| 11 | |||
| 12 | .text | ||
| 13 | |||
| 14 | .align 4 /* just in case */ | ||
| 15 | |||
| 16 | ENTRY(__mcount) | ||
| 17 | [--sp] = i0; | ||
| 18 | [--sp] = i1; | ||
| 19 | [--sp] = i2; | ||
| 20 | [--sp] = i3; | ||
| 21 | [--sp] = l0; | ||
| 22 | [--sp] = l1; | ||
| 23 | [--sp] = l2; | ||
| 24 | [--sp] = l3; | ||
| 25 | [--sp] = m0; | ||
| 26 | [--sp] = m1; | ||
| 27 | [--sp] = m2; | ||
| 28 | [--sp] = m3; | ||
| 29 | [--sp] = b0; | ||
| 30 | [--sp] = b1; | ||
| 31 | [--sp] = b2; | ||
| 32 | [--sp] = b3; | ||
| 33 | [--sp] = ( r7:0, p5:0 ); | ||
| 34 | [--sp] = ASTAT; | ||
| 35 | |||
| 36 | p1.L = _ipipe_trace_enable; | ||
| 37 | p1.H = _ipipe_trace_enable; | ||
| 38 | r7 = [p1]; | ||
| 39 | CC = r7 == 0; | ||
| 40 | if CC jump out; | ||
| 41 | link 0x10; | ||
| 42 | r0 = 0x0; | ||
| 43 | [sp + 0xc] = r0; /* v */ | ||
| 44 | r0 = 0x0; /* type: IPIPE_TRACE_FN */ | ||
| 45 | r1 = rets; | ||
| 46 | p0 = [fp]; /* p0: Prior FP */ | ||
| 47 | r2 = [p0 + 4]; /* r2: Prior RETS */ | ||
| 48 | call ___ipipe_trace; | ||
| 49 | unlink; | ||
| 50 | out: | ||
| 51 | ASTAT = [sp++]; | ||
| 52 | ( r7:0, p5:0 ) = [sp++]; | ||
| 53 | b3 = [sp++]; | ||
| 54 | b2 = [sp++]; | ||
| 55 | b1 = [sp++]; | ||
| 56 | b0 = [sp++]; | ||
| 57 | m3 = [sp++]; | ||
| 58 | m2 = [sp++]; | ||
| 59 | m1 = [sp++]; | ||
| 60 | m0 = [sp++]; | ||
| 61 | l3 = [sp++]; | ||
| 62 | l2 = [sp++]; | ||
| 63 | l1 = [sp++]; | ||
| 64 | l0 = [sp++]; | ||
| 65 | i3 = [sp++]; | ||
| 66 | i2 = [sp++]; | ||
| 67 | i1 = [sp++]; | ||
| 68 | i0 = [sp++]; | ||
| 69 | rts; | ||
| 70 | ENDPROC(__mcount) | ||
| @@ -344,6 +344,87 @@ void finish_atomic_sections (struct pt_regs *regs) · 343 unmodified lines | |||
| 344 | } | 344 | } |
| 345 | } | 345 | } |
| 346 | 346 | ||
| 347 | static inline | ||
| 348 | int in_mem(unsigned long addr, unsigned long size, | ||
| 349 | unsigned long start, unsigned long end) | ||
| 350 | { | ||
| 351 | return addr >= start && addr + size <= end; | ||
| 352 | } | ||
| 353 | static inline | ||
| 354 | int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off, | ||
| 355 | unsigned long const_addr, unsigned long const_size) | ||
| 356 | { | ||
| 357 | return const_size && | ||
| 358 | in_mem(addr, size, const_addr + off, const_addr + const_size); | ||
| 359 | } | ||
| 360 | static inline | ||
| 361 | int in_mem_const(unsigned long addr, unsigned long size, | ||
| 362 | unsigned long const_addr, unsigned long const_size) | ||
| 363 | { | ||
| 364 | return in_mem_const_off(addr, 0, size, const_addr, const_size); | ||
| 365 | } | ||
| 366 | #define IN_ASYNC(bnum, bctlnum) \ | ||
| 367 | ({ \ | ||
| 368 | (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? -EFAULT : \ | ||
| 369 | bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? -EFAULT : \ | ||
| 370 | BFIN_MEM_ACCESS_CORE; \ | ||
| 371 | }) | ||
| 372 | |||
| 373 | int bfin_mem_access_type(unsigned long addr, unsigned long size) | ||
| 374 | { | ||
| 375 | int cpu = raw_smp_processor_id(); | ||
| 376 | |||
| 377 | /* Check that things do not wrap around */ | ||
| 378 | if (addr > ULONG_MAX - size) | ||
| 379 | return -EFAULT; | ||
| 380 | |||
| 381 | if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end)) | ||
| 382 | return BFIN_MEM_ACCESS_CORE; | ||
| 383 | |||
| 384 | if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH)) | ||
| 385 | return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; | ||
| 386 | if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH)) | ||
| 387 | return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; | ||
| 388 | if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH)) | ||
| 389 | return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; | ||
| 390 | if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) | ||
| 391 | return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; | ||
| 392 | #ifdef COREB_L1_CODE_START | ||
| 393 | if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) | ||
| 394 | return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA; | ||
| 395 | if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) | ||
| 396 | return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT; | ||
| 397 | if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) | ||
| 398 | return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; | ||
| 399 | if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) | ||
| 400 | return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA; | ||
| 401 | #endif | ||
| 402 | if (in_mem_const(addr, size, L2_START, L2_LENGTH)) | ||
| 403 | return BFIN_MEM_ACCESS_CORE; | ||
| 404 | |||
| 405 | if (addr >= SYSMMR_BASE) | ||
| 406 | return BFIN_MEM_ACCESS_CORE_ONLY; | ||
| 407 | |||
| 408 | /* We can't read EBIU banks that aren't enabled or we end up hanging | ||
| 409 | * on the access to the async space. | ||
| 410 | */ | ||
| 411 | if (in_mem_const(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK0_SIZE)) | ||
| 412 | return IN_ASYNC(0, 0); | ||
| 413 | if (in_mem_const(addr, size, ASYNC_BANK1_BASE, ASYNC_BANK1_SIZE)) | ||
| 414 | return IN_ASYNC(1, 0); | ||
| 415 | if (in_mem_const(addr, size, ASYNC_BANK2_BASE, ASYNC_BANK2_SIZE)) | ||
| 416 | return IN_ASYNC(2, 1); | ||
| 417 | if (in_mem_const(addr, size, ASYNC_BANK3_BASE, ASYNC_BANK3_SIZE)) | ||
| 418 | return IN_ASYNC(3, 1); | ||
| 419 | |||
| 420 | if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH)) | ||
| 421 | return BFIN_MEM_ACCESS_CORE; | ||
| 422 | if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH)) | ||
| 423 | return BFIN_MEM_ACCESS_DMA; | ||
| 424 | |||
| 425 | return -EFAULT; | ||
| 426 | } | ||
| 427 | |||
| 347 | #if defined(CONFIG_ACCESS_CHECK) | 428 | #if defined(CONFIG_ACCESS_CHECK) |
| 348 | #ifdef CONFIG_ACCESS_OK_L1 | 429 | #ifdef CONFIG_ACCESS_OK_L1 |
| 349 | __attribute__((l1_text)) | 430 | __attribute__((l1_text)) |
| @@ -353,51 +434,61 @@ int _access_ok(unsigned long addr, unsigned long size) · 3 unmodified lines | |||
| 353 | { | 434 | { |
| 354 | if (size == 0) | 435 | if (size == 0) |
| 355 | return 1; | 436 | return 1; |
| 356 | if (addr > (addr + size)) | 437 | /* Check that things do not wrap around */ |
| 438 | if (addr > ULONG_MAX - size) | ||
| 357 | return 0; | 439 | return 0; |
| 358 | if (segment_eq(get_fs(), KERNEL_DS)) | 440 | if (segment_eq(get_fs(), KERNEL_DS)) |
| 359 | return 1; | 441 | return 1; |
| 360 | #ifdef CONFIG_MTD_UCLINUX | 442 | #ifdef CONFIG_MTD_UCLINUX |
| 361 | if (addr >= memory_start && (addr + size) <= memory_end) | 443 | if (1) |
| 362 | return 1; | 444 | #else |
| 363 | if (addr >= memory_mtd_end && (addr + size) <= physical_mem_end) | 445 | if (0) |
| 446 | #endif | ||
| 447 | { | ||
| 448 | if (in_mem(addr, size, memory_start, memory_end)) | ||
| 449 | return 1; | ||
| 450 | if (in_mem(addr, size, memory_mtd_end, physical_mem_end)) | ||
| 451 | return 1; | ||
| 452 | # ifndef CONFIG_ROMFS_ON_MTD | ||
| 453 | if (0) | ||
| 454 | # endif | ||
| 455 | /* For XIP, allow user space to use pointers within the ROMFS. */ | ||
| 456 | if (in_mem(addr, size, memory_mtd_start, memory_mtd_end)) | ||
| 457 | return 1; | ||
| 458 | } else { | ||
| 459 | if (in_mem(addr, size, memory_start, physical_mem_end)) | ||
| 460 | return 1; | ||
| 461 | } | ||
| 462 | |||
| 463 | if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end)) | ||
| 364 | return 1; | 464 | return 1; |
| 365 | 465 | ||
| 366 | #ifdef CONFIG_ROMFS_ON_MTD | 466 | if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH)) |
| 367 | /* For XIP, allow user space to use pointers within the ROMFS. */ | ||
| 368 | if (addr >= memory_mtd_start && (addr + size) <= memory_mtd_end) | ||
| 369 | return 1; | 467 | return 1; |
| 370 | #endif | 468 | if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH)) |
| 371 | #else | ||
| 372 | if (addr >= memory_start && (addr + size) <= physical_mem_end) | ||
| 373 | return 1; | 469 | return 1; |
| 374 | #endif | 470 | if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH)) |
| 375 | if (addr >= (unsigned long)__init_begin && | ||
| 376 | addr + size <= (unsigned long)__init_end) | ||
| 377 | return 1; | 471 | return 1; |
| 378 | if (addr >= get_l1_scratch_start() | 472 | if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH)) |
| 379 | && addr + size <= get_l1_scratch_start() + L1_SCRATCH_LENGTH) | ||
| 380 | return 1; | 473 | return 1; |
| 381 | #if L1_CODE_LENGTH != 0 | 474 | #ifdef COREB_L1_CODE_START |
| 382 | if (addr >= get_l1_code_start() + (_etext_l1 - _stext_l1) | 475 | if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) |
| 383 | && addr + size <= get_l1_code_start() + L1_CODE_LENGTH) | ||
| 384 | return 1; | 476 | return 1; |
| 385 | #endif | 477 | if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH)) |
| 386 | #if L1_DATA_A_LENGTH != 0 | ||
| 387 | if (addr >= get_l1_data_a_start() + (_ebss_l1 - _sdata_l1) | ||
| 388 | && addr + size <= get_l1_data_a_start() + L1_DATA_A_LENGTH) | ||
| 389 | return 1; | 478 | return 1; |
| 390 | #endif | 479 | if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) |
| 391 | #if L1_DATA_B_LENGTH != 0 | ||
| 392 | if (addr >= get_l1_data_b_start() + (_ebss_b_l1 - _sdata_b_l1) | ||
| 393 | && addr + size <= get_l1_data_b_start() + L1_DATA_B_LENGTH) | ||
| 394 | return 1; | 480 | return 1; |
| 395 | #endif | 481 | if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) |
| 396 | #if L2_LENGTH != 0 | ||
| 397 | if (addr >= L2_START + (_ebss_l2 - _stext_l2) | ||
| 398 | && addr + size <= L2_START + L2_LENGTH) | ||
| 399 | return 1; | 482 | return 1; |
| 400 | #endif | 483 | #endif |
| 484 | if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH)) | ||
| 485 | return 1; | ||
| 486 | |||
| 487 | if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH)) | ||
| 488 | return 1; | ||
| 489 | if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH)) | ||
| 490 | return 1; | ||
| 491 | |||
| 401 | return 0; | 492 | return 0; |
| 402 | } | 493 | } |
| 403 | EXPORT_SYMBOL(_access_ok); | 494 | EXPORT_SYMBOL(_access_ok); |
| @@ -117,15 +117,49 @@ void __cpuinit bfin_setup_caches(unsigned int cpu) · 116 unmodified lines | |||
| 117 | */ | 117 | */ |
| 118 | #ifdef CONFIG_BFIN_ICACHE | 118 | #ifdef CONFIG_BFIN_ICACHE |
| 119 | printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); | 119 | printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); |
| 120 | printk(KERN_INFO " External memory:" | ||
| 121 | # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE | ||
| 122 | " cacheable" | ||
| 123 | # else | ||
| 124 | " uncacheable" | ||
| 125 | # endif | ||
| 126 | " in instruction cache\n"); | ||
| 127 | if (L2_LENGTH) | ||
| 128 | printk(KERN_INFO " L2 SRAM :" | ||
| 129 | # ifdef CONFIG_BFIN_L2_ICACHEABLE | ||
| 130 | " cacheable" | ||
| 131 | # else | ||
| 132 | " uncacheable" | ||
| 133 | # endif | ||
| 134 | " in instruction cache\n"); | ||
| 135 | |||
| 136 | #else | ||
| 137 | printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu); | ||
| 120 | #endif | 138 | #endif |
| 139 | |||
| 121 | #ifdef CONFIG_BFIN_DCACHE | 140 | #ifdef CONFIG_BFIN_DCACHE |
| 122 | printk(KERN_INFO "Data Cache Enabled for CPU%u" | 141 | printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu); |
| 123 | # if defined CONFIG_BFIN_WB | 142 | printk(KERN_INFO " External memory:" |
| 124 | " (write-back)" | 143 | # if defined CONFIG_BFIN_EXTMEM_WRITEBACK |
| 125 | # elif defined CONFIG_BFIN_WT | 144 | " cacheable (write-back)" |
| 126 | " (write-through)" | 145 | # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH |
| 146 | " cacheable (write-through)" | ||
| 147 | # else | ||
| 148 | " uncacheable" | ||
| 127 | # endif | 149 | # endif |
| 128 | "\n", cpu); | 150 | " in data cache\n"); |
| 151 | if (L2_LENGTH) | ||
| 152 | printk(KERN_INFO " L2 SRAM :" | ||
| 153 | # if defined CONFIG_BFIN_L2_WRITEBACK | ||
| 154 | " cacheable (write-back)" | ||
| 155 | # elif defined CONFIG_BFIN_L2_WRITETHROUGH | ||
| 156 | " cacheable (write-through)" | ||
| 157 | # else | ||
| 158 | " uncacheable" | ||
| 159 | # endif | ||
| 160 | " in data cache\n"); | ||
| 161 | #else | ||
| 162 | printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu); | ||
| 129 | #endif | 163 | #endif |
| 130 | } | 164 | } |
| 131 | 165 | ||
| @@ -443,9 +477,11 @@ static __init void parse_cmdline_early(char *cmdline_p) · 311 unmodified lines | |||
| 443 | } else if (!memcmp(to, "clkin_hz=", 9)) { | 477 | } else if (!memcmp(to, "clkin_hz=", 9)) { |
| 444 | to += 9; | 478 | to += 9; |
| 445 | early_init_clkin_hz(to); | 479 | early_init_clkin_hz(to); |
| 480 | #ifdef CONFIG_EARLY_PRINTK | ||
| 446 | } else if (!memcmp(to, "earlyprintk=", 12)) { | 481 | } else if (!memcmp(to, "earlyprintk=", 12)) { |
| 447 | to += 12; | 482 | to += 12; |
| 448 | setup_early_printk(to); | 483 | setup_early_printk(to); |
| 484 | #endif | ||
| 449 | } else if (!memcmp(to, "memmap=", 7)) { | 485 | } else if (!memcmp(to, "memmap=", 7)) { |
| 450 | to += 7; | 486 | to += 7; |
| 451 | parse_memmap(to); | 487 | parse_memmap(to); |
| @@ -516,7 +552,7 @@ static __init void memory_setup(void) · 64 unmodified lines | |||
| 516 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) | 552 | && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) |
| 517 | mtd_size = | 553 | mtd_size = |
| 518 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); | 554 | PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); |
| 519 | # if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) | 555 | # if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) |
| 520 | /* Due to a Hardware Anomaly we need to limit the size of usable | 556 | /* Due to a Hardware Anomaly we need to limit the size of usable |
| 521 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | 557 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on |
| 522 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | 558 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception |
| @@ -544,7 +580,7 @@ static __init void memory_setup(void) · 21 unmodified lines | |||
| 544 | dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); | 580 | dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); |
| 545 | #endif /* CONFIG_MTD_UCLINUX */ | 581 | #endif /* CONFIG_MTD_UCLINUX */ |
| 546 | 582 | ||
| 547 | #if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) | 583 | #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) |
| 548 | /* Due to a Hardware Anomaly we need to limit the size of usable | 584 | /* Due to a Hardware Anomaly we need to limit the size of usable |
| 549 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on | 585 | * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on |
| 550 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception | 586 | * 05000263 - Hardware loop corrupted when taking an ICPLB exception |
| @@ -764,6 +800,11 @@ void __init setup_arch(char **cmdline_p) · 213 unmodified lines | |||
| 764 | { | 800 | { |
| 765 | unsigned long sclk, cclk; | 801 | unsigned long sclk, cclk; |
| 766 | 802 | ||
| 803 | /* Check to make sure we are running on the right processor */ | ||
| 804 | if (unlikely(CPUID != bfin_cpuid())) | ||
| 805 | printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", | ||
| 806 | CPU, bfin_cpuid(), bfin_revid()); | ||
| 807 | |||
| 767 | #ifdef CONFIG_DUMMY_CONSOLE | 808 | #ifdef CONFIG_DUMMY_CONSOLE |
| 768 | conswitchp = &dummy_con; | 809 | conswitchp = &dummy_con; |
| 769 | #endif | 810 | #endif |
| @@ -778,14 +819,17 @@ void __init setup_arch(char **cmdline_p) · 8 unmodified lines | |||
| 778 | memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); | 819 | memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); |
| 779 | boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; | 820 | boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; |
| 780 | 821 | ||
| 781 | /* setup memory defaults from the user config */ | ||
| 782 | physical_mem_end = 0; | ||
| 783 | _ramend = get_mem_size() * 1024 * 1024; | ||
| 784 | |||
| 785 | memset(&bfin_memmap, 0, sizeof(bfin_memmap)); | 822 | memset(&bfin_memmap, 0, sizeof(bfin_memmap)); |
| 786 | 823 | ||
| 824 | /* If the user does not specify things on the command line, use | ||
| 825 | * what the bootloader set things up as | ||
| 826 | */ | ||
| 827 | physical_mem_end = 0; | ||
| 787 | parse_cmdline_early(&command_line[0]); | 828 | parse_cmdline_early(&command_line[0]); |
| 788 | 829 | ||
| 830 | if (_ramend == 0) | ||
| 831 | _ramend = get_mem_size() * 1024 * 1024; | ||
| 832 | |||
| 789 | if (physical_mem_end == 0) | 833 | if (physical_mem_end == 0) |
| 790 | physical_mem_end = _ramend; | 834 | physical_mem_end = _ramend; |
| 791 | 835 | ||
| @@ -837,7 +881,8 @@ void __init setup_arch(char **cmdline_p) · 45 unmodified lines | |||
| 837 | defined(CONFIG_BF538) || defined(CONFIG_BF539) | 881 | defined(CONFIG_BF538) || defined(CONFIG_BF539) |
| 838 | _bfin_swrst = bfin_read_SWRST(); | 882 | _bfin_swrst = bfin_read_SWRST(); |
| 839 | #else | 883 | #else |
| 840 | _bfin_swrst = bfin_read_SYSCR(); | 884 | /* Clear boot mode field */ |
| 885 | _bfin_swrst = bfin_read_SYSCR() & ~0xf; | ||
| 841 | #endif | 886 | #endif |
| 842 | 887 | ||
| 843 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT | 888 | #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT |
| @@ -875,10 +920,7 @@ void __init setup_arch(char **cmdline_p) · 31 unmodified lines | |||
| 875 | else | 920 | else |
| 876 | printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid()); | 921 | printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid()); |
| 877 | 922 | ||
| 878 | if (unlikely(CPUID != bfin_cpuid())) | 923 | if (likely(CPUID == bfin_cpuid())) { |
| 879 | printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", | ||
| 880 | CPU, bfin_cpuid(), bfin_revid()); | ||
| 881 | else { | ||
| 882 | if (bfin_revid() != bfin_compiled_revid()) { | 924 | if (bfin_revid() != bfin_compiled_revid()) { |
| 883 | if (bfin_compiled_revid() == -1) | 925 | if (bfin_compiled_revid() == -1) |
| 884 | printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", | 926 | printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", |
| @@ -1157,16 +1199,25 @@ static int show_cpuinfo(struct seq_file *m, void *v) · 272 unmodified lines | |||
| 1157 | icache_size = 0; | 1199 | icache_size = 0; |
| 1158 | 1200 | ||
| 1159 | seq_printf(m, "cache size\t: %d KB(L1 icache) " | 1201 | seq_printf(m, "cache size\t: %d KB(L1 icache) " |
| 1160 | "%d KB(L1 dcache%s) %d KB(L2 cache)\n", | 1202 | "%d KB(L1 dcache) %d KB(L2 cache)\n", |
| 1161 | icache_size, dcache_size, | 1203 | icache_size, dcache_size, 0); |
| 1162 | #if defined CONFIG_BFIN_WB | ||
| 1163 | "-wb" | ||
| 1164 | #elif defined CONFIG_BFIN_WT | ||
| 1165 | "-wt" | ||
| 1166 | #endif | ||
| 1167 | "", 0); | ||
| 1168 | |||
| 1169 | seq_printf(m, "%s\n", cache); | 1204 | seq_printf(m, "%s\n", cache); |
| 1205 | seq_printf(m, "external memory\t: " | ||
| 1206 | #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) | ||
| 1207 | "cacheable" | ||
| 1208 | #else | ||
| 1209 | "uncacheable" | ||
| 1210 | #endif | ||
| 1211 | " in instruction cache\n"); | ||
| 1212 | seq_printf(m, "external memory\t: " | ||
| 1213 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) | ||
| 1214 | "cacheable (write-back)" | ||
| 1215 | #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) | ||
| 1216 | "cacheable (write-through)" | ||
| 1217 | #else | ||
| 1218 | "uncacheable" | ||
| 1219 | #endif | ||
| 1220 | " in data cache\n"); | ||
| 1170 | 1221 | ||
| 1171 | if (icache_size) | 1222 | if (icache_size) |
| 1172 | seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", | 1223 | seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", |
| @@ -1239,8 +1290,25 @@ static int show_cpuinfo(struct seq_file *m, void *v) · 66 unmodified lines | |||
| 1239 | if (cpu_num != num_possible_cpus() - 1) | 1290 | if (cpu_num != num_possible_cpus() - 1) |
| 1240 | return 0; | 1291 | return 0; |
| 1241 | 1292 | ||
| 1242 | if (L2_LENGTH) | 1293 | if (L2_LENGTH) { |
| 1243 | seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); | 1294 | seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); |
| 1295 | seq_printf(m, "L2 SRAM\t\t: " | ||
| 1296 | #if defined(CONFIG_BFIN_L2_ICACHEABLE) | ||
| 1297 | "cacheable" | ||
| 1298 | #else | ||
| 1299 | "uncacheable" | ||
| 1300 | #endif | ||
| 1301 | " in instruction cache\n"); | ||
| 1302 | seq_printf(m, "L2 SRAM\t\t: " | ||
| 1303 | #if defined(CONFIG_BFIN_L2_WRITEBACK) | ||
| 1304 | "cacheable (write-back)" | ||
| 1305 | #elif defined(CONFIG_BFIN_L2_WRITETHROUGH) | ||
| 1306 | "cacheable (write-through)" | ||
| 1307 | #else | ||
| 1308 | "uncacheable" | ||
| 1309 | #endif | ||
| 1310 | " in data cache\n"); | ||
| 1311 | } | ||
| 1244 | seq_printf(m, "board name\t: %s\n", bfin_board_name); | 1312 | seq_printf(m, "board name\t: %s\n", bfin_board_name); |
| 1245 | seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", | 1313 | seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", |
| 1246 | physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); | 1314 | physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); |
| @@ -37,6 +37,7 @@ · 36 unmodified lines | |||
| 37 | #include <asm/traps.h> | 37 | #include <asm/traps.h> |
| 38 | #include <asm/cacheflush.h> | 38 | #include <asm/cacheflush.h> |
| 39 | #include <asm/cplb.h> | 39 | #include <asm/cplb.h> |
| 40 | #include <asm/dma.h> | ||
| 40 | #include <asm/blackfin.h> | 41 | #include <asm/blackfin.h> |
| 41 | #include <asm/irq_handler.h> | 42 | #include <asm/irq_handler.h> |
| 42 | #include <linux/irq.h> | 43 | #include <linux/irq.h> |
| @@ -636,57 +637,30 @@ asmlinkage void trap_c(struct pt_regs *fp) · 593 unmodified lines | |||
| 636 | */ | 637 | */ |
| 637 | static bool get_instruction(unsigned short *val, unsigned short *address) | 638 | static bool get_instruction(unsigned short *val, unsigned short *address) |
| 638 | { | 639 | { |
| 639 | 640 | unsigned long addr = (unsigned long)address; | |
| 640 | unsigned long addr; | ||
| 641 | |||
| 642 | addr = (unsigned long)address; | ||
| 643 | 641 | ||
| 644 | /* Check for odd addresses */ | 642 | /* Check for odd addresses */ |
| 645 | if (addr & 0x1) | 643 | if (addr & 0x1) |
| 646 | return false; | 644 | return false; |
| 647 | 645 | ||
| 648 | /* Check that things do not wrap around */ | 646 | /* MMR region will never have instructions */ |
| 649 | if (addr > (addr + 2)) | 647 | if (addr >= SYSMMR_BASE) |
| 650 | return false; | 648 | return false; |
| 651 | 649 | ||
| 652 | /* | 650 | switch (bfin_mem_access_type(addr, 2)) { |
| 653 | * Since we are in exception context, we need to do a little address checking | 651 | case BFIN_MEM_ACCESS_CORE: |
| 654 | * We need to make sure we are only accessing valid memory, and | 652 | case BFIN_MEM_ACCESS_CORE_ONLY: |
| 655 | * we don't read something in the async space that can hang forever | 653 | *val = *address; |
| 656 | */ | 654 | return true; |
| 657 | if ((addr >= FIXED_CODE_START && (addr + 2) <= physical_mem_end) || | 655 | case BFIN_MEM_ACCESS_DMA: |
| 658 | #if L2_LENGTH != 0 | 656 | dma_memcpy(val, address, 2); |
| 659 | (addr >= L2_START && (addr + 2) <= (L2_START + L2_LENGTH)) || | 657 | return true; |
| 660 | #endif | 658 | case BFIN_MEM_ACCESS_ITEST: |
| 661 | (addr >= BOOT_ROM_START && (addr + 2) <= (BOOT_ROM_START + BOOT_ROM_LENGTH)) || | 659 | isram_memcpy(val, address, 2); |
| 662 | #if L1_DATA_A_LENGTH != 0 | 660 | return true; |
| 663 | (addr >= L1_DATA_A_START && (addr + 2) <= (L1_DATA_A_START + L1_DATA_A_LENGTH)) || | 661 | default: /* invalid access */ |
| 664 | #endif | 662 | return false; |
| 665 | #if L1_DATA_B_LENGTH != 0 | ||
| 666 | (addr >= L1_DATA_B_START && (addr + 2) <= (L1_DATA_B_START + L1_DATA_B_LENGTH)) || | ||
| 667 | #endif | ||
| 668 | (addr >= L1_SCRATCH_START && (addr + 2) <= (L1_SCRATCH_START + L1_SCRATCH_LENGTH)) || | ||
| 669 | (!(bfin_read_EBIU_AMBCTL0() & B0RDYEN) && | ||
| 670 | addr >= ASYNC_BANK0_BASE && (addr + 2) <= (ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)) || | ||
| 671 | (!(bfin_read_EBIU_AMBCTL0() & B1RDYEN) && | ||
| 672 | addr >= ASYNC_BANK1_BASE && (addr + 2) <= (ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)) || | ||
| 673 | (!(bfin_read_EBIU_AMBCTL1() & B2RDYEN) && | ||
| 674 | addr >= ASYNC_BANK2_BASE && (addr + 2) <= (ASYNC_BANK2_BASE + ASYNC_BANK1_SIZE)) || | ||
| 675 | (!(bfin_read_EBIU_AMBCTL1() & B3RDYEN) && | ||
| 676 | addr >= ASYNC_BANK3_BASE && (addr + 2) <= (ASYNC_BANK3_BASE + ASYNC_BANK1_SIZE))) { | ||
| 677 | *val = *address; | ||
| 678 | return true; | ||
| 679 | } | 663 | } |
| 680 | |||
| 681 | #if L1_CODE_LENGTH != 0 | ||
| 682 | if (addr >= L1_CODE_START && (addr + 2) <= (L1_CODE_START + L1_CODE_LENGTH)) { | ||
| 683 | isram_memcpy(val, address, 2); | ||
| 684 | return true; | ||
| 685 | } | ||
| 686 | #endif | ||
| 687 | |||
| 688 | |||
| 689 | return false; | ||
| 690 | } | 664 | } |
| 691 | 665 | ||
| 692 | /* | 666 | /* |
| @@ -119,13 +119,19 @@ static struct platform_device bfin_mac_device = { · 118 unmodified lines | |||
| 119 | }; | 119 | }; |
| 120 | 120 | ||
| 121 | #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) | 121 | #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) |
| 122 | static struct dsa_platform_data ksz8893m_switch_data = { | 122 | static struct dsa_chip_data ksz8893m_switch_chip_data = { |
| 123 | .mii_bus = &bfin_mii_bus.dev, | 123 | .mii_bus = &bfin_mii_bus.dev, |
| 124 | .port_names = { | ||
| 125 | NULL, | ||
| 126 | "eth%d", | ||
| 127 | "eth%d", | ||
| 128 | "cpu", | ||
| 129 | }, | ||
| 130 | }; | ||
| 131 | static struct dsa_platform_data ksz8893m_switch_data = { | ||
| 132 | .nr_chips = 1, | ||
| 124 | .netdev = &bfin_mac_device.dev, | 133 | .netdev = &bfin_mac_device.dev, |
| 125 | .port_names[0] = NULL, | 134 | .chip = &ksz8893m_switch_chip_data, |
| 126 | .port_names[1] = "eth%d", | ||
| 127 | .port_names[2] = "eth%d", | ||
| 128 | .port_names[3] = "cpu", | ||
| 129 | }; | 135 | }; |
| 130 | 136 | ||
| 131 | static struct platform_device ksz8893m_switch_device = { | 137 | static struct platform_device ksz8893m_switch_device = { |
| @@ -7,7 +7,7 @@ · 6 unmodified lines | |||
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file should be up to date with: | 9 | /* This file should be up to date with: |
| 10 | * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List | 10 | * - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ | 13 | /* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ |
| @@ -18,7 +18,7 @@ · 4 unmodified lines | |||
| 18 | #ifndef _MACH_ANOMALY_H_ | 18 | #ifndef _MACH_ANOMALY_H_ |
| 19 | #define _MACH_ANOMALY_H_ | 19 | #define _MACH_ANOMALY_H_ |
| 20 | 20 | ||
| 21 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | 21 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
| 22 | #define ANOMALY_05000074 (1) | 22 | #define ANOMALY_05000074 (1) |
| 23 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 23 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 24 | #define ANOMALY_05000122 (1) | 24 | #define ANOMALY_05000122 (1) |
| @@ -45,29 +45,31 @@ · 20 unmodified lines | |||
| 45 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ | 45 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ |
| 46 | #define ANOMALY_05000426 (1) | 46 | #define ANOMALY_05000426 (1) |
| 47 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ | 47 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ |
| 48 | #define ANOMALY_05000430 (1) | 48 | #define ANOMALY_05000430 (__SILICON_REVISION__ < 1) |
| 49 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ | 49 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ |
| 50 | #define ANOMALY_05000431 (1) | 50 | #define ANOMALY_05000431 (1) |
| 51 | /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ | 51 | /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ |
| 52 | #define ANOMALY_05000435 (1) | 52 | #define ANOMALY_05000435 (__SILICON_REVISION__ < 1) |
| 53 | /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ | 53 | /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ |
| 54 | #define ANOMALY_05000438 (1) | 54 | #define ANOMALY_05000438 (__SILICON_REVISION__ < 1) |
| 55 | /* Preboot Cannot be Used to Alter the PLL_DIV Register */ | 55 | /* Preboot Cannot be Used to Alter the PLL_DIV Register */ |
| 56 | #define ANOMALY_05000439 (1) | 56 | #define ANOMALY_05000439 (__SILICON_REVISION__ < 1) |
| 57 | /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ | 57 | /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ |
| 58 | #define ANOMALY_05000440 (1) | 58 | #define ANOMALY_05000440 (__SILICON_REVISION__ < 1) |
| 59 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 59 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 60 | #define ANOMALY_05000443 (1) | 60 | #define ANOMALY_05000443 (1) |
| 61 | /* Incorrect L1 Instruction Bank B Memory Map Location */ | 61 | /* Incorrect L1 Instruction Bank B Memory Map Location */ |
| 62 | #define ANOMALY_05000444 (1) | 62 | #define ANOMALY_05000444 (__SILICON_REVISION__ < 1) |
| 63 | /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ | 63 | /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ |
| 64 | #define ANOMALY_05000452 (1) | 64 | #define ANOMALY_05000452 (__SILICON_REVISION__ < 1) |
| 65 | /* PWM_TRIPB Signal Not Available on PG10 */ | 65 | /* PWM_TRIPB Signal Not Available on PG10 */ |
| 66 | #define ANOMALY_05000453 (1) | 66 | #define ANOMALY_05000453 (__SILICON_REVISION__ < 1) |
| 67 | /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ | 67 | /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ |
| 68 | #define ANOMALY_05000455 (1) | 68 | #define ANOMALY_05000455 (__SILICON_REVISION__ < 1) |
| 69 | /* False Hardware Error when RETI points to invalid memory */ | 69 | /* False Hardware Error when RETI Points to Invalid Memory */ |
| 70 | #define ANOMALY_05000461 (1) | 70 | #define ANOMALY_05000461 (1) |
| 71 | /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ | ||
| 72 | #define ANOMALY_05000462 (1) | ||
| 71 | 73 | ||
| 72 | /* Anomalies that don't exist on this proc */ | 74 | /* Anomalies that don't exist on this proc */ |
| 73 | #define ANOMALY_05000099 (0) | 75 | #define ANOMALY_05000099 (0) |
| @@ -78,24 +80,30 @@ · 4 unmodified lines | |||
| 78 | #define ANOMALY_05000158 (0) | 80 | #define ANOMALY_05000158 (0) |
| 79 | #define ANOMALY_05000171 (0) | 81 | #define ANOMALY_05000171 (0) |
| 80 | #define ANOMALY_05000179 (0) | 82 | #define ANOMALY_05000179 (0) |
| 83 | #define ANOMALY_05000182 (0) | ||
| 81 | #define ANOMALY_05000183 (0) | 84 | #define ANOMALY_05000183 (0) |
| 82 | #define ANOMALY_05000198 (0) | 85 | #define ANOMALY_05000198 (0) |
| 86 | #define ANOMALY_05000202 (0) | ||
| 83 | #define ANOMALY_05000215 (0) | 87 | #define ANOMALY_05000215 (0) |
| 84 | #define ANOMALY_05000220 (0) | 88 | #define ANOMALY_05000220 (0) |
| 85 | #define ANOMALY_05000227 (0) | 89 | #define ANOMALY_05000227 (0) |
| 86 | #define ANOMALY_05000230 (0) | 90 | #define ANOMALY_05000230 (0) |
| 87 | #define ANOMALY_05000231 (0) | 91 | #define ANOMALY_05000231 (0) |
| 88 | #define ANOMALY_05000233 (0) | 92 | #define ANOMALY_05000233 (0) |
| 93 | #define ANOMALY_05000234 (0) | ||
| 89 | #define ANOMALY_05000242 (0) | 94 | #define ANOMALY_05000242 (0) |
| 90 | #define ANOMALY_05000244 (0) | 95 | #define ANOMALY_05000244 (0) |
| 91 | #define ANOMALY_05000248 (0) | 96 | #define ANOMALY_05000248 (0) |
| 92 | #define ANOMALY_05000250 (0) | 97 | #define ANOMALY_05000250 (0) |
| 98 | #define ANOMALY_05000257 (0) | ||
| 93 | #define ANOMALY_05000261 (0) | 99 | #define ANOMALY_05000261 (0) |
| 94 | #define ANOMALY_05000263 (0) | 100 | #define ANOMALY_05000263 (0) |
| 95 | #define ANOMALY_05000266 (0) | 101 | #define ANOMALY_05000266 (0) |
| 96 | #define ANOMALY_05000273 (0) | 102 | #define ANOMALY_05000273 (0) |
| 97 | #define ANOMALY_05000274 (0) | 103 | #define ANOMALY_05000274 (0) |
| 98 | #define ANOMALY_05000278 (0) | 104 | #define ANOMALY_05000278 (0) |
| 105 | #define ANOMALY_05000281 (0) | ||
| 106 | #define ANOMALY_05000283 (0) | ||
| 99 | #define ANOMALY_05000285 (0) | 107 | #define ANOMALY_05000285 (0) |
| 100 | #define ANOMALY_05000287 (0) | 108 | #define ANOMALY_05000287 (0) |
| 101 | #define ANOMALY_05000301 (0) | 109 | #define ANOMALY_05000301 (0) |
| @@ -103,10 +111,13 @@ · 1 unmodified line | |||
| 103 | #define ANOMALY_05000307 (0) | 111 | #define ANOMALY_05000307 (0) |
| 104 | #define ANOMALY_05000311 (0) | 112 | #define ANOMALY_05000311 (0) |
| 105 | #define ANOMALY_05000312 (0) | 113 | #define ANOMALY_05000312 (0) |
| 114 | #define ANOMALY_05000315 (0) | ||
| 106 | #define ANOMALY_05000323 (0) | 115 | #define ANOMALY_05000323 (0) |
| 107 | #define ANOMALY_05000353 (0) | 116 | #define ANOMALY_05000353 (0) |
| 117 | #define ANOMALY_05000357 (0) | ||
| 108 | #define ANOMALY_05000362 (1) | 118 | #define ANOMALY_05000362 (1) |
| 109 | #define ANOMALY_05000363 (0) | 119 | #define ANOMALY_05000363 (0) |
| 120 | #define ANOMALY_05000371 (0) | ||
| 110 | #define ANOMALY_05000380 (0) | 121 | #define ANOMALY_05000380 (0) |
| 111 | #define ANOMALY_05000386 (0) | 122 | #define ANOMALY_05000386 (0) |
| 112 | #define ANOMALY_05000389 (0) | 123 | #define ANOMALY_05000389 (0) |
| @@ -117,5 +128,7 @@ · 4 unmodified lines | |||
| 117 | #define ANOMALY_05000448 (0) | 128 | #define ANOMALY_05000448 (0) |
| 118 | #define ANOMALY_05000456 (0) | 129 | #define ANOMALY_05000456 (0) |
| 119 | #define ANOMALY_05000450 (0) | 130 | #define ANOMALY_05000450 (0) |
| 131 | #define ANOMALY_05000465 (0) | ||
| 132 | #define ANOMALY_05000467 (0) | ||
| 120 | 133 | ||
| 121 | #endif | 134 | #endif |
| @@ -33,7 +33,6 @@ · 32 unmodified lines | |||
| 33 | #define _MACH_BLACKFIN_H_ | 33 | #define _MACH_BLACKFIN_H_ |
| 34 | 34 | ||
| 35 | #include "bf518.h" | 35 | #include "bf518.h" |
| 36 | #include "mem_map.h" | ||
| 37 | #include "defBF512.h" | 36 | #include "defBF512.h" |
| 38 | #include "anomaly.h" | 37 | #include "anomaly.h" |
| 39 | 38 | ||
| @@ -1,38 +1,16 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * file: include/asm-blackfin/mach-bf518/mem_map.h | 2 | * BF51x memory map |
| 3 | * based on: include/asm-blackfin/mach-bf527/mem_map.h | ||
| 4 | * author: Bryan Wu <cooloney@kernel.org> | ||
| 5 | * | 3 | * |
| 6 | * created: | 4 | * Copyright 2004-2009 Analog Devices Inc. |
| 7 | * description: | 5 | * Licensed under the GPL-2 or later. |
| 8 | * Memory MAP Common header file for blackfin BF518/6/4/2 of processors. | ||
| 9 | * rev: | ||
| 10 | * | ||
| 11 | * modified: | ||
| 12 | * | ||
| 13 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * this program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the gnu general public license as published by | ||
| 17 | * the free software foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * this program is distributed in the hope that it will be useful, | ||
| 21 | * but without any warranty; without even the implied warranty of | ||
| 22 | * merchantability or fitness for a particular purpose. see the | ||
| 23 | * gnu general public license for more details. | ||
| 24 | * | ||
| 25 | * you should have received a copy of the gnu general public license | ||
| 26 | * along with this program; see the file copying. | ||
| 27 | * if not, write to the free software foundation, | ||
| 28 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 29 | */ | 6 | */ |
| 30 | 7 | ||
| 31 | #ifndef _MEM_MAP_518_H_ | 8 | #ifndef __BFIN_MACH_MEM_MAP_H__ |
| 32 | #define _MEM_MAP_518_H_ | 9 | #define __BFIN_MACH_MEM_MAP_H__ |
| 33 | 10 | ||
| 34 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ | 11 | #ifndef __BFIN_MEM_MAP_H__ |
| 35 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ | 12 | # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" |
| 13 | #endif | ||
| 36 | 14 | ||
| 37 | /* Async Memory Banks */ | 15 | /* Async Memory Banks */ |
| 38 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ | 16 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ |
| @@ -89,20 +67,4 @@ · 50 unmodified lines | |||
| 89 | #define BFIN_DSUPBANKS 0 | 67 | #define BFIN_DSUPBANKS 0 |
| 90 | #endif /*CONFIG_BFIN_DCACHE */ | 68 | #endif /*CONFIG_BFIN_DCACHE */ |
| 91 | 69 | ||
| 92 | /* Level 2 Memory - none */ | 70 | #endif |
| 93 | |||
| 94 | #define L2_START 0 | ||
| 95 | #define L2_LENGTH 0 | ||
| 96 | |||
| 97 | /* Scratch Pad Memory */ | ||
| 98 | |||
| 99 | #define L1_SCRATCH_START 0xFFB00000 | ||
| 100 | #define L1_SCRATCH_LENGTH 0x1000 | ||
| 101 | |||
| 102 | #define GET_PDA_SAFE(preg) \ | ||
| 103 | preg.l = _cpu_pda; \ | ||
| 104 | preg.h = _cpu_pda; | ||
| 105 | |||
| 106 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 107 | |||
| 108 | #endif /* _MEM_MAP_518_H_ */ | ||
| @@ -78,7 +78,6 @@ static struct resource bfin_isp1760_resources[] = { · 77 unmodified lines | |||
| 78 | 78 | ||
| 79 | static struct isp1760_platform_data isp1760_priv = { | 79 | static struct isp1760_platform_data isp1760_priv = { |
| 80 | .is_isp1761 = 0, | 80 | .is_isp1761 = 0, |
| 81 | .port1_disable = 0, | ||
| 82 | .bus_width_16 = 1, | 81 | .bus_width_16 = 1, |
| 83 | .port1_otg = 0, | 82 | .port1_otg = 0, |
| 84 | .analog_oc = 0, | 83 | .analog_oc = 0, |
| @@ -237,10 +237,10 @@ static struct flash_platform_data bfin_spi_flash_data = { · 236 unmodified lines | |||
| 237 | .name = "m25p80", | 237 | .name = "m25p80", |
| 238 | .parts = bfin_spi_flash_partitions, | 238 | .parts = bfin_spi_flash_partitions, |
| 239 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | 239 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), |
| 240 | .type = "m25p16", | 240 | .type = "sst25wf040", |
| 241 | }; | 241 | }; |
| 242 | 242 | ||
| 243 | /* SPI flash chip (m25p64) */ | 243 | /* SPI flash chip (sst25wf040) */ |
| 244 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | 244 | static struct bfin5xx_spi_chip spi_flash_chip_info = { |
| 245 | .enable_dma = 0, /* use dma transfer with this chip*/ | 245 | .enable_dma = 0, /* use dma transfer with this chip*/ |
| 246 | .bits_per_word = 8, | 246 | .bits_per_word = 8, |
| @@ -77,7 +77,6 @@ static struct resource bfin_isp1760_resources[] = { · 76 unmodified lines | |||
| 77 | 77 | ||
| 78 | static struct isp1760_platform_data isp1760_priv = { | 78 | static struct isp1760_platform_data isp1760_priv = { |
| 79 | .is_isp1761 = 0, | 79 | .is_isp1761 = 0, |
| 80 | .port1_disable = 0, | ||
| 81 | .bus_width_16 = 1, | 80 | .bus_width_16 = 1, |
| 82 | .port1_otg = 0, | 81 | .port1_otg = 0, |
| 83 | .analog_oc = 0, | 82 | .analog_oc = 0, |
| @@ -34,7 +34,7 @@ · 33 unmodified lines | |||
| 34 | #define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) | 34 | #define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) |
| 35 | #define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) | 35 | #define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) |
| 36 | 36 | ||
| 37 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | 37 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
| 38 | #define ANOMALY_05000074 (1) | 38 | #define ANOMALY_05000074 (1) |
| 39 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | 39 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
| 40 | #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ | 40 | #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ |
| @@ -184,8 +184,12 @@ · 143 unmodified lines | |||
| 184 | #define ANOMALY_05000456 (1) | 184 | #define ANOMALY_05000456 (1) |
| 185 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ | 185 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ |
| 186 | #define ANOMALY_05000457 (1) | 186 | #define ANOMALY_05000457 (1) |
| 187 | /* False Hardware Error when RETI points to invalid memory */ | 187 | /* False Hardware Error when RETI Points to Invalid Memory */ |
| 188 | #define ANOMALY_05000461 (1) | 188 | #define ANOMALY_05000461 (1) |
| 189 | /* USB Rx DMA hang */ | ||
| 190 | #define ANOMALY_05000465 (1) | ||
| 191 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ | ||
| 192 | #define ANOMALY_05000467 (1) | ||
| 189 | 193 | ||
| 190 | /* Anomalies that don't exist on this proc */ | 194 | /* Anomalies that don't exist on this proc */ |
| 191 | #define ANOMALY_05000099 (0) | 195 | #define ANOMALY_05000099 (0) |
| @@ -195,24 +199,30 @@ · 3 unmodified lines | |||
| 195 | #define ANOMALY_05000158 (0) | 199 | #define ANOMALY_05000158 (0) |
| 196 | #define ANOMALY_05000171 (0) | 200 | #define ANOMALY_05000171 (0) |
| 197 | #define ANOMALY_05000179 (0) | 201 | #define ANOMALY_05000179 (0) |
| 202 | #define ANOMALY_05000182 (0) | ||
| 198 | #define ANOMALY_05000183 (0) | 203 | #define ANOMALY_05000183 (0) |
| 199 | #define ANOMALY_05000198 (0) | 204 | #define ANOMALY_05000198 (0) |
| 205 | #define ANOMALY_05000202 (0) | ||
| 200 | #define ANOMALY_05000215 (0) | 206 | #define ANOMALY_05000215 (0) |
| 201 | #define ANOMALY_05000220 (0) | 207 | #define ANOMALY_05000220 (0) |
| 202 | #define ANOMALY_05000227 (0) | 208 | #define ANOMALY_05000227 (0) |
| 203 | #define ANOMALY_05000230 (0) | 209 | #define ANOMALY_05000230 (0) |
| 204 | #define ANOMALY_05000231 (0) | 210 | #define ANOMALY_05000231 (0) |
| 205 | #define ANOMALY_05000233 (0) | 211 | #define ANOMALY_05000233 (0) |
| 212 | #define ANOMALY_05000234 (0) | ||
| 206 | #define ANOMALY_05000242 (0) | 213 | #define ANOMALY_05000242 (0) |
| 207 | #define ANOMALY_05000244 (0) | 214 | #define ANOMALY_05000244 (0) |
| 208 | #define ANOMALY_05000248 (0) | 215 | #define ANOMALY_05000248 (0) |
| 209 | #define ANOMALY_05000250 (0) | 216 | #define ANOMALY_05000250 (0) |
| 217 | #define ANOMALY_05000257 (0) | ||
| 210 | #define ANOMALY_05000261 (0) | 218 | #define ANOMALY_05000261 (0) |
| 211 | #define ANOMALY_05000263 (0) | 219 | #define ANOMALY_05000263 (0) |
| 212 | #define ANOMALY_05000266 (0) | 220 | #define ANOMALY_05000266 (0) |
| 213 | #define ANOMALY_05000273 (0) | 221 | #define ANOMALY_05000273 (0) |
| 214 | #define ANOMALY_05000274 (0) | 222 | #define ANOMALY_05000274 (0) |
| 215 | #define ANOMALY_05000278 (0) | 223 | #define ANOMALY_05000278 (0) |
| 224 | #define ANOMALY_05000281 (0) | ||
| 225 | #define ANOMALY_05000283 (0) | ||
| 216 | #define ANOMALY_05000285 (0) | 226 | #define ANOMALY_05000285 (0) |
| 217 | #define ANOMALY_05000287 (0) | 227 | #define ANOMALY_05000287 (0) |
| 218 | #define ANOMALY_05000301 (0) | 228 | #define ANOMALY_05000301 (0) |
| @@ -220,6 +230,7 @@ · 1 unmodified line | |||
| 220 | #define ANOMALY_05000307 (0) | 230 | #define ANOMALY_05000307 (0) |
| 221 | #define ANOMALY_05000311 (0) | 231 | #define ANOMALY_05000311 (0) |
| 222 | #define ANOMALY_05000312 (0) | 232 | #define ANOMALY_05000312 (0) |
| 233 | #define ANOMALY_05000315 (0) | ||
| 223 | #define ANOMALY_05000323 (0) | 234 | #define ANOMALY_05000323 (0) |
| 224 | #define ANOMALY_05000362 (1) | 235 | #define ANOMALY_05000362 (1) |
| 225 | #define ANOMALY_05000363 (0) | 236 | #define ANOMALY_05000363 (0) |
| @@ -33,7 +33,6 @@ · 32 unmodified lines | |||
| 33 | #define _MACH_BLACKFIN_H_ | 33 | #define _MACH_BLACKFIN_H_ |
| 34 | 34 | ||
| 35 | #include "bf527.h" | 35 | #include "bf527.h" |
| 36 | #include "mem_map.h" | ||
| 37 | #include "defBF522.h" | 36 | #include "defBF522.h" |
| 38 | #include "anomaly.h" | 37 | #include "anomaly.h" |
| 39 | 38 | ||
| @@ -1,38 +1,16 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * file: include/asm-blackfin/mach-bf527/mem_map.h | 2 | * BF52x memory map |
| 3 | * based on: include/asm-blackfin/mach-bf537/mem_map.h | ||
| 4 | * author: Michael Hennerich (michael.hennerich@analog.com) | ||
| 5 | * | 3 | * |
| 6 | * created: | 4 | * Copyright 2004-2009 Analog Devices Inc. |
| 7 | * description: | 5 | * Licensed under the GPL-2 or later. |
| 8 | * Memory MAP Common header file for blackfin BF527/5/2 of processors. | ||
| 9 | * rev: | ||
| 10 | * | ||
| 11 | * modified: | ||
| 12 | * | ||
| 13 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * this program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the gnu general public license as published by | ||
| 17 | * the free software foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * this program is distributed in the hope that it will be useful, | ||
| 21 | * but without any warranty; without even the implied warranty of | ||
| 22 | * merchantability or fitness for a particular purpose. see the | ||
| 23 | * gnu general public license for more details. | ||
| 24 | * | ||
| 25 | * you should have received a copy of the gnu general public license | ||
| 26 | * along with this program; see the file copying. | ||
| 27 | * if not, write to the free software foundation, | ||
| 28 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 29 | */ | 6 | */ |
| 30 | 7 | ||
| 31 | #ifndef _MEM_MAP_527_H_ | 8 | #ifndef __BFIN_MACH_MEM_MAP_H__ |
| 32 | #define _MEM_MAP_527_H_ | 9 | #define __BFIN_MACH_MEM_MAP_H__ |
| 33 | 10 | ||
| 34 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ | 11 | #ifndef __BFIN_MEM_MAP_H__ |
| 35 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ | 12 | # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" |
| 13 | #endif | ||
| 36 | 14 | ||
| 37 | /* Async Memory Banks */ | 15 | /* Async Memory Banks */ |
| 38 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ | 16 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ |
| @@ -89,20 +67,4 @@ · 50 unmodified lines | |||
| 89 | #define BFIN_DSUPBANKS 0 | 67 | #define BFIN_DSUPBANKS 0 |
| 90 | #endif /*CONFIG_BFIN_DCACHE */ | 68 | #endif /*CONFIG_BFIN_DCACHE */ |
| 91 | 69 | ||
| 92 | /* Level 2 Memory - none */ | 70 | #endif |
| 93 | |||
| 94 | #define L2_START 0 | ||
| 95 | #define L2_LENGTH 0 | ||
| 96 | |||
| 97 | /* Scratch Pad Memory */ | ||
| 98 | |||
| 99 | #define L1_SCRATCH_START 0xFFB00000 | ||
| 100 | #define L1_SCRATCH_LENGTH 0x1000 | ||
| 101 | |||
| 102 | #define GET_PDA_SAFE(preg) \ | ||
| 103 | preg.l = _cpu_pda; \ | ||
| 104 | preg.h = _cpu_pda; | ||
| 105 | |||
| 106 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 107 | |||
| 108 | #endif /* _MEM_MAP_527_H_ */ | ||
| @@ -32,6 +32,7 @@ · 31 unmodified lines | |||
| 32 | #include <linux/platform_device.h> | 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/mtd/mtd.h> | 33 | #include <linux/mtd/mtd.h> |
| 34 | #include <linux/mtd/partitions.h> | 34 | #include <linux/mtd/partitions.h> |
| 35 | #include <linux/mtd/plat-ram.h> | ||
| 35 | #include <linux/spi/spi.h> | 36 | #include <linux/spi/spi.h> |
| 36 | #include <linux/spi/flash.h> | 37 | #include <linux/spi/flash.h> |
| 37 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | 38 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
| @@ -86,6 +87,101 @@ static struct platform_device smc91x_device = { · 48 unmodified lines | |||
| 86 | }; | 87 | }; |
| 87 | #endif | 88 | #endif |
| 88 | 89 | ||
| 90 | #if defined(CONFIG_MTD_PSD4256G) || defined(CONFIG_MTD_PSD4256G_MODULE) | ||
| 91 | static const char *map_probes[] = { | ||
| 92 | "stm_flash", | ||
| 93 | NULL, | ||
| 94 | }; | ||
| 95 | |||
| 96 | static struct platdata_mtd_ram stm_pri_data_a = { | ||
| 97 | .mapname = "Flash A Primary", | ||
| 98 | .map_probes = map_probes, | ||
| 99 | .bankwidth = 2, | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct resource stm_pri_resource_a = { | ||
| 103 | .start = 0x20000000, | ||
| 104 | .end = 0x200fffff, | ||
| 105 | .flags = IORESOURCE_MEM, | ||
| 106 | }; | ||
| 107 | |||
| 108 | static struct platform_device stm_pri_device_a = { | ||
| 109 | .name = "mtd-ram", | ||
| 110 | .id = 0, | ||
| 111 | .dev = { | ||
| 112 | .platform_data = &stm_pri_data_a, | ||
| 113 | }, | ||
| 114 | .num_resources = 1, | ||
| 115 | .resource = &stm_pri_resource_a, | ||
| 116 | }; | ||
| 117 | |||
| 118 | static struct platdata_mtd_ram stm_pri_data_b = { | ||
| 119 | .mapname = "Flash B Primary", | ||
| 120 | .map_probes = map_probes, | ||
| 121 | .bankwidth = 2, | ||
| 122 | }; | ||
| 123 | |||
| 124 | static struct resource stm_pri_resource_b = { | ||
| 125 | .start = 0x20100000, | ||
| 126 | .end = 0x201fffff, | ||
| 127 | .flags = IORESOURCE_MEM, | ||
| 128 | }; | ||
| 129 | |||
| 130 | static struct platform_device stm_pri_device_b = { | ||
| 131 | .name = "mtd-ram", | ||
| 132 | .id = 4, | ||
| 133 | .dev = { | ||
| 134 | .platform_data = &stm_pri_data_b, | ||
| 135 | }, | ||
| 136 | .num_resources = 1, | ||
| 137 | .resource = &stm_pri_resource_b, | ||
| 138 | }; | ||
| 139 | #endif | ||
| 140 | |||
| 141 | #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) | ||
| 142 | static struct platdata_mtd_ram sram_data_a = { | ||
| 143 | .mapname = "Flash A SRAM", | ||
| 144 | .bankwidth = 2, | ||
| 145 | }; | ||
| 146 | |||
| 147 | static struct resource sram_resource_a = { | ||
| 148 | .start = 0x20240000, | ||
| 149 | .end = 0x2024ffff, | ||
| 150 | .flags = IORESOURCE_MEM, | ||
| 151 | }; | ||
| 152 | |||
| 153 | static struct platform_device sram_device_a = { | ||
| 154 | .name = "mtd-ram", | ||
| 155 | .id = 8, | ||
| 156 | .dev = { | ||
| 157 | .platform_data = &sram_data_a, | ||
| 158 | }, | ||
| 159 | .num_resources = 1, | ||
| 160 | .resource = &sram_resource_a, | ||
| 161 | }; | ||
| 162 | |||
| 163 | static struct platdata_mtd_ram sram_data_b = { | ||
| 164 | .mapname = "Flash B SRAM", | ||
| 165 | .bankwidth = 2, | ||
| 166 | }; | ||
| 167 | |||
| 168 | static struct resource sram_resource_b = { | ||
| 169 | .start = 0x202c0000, | ||
| 170 | .end = 0x202cffff, | ||
| 171 | .flags = IORESOURCE_MEM, | ||
| 172 | }; | ||
| 173 | |||
| 174 | static struct platform_device sram_device_b = { | ||
| 175 | .name = "mtd-ram", | ||
| 176 | .id = 9, | ||
| 177 | .dev = { | ||
| 178 | .platform_data = &sram_data_b, | ||
| 179 | }, | ||
| 180 | .num_resources = 1, | ||
| 181 | .resource = &sram_resource_b, | ||
| 182 | }; | ||
| 183 | #endif | ||
| 184 | |||
| 89 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | 185 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) |
| 90 | static struct mtd_partition bfin_spi_flash_partitions[] = { | 186 | static struct mtd_partition bfin_spi_flash_partitions[] = { |
| 91 | { | 187 | { |
| @@ -357,6 +453,16 @@ static struct platform_device *ezkit_devices[] __initdata = { · 265 unmodified lines | |||
| 357 | 453 | ||
| 358 | &bfin_dpmc, | 454 | &bfin_dpmc, |
| 359 | 455 | ||
| 456 | #if defined(CONFIG_MTD_PSD4256G) || defined(CONFIG_MTD_PSD4256G_MODULE) | ||
| 457 | &stm_pri_device_a, | ||
| 458 | &stm_pri_device_b, | ||
| 459 | #endif | ||
| 460 | |||
| 461 | #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) | ||
| 462 | &sram_device_a, | ||
| 463 | &sram_device_b, | ||
| 464 | #endif | ||
| 465 | |||
| 360 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 466 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
| 361 | &smc91x_device, | 467 | &smc91x_device, |
| 362 | #endif | 468 | #endif |
| @@ -34,7 +34,7 @@ · 33 unmodified lines | |||
| 34 | # define ANOMALY_BF533 0 | 34 | # define ANOMALY_BF533 0 |
| 35 | #endif | 35 | #endif |
| 36 | 36 | ||
| 37 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | 37 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
| 38 | #define ANOMALY_05000074 (1) | 38 | #define ANOMALY_05000074 (1) |
| 39 | /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ | 39 | /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ |
| 40 | #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) | 40 | #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) |
| @@ -46,7 +46,7 @@ · 5 unmodified lines | |||
| 46 | #define ANOMALY_05000122 (1) | 46 | #define ANOMALY_05000122 (1) |
| 47 | /* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ | 47 | /* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ |
| 48 | #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) | 48 | #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) |
| 49 | /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ | 49 | /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ |
| 50 | #define ANOMALY_05000166 (1) | 50 | #define ANOMALY_05000166 (1) |
| 51 | /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ | 51 | /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ |
| 52 | #define ANOMALY_05000167 (1) | 52 | #define ANOMALY_05000167 (1) |
| @@ -56,13 +56,13 @@ · 3 unmodified lines | |||
| 56 | #define ANOMALY_05000180 (1) | 56 | #define ANOMALY_05000180 (1) |
| 57 | /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ | 57 | /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ |
| 58 | #define ANOMALY_05000183 (__SILICON_REVISION__ < 4) | 58 | #define ANOMALY_05000183 (__SILICON_REVISION__ < 4) |
| 59 | /* False Protection Exceptions */ | 59 | /* False Protection Exceptions when Speculative Fetch Is Cancelled */ |
| 60 | #define ANOMALY_05000189 (__SILICON_REVISION__ < 4) | 60 | #define ANOMALY_05000189 (__SILICON_REVISION__ < 4) |
| 61 | /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ | 61 | /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ |
| 62 | #define ANOMALY_05000193 (__SILICON_REVISION__ < 4) | 62 | #define ANOMALY_05000193 (__SILICON_REVISION__ < 4) |
| 63 | /* Restarting SPORT in Specific Modes May Cause Data Corruption */ | 63 | /* Restarting SPORT in Specific Modes May Cause Data Corruption */ |
| 64 | #define ANOMALY_05000194 (__SILICON_REVISION__ < 4) | 64 | #define ANOMALY_05000194 (__SILICON_REVISION__ < 4) |
| 65 | /* Failing MMR Accesses When Stalled by Preceding Memory Read */ | 65 | /* Failing MMR Accesses when Preceding Memory Read Stalls */ |
| 66 | #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) | 66 | #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) |
| 67 | /* Current DMA Address Shows Wrong Value During Carry Fix */ | 67 | /* Current DMA Address Shows Wrong Value During Carry Fix */ |
| 68 | #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) | 68 | #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) |
| @@ -74,7 +74,7 @@ · 5 unmodified lines | |||
| 74 | #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) | 74 | #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) |
| 75 | /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ | 75 | /* Specific Sequence That Can Cause DMA Error or DMA Stopping */ |
| 76 | #define ANOMALY_05000203 (__SILICON_REVISION__ < 4) | 76 | #define ANOMALY_05000203 (__SILICON_REVISION__ < 4) |
| 77 | /* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ | 77 | /* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ |
| 78 | #define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) | 78 | #define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) |
| 79 | /* Recovery from "Brown-Out" Condition */ | 79 | /* Recovery from "Brown-Out" Condition */ |
| 80 | #define ANOMALY_05000207 (__SILICON_REVISION__ < 4) | 80 | #define ANOMALY_05000207 (__SILICON_REVISION__ < 4) |
| @@ -106,7 +106,7 @@ · 25 unmodified lines | |||
| 106 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) | 106 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) |
| 107 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ | 107 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 108 | #define ANOMALY_05000245 (1) | 108 | #define ANOMALY_05000245 (1) |
| 109 | /* Data CPLBs Should Prevent Spurious Hardware Errors */ | 109 | /* Data CPLBs Should Prevent False Hardware Errors */ |
| 110 | #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) | 110 | #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) |
| 111 | /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ | 111 | /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ |
| 112 | #define ANOMALY_05000250 (__SILICON_REVISION__ == 4) | 112 | #define ANOMALY_05000250 (__SILICON_REVISION__ == 4) |
| @@ -148,21 +148,21 @@ · 35 unmodified lines | |||
| 148 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) | 148 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) |
| 149 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ | 149 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ |
| 150 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) | 150 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) |
| 151 | /* False Hardware Error Exception When ISR Context Is Not Restored */ | 151 | /* False Hardware Error Exception when ISR Context Is Not Restored */ |
| 152 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) | 152 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) |
| 153 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ | 153 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ |
| 154 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) | 154 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) |
| 155 | /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ | 155 | /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ |
| 156 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 6) | 156 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 6) |
| 157 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ | 157 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ |
| 158 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 6) | 158 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 6) |
| 159 | /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ | 159 | /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ |
| 160 | #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) | 160 | #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) |
| 161 | /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ | 161 | /* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ |
| 162 | #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) | 162 | #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) |
| 163 | /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ | 163 | /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ |
| 164 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) | 164 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) |
| 165 | /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ | 165 | /* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */ |
| 166 | #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) | 166 | #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) |
| 167 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ | 167 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ |
| 168 | #define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ | 168 | #define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ |
| @@ -170,11 +170,11 @@ · 1 unmodified line | |||
| 170 | #define ANOMALY_05000310 (1) | 170 | #define ANOMALY_05000310 (1) |
| 171 | /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ | 171 | /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ |
| 172 | #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) | 172 | #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) |
| 173 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | 173 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
| 174 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) | 174 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) |
| 175 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ | 175 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
| 176 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) | 176 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) |
| 177 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ | 177 | /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ |
| 178 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) | 178 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) |
| 179 | /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ | 179 | /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ |
| 180 | #define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) | 180 | #define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) |
| @@ -200,7 +200,7 @@ · 19 unmodified lines | |||
| 200 | #define ANOMALY_05000426 (1) | 200 | #define ANOMALY_05000426 (1) |
| 201 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 201 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 202 | #define ANOMALY_05000443 (1) | 202 | #define ANOMALY_05000443 (1) |
| 203 | /* False Hardware Error when RETI points to invalid memory */ | 203 | /* False Hardware Error when RETI Points to Invalid Memory */ |
| 204 | #define ANOMALY_05000461 (1) | 204 | #define ANOMALY_05000461 (1) |
| 205 | 205 | ||
| 206 | /* These anomalies have been "phased" out of analog.com anomaly sheets and are | 206 | /* These anomalies have been "phased" out of analog.com anomaly sheets and are |
| @@ -215,17 +215,17 @@ · 8 unmodified lines | |||
| 215 | #define ANOMALY_05000070 (__SILICON_REVISION__ < 2) | 215 | #define ANOMALY_05000070 (__SILICON_REVISION__ < 2) |
| 216 | /* Writing FIO_DIR can corrupt a programmable flag's data */ | 216 | /* Writing FIO_DIR can corrupt a programmable flag's data */ |
| 217 | #define ANOMALY_05000079 (__SILICON_REVISION__ < 2) | 217 | #define ANOMALY_05000079 (__SILICON_REVISION__ < 2) |
| 218 | /* Timer Auto-Baud Mode requires the UART clock to be enabled */ | 218 | /* Timer Auto-Baud Mode requires the UART clock to be enabled. */ |
| 219 | #define ANOMALY_05000086 (__SILICON_REVISION__ < 2) | 219 | #define ANOMALY_05000086 (__SILICON_REVISION__ < 2) |
| 220 | /* Internal Clocking Modes on SPORT0 not supported */ | 220 | /* Internal Clocking Modes on SPORT0 not supported */ |
| 221 | #define ANOMALY_05000088 (__SILICON_REVISION__ < 2) | 221 | #define ANOMALY_05000088 (__SILICON_REVISION__ < 2) |
| 222 | /* Internal voltage regulator does not wake up from an RTC wakeup */ | 222 | /* Internal voltage regulator does not wake up from an RTC wakeup */ |
| 223 | #define ANOMALY_05000092 (__SILICON_REVISION__ < 2) | 223 | #define ANOMALY_05000092 (__SILICON_REVISION__ < 2) |
| 224 | /* The IFLUSH instruction must be preceded by a CSYNC instruction */ | 224 | /* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */ |
| 225 | #define ANOMALY_05000093 (__SILICON_REVISION__ < 2) | 225 | #define ANOMALY_05000093 (__SILICON_REVISION__ < 2) |
| 226 | /* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */ | 226 | /* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */ |
| 227 | #define ANOMALY_05000095 (__SILICON_REVISION__ < 2) | 227 | #define ANOMALY_05000095 (__SILICON_REVISION__ < 2) |
| 228 | /* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */ | 228 | /* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */ |
| 229 | #define ANOMALY_05000096 (__SILICON_REVISION__ < 2) | 229 | #define ANOMALY_05000096 (__SILICON_REVISION__ < 2) |
| 230 | /* Performance Monitor 0 and 1 are swapped when monitoring memory events */ | 230 | /* Performance Monitor 0 and 1 are swapped when monitoring memory events */ |
| 231 | #define ANOMALY_05000097 (__SILICON_REVISION__ < 2) | 231 | #define ANOMALY_05000097 (__SILICON_REVISION__ < 2) |
| @@ -235,45 +235,45 @@ · 3 unmodified lines | |||
| 235 | #define ANOMALY_05000100 (__SILICON_REVISION__ < 2) | 235 | #define ANOMALY_05000100 (__SILICON_REVISION__ < 2) |
| 236 | /* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ | 236 | /* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ |
| 237 | #define ANOMALY_05000101 (__SILICON_REVISION__ < 2) | 237 | #define ANOMALY_05000101 (__SILICON_REVISION__ < 2) |
| 238 | /* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ | 238 | /* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ |
| 239 | #define ANOMALY_05000102 (__SILICON_REVISION__ < 2) | 239 | #define ANOMALY_05000102 (__SILICON_REVISION__ < 2) |
| 240 | /* Incorrect value written to the cycle counters */ | 240 | /* Incorrect Value Written to the Cycle Counters */ |
| 241 | #define ANOMALY_05000103 (__SILICON_REVISION__ < 2) | 241 | #define ANOMALY_05000103 (__SILICON_REVISION__ < 2) |
| 242 | /* Stores to L1 Data memory incorrect when a specific sequence is followed */ | 242 | /* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */ |
| 243 | #define ANOMALY_05000104 (__SILICON_REVISION__ < 2) | 243 | #define ANOMALY_05000104 (__SILICON_REVISION__ < 2) |
| 244 | /* Programmable Flag (PF3) functionality not supported in all PPI modes */ | 244 | /* Programmable Flag (PF3) functionality not supported in all PPI modes */ |
| 245 | #define ANOMALY_05000106 (__SILICON_REVISION__ < 2) | 245 | #define ANOMALY_05000106 (__SILICON_REVISION__ < 2) |
| 246 | /* Data store can be lost when targeting a cache line fill */ | 246 | /* Data store can be lost when targeting a cache line fill */ |
| 247 | #define ANOMALY_05000107 (__SILICON_REVISION__ < 2) | 247 | #define ANOMALY_05000107 (__SILICON_REVISION__ < 2) |
| 248 | /* Reserved bits in SYSCFG register not set at power on */ | 248 | /* Reserved Bits in SYSCFG Register Not Set at Power-On */ |
| 249 | #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) | 249 | #define ANOMALY_05000109 (__SILICON_REVISION__ < 3) |
| 250 | /* Infinite Core Stall */ | 250 | /* Infinite Core Stall */ |
| 251 | #define ANOMALY_05000114 (__SILICON_REVISION__ < 2) | 251 | #define ANOMALY_05000114 (__SILICON_REVISION__ < 2) |
| 252 | /* PPI_FSx may glitch when generated by the on chip Timers */ | 252 | /* PPI_FSx may glitch when generated by the on chip Timers. */ |
| 253 | #define ANOMALY_05000115 (__SILICON_REVISION__ < 2) | 253 | #define ANOMALY_05000115 (__SILICON_REVISION__ < 2) |
| 254 | /* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ | 254 | /* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ |
| 255 | #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) | 255 | #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) |
| 256 | /* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ | 256 | /* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ |
| 257 | #define ANOMALY_05000117 (__SILICON_REVISION__ < 2) | 257 | #define ANOMALY_05000117 (__SILICON_REVISION__ < 2) |
| 258 | /* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ | 258 | /* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ |
| 259 | #define ANOMALY_05000118 (__SILICON_REVISION__ < 2) | 259 | #define ANOMALY_05000118 (__SILICON_REVISION__ < 2) |
| 260 | /* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ | 260 | /* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */ |
| 261 | #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) | 261 | #define ANOMALY_05000123 (__SILICON_REVISION__ < 3) |
| 262 | /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ | 262 | /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ |
| 263 | #define ANOMALY_05000124 (__SILICON_REVISION__ < 3) | 263 | #define ANOMALY_05000124 (__SILICON_REVISION__ < 3) |
| 264 | /* Erroneous exception when enabling cache */ | 264 | /* Erroneous Exception when Enabling Cache */ |
| 265 | #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) | 265 | #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) |
| 266 | /* SPI clock polarity and phase bits incorrect during booting */ | 266 | /* SPI clock polarity and phase bits incorrect during booting */ |
| 267 | #define ANOMALY_05000126 (__SILICON_REVISION__ < 3) | 267 | #define ANOMALY_05000126 (__SILICON_REVISION__ < 3) |
| 268 | /* DMEM_CONTROL is not set on Reset */ | 268 | /* DMEM_CONTROL<12> Is Not Set on Reset */ |
| 269 | #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) | 269 | #define ANOMALY_05000137 (__SILICON_REVISION__ < 3) |
| 270 | /* SPI boot will not complete if there is a zero fill block in the loader file */ | 270 | /* SPI boot will not complete if there is a zero fill block in the loader file */ |
| 271 | #define ANOMALY_05000138 (__SILICON_REVISION__ == 2) | 271 | #define ANOMALY_05000138 (__SILICON_REVISION__ == 2) |
| 272 | /* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */ | 272 | /* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */ |
| 273 | #define ANOMALY_05000139 (__SILICON_REVISION__ < 2) | 273 | #define ANOMALY_05000139 (__SILICON_REVISION__ < 2) |
| 274 | /* Allowing the SPORT RX FIFO to fill will cause an overflow */ | 274 | /* Allowing the SPORT RX FIFO to fill will cause an overflow */ |
| 275 | #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) | 275 | #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) |
| 276 | /* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ | 276 | /* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ |
| 277 | #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) | 277 | #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) |
| 278 | /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ | 278 | /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ |
| 279 | #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) | 279 | #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) |
| @@ -287,7 +287,7 @@ · 7 unmodified lines | |||
| 287 | #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) | 287 | #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) |
| 288 | /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ | 288 | /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ |
| 289 | #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) | 289 | #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) |
| 290 | /* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ | 290 | /* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */ |
| 291 | #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) | 291 | #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) |
| 292 | /* Frame Delay in SPORT Multichannel Mode */ | 292 | /* Frame Delay in SPORT Multichannel Mode */ |
| 293 | #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) | 293 | #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) |
| @@ -295,13 +295,13 @@ · 1 unmodified line | |||
| 295 | #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) | 295 | #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) |
| 296 | /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ | 296 | /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ |
| 297 | #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) | 297 | #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) |
| 298 | /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ | 298 | /* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ |
| 299 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) | 299 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) |
| 300 | /* SPORT transmit data is not gated by external frame sync in certain conditions */ | 300 | /* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ |
| 301 | #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) | 301 | #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) |
| 302 | /* SDRAM auto-refresh and subsequent Power Ups */ | 302 | /* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ |
| 303 | #define ANOMALY_05000168 (__SILICON_REVISION__ < 3) | 303 | #define ANOMALY_05000168 (__SILICON_REVISION__ < 3) |
| 304 | /* DATA CPLB page miss can result in lost write-through cache data writes */ | 304 | /* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ |
| 305 | #define ANOMALY_05000169 (__SILICON_REVISION__ < 3) | 305 | #define ANOMALY_05000169 (__SILICON_REVISION__ < 3) |
| 306 | /* DMA vs Core accesses to external memory */ | 306 | /* DMA vs Core accesses to external memory */ |
| 307 | #define ANOMALY_05000173 (__SILICON_REVISION__ < 3) | 307 | #define ANOMALY_05000173 (__SILICON_REVISION__ < 3) |
| @@ -309,15 +309,15 @@ · 1 unmodified line | |||
| 309 | #define ANOMALY_05000174 (__SILICON_REVISION__ < 3) | 309 | #define ANOMALY_05000174 (__SILICON_REVISION__ < 3) |
| 310 | /* Overlapping Sequencer and Memory Stalls */ | 310 | /* Overlapping Sequencer and Memory Stalls */ |
| 311 | #define ANOMALY_05000175 (__SILICON_REVISION__ < 3) | 311 | #define ANOMALY_05000175 (__SILICON_REVISION__ < 3) |
| 312 | /* Multiplication of (-1) by (-1) followed by an accumulator saturation */ | 312 | /* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ |
| 313 | #define ANOMALY_05000176 (__SILICON_REVISION__ < 3) | 313 | #define ANOMALY_05000176 (__SILICON_REVISION__ < 3) |
| 314 | /* Disabling the PPI resets the PPI configuration registers */ | 314 | /* Disabling the PPI Resets the PPI Configuration Registers */ |
| 315 | #define ANOMALY_05000181 (__SILICON_REVISION__ < 3) | 315 | #define ANOMALY_05000181 (__SILICON_REVISION__ < 3) |
| 316 | /* PPI TX Mode with 2 External Frame Syncs */ | 316 | /* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ |
| 317 | #define ANOMALY_05000185 (__SILICON_REVISION__ < 3) | 317 | #define ANOMALY_05000185 (__SILICON_REVISION__ < 3) |
| 318 | /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ | 318 | /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ |
| 319 | #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) | 319 | #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) |
| 320 | /* In PPI Transmit Modes with External Frame Syncs POLC */ | 320 | /* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */ |
| 321 | #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) | 321 | #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) |
| 322 | /* Internal Voltage Regulator may not start up */ | 322 | /* Internal Voltage Regulator may not start up */ |
| 323 | #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) | 323 | #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) |
| @@ -326,6 +326,7 @@ · 2 unmodified lines | |||
| 326 | #define ANOMALY_05000120 (0) | 326 | #define ANOMALY_05000120 (0) |
| 327 | #define ANOMALY_05000149 (0) | 327 | #define ANOMALY_05000149 (0) |
| 328 | #define ANOMALY_05000171 (0) | 328 | #define ANOMALY_05000171 (0) |
| 329 | #define ANOMALY_05000182 (0) | ||
| 329 | #define ANOMALY_05000220 (0) | 330 | #define ANOMALY_05000220 (0) |
| 330 | #define ANOMALY_05000248 (0) | 331 | #define ANOMALY_05000248 (0) |
| 331 | #define ANOMALY_05000266 (0) | 332 | #define ANOMALY_05000266 (0) |
| @@ -345,5 +346,7 @@ · 13 unmodified lines | |||
| 345 | #define ANOMALY_05000448 (0) | 346 | #define ANOMALY_05000448 (0) |
| 346 | #define ANOMALY_05000456 (0) | 347 | #define ANOMALY_05000456 (0) |
| 347 | #define ANOMALY_05000450 (0) | 348 | #define ANOMALY_05000450 (0) |
| 349 | #define ANOMALY_05000465 (0) | ||
| 350 | #define ANOMALY_05000467 (0) | ||
| 348 | 351 | ||
| 349 | #endif | 352 | #endif |
| @@ -34,7 +34,6 @@ · 33 unmodified lines | |||
| 34 | #define BF533_FAMILY | 34 | #define BF533_FAMILY |
| 35 | 35 | ||
| 36 | #include "bf533.h" | 36 | #include "bf533.h" |
| 37 | #include "mem_map.h" | ||
| 38 | #include "defBF532.h" | 37 | #include "defBF532.h" |
| 39 | #include "anomaly.h" | 38 | #include "anomaly.h" |
| 40 | 39 | ||
| @@ -1,38 +1,16 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * File: include/asm-blackfin/mach-bf533/mem_map.h | 2 | * BF533 memory map |
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | 3 | * |
| 6 | * Created: | 4 | * Copyright 2004-2009 Analog Devices Inc. |
| 7 | * Description: | 5 | * Licensed under the GPL-2 or later. |
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | 6 | */ |
| 30 | 7 | ||
| 31 | #ifndef _MEM_MAP_533_H_ | 8 | #ifndef __BFIN_MACH_MEM_MAP_H__ |
| 32 | #define _MEM_MAP_533_H_ | 9 | #define __BFIN_MACH_MEM_MAP_H__ |
| 33 | 10 | ||
| 34 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ | 11 | #ifndef __BFIN_MEM_MAP_H__ |
| 35 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ | 12 | # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" |
| 13 | #endif | ||
| 36 | 14 | ||
| 37 | /* Async Memory Banks */ | 15 | /* Async Memory Banks */ |
| 38 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ | 16 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ |
| @@ -158,20 +136,4 @@ · 119 unmodified lines | |||
| 158 | 136 | ||
| 159 | #endif | 137 | #endif |
| 160 | 138 | ||
| 161 | /* Level 2 Memory - none */ | 139 | #endif |
| 162 | |||
| 163 | #define L2_START 0 | ||
| 164 | #define L2_LENGTH 0 | ||
| 165 | |||
| 166 | /* Scratch Pad Memory */ | ||
| 167 | |||
| 168 | #define L1_SCRATCH_START 0xFFB00000 | ||
| 169 | #define L1_SCRATCH_LENGTH 0x1000 | ||
| 170 | |||
| 171 | #define GET_PDA_SAFE(preg) \ | ||
| 172 | preg.l = _cpu_pda; \ | ||
| 173 | preg.h = _cpu_pda; | ||
| 174 | |||
| 175 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 176 | |||
| 177 | #endif /* _MEM_MAP_533_H_ */ | ||
| @@ -79,7 +79,6 @@ static struct resource bfin_isp1760_resources[] = { · 78 unmodified lines | |||
| 79 | 79 | ||
| 80 | static struct isp1760_platform_data isp1760_priv = { | 80 | static struct isp1760_platform_data isp1760_priv = { |
| 81 | .is_isp1761 = 0, | 81 | .is_isp1761 = 0, |
| 82 | .port1_disable = 0, | ||
| 83 | .bus_width_16 = 1, | 82 | .bus_width_16 = 1, |
| 84 | .port1_otg = 0, | 83 | .port1_otg = 0, |
| 85 | .analog_oc = 0, | 84 | .analog_oc = 0, |
| @@ -34,13 +34,13 @@ · 33 unmodified lines | |||
| 34 | # define ANOMALY_BF537 0 | 34 | # define ANOMALY_BF537 0 |
| 35 | #endif | 35 | #endif |
| 36 | 36 | ||
| 37 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | 37 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
| 38 | #define ANOMALY_05000074 (1) | 38 | #define ANOMALY_05000074 (1) |
| 39 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | 39 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
| 40 | #define ANOMALY_05000119 (1) | 40 | #define ANOMALY_05000119 (1) |
| 41 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 41 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 42 | #define ANOMALY_05000122 (1) | 42 | #define ANOMALY_05000122 (1) |
| 43 | /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ | 43 | /* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ |
| 44 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) | 44 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) |
| 45 | /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ | 45 | /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ |
| 46 | #define ANOMALY_05000180 (1) | 46 | #define ANOMALY_05000180 (1) |
| @@ -50,11 +50,11 @@ · 3 unmodified lines | |||
| 50 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) | 50 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) |
| 51 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ | 51 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 52 | #define ANOMALY_05000245 (1) | 52 | #define ANOMALY_05000245 (1) |
| 53 | /* CLKIN Buffer Output Enable Reset Behavior Is Changed */ | 53 | /* Buffered CLKIN Output Is Disabled by Default */ |
| 54 | #define ANOMALY_05000247 (1) | 54 | #define ANOMALY_05000247 (1) |
| 55 | /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ | 55 | /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ |
| 56 | #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) | 56 | #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) |
| 57 | /* EMAC Tx DMA error after an early frame abort */ | 57 | /* EMAC TX DMA Error After an Early Frame Abort */ |
| 58 | #define ANOMALY_05000252 (__SILICON_REVISION__ < 3) | 58 | #define ANOMALY_05000252 (__SILICON_REVISION__ < 3) |
| 59 | /* Maximum External Clock Speed for Timers */ | 59 | /* Maximum External Clock Speed for Timers */ |
| 60 | #define ANOMALY_05000253 (__SILICON_REVISION__ < 3) | 60 | #define ANOMALY_05000253 (__SILICON_REVISION__ < 3) |
| @@ -62,7 +62,7 @@ · 1 unmodified line | |||
| 62 | #define ANOMALY_05000254 (__SILICON_REVISION__ > 2) | 62 | #define ANOMALY_05000254 (__SILICON_REVISION__ > 2) |
| 63 | /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ | 63 | /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ |
| 64 | #define ANOMALY_05000255 (__SILICON_REVISION__ < 3) | 64 | #define ANOMALY_05000255 (__SILICON_REVISION__ < 3) |
| 65 | /* EMAC MDIO input latched on wrong MDC edge */ | 65 | /* EMAC MDIO Input Latched on Wrong MDC Edge */ |
| 66 | #define ANOMALY_05000256 (__SILICON_REVISION__ < 3) | 66 | #define ANOMALY_05000256 (__SILICON_REVISION__ < 3) |
| 67 | /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ | 67 | /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ |
| 68 | #define ANOMALY_05000257 (__SILICON_REVISION__ < 3) | 68 | #define ANOMALY_05000257 (__SILICON_REVISION__ < 3) |
| @@ -80,7 +80,7 @@ · 11 unmodified lines | |||
| 80 | #define ANOMALY_05000264 (__SILICON_REVISION__ < 3) | 80 | #define ANOMALY_05000264 (__SILICON_REVISION__ < 3) |
| 81 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | 81 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
| 82 | #define ANOMALY_05000265 (1) | 82 | #define ANOMALY_05000265 (1) |
| 83 | /* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ | 83 | /* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */ |
| 84 | #define ANOMALY_05000268 (__SILICON_REVISION__ < 3) | 84 | #define ANOMALY_05000268 (__SILICON_REVISION__ < 3) |
| 85 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ | 85 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ |
| 86 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 3) | 86 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 3) |
| @@ -92,15 +92,15 @@ · 5 unmodified lines | |||
| 92 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) | 92 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) |
| 93 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ | 93 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ |
| 94 | #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) | 94 | #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) |
| 95 | /* SPI Master boot mode does not work well with Atmel Data flash devices */ | 95 | /* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ |
| 96 | #define ANOMALY_05000280 (1) | 96 | #define ANOMALY_05000280 (1) |
| 97 | /* False Hardware Error Exception When ISR Context Is Not Restored */ | 97 | /* False Hardware Error Exception when ISR Context Is Not Restored */ |
| 98 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) | 98 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) |
| 99 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ | 99 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ |
| 100 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) | 100 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) |
| 101 | /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ | 101 | /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ |
| 102 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 3) | 102 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 3) |
| 103 | /* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ | 103 | /* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */ |
| 104 | #define ANOMALY_05000285 (__SILICON_REVISION__ < 3) | 104 | #define ANOMALY_05000285 (__SILICON_REVISION__ < 3) |
| 105 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ | 105 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ |
| 106 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 3) | 106 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 3) |
| @@ -112,25 +112,25 @@ · 5 unmodified lines | |||
| 112 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 3) | 112 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 3) |
| 113 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ | 113 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ |
| 114 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) | 114 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) |
| 115 | /* Writing UART_THR while UART clock is disabled sends erroneous start bit */ | 115 | /* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */ |
| 116 | #define ANOMALY_05000309 (__SILICON_REVISION__ < 3) | 116 | #define ANOMALY_05000309 (__SILICON_REVISION__ < 3) |
| 117 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | 117 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 118 | #define ANOMALY_05000310 (1) | 118 | #define ANOMALY_05000310 (1) |
| 119 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | 119 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
| 120 | #define ANOMALY_05000312 (1) | 120 | #define ANOMALY_05000312 (1) |
| 121 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ | 121 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
| 122 | #define ANOMALY_05000313 (1) | 122 | #define ANOMALY_05000313 (1) |
| 123 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ | 123 | /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ |
| 124 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 3) | 124 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 3) |
| 125 | /* EMAC RMII mode: collisions occur in Full Duplex mode */ | 125 | /* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */ |
| 126 | #define ANOMALY_05000316 (__SILICON_REVISION__ < 3) | 126 | #define ANOMALY_05000316 (__SILICON_REVISION__ < 3) |
| 127 | /* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ | 127 | /* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */ |
| 128 | #define ANOMALY_05000321 (__SILICON_REVISION__ < 3) | 128 | #define ANOMALY_05000321 (__SILICON_REVISION__ < 3) |
| 129 | /* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ | 129 | /* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */ |
| 130 | #define ANOMALY_05000322 (1) | 130 | #define ANOMALY_05000322 (1) |
| 131 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ | 131 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ |
| 132 | #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) | 132 | #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) |
| 133 | /* New Feature: UART Remains Enabled after UART Boot */ | 133 | /* UART Gets Disabled after UART Boot */ |
| 134 | #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) | 134 | #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) |
| 135 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ | 135 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ |
| 136 | #define ANOMALY_05000355 (1) | 136 | #define ANOMALY_05000355 (1) |
| @@ -154,7 +154,7 @@ · 17 unmodified lines | |||
| 154 | #define ANOMALY_05000426 (1) | 154 | #define ANOMALY_05000426 (1) |
| 155 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 155 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 156 | #define ANOMALY_05000443 (1) | 156 | #define ANOMALY_05000443 (1) |
| 157 | /* False Hardware Error when RETI points to invalid memory */ | 157 | /* False Hardware Error when RETI Points to Invalid Memory */ |
| 158 | #define ANOMALY_05000461 (1) | 158 | #define ANOMALY_05000461 (1) |
| 159 | 159 | ||
| 160 | /* Anomalies that don't exist on this proc */ | 160 | /* Anomalies that don't exist on this proc */ |
| @@ -165,14 +165,17 @@ · 4 unmodified lines | |||
| 165 | #define ANOMALY_05000158 (0) | 165 | #define ANOMALY_05000158 (0) |
| 166 | #define ANOMALY_05000171 (0) | 166 | #define ANOMALY_05000171 (0) |
| 167 | #define ANOMALY_05000179 (0) | 167 | #define ANOMALY_05000179 (0) |
| 168 | #define ANOMALY_05000182 (0) | ||
| 168 | #define ANOMALY_05000183 (0) | 169 | #define ANOMALY_05000183 (0) |
| 169 | #define ANOMALY_05000198 (0) | 170 | #define ANOMALY_05000198 (0) |
| 171 | #define ANOMALY_05000202 (0) | ||
| 170 | #define ANOMALY_05000215 (0) | 172 | #define ANOMALY_05000215 (0) |
| 171 | #define ANOMALY_05000220 (0) | 173 | #define ANOMALY_05000220 (0) |
| 172 | #define ANOMALY_05000227 (0) | 174 | #define ANOMALY_05000227 (0) |
| 173 | #define ANOMALY_05000230 (0) | 175 | #define ANOMALY_05000230 (0) |
| 174 | #define ANOMALY_05000231 (0) | 176 | #define ANOMALY_05000231 (0) |
| 175 | #define ANOMALY_05000233 (0) | 177 | #define ANOMALY_05000233 (0) |
| 178 | #define ANOMALY_05000234 (0) | ||
| 176 | #define ANOMALY_05000242 (0) | 179 | #define ANOMALY_05000242 (0) |
| 177 | #define ANOMALY_05000248 (0) | 180 | #define ANOMALY_05000248 (0) |
| 178 | #define ANOMALY_05000266 (0) | 181 | #define ANOMALY_05000266 (0) |
| @@ -195,5 +198,7 @@ · 16 unmodified lines | |||
| 195 | #define ANOMALY_05000448 (0) | 198 | #define ANOMALY_05000448 (0) |
| 196 | #define ANOMALY_05000456 (0) | 199 | #define ANOMALY_05000456 (0) |
| 197 | #define ANOMALY_05000450 (0) | 200 | #define ANOMALY_05000450 (0) |
| 201 | #define ANOMALY_05000465 (0) | ||
| 202 | #define ANOMALY_05000467 (0) | ||
| 198 | 203 | ||
| 199 | #endif | 204 | #endif |
| @@ -35,7 +35,6 @@ · 34 unmodified lines | |||
| 35 | #define BF537_FAMILY | 35 | #define BF537_FAMILY |
| 36 | 36 | ||
| 37 | #include "bf537.h" | 37 | #include "bf537.h" |
| 38 | #include "mem_map.h" | ||
| 39 | #include "defBF534.h" | 38 | #include "defBF534.h" |
| 40 | #include "anomaly.h" | 39 | #include "anomaly.h" |
| 41 | 40 | ||
| @@ -1,38 +1,16 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * file: include/asm-blackfin/mach-bf537/mem_map.h | 2 | * BF537 memory map |
| 3 | * based on: | ||
| 4 | * author: | ||
| 5 | * | 3 | * |
| 6 | * created: | 4 | * Copyright 2004-2009 Analog Devices Inc. |
| 7 | * description: | 5 | * Licensed under the GPL-2 or later. |
| 8 | * Memory MAP Common header file for blackfin BF537/6/4 of processors. | ||
| 9 | * rev: | ||
| 10 | * | ||
| 11 | * modified: | ||
| 12 | * | ||
| 13 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * this program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the gnu general public license as published by | ||
| 17 | * the free software foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * this program is distributed in the hope that it will be useful, | ||
| 21 | * but without any warranty; without even the implied warranty of | ||
| 22 | * merchantability or fitness for a particular purpose. see the | ||
| 23 | * gnu general public license for more details. | ||
| 24 | * | ||
| 25 | * you should have received a copy of the gnu general public license | ||
| 26 | * along with this program; see the file copying. | ||
| 27 | * if not, write to the free software foundation, | ||
| 28 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 29 | */ | 6 | */ |
| 30 | 7 | ||
| 31 | #ifndef _MEM_MAP_537_H_ | 8 | #ifndef __BFIN_MACH_MEM_MAP_H__ |
| 32 | #define _MEM_MAP_537_H_ | 9 | #define __BFIN_MACH_MEM_MAP_H__ |
| 33 | 10 | ||
| 34 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ | 11 | #ifndef __BFIN_MEM_MAP_H__ |
| 35 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ | 12 | # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" |
| 13 | #endif | ||
| 36 | 14 | ||
| 37 | /* Async Memory Banks */ | 15 | /* Async Memory Banks */ |
| 38 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ | 16 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ |
| @@ -166,20 +144,4 @@ · 127 unmodified lines | |||
| 166 | 144 | ||
| 167 | #endif | 145 | #endif |
| 168 | 146 | ||
| 169 | /* Level 2 Memory - none */ | 147 | #endif |
| 170 | |||
| 171 | #define L2_START 0 | ||
| 172 | #define L2_LENGTH 0 | ||
| 173 | |||
| 174 | /* Scratch Pad Memory */ | ||
| 175 | |||
| 176 | #define L1_SCRATCH_START 0xFFB00000 | ||
| 177 | #define L1_SCRATCH_LENGTH 0x1000 | ||
| 178 | |||
| 179 | #define GET_PDA_SAFE(preg) \ | ||
| 180 | preg.l = _cpu_pda; \ | ||
| 181 | preg.h = _cpu_pda; | ||
| 182 | |||
| 183 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 184 | |||
| 185 | #endif /* _MEM_MAP_537_H_ */ | ||
| @@ -30,13 +30,13 @@ · 29 unmodified lines | |||
| 30 | # define ANOMALY_BF539 0 | 30 | # define ANOMALY_BF539 0 |
| 31 | #endif | 31 | #endif |
| 32 | 32 | ||
| 33 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | 33 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
| 34 | #define ANOMALY_05000074 (1) | 34 | #define ANOMALY_05000074 (1) |
| 35 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | 35 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
| 36 | #define ANOMALY_05000119 (1) | 36 | #define ANOMALY_05000119 (1) |
| 37 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 37 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 38 | #define ANOMALY_05000122 (1) | 38 | #define ANOMALY_05000122 (1) |
| 39 | /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ | 39 | /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ |
| 40 | #define ANOMALY_05000166 (1) | 40 | #define ANOMALY_05000166 (1) |
| 41 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ | 41 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ |
| 42 | #define ANOMALY_05000179 (1) | 42 | #define ANOMALY_05000179 (1) |
| @@ -70,11 +70,11 @@ · 27 unmodified lines | |||
| 70 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) | 70 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) |
| 71 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ | 71 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ |
| 72 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) | 72 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) |
| 73 | /* False Hardware Error Exception When ISR Context Is Not Restored */ | 73 | /* False Hardware Error Exception when ISR Context Is Not Restored */ |
| 74 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) | 74 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) |
| 75 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ | 75 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ |
| 76 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) | 76 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) |
| 77 | /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ | 77 | /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ |
| 78 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 4) | 78 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 4) |
| 79 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ | 79 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ |
| 80 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 4) | 80 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 4) |
| @@ -92,11 +92,11 @@ · 11 unmodified lines | |||
| 92 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 4) | 92 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 4) |
| 93 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | 93 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 94 | #define ANOMALY_05000310 (1) | 94 | #define ANOMALY_05000310 (1) |
| 95 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | 95 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
| 96 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 5) | 96 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 5) |
| 97 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ | 97 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
| 98 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) | 98 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) |
| 99 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ | 99 | /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ |
| 100 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) | 100 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) |
| 101 | /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ | 101 | /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ |
| 102 | #define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) | 102 | #define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) |
| @@ -110,7 +110,7 @@ · 7 unmodified lines | |||
| 110 | #define ANOMALY_05000371 (__SILICON_REVISION__ < 5) | 110 | #define ANOMALY_05000371 (__SILICON_REVISION__ < 5) |
| 111 | /* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */ | 111 | /* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */ |
| 112 | #define ANOMALY_05000374 (__SILICON_REVISION__ == 4) | 112 | #define ANOMALY_05000374 (__SILICON_REVISION__ == 4) |
| 113 | /* New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) */ | 113 | /* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */ |
| 114 | #define ANOMALY_05000375 (__SILICON_REVISION__ < 4) | 114 | #define ANOMALY_05000375 (__SILICON_REVISION__ < 4) |
| 115 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ | 115 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ |
| 116 | #define ANOMALY_05000402 (__SILICON_REVISION__ < 4) | 116 | #define ANOMALY_05000402 (__SILICON_REVISION__ < 4) |
| @@ -126,26 +126,32 @@ · 9 unmodified lines | |||
| 126 | #define ANOMALY_05000436 (__SILICON_REVISION__ > 3) | 126 | #define ANOMALY_05000436 (__SILICON_REVISION__ > 3) |
| 127 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 127 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 128 | #define ANOMALY_05000443 (1) | 128 | #define ANOMALY_05000443 (1) |
| 129 | /* False Hardware Error when RETI points to invalid memory */ | 129 | /* False Hardware Error when RETI Points to Invalid Memory */ |
| 130 | #define ANOMALY_05000461 (1) | 130 | #define ANOMALY_05000461 (1) |
| 131 | 131 | ||
| 132 | /* Anomalies that don't exist on this proc */ | 132 | /* Anomalies that don't exist on this proc */ |
| 133 | #define ANOMALY_05000099 (0) | 133 | #define ANOMALY_05000099 (0) |
| 134 | #define ANOMALY_05000120 (0) | 134 | #define ANOMALY_05000120 (0) |
| 135 | #define ANOMALY_05000125 (0) | ||
| 135 | #define ANOMALY_05000149 (0) | 136 | #define ANOMALY_05000149 (0) |
| 136 | #define ANOMALY_05000158 (0) | 137 | #define ANOMALY_05000158 (0) |
| 137 | #define ANOMALY_05000171 (0) | 138 | #define ANOMALY_05000171 (0) |
| 139 | #define ANOMALY_05000182 (0) | ||
| 138 | #define ANOMALY_05000198 (0) | 140 | #define ANOMALY_05000198 (0) |
| 141 | #define ANOMALY_05000202 (0) | ||
| 139 | #define ANOMALY_05000215 (0) | 142 | #define ANOMALY_05000215 (0) |
| 140 | #define ANOMALY_05000220 (0) | 143 | #define ANOMALY_05000220 (0) |
| 141 | #define ANOMALY_05000227 (0) | 144 | #define ANOMALY_05000227 (0) |
| 142 | #define ANOMALY_05000230 (0) | 145 | #define ANOMALY_05000230 (0) |
| 143 | #define ANOMALY_05000231 (0) | 146 | #define ANOMALY_05000231 (0) |
| 147 | #define ANOMALY_05000234 (0) | ||
| 144 | #define ANOMALY_05000242 (0) | 148 | #define ANOMALY_05000242 (0) |
| 145 | #define ANOMALY_05000248 (0) | 149 | #define ANOMALY_05000248 (0) |
| 146 | #define ANOMALY_05000250 (0) | 150 | #define ANOMALY_05000250 (0) |
| 147 | #define ANOMALY_05000254 (0) | 151 | #define ANOMALY_05000254 (0) |
| 152 | #define ANOMALY_05000257 (0) | ||
| 148 | #define ANOMALY_05000263 (0) | 153 | #define ANOMALY_05000263 (0) |
| 154 | #define ANOMALY_05000266 (0) | ||
| 149 | #define ANOMALY_05000274 (0) | 155 | #define ANOMALY_05000274 (0) |
| 150 | #define ANOMALY_05000287 (0) | 156 | #define ANOMALY_05000287 (0) |
| 151 | #define ANOMALY_05000305 (0) | 157 | #define ANOMALY_05000305 (0) |
| @@ -166,5 +172,7 @@ · 14 unmodified lines | |||
| 166 | #define ANOMALY_05000448 (0) | 172 | #define ANOMALY_05000448 (0) |
| 167 | #define ANOMALY_05000456 (0) | 173 | #define ANOMALY_05000456 (0) |
| 168 | #define ANOMALY_05000450 (0) | 174 | #define ANOMALY_05000450 (0) |
| 175 | #define ANOMALY_05000465 (0) | ||
| 176 | #define ANOMALY_05000467 (0) | ||
| 169 | 177 | ||
| 170 | #endif | 178 | #endif |
| @@ -35,7 +35,6 @@ · 34 unmodified lines | |||
| 35 | #define BF538_FAMILY | 35 | #define BF538_FAMILY |
| 36 | 36 | ||
| 37 | #include "bf538.h" | 37 | #include "bf538.h" |
| 38 | #include "mem_map.h" | ||
| 39 | #include "defBF539.h" | 38 | #include "defBF539.h" |
| 40 | #include "anomaly.h" | 39 | #include "anomaly.h" |
| 41 | 40 | ||
| @@ -1,38 +1,16 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * File: include/asm-blackfin/mach-bf538/mem_map.h | 2 | * BF538 memory map |
| 3 | * Based on: | ||
| 4 | * Author: | ||
| 5 | * | 3 | * |
| 6 | * Created: | 4 | * Copyright 2004-2009 Analog Devices Inc. |
| 7 | * Description: | 5 | * Licensed under the GPL-2 or later. |
| 8 | * | ||
| 9 | * Rev: | ||
| 10 | * | ||
| 11 | * Modified: | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; see the file COPYING. | ||
| 27 | * If not, write to the Free Software Foundation, | ||
| 28 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 29 | */ | 6 | */ |
| 30 | 7 | ||
| 31 | #ifndef _MEM_MAP_538_H_ | 8 | #ifndef __BFIN_MACH_MEM_MAP_H__ |
| 32 | #define _MEM_MAP_538_H_ | 9 | #define __BFIN_MACH_MEM_MAP_H__ |
| 33 | 10 | ||
| 34 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ | 11 | #ifndef __BFIN_MEM_MAP_H__ |
| 35 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ | 12 | # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" |
| 13 | #endif | ||
| 36 | 14 | ||
| 37 | /* Async Memory Banks */ | 15 | /* Async Memory Banks */ |
| 38 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ | 16 | #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ |
| @@ -93,21 +71,4 @@ · 54 unmodified lines | |||
| 93 | #define BFIN_DSUPBANKS 0 | 71 | #define BFIN_DSUPBANKS 0 |
| 94 | #endif /*CONFIG_BFIN_DCACHE*/ | 72 | #endif /*CONFIG_BFIN_DCACHE*/ |
| 95 | 73 | ||
| 96 | 74 | #endif | |
| 97 | /* Level 2 Memory - none */ | ||
| 98 | |||
| 99 | #define L2_START 0 | ||
| 100 | #define L2_LENGTH 0 | ||
| 101 | |||
| 102 | /* Scratch Pad Memory */ | ||
| 103 | |||
| 104 | #define L1_SCRATCH_START 0xFFB00000 | ||
| 105 | #define L1_SCRATCH_LENGTH 0x1000 | ||
| 106 | |||
| 107 | #define GET_PDA_SAFE(preg) \ | ||
| 108 | preg.l = _cpu_pda; \ | ||
| 109 | preg.h = _cpu_pda; | ||
| 110 | |||
| 111 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 112 | |||
| 113 | #endif /* _MEM_MAP_538_H_ */ | ||
| @@ -76,7 +76,6 @@ static struct resource bfin_isp1760_resources[] = { · 75 unmodified lines | |||
| 76 | 76 | ||
| 77 | static struct isp1760_platform_data isp1760_priv = { | 77 | static struct isp1760_platform_data isp1760_priv = { |
| 78 | .is_isp1761 = 0, | 78 | .is_isp1761 = 0, |
| 79 | .port1_disable = 0, | ||
| 80 | .bus_width_16 = 1, | 79 | .bus_width_16 = 1, |
| 81 | .port1_otg = 0, | 80 | .port1_otg = 0, |
| 82 | .analog_oc = 0, | 81 | .analog_oc = 0, |
| @@ -18,7 +18,7 @@ · 17 unmodified lines | |||
| 18 | # error will not work on BF548 silicon version 0.0, or 0.1 | 18 | # error will not work on BF548 silicon version 0.0, or 0.1 |
| 19 | #endif | 19 | #endif |
| 20 | 20 | ||
| 21 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | 21 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
| 22 | #define ANOMALY_05000074 (1) | 22 | #define ANOMALY_05000074 (1) |
| 23 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | 23 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
| 24 | #define ANOMALY_05000119 (1) | 24 | #define ANOMALY_05000119 (1) |
| @@ -30,17 +30,17 @@ · 5 unmodified lines | |||
| 30 | #define ANOMALY_05000265 (1) | 30 | #define ANOMALY_05000265 (1) |
| 31 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | 31 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ |
| 32 | #define ANOMALY_05000272 (1) | 32 | #define ANOMALY_05000272 (1) |
| 33 | /* False Hardware Error Exception When ISR Context Is Not Restored */ | 33 | /* False Hardware Error Exception when ISR Context Is Not Restored */ |
| 34 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) | 34 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) |
| 35 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ | 35 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ |
| 36 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) | 36 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) |
| 37 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | 37 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 38 | #define ANOMALY_05000310 (1) | 38 | #define ANOMALY_05000310 (1) |
| 39 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | 39 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
| 40 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 1) | 40 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 1) |
| 41 | /* TWI Slave Boot Mode Is Not Functional */ | 41 | /* TWI Slave Boot Mode Is Not Functional */ |
| 42 | #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) | 42 | #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) |
| 43 | /* External FIFO Boot Mode Is Not Functional */ | 43 | /* FIFO Boot Mode Not Functional */ |
| 44 | #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) | 44 | #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) |
| 45 | /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ | 45 | /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ |
| 46 | #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) | 46 | #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) |
| @@ -178,8 +178,12 @@ · 131 unmodified lines | |||
| 178 | #define ANOMALY_05000450 (1) | 178 | #define ANOMALY_05000450 (1) |
| 179 | /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ | 179 | /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ |
| 180 | #define ANOMALY_05000456 (__SILICON_REVISION__ < 3) | 180 | #define ANOMALY_05000456 (__SILICON_REVISION__ < 3) |
| 181 | /* False Hardware Error when RETI points to invalid memory */ | 181 | /* False Hardware Error when RETI Points to Invalid Memory */ |
| 182 | #define ANOMALY_05000461 (1) | 182 | #define ANOMALY_05000461 (1) |
| 183 | /* USB Rx DMA hang */ | ||
| 184 | #define ANOMALY_05000465 (1) | ||
| 185 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ | ||
| 186 | #define ANOMALY_05000467 (1) | ||
| 183 | 187 | ||
| 184 | /* Anomalies that don't exist on this proc */ | 188 | /* Anomalies that don't exist on this proc */ |
| 185 | #define ANOMALY_05000099 (0) | 189 | #define ANOMALY_05000099 (0) |
| @@ -189,30 +193,36 @@ · 3 unmodified lines | |||
| 189 | #define ANOMALY_05000158 (0) | 193 | #define ANOMALY_05000158 (0) |
| 190 | #define ANOMALY_05000171 (0) | 194 | #define ANOMALY_05000171 (0) |
| 191 | #define ANOMALY_05000179 (0) | 195 | #define ANOMALY_05000179 (0) |
| 196 | #define ANOMALY_05000182 (0) | ||
| 192 | #define ANOMALY_05000183 (0) | 197 | #define ANOMALY_05000183 (0) |
| 193 | #define ANOMALY_05000198 (0) | 198 | #define ANOMALY_05000198 (0) |
| 199 | #define ANOMALY_05000202 (0) | ||
| 194 | #define ANOMALY_05000215 (0) | 200 | #define ANOMALY_05000215 (0) |
| 195 | #define ANOMALY_05000220 (0) | 201 | #define ANOMALY_05000220 (0) |
| 196 | #define ANOMALY_05000227 (0) | 202 | #define ANOMALY_05000227 (0) |
| 197 | #define ANOMALY_05000230 (0) | 203 | #define ANOMALY_05000230 (0) |
| 198 | #define ANOMALY_05000231 (0) | 204 | #define ANOMALY_05000231 (0) |
| 199 | #define ANOMALY_05000233 (0) | 205 | #define ANOMALY_05000233 (0) |
| 206 | #define ANOMALY_05000234 (0) | ||
| 200 | #define ANOMALY_05000242 (0) | 207 | #define ANOMALY_05000242 (0) |
| 201 | #define ANOMALY_05000244 (0) | 208 | #define ANOMALY_05000244 (0) |
| 202 | #define ANOMALY_05000248 (0) | 209 | #define ANOMALY_05000248 (0) |
| 203 | #define ANOMALY_05000250 (0) | 210 | #define ANOMALY_05000250 (0) |
| 204 | #define ANOMALY_05000254 (0) | 211 | #define ANOMALY_05000254 (0) |
| 212 | #define ANOMALY_05000257 (0) | ||
| 205 | #define ANOMALY_05000261 (0) | 213 | #define ANOMALY_05000261 (0) |
| 206 | #define ANOMALY_05000263 (0) | 214 | #define ANOMALY_05000263 (0) |
| 207 | #define ANOMALY_05000266 (0) | 215 | #define ANOMALY_05000266 (0) |
| 208 | #define ANOMALY_05000273 (0) | 216 | #define ANOMALY_05000273 (0) |
| 209 | #define ANOMALY_05000274 (0) | 217 | #define ANOMALY_05000274 (0) |
| 210 | #define ANOMALY_05000278 (0) | 218 | #define ANOMALY_05000278 (0) |
| 219 | #define ANOMALY_05000283 (0) | ||
| 211 | #define ANOMALY_05000287 (0) | 220 | #define ANOMALY_05000287 (0) |
| 212 | #define ANOMALY_05000301 (0) | 221 | #define ANOMALY_05000301 (0) |
| 213 | #define ANOMALY_05000305 (0) | 222 | #define ANOMALY_05000305 (0) |
| 214 | #define ANOMALY_05000307 (0) | 223 | #define ANOMALY_05000307 (0) |
| 215 | #define ANOMALY_05000311 (0) | 224 | #define ANOMALY_05000311 (0) |
| 225 | #define ANOMALY_05000315 (0) | ||
| 216 | #define ANOMALY_05000323 (0) | 226 | #define ANOMALY_05000323 (0) |
| 217 | #define ANOMALY_05000362 (1) | 227 | #define ANOMALY_05000362 (1) |
| 218 | #define ANOMALY_05000363 (0) | 228 | #define ANOMALY_05000363 (0) |
| @@ -33,7 +33,6 @@ · 32 unmodified lines | |||
| 33 | #define _MACH_BLACKFIN_H_ | 33 | #define _MACH_BLACKFIN_H_ |
| 34 | 34 | ||
| 35 | #include "bf548.h" | 35 | #include "bf548.h" |
| 36 | #include "mem_map.h" | ||
| 37 | #include "anomaly.h" | 36 | #include "anomaly.h" |
| 38 | 37 | ||
| 39 | #ifdef CONFIG_BF542 | 38 | #ifdef CONFIG_BF542 |
| @@ -1,38 +1,16 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * file: include/asm-blackfin/mach-bf548/mem_map.h | 2 | * BF548 memory map |
| 3 | * based on: | ||
| 4 | * author: | ||
| 5 | * | 3 | * |
| 6 | * created: | 4 | * Copyright 2004-2009 Analog Devices Inc. |
| 7 | * description: | 5 | * Licensed under the GPL-2 or later. |
| 8 | * Memory MAP Common header file for blackfin BF537/6/4 of processors. | ||
| 9 | * rev: | ||
| 10 | * | ||
| 11 | * modified: | ||
| 12 | * | ||
| 13 | * bugs: enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * this program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the gnu general public license as published by | ||
| 17 | * the free software foundation; either version 2, or (at your option) | ||
| 18 | * any later version. | ||
| 19 | * | ||
| 20 | * this program is distributed in the hope that it will be useful, | ||
| 21 | * but without any warranty; without even the implied warranty of | ||
| 22 | * merchantability or fitness for a particular purpose. see the | ||
| 23 | * gnu general public license for more details. | ||
| 24 | * | ||
| 25 | * you should have received a copy of the gnu general public license | ||
| 26 | * along with this program; see the file copying. | ||
| 27 | * if not, write to the free software foundation, | ||
| 28 | * 59 temple place - suite 330, boston, ma 02111-1307, usa. | ||
| 29 | */ | 6 | */ |
| 30 | 7 | ||
| 31 | #ifndef _MEM_MAP_548_H_ | 8 | #ifndef __BFIN_MACH_MEM_MAP_H__ |
| 32 | #define _MEM_MAP_548_H_ | 9 | #define __BFIN_MACH_MEM_MAP_H__ |
| 33 | 10 | ||
| 34 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ | 11 | #ifndef __BFIN_MEM_MAP_H__ |
| 35 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ | 12 | # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" |
| 13 | #endif | ||
| 36 | 14 | ||
| 37 | /* Async Memory Banks */ | 15 | /* Async Memory Banks */ |
| 38 | #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ | 16 | #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ |
| @@ -103,15 +81,4 @@ · 64 unmodified lines | |||
| 103 | # define L2_LENGTH 0x20000 | 81 | # define L2_LENGTH 0x20000 |
| 104 | #endif | 82 | #endif |
| 105 | 83 | ||
| 106 | /* Scratch Pad Memory */ | 84 | #endif |
| 107 | |||
| 108 | #define L1_SCRATCH_START 0xFFB00000 | ||
| 109 | #define L1_SCRATCH_LENGTH 0x1000 | ||
| 110 | |||
| 111 | #define GET_PDA_SAFE(preg) \ | ||
| 112 | preg.l = _cpu_pda; \ | ||
| 113 | preg.h = _cpu_pda; | ||
| 114 | |||
| 115 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 116 | |||
| 117 | #endif/* _MEM_MAP_548_H_ */ | ||
| @@ -62,7 +62,6 @@ static struct resource bfin_isp1760_resources[] = { · 61 unmodified lines | |||
| 62 | 62 | ||
| 63 | static struct isp1760_platform_data isp1760_priv = { | 63 | static struct isp1760_platform_data isp1760_priv = { |
| 64 | .is_isp1761 = 0, | 64 | .is_isp1761 = 0, |
| 65 | .port1_disable = 0, | ||
| 66 | .bus_width_16 = 1, | 65 | .bus_width_16 = 1, |
| 67 | .port1_otg = 0, | 66 | .port1_otg = 0, |
| 68 | .analog_oc = 0, | 67 | .analog_oc = 0, |
| @@ -18,19 +18,19 @@ · 17 unmodified lines | |||
| 18 | # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 | 18 | # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 |
| 19 | #endif | 19 | #endif |
| 20 | 20 | ||
| 21 | /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ | 21 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
| 22 | #define ANOMALY_05000074 (1) | 22 | #define ANOMALY_05000074 (1) |
| 23 | /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ | 23 | /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ |
| 24 | #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) | 24 | #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) |
| 25 | /* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ | 25 | /* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ |
| 26 | #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) | 26 | #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) |
| 27 | /* Testset instructions restricted to 32-bit aligned memory locations */ | 27 | /* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ |
| 28 | #define ANOMALY_05000120 (1) | 28 | #define ANOMALY_05000120 (1) |
| 29 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 29 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
| 30 | #define ANOMALY_05000122 (1) | 30 | #define ANOMALY_05000122 (1) |
| 31 | /* Erroneous exception when enabling cache */ | 31 | /* Erroneous Exception when Enabling Cache */ |
| 32 | #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) | 32 | #define ANOMALY_05000125 (__SILICON_REVISION__ < 3) |
| 33 | /* Signbits instruction not functional under certain conditions */ | 33 | /* SIGNBITS Instruction Not Functional under Certain Conditions */ |
| 34 | #define ANOMALY_05000127 (1) | 34 | #define ANOMALY_05000127 (1) |
| 35 | /* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ | 35 | /* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ |
| 36 | #define ANOMALY_05000134 (__SILICON_REVISION__ < 3) | 36 | #define ANOMALY_05000134 (__SILICON_REVISION__ < 3) |
| @@ -40,7 +40,7 @@ · 3 unmodified lines | |||
| 40 | #define ANOMALY_05000136 (__SILICON_REVISION__ < 3) | 40 | #define ANOMALY_05000136 (__SILICON_REVISION__ < 3) |
| 41 | /* Allowing the SPORT RX FIFO to fill will cause an overflow */ | 41 | /* Allowing the SPORT RX FIFO to fill will cause an overflow */ |
| 42 | #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) | 42 | #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) |
| 43 | /* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ | 43 | /* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ |
| 44 | #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) | 44 | #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) |
| 45 | /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ | 45 | /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ |
| 46 | #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) | 46 | #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) |
| @@ -52,7 +52,7 @@ · 5 unmodified lines | |||
| 52 | #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) | 52 | #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) |
| 53 | /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ | 53 | /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ |
| 54 | #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) | 54 | #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) |
| 55 | /* IMDMA S1/D1 channel may stall */ | 55 | /* IMDMA S1/D1 Channel May Stall */ |
| 56 | #define ANOMALY_05000149 (1) | 56 | #define ANOMALY_05000149 (1) |
| 57 | /* DMA engine may lose data due to incorrect handshaking */ | 57 | /* DMA engine may lose data due to incorrect handshaking */ |
| 58 | #define ANOMALY_05000150 (__SILICON_REVISION__ < 3) | 58 | #define ANOMALY_05000150 (__SILICON_REVISION__ < 3) |
| @@ -66,7 +66,7 @@ · 7 unmodified lines | |||
| 66 | #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) | 66 | #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) |
| 67 | /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ | 67 | /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ |
| 68 | #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) | 68 | #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) |
| 69 | /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ | 69 | /* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ |
| 70 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) | 70 | #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) |
| 71 | /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ | 71 | /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ |
| 72 | #define ANOMALY_05000159 (__SILICON_REVISION__ < 3) | 72 | #define ANOMALY_05000159 (__SILICON_REVISION__ < 3) |
| @@ -76,17 +76,17 @@ · 3 unmodified lines | |||
| 76 | #define ANOMALY_05000161 (__SILICON_REVISION__ < 3) | 76 | #define ANOMALY_05000161 (__SILICON_REVISION__ < 3) |
| 77 | /* DMEM_CONTROL<12> is not set on Reset */ | 77 | /* DMEM_CONTROL<12> is not set on Reset */ |
| 78 | #define ANOMALY_05000162 (__SILICON_REVISION__ < 3) | 78 | #define ANOMALY_05000162 (__SILICON_REVISION__ < 3) |
| 79 | /* SPORT transmit data is not gated by external frame sync in certain conditions */ | 79 | /* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ |
| 80 | #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) | 80 | #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) |
| 81 | /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ | 81 | /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ |
| 82 | #define ANOMALY_05000166 (1) | 82 | #define ANOMALY_05000166 (1) |
| 83 | /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ | 83 | /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ |
| 84 | #define ANOMALY_05000167 (1) | 84 | #define ANOMALY_05000167 (1) |
| 85 | /* SDRAM auto-refresh and subsequent Power Ups */ | 85 | /* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */ |
| 86 | #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) | 86 | #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) |
| 87 | /* DATA CPLB page miss can result in lost write-through cache data writes */ | 87 | /* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */ |
| 88 | #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) | 88 | #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) |
| 89 | /* Boot-ROM code modifies SICA_IWRx wakeup registers */ | 89 | /* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ |
| 90 | #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) | 90 | #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) |
| 91 | /* DSPID register values incorrect */ | 91 | /* DSPID register values incorrect */ |
| 92 | #define ANOMALY_05000172 (__SILICON_REVISION__ < 3) | 92 | #define ANOMALY_05000172 (__SILICON_REVISION__ < 3) |
| @@ -96,29 +96,29 @@ · 3 unmodified lines | |||
| 96 | #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) | 96 | #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) |
| 97 | /* Overlapping Sequencer and Memory Stalls */ | 97 | /* Overlapping Sequencer and Memory Stalls */ |
| 98 | #define ANOMALY_05000175 (__SILICON_REVISION__ < 5) | 98 | #define ANOMALY_05000175 (__SILICON_REVISION__ < 5) |
| 99 | /* Multiplication of (-1) by (-1) followed by an accumulator saturation */ | 99 | /* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */ |
| 100 | #define ANOMALY_05000176 (__SILICON_REVISION__ < 5) | 100 | #define ANOMALY_05000176 (__SILICON_REVISION__ < 5) |
| 101 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ | 101 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ |
| 102 | #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) | 102 | #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) |
| 103 | /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ | 103 | /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ |
| 104 | #define ANOMALY_05000180 (1) | 104 | #define ANOMALY_05000180 (1) |
| 105 | /* Disabling the PPI resets the PPI configuration registers */ | 105 | /* Disabling the PPI Resets the PPI Configuration Registers */ |
| 106 | #define ANOMALY_05000181 (__SILICON_REVISION__ < 5) | 106 | #define ANOMALY_05000181 (__SILICON_REVISION__ < 5) |
| 107 | /* IMDMA does not operate to full speed for 600MHz and higher devices */ | 107 | /* Internal Memory DMA Does Not Operate at Full Speed */ |
| 108 | #define ANOMALY_05000182 (1) | 108 | #define ANOMALY_05000182 (1) |
| 109 | /* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ | 109 | /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ |
| 110 | #define ANOMALY_05000184 (__SILICON_REVISION__ < 5) | 110 | #define ANOMALY_05000184 (__SILICON_REVISION__ < 5) |
| 111 | /* PPI TX Mode with 2 External Frame Syncs */ | 111 | /* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */ |
| 112 | #define ANOMALY_05000185 (__SILICON_REVISION__ < 5) | 112 | #define ANOMALY_05000185 (__SILICON_REVISION__ < 5) |
| 113 | /* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ | 113 | /* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */ |
| 114 | #define ANOMALY_05000186 (__SILICON_REVISION__ < 5) | 114 | #define ANOMALY_05000186 (__SILICON_REVISION__ < 5) |
| 115 | /* IMDMA Corrupted Data after a Halt */ | 115 | /* IMDMA Corrupted Data after a Halt */ |
| 116 | #define ANOMALY_05000187 (1) | 116 | #define ANOMALY_05000187 (1) |
| 117 | /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ | 117 | /* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ |
| 118 | #define ANOMALY_05000188 (__SILICON_REVISION__ < 5) | 118 | #define ANOMALY_05000188 (__SILICON_REVISION__ < 5) |
| 119 | /* False Protection Exceptions */ | 119 | /* False Protection Exceptions when Speculative Fetch Is Cancelled */ |
| 120 | #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) | 120 | #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) |
| 121 | /* PPI not functional at core voltage < 1Volt */ | 121 | /* PPI Not Functional at Core Voltage < 1Volt */ |
| 122 | #define ANOMALY_05000190 (1) | 122 | #define ANOMALY_05000190 (1) |
| 123 | /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ | 123 | /* PPI does not invert the Driving PPICLK edge in Transmit Modes */ |
| 124 | #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) | 124 | #define ANOMALY_05000191 (__SILICON_REVISION__ < 3) |
| @@ -126,7 +126,7 @@ · 1 unmodified line | |||
| 126 | #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) | 126 | #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) |
| 127 | /* Restarting SPORT in Specific Modes May Cause Data Corruption */ | 127 | /* Restarting SPORT in Specific Modes May Cause Data Corruption */ |
| 128 | #define ANOMALY_05000194 (__SILICON_REVISION__ < 5) | 128 | #define ANOMALY_05000194 (__SILICON_REVISION__ < 5) |
| 129 | /* Failing MMR Accesses When Stalled by Preceding Memory Read */ | 129 | /* Failing MMR Accesses when Preceding Memory Read Stalls */ |
| 130 | #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) | 130 | #define ANOMALY_05000198 (__SILICON_REVISION__ < 5) |
| 131 | /* Current DMA Address Shows Wrong Value During Carry Fix */ | 131 | /* Current DMA Address Shows Wrong Value During Carry Fix */ |
| 132 | #define ANOMALY_05000199 (__SILICON_REVISION__ < 5) | 132 | #define ANOMALY_05000199 (__SILICON_REVISION__ < 5) |
| @@ -134,9 +134,9 @@ · 1 unmodified line | |||
| 134 | #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) | 134 | #define ANOMALY_05000200 (__SILICON_REVISION__ < 5) |
| 135 | /* Possible Infinite Stall with Specific Dual-DAG Situation */ | 135 | /* Possible Infinite Stall with Specific Dual-DAG Situation */ |
| 136 | #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) | 136 | #define ANOMALY_05000202 (__SILICON_REVISION__ < 5) |
| 137 | /* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ | 137 | /* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */ |
| 138 | #define ANOMALY_05000204 (__SILICON_REVISION__ < 5) | 138 | #define ANOMALY_05000204 (__SILICON_REVISION__ < 5) |
| 139 | /* Specific sequence that can cause DMA error or DMA stopping */ | 139 | /* Specific Sequence that Can Cause DMA Error or DMA Stopping */ |
| 140 | #define ANOMALY_05000205 (__SILICON_REVISION__ < 5) | 140 | #define ANOMALY_05000205 (__SILICON_REVISION__ < 5) |
| 141 | /* Recovery from "Brown-Out" Condition */ | 141 | /* Recovery from "Brown-Out" Condition */ |
| 142 | #define ANOMALY_05000207 (__SILICON_REVISION__ < 5) | 142 | #define ANOMALY_05000207 (__SILICON_REVISION__ < 5) |
| @@ -158,7 +158,7 @@ · 15 unmodified lines | |||
| 158 | #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) | 158 | #define ANOMALY_05000230 (__SILICON_REVISION__ < 5) |
| 159 | /* UART STB Bit Incorrectly Affects Receiver Setting */ | 159 | /* UART STB Bit Incorrectly Affects Receiver Setting */ |
| 160 | #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) | 160 | #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) |
| 161 | /* SPORT data transmit lines are incorrectly driven in multichannel mode */ | 161 | /* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */ |
| 162 | #define ANOMALY_05000232 (__SILICON_REVISION__ < 5) | 162 | #define ANOMALY_05000232 (__SILICON_REVISION__ < 5) |
| 163 | /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ | 163 | /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ |
| 164 | #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) | 164 | #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) |
| @@ -166,7 +166,7 @@ · 1 unmodified line | |||
| 166 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) | 166 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) |
| 167 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ | 167 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 168 | #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) | 168 | #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) |
| 169 | /* TESTSET operation forces stall on the other core */ | 169 | /* TESTSET Operation Forces Stall on the Other Core */ |
| 170 | #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) | 170 | #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) |
| 171 | /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ | 171 | /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ |
| 172 | #define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) | 172 | #define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) |
| @@ -192,9 +192,9 @@ · 19 unmodified lines | |||
| 192 | #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) | 192 | #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) |
| 193 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | 193 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
| 194 | #define ANOMALY_05000265 (__SILICON_REVISION__ < 5) | 194 | #define ANOMALY_05000265 (__SILICON_REVISION__ < 5) |
| 195 | /* IMDMA destination IRQ status must be read prior to using IMDMA */ | 195 | /* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */ |
| 196 | #define ANOMALY_05000266 (__SILICON_REVISION__ > 3) | 196 | #define ANOMALY_05000266 (__SILICON_REVISION__ > 3) |
| 197 | /* IMDMA may corrupt data under certain conditions */ | 197 | /* IMDMA May Corrupt Data under Certain Conditions */ |
| 198 | #define ANOMALY_05000267 (1) | 198 | #define ANOMALY_05000267 (1) |
| 199 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ | 199 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ |
| 200 | #define ANOMALY_05000269 (1) | 200 | #define ANOMALY_05000269 (1) |
| @@ -202,7 +202,7 @@ · 1 unmodified line | |||
| 202 | #define ANOMALY_05000270 (1) | 202 | #define ANOMALY_05000270 (1) |
| 203 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | 203 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ |
| 204 | #define ANOMALY_05000272 (1) | 204 | #define ANOMALY_05000272 (1) |
| 205 | /* Data cache write back to external synchronous memory may be lost */ | 205 | /* Data Cache Write Back to External Synchronous Memory May Be Lost */ |
| 206 | #define ANOMALY_05000274 (1) | 206 | #define ANOMALY_05000274 (1) |
| 207 | /* PPI Timing and Sampling Information Updates */ | 207 | /* PPI Timing and Sampling Information Updates */ |
| 208 | #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) | 208 | #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) |
| @@ -212,17 +212,17 @@ · 3 unmodified lines | |||
| 212 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) | 212 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) |
| 213 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ | 213 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ |
| 214 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) | 214 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) |
| 215 | /* False Hardware Error Exception When ISR Context Is Not Restored */ | 215 | /* False Hardware Error Exception when ISR Context Is Not Restored */ |
| 216 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 5) | 216 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 5) |
| 217 | /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ | 217 | /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ |
| 218 | #define ANOMALY_05000283 (1) | 218 | #define ANOMALY_05000283 (1) |
| 219 | /* A read will receive incorrect data under certain conditions */ | 219 | /* Reads Will Receive Incorrect Data under Certain Conditions */ |
| 220 | #define ANOMALY_05000287 (__SILICON_REVISION__ < 5) | 220 | #define ANOMALY_05000287 (__SILICON_REVISION__ < 5) |
| 221 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ | 221 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ |
| 222 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 5) | 222 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 5) |
| 223 | /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ | 223 | /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ |
| 224 | #define ANOMALY_05000301 (1) | 224 | #define ANOMALY_05000301 (1) |
| 225 | /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ | 225 | /* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */ |
| 226 | #define ANOMALY_05000302 (1) | 226 | #define ANOMALY_05000302 (1) |
| 227 | /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ | 227 | /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ |
| 228 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) | 228 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) |
| @@ -230,25 +230,25 @@ · 1 unmodified line | |||
| 230 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 5) | 230 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 5) |
| 231 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | 231 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 232 | #define ANOMALY_05000310 (1) | 232 | #define ANOMALY_05000310 (1) |
| 233 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | 233 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
| 234 | #define ANOMALY_05000312 (1) | 234 | #define ANOMALY_05000312 (1) |
| 235 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ | 235 | /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
| 236 | #define ANOMALY_05000313 (1) | 236 | #define ANOMALY_05000313 (1) |
| 237 | /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ | 237 | /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ |
| 238 | #define ANOMALY_05000315 (1) | 238 | #define ANOMALY_05000315 (1) |
| 239 | /* PF2 Output Remains Asserted After SPI Master Boot */ | 239 | /* PF2 Output Remains Asserted after SPI Master Boot */ |
| 240 | #define ANOMALY_05000320 (__SILICON_REVISION__ > 3) | 240 | #define ANOMALY_05000320 (__SILICON_REVISION__ > 3) |
| 241 | /* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ | 241 | /* Erroneous GPIO Flag Pin Operations under Specific Sequences */ |
| 242 | #define ANOMALY_05000323 (1) | 242 | #define ANOMALY_05000323 (1) |
| 243 | /* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ | 243 | /* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */ |
| 244 | #define ANOMALY_05000326 (__SILICON_REVISION__ > 3) | 244 | #define ANOMALY_05000326 (__SILICON_REVISION__ > 3) |
| 245 | /* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ | 245 | /* 24-Bit SPI Boot Mode Is Not Functional */ |
| 246 | #define ANOMALY_05000331 (__SILICON_REVISION__ < 5) | 246 | #define ANOMALY_05000331 (__SILICON_REVISION__ < 5) |
| 247 | /* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ | 247 | /* Slave SPI Boot Mode Is Not Functional */ |
| 248 | #define ANOMALY_05000332 (__SILICON_REVISION__ < 5) | 248 | #define ANOMALY_05000332 (__SILICON_REVISION__ < 5) |
| 249 | /* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ | 249 | /* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */ |
| 250 | #define ANOMALY_05000333 (__SILICON_REVISION__ < 5) | 250 | #define ANOMALY_05000333 (__SILICON_REVISION__ < 5) |
| 251 | /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ | 251 | /* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */ |
| 252 | #define ANOMALY_05000339 (__SILICON_REVISION__ < 5) | 252 | #define ANOMALY_05000339 (__SILICON_REVISION__ < 5) |
| 253 | /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ | 253 | /* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ |
| 254 | #define ANOMALY_05000343 (__SILICON_REVISION__ < 5) | 254 | #define ANOMALY_05000343 (__SILICON_REVISION__ < 5) |
| @@ -276,7 +276,7 @@ · 21 unmodified lines | |||
| 276 | #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) | 276 | #define ANOMALY_05000428 (__SILICON_REVISION__ > 3) |
| 277 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 277 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 278 | #define ANOMALY_05000443 (1) | 278 | #define ANOMALY_05000443 (1) |
| 279 | /* False Hardware Error when RETI points to invalid memory */ | 279 | /* False Hardware Error when RETI Points to Invalid Memory */ |
| 280 | #define ANOMALY_05000461 (1) | 280 | #define ANOMALY_05000461 (1) |
| 281 | 281 | ||
| 282 | /* Anomalies that don't exist on this proc */ | 282 | /* Anomalies that don't exist on this proc */ |
| @@ -284,6 +284,7 @@ · 1 unmodified line | |||
| 284 | #define ANOMALY_05000158 (0) | 284 | #define ANOMALY_05000158 (0) |
| 285 | #define ANOMALY_05000183 (0) | 285 | #define ANOMALY_05000183 (0) |
| 286 | #define ANOMALY_05000233 (0) | 286 | #define ANOMALY_05000233 (0) |
| 287 | #define ANOMALY_05000234 (0) | ||
| 287 | #define ANOMALY_05000273 (0) | 288 | #define ANOMALY_05000273 (0) |
| 288 | #define ANOMALY_05000311 (0) | 289 | #define ANOMALY_05000311 (0) |
| 289 | #define ANOMALY_05000353 (1) | 290 | #define ANOMALY_05000353 (1) |
| @@ -298,5 +299,7 @@ · 8 unmodified lines | |||
| 298 | #define ANOMALY_05000448 (0) | 299 | #define ANOMALY_05000448 (0) |
| 299 | #define ANOMALY_05000456 (0) | 300 | #define ANOMALY_05000456 (0) |
| 300 | #define ANOMALY_05000450 (0) | 301 | #define ANOMALY_05000450 (0) |
| 302 | #define ANOMALY_05000465 (0) | ||
| 303 | #define ANOMALY_05000467 (0) | ||
| 301 | 304 | ||
| 302 | #endif | 305 | #endif |
| @@ -34,7 +34,6 @@ · 33 unmodified lines | |||
| 34 | #define BF561_FAMILY | 34 | #define BF561_FAMILY |
| 35 | 35 | ||
| 36 | #include "bf561.h" | 36 | #include "bf561.h" |
| 37 | #include "mem_map.h" | ||
| 38 | #include "defBF561.h" | 37 | #include "defBF561.h" |
| 39 | #include "anomaly.h" | 38 | #include "anomaly.h" |
| 40 | 39 | ||
| @@ -1,13 +1,16 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Memory MAP | 2 | * BF561 memory map |
| 3 | * Common header file for blackfin BF561 of processors. | 3 | * |
| 4 | * Copyright 2004-2009 Analog Devices Inc. | ||
| 5 | * Licensed under the GPL-2 or later. | ||
| 4 | */ | 6 | */ |
| 5 | 7 | ||
| 6 | #ifndef _MEM_MAP_561_H_ | 8 | #ifndef __BFIN_MACH_MEM_MAP_H__ |
| 7 | #define _MEM_MAP_561_H_ | 9 | #define __BFIN_MACH_MEM_MAP_H__ |
| 8 | 10 | ||
| 9 | #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ | 11 | #ifndef __BFIN_MEM_MAP_H__ |
| 10 | #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ | 12 | # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" |
| 13 | #endif | ||
| 11 | 14 | ||
| 12 | /* Async Memory Banks */ | 15 | /* Async Memory Banks */ |
| 13 | #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ | 16 | #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ |
| @@ -82,9 +85,6 @@ · 68 unmodified lines | |||
| 82 | #define COREA_L1_SCRATCH_START 0xFFB00000 | 85 | #define COREA_L1_SCRATCH_START 0xFFB00000 |
| 83 | #define COREB_L1_SCRATCH_START 0xFF700000 | 86 | #define COREB_L1_SCRATCH_START 0xFF700000 |
| 84 | 87 | ||
| 85 | #define L1_SCRATCH_START COREA_L1_SCRATCH_START | ||
| 86 | #define L1_SCRATCH_LENGTH 0x1000 | ||
| 87 | |||
| 88 | #ifdef __ASSEMBLY__ | 88 | #ifdef __ASSEMBLY__ |
| 89 | 89 | ||
| 90 | /* | 90 | /* |
| @@ -155,14 +155,42 @@ · 64 unmodified lines | |||
| 155 | dreg = ROT dreg BY -1; \ | 155 | dreg = ROT dreg BY -1; \ |
| 156 | dreg = CC; | 156 | dreg = CC; |
| 157 | 157 | ||
| 158 | #else | 158 | static inline unsigned long get_l1_scratch_start_cpu(int cpu) |
| 159 | #define GET_PDA_SAFE(preg) \ | 159 | { |
| 160 | preg.l = _cpu_pda; \ | 160 | return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; |
| 161 | preg.h = _cpu_pda; | 161 | } |
| 162 | static inline unsigned long get_l1_code_start_cpu(int cpu) | ||
| 163 | { | ||
| 164 | return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START; | ||
| 165 | } | ||
| 166 | static inline unsigned long get_l1_data_a_start_cpu(int cpu) | ||
| 167 | { | ||
| 168 | return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START; | ||
| 169 | } | ||
| 170 | static inline unsigned long get_l1_data_b_start_cpu(int cpu) | ||
| 171 | { | ||
| 172 | return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START; | ||
| 173 | } | ||
| 174 | |||
| 175 | static inline unsigned long get_l1_scratch_start(void) | ||
| 176 | { | ||
| 177 | return get_l1_scratch_start_cpu(blackfin_core_id()); | ||
| 178 | } | ||
| 179 | static inline unsigned long get_l1_code_start(void) | ||
| 180 | { | ||
| 181 | return get_l1_code_start_cpu(blackfin_core_id()); | ||
| 182 | } | ||
| 183 | static inline unsigned long get_l1_data_a_start(void) | ||
| 184 | { | ||
| 185 | return get_l1_data_a_start_cpu(blackfin_core_id()); | ||
| 186 | } | ||
| 187 | static inline unsigned long get_l1_data_b_start(void) | ||
| 188 | { | ||
| 189 | return get_l1_data_b_start_cpu(blackfin_core_id()); | ||
| 190 | } | ||
| 162 | 191 | ||
| 163 | #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) | ||
| 164 | #endif /* CONFIG_SMP */ | 192 | #endif /* CONFIG_SMP */ |
| 165 | 193 | ||
| 166 | #endif /* __ASSEMBLY__ */ | 194 | #endif /* __ASSEMBLY__ */ |
| 167 | 195 | ||
| 168 | #endif /* _MEM_MAP_533_H_ */ | 196 | #endif |
| @@ -74,7 +74,7 @@ · 73 unmodified lines | |||
| 74 | 74 | ||
| 75 | /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ | 75 | /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ |
| 76 | #if ANOMALY_05000220 && \ | 76 | #if ANOMALY_05000220 && \ |
| 77 | ((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \ | 77 | ((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \ |
| 78 | (!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB))) | 78 | (!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK))) |
| 79 | # error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB. | 79 | # error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB. |
| 80 | #endif | 80 | #endif |
| @@ -141,7 +141,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) · 140 unmodified lines | |||
| 141 | sclk = get_sclk() / 1000; | 141 | sclk = get_sclk() / 1000; |
| 142 | 142 | ||
| 143 | #if ANOMALY_05000273 || ANOMALY_05000274 || \ | 143 | #if ANOMALY_05000273 || ANOMALY_05000274 || \ |
| 144 | (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) | 144 | (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) |
| 145 | min_cclk = sclk * 2; | 145 | min_cclk = sclk * 2; |
| 146 | #else | 146 | #else |
| 147 | min_cclk = sclk; | 147 | min_cclk = sclk; |
| @@ -1609,6 +1609,7 @@ ENTRY(_sys_call_table) · 1608 unmodified lines | |||
| 1609 | .long _sys_preadv | 1609 | .long _sys_preadv |
| 1610 | .long _sys_pwritev | 1610 | .long _sys_pwritev |
| 1611 | .long _sys_rt_tgsigqueueinfo | 1611 | .long _sys_rt_tgsigqueueinfo |
| 1612 | .long _sys_perf_counter_open | ||
| 1612 | 1613 | ||
| 1613 | .rept NR_syscalls-(.-_sys_call_table)/4 | 1614 | .rept NR_syscalls-(.-_sys_call_table)/4 |
| 1614 | .long _sys_ni_syscall | 1615 | .long _sys_ni_syscall |
| @@ -1052,35 +1052,34 @@ int __init init_arch_irq(void) · 1051 unmodified lines | |||
| 1052 | set_irq_chained_handler(irq, bfin_demux_error_irq); | 1052 | set_irq_chained_handler(irq, bfin_demux_error_irq); |
| 1053 | break; | 1053 | break; |
| 1054 | #endif | 1054 | #endif |
| 1055 | #if defined(CONFIG_TICKSOURCE_GPTMR0) | ||
| 1056 | case IRQ_TIMER0: | ||
| 1057 | set_irq_handler(irq, handle_percpu_irq); | ||
| 1058 | break; | ||
| 1059 | #endif | ||
| 1060 | #ifdef CONFIG_SMP | 1055 | #ifdef CONFIG_SMP |
| 1061 | case IRQ_SUPPLE_0: | 1056 | case IRQ_SUPPLE_0: |
| 1062 | case IRQ_SUPPLE_1: | 1057 | case IRQ_SUPPLE_1: |
| 1063 | set_irq_handler(irq, handle_percpu_irq); | 1058 | set_irq_handler(irq, handle_percpu_irq); |
| 1064 | break; | 1059 | break; |
| 1065 | #endif | 1060 | #endif |
| 1066 | default: | ||
| 1067 | #ifdef CONFIG_IPIPE | 1061 | #ifdef CONFIG_IPIPE |
| 1068 | /* | 1062 | #ifndef CONFIG_TICKSOURCE_CORETMR |
| 1069 | * We want internal interrupt sources to be | 1063 | case IRQ_TIMER0: |
| 1070 | * masked, because ISRs may trigger interrupts | 1064 | set_irq_handler(irq, handle_simple_irq); |
| 1071 | * recursively (e.g. DMA), but interrupts are | 1065 | break; |
| 1072 | * _not_ masked at CPU level. So let's handle | 1066 | #endif /* !CONFIG_TICKSOURCE_CORETMR */ |
| 1073 | * most of them as level interrupts, except | 1067 | case IRQ_CORETMR: |
| 1074 | * the timer interrupt which is special. | 1068 | set_irq_handler(irq, handle_simple_irq); |
| 1075 | */ | 1069 | break; |
| 1076 | if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR) | 1070 | default: |
| 1077 | set_irq_handler(irq, handle_simple_irq); | 1071 | set_irq_handler(irq, handle_level_irq); |
| 1078 | else | 1072 | break; |
| 1079 | set_irq_handler(irq, handle_level_irq); | ||
| 1080 | #else /* !CONFIG_IPIPE */ | 1073 | #else /* !CONFIG_IPIPE */ |
| 1074 | #ifdef CONFIG_TICKSOURCE_GPTMR0 | ||
| 1075 | case IRQ_TIMER0: | ||
| 1076 | set_irq_handler(irq, handle_percpu_irq); | ||
| 1077 | break; | ||
| 1078 | #endif /* CONFIG_TICKSOURCE_GPTMR0 */ | ||
| 1079 | default: | ||
| 1081 | set_irq_handler(irq, handle_simple_irq); | 1080 | set_irq_handler(irq, handle_simple_irq); |
| 1082 | #endif /* !CONFIG_IPIPE */ | ||
| 1083 | break; | 1081 | break; |
| 1082 | #endif /* !CONFIG_IPIPE */ | ||
| 1084 | } | 1083 | } |
| 1085 | } | 1084 | } |
| 1086 | 1085 | ||
| @@ -1224,15 +1223,14 @@ __attribute__((l1_text)) · 137 unmodified lines | |||
| 1224 | asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | 1223 | asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) |
| 1225 | { | 1224 | { |
| 1226 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); | 1225 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); |
| 1227 | struct ipipe_domain *this_domain = ipipe_current_domain; | 1226 | struct ipipe_domain *this_domain = __ipipe_current_domain; |
| 1228 | struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; | 1227 | struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; |
| 1229 | struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; | 1228 | struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; |
| 1230 | int irq, s; | 1229 | int irq, s; |
| 1231 | 1230 | ||
| 1232 | if (likely(vec == EVT_IVTMR_P)) { | 1231 | if (likely(vec == EVT_IVTMR_P)) |
| 1233 | irq = IRQ_CORETMR; | 1232 | irq = IRQ_CORETMR; |
| 1234 | 1233 | else { | |
| 1235 | } else { | ||
| 1236 | #if defined(SIC_ISR0) || defined(SICA_ISR0) | 1234 | #if defined(SIC_ISR0) || defined(SICA_ISR0) |
| 1237 | unsigned long sic_status[3]; | 1235 | unsigned long sic_status[3]; |
| 1238 | 1236 | ||
| @@ -1262,12 +1260,11 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) · 23 unmodified lines | |||
| 1262 | break; | 1260 | break; |
| 1263 | } | 1261 | } |
| 1264 | #endif | 1262 | #endif |
| 1265 | |||
| 1266 | irq = ivg->irqno; | 1263 | irq = ivg->irqno; |
| 1267 | } | 1264 | } |
| 1268 | 1265 | ||
| 1269 | if (irq == IRQ_SYSTMR) { | 1266 | if (irq == IRQ_SYSTMR) { |
| 1270 | #ifndef CONFIG_GENERIC_CLOCKEVENTS | 1267 | #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0) |
| 1271 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ | 1268 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ |
| 1272 | #endif | 1269 | #endif |
| 1273 | /* This is basically what we need from the register frame. */ | 1270 | /* This is basically what we need from the register frame. */ |
| @@ -132,7 +132,7 @@ int bf53x_resume_l1_mem(unsigned char *memptr) · 131 unmodified lines | |||
| 132 | return 0; | 132 | return 0; |
| 133 | } | 133 | } |
| 134 | 134 | ||
| 135 | #ifdef CONFIG_BFIN_WB | 135 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
| 136 | static void flushinv_all_dcache(void) | 136 | static void flushinv_all_dcache(void) |
| 137 | { | 137 | { |
| 138 | u32 way, bank, subbank, set; | 138 | u32 way, bank, subbank, set; |
| @@ -175,7 +175,7 @@ static inline void dcache_disable(void) · 36 unmodified lines | |||
| 175 | #ifdef CONFIG_BFIN_DCACHE | 175 | #ifdef CONFIG_BFIN_DCACHE |
| 176 | unsigned long ctrl; | 176 | unsigned long ctrl; |
| 177 | 177 | ||
| 178 | #ifdef CONFIG_BFIN_WB | 178 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
| 179 | flushinv_all_dcache(); | 179 | flushinv_all_dcache(); |
| 180 | #endif | 180 | #endif |
| 181 | SSYNC(); | 181 | SSYNC(); |
| @@ -160,7 +160,7 @@ void __init mem_init(void) · 159 unmodified lines | |||
| 160 | 160 | ||
| 161 | /* do not count in kernel image between _rambase and _ramstart */ | 161 | /* do not count in kernel image between _rambase and _ramstart */ |
| 162 | reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; | 162 | reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; |
| 163 | #if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) | 163 | #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263) |
| 164 | reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT; | 164 | reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT; |
| 165 | #endif | 165 | #endif |
| 166 | 166 | ||
| @@ -24,7 +24,7 @@ int cris_request_dma(unsigned int dmanr, const char * device_id, · 23 unmodified lines | |||
| 24 | unsigned long int gens; | 24 | unsigned long int gens; |
| 25 | int fail = -EINVAL; | 25 | int fail = -EINVAL; |
| 26 | 26 | ||
| 27 | if ((dmanr < 0) || (dmanr >= MAX_DMA_CHANNELS)) { | 27 | if (dmanr >= MAX_DMA_CHANNELS) { |
| 28 | printk(KERN_CRIT "cris_request_dma: invalid DMA channel %u\n", dmanr); | 28 | printk(KERN_CRIT "cris_request_dma: invalid DMA channel %u\n", dmanr); |
| 29 | return -EINVAL; | 29 | return -EINVAL; |
| 30 | } | 30 | } |
| @@ -213,7 +213,7 @@ int cris_request_dma(unsigned int dmanr, const char * device_id, · 182 unmodified lines | |||
| 213 | void cris_free_dma(unsigned int dmanr, const char * device_id) | 213 | void cris_free_dma(unsigned int dmanr, const char * device_id) |
| 214 | { | 214 | { |
| 215 | unsigned long flags; | 215 | unsigned long flags; |
| 216 | if ((dmanr < 0) || (dmanr >= MAX_DMA_CHANNELS)) { | 216 | if (dmanr >= MAX_DMA_CHANNELS) { |
| 217 | printk(KERN_CRIT "cris_free_dma: invalid DMA channel %u\n", dmanr); | 217 | printk(KERN_CRIT "cris_free_dma: invalid DMA channel %u\n", dmanr); |
| 218 | return; | 218 | return; |
| 219 | } | 219 | } |
| @@ -1395,7 +1395,7 @@ static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char · 1394 unmodified lines | |||
| 1395 | if (padlen < MD5_MIN_PAD_LENGTH) padlen += MD5_BLOCK_LENGTH; | 1395 | if (padlen < MD5_MIN_PAD_LENGTH) padlen += MD5_BLOCK_LENGTH; |
| 1396 | 1396 | ||
| 1397 | p = kmalloc(padlen, alloc_flag); | 1397 | p = kmalloc(padlen, alloc_flag); |
| 1398 | if (!pad) return -ENOMEM; | 1398 | if (!p) return -ENOMEM; |
| 1399 | 1399 | ||
| 1400 | *p = 0x80; | 1400 | *p = 0x80; |
| 1401 | memset(p+1, 0, padlen - 1); | 1401 | memset(p+1, 0, padlen - 1); |
| @@ -1427,7 +1427,7 @@ static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, cha · 25 unmodified lines | |||
| 1427 | if (padlen < SHA1_MIN_PAD_LENGTH) padlen += SHA1_BLOCK_LENGTH; | 1427 | if (padlen < SHA1_MIN_PAD_LENGTH) padlen += SHA1_BLOCK_LENGTH; |
| 1428 | 1428 | ||
| 1429 | p = kmalloc(padlen, alloc_flag); | 1429 | p = kmalloc(padlen, alloc_flag); |
| 1430 | if (!pad) return -ENOMEM; | 1430 | if (!p) return -ENOMEM; |
| 1431 | 1431 | ||
| 1432 | *p = 0x80; | 1432 | *p = 0x80; |
| 1433 | memset(p+1, 0, padlen - 1); | 1433 | memset(p+1, 0, padlen - 1); |
| @@ -430,8 +430,8 @@ crisv32_do_multiple(struct pt_regs* regs) · 429 unmodified lines | |||
| 430 | masked[i] &= ~TIMER_MASK; | 430 | masked[i] &= ~TIMER_MASK; |
| 431 | do_IRQ(TIMER0_INTR_VECT, regs); | 431 | do_IRQ(TIMER0_INTR_VECT, regs); |
| 432 | } | 432 | } |
| 433 | } | ||
| 434 | #endif | 433 | #endif |
| 434 | } | ||
| 435 | 435 | ||
| 436 | #ifdef IGNORE_MASK | 436 | #ifdef IGNORE_MASK |
| 437 | /* Remove IRQs that can't be handled as multiple. */ | 437 | /* Remove IRQs that can't be handled as multiple. */ |
| @@ -3,5 +3,5 @@ · 2 unmodified lines | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \ | 5 | lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \ |
| 6 | csumcpfruser.o spinlock.o delay.o | 6 | csumcpfruser.o spinlock.o delay.o strcmp.o |
| 7 | 7 | ||
| @@ -0,0 +1,21 @@ | |||
| 1 | ; strcmp.S -- CRISv32 version. | ||
| 2 | ; Copyright (C) 2008 AXIS Communications AB | ||
| 3 | ; Written by Edgar E. Iglesias | ||
| 4 | ; | ||
| 5 | ; This source code is licensed under the GNU General Public License, | ||
| 6 | ; Version 2. See the file COPYING for more details. | ||
| 7 | |||
| 8 | .global strcmp | ||
| 9 | .type strcmp,@function | ||
| 10 | strcmp: | ||
| 11 | 1: | ||
| 12 | move.b [$r10+], $r12 | ||
| 13 | seq $r13 | ||
| 14 | sub.b [$r11+], $r12 | ||
| 15 | or.b $r12, $r13 | ||
| 16 | beq 1b | ||
| 17 | nop | ||
| 18 | |||
| 19 | ret | ||
| 20 | movs.b $r12, $r10 | ||
| 21 | .size strcmp, . - strcmp | ||
| @@ -78,7 +78,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) · 77 unmodified lines | |||
| 78 | { | 78 | { |
| 79 | __raw_spin_lock(&rw->slock); | 79 | __raw_spin_lock(&rw->slock); |
| 80 | while (rw->lock != RW_LOCK_BIAS); | 80 | while (rw->lock != RW_LOCK_BIAS); |
| 81 | rw->lock == 0; | 81 | rw->lock = 0; |
| 82 | __raw_spin_unlock(&rw->slock); | 82 | __raw_spin_unlock(&rw->slock); |
| 83 | } | 83 | } |
| 84 | 84 | ||
| @@ -93,7 +93,7 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw) · 8 unmodified lines | |||
| 93 | { | 93 | { |
| 94 | __raw_spin_lock(&rw->slock); | 94 | __raw_spin_lock(&rw->slock); |
| 95 | while (rw->lock != RW_LOCK_BIAS); | 95 | while (rw->lock != RW_LOCK_BIAS); |
| 96 | rw->lock == RW_LOCK_BIAS; | 96 | rw->lock = RW_LOCK_BIAS; |
| 97 | __raw_spin_unlock(&rw->slock); | 97 | __raw_spin_unlock(&rw->slock); |
| 98 | } | 98 | } |
| 99 | 99 | ||
| @@ -114,7 +114,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) · 14 unmodified lines | |||
| 114 | int ret = 0; | 114 | int ret = 0; |
| 115 | __raw_spin_lock(&rw->slock); | 115 | __raw_spin_lock(&rw->slock); |
| 116 | if (rw->lock == RW_LOCK_BIAS) { | 116 | if (rw->lock == RW_LOCK_BIAS) { |
| 117 | rw->lock == 0; | 117 | rw->lock = 0; |
| 118 | ret = 1; | 118 | ret = 1; |
| 119 | } | 119 | } |
| 120 | __raw_spin_unlock(&rw->slock); | 120 | __raw_spin_unlock(&rw->slock); |
| @@ -11,4 +11,10 @@ extern void *memcpy(void *, const void *, size_t); · 10 unmodified lines | |||
| 11 | #define __HAVE_ARCH_MEMSET | 11 | #define __HAVE_ARCH_MEMSET |
| 12 | extern void *memset(void *, int, size_t); | 12 | extern void *memset(void *, int, size_t); |
| 13 | 13 | ||
| 14 | #ifdef CONFIG_ETRAX_ARCH_V32 | ||
| 15 | /* For v32 we provide strcmp. */ | ||
| 16 | #define __HAVE_ARCH_STRCMP | ||
| 17 | extern int strcmp(const char *s1, const char *s2); | ||
| 18 | #endif | ||
| 19 | |||
| 14 | #endif | 20 | #endif |
| @@ -7,6 +7,7 @@ config FRV · 6 unmodified lines | |||
| 7 | default y | 7 | default y |
| 8 | select HAVE_IDE | 8 | select HAVE_IDE |
| 9 | select HAVE_ARCH_TRACEHOOK | 9 | select HAVE_ARCH_TRACEHOOK |
| 10 | select HAVE_PERF_COUNTERS | ||
| 10 | 11 | ||
| 11 | config ZONE_DMA | 12 | config ZONE_DMA |
| 12 | bool | 13 | bool |
| @@ -121,10 +121,72 @@ static inline void atomic_dec(atomic_t *v) · 120 unmodified lines | |||
| 121 | #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) | 121 | #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) |
| 122 | #define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0) | 122 | #define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0) |
| 123 | 123 | ||
| 124 | /* | ||
| 125 | * 64-bit atomic ops | ||
| 126 | */ | ||
| 127 | typedef struct { | ||
| 128 | volatile long long counter; | ||
| 129 | } atomic64_t; | ||
| 130 | |||
| 131 | #define ATOMIC64_INIT(i) { (i) } | ||
| 132 | |||
| 133 | static inline long long atomic64_read(atomic64_t *v) | ||
| 134 | { | ||
| 135 | long long counter; | ||
| 136 | |||
| 137 | asm("ldd%I1 %M1,%0" | ||
| 138 | : "=e"(counter) | ||
| 139 | : "m"(v->counter)); | ||
| 140 | return counter; | ||
| 141 | } | ||
| 142 | |||
| 143 | static inline void atomic64_set(atomic64_t *v, long long i) | ||
| 144 | { | ||
| 145 | asm volatile("std%I0 %1,%M0" | ||
| 146 | : "=m"(v->counter) | ||
| 147 | : "e"(i)); | ||
| 148 | } | ||
| 149 | |||
| 150 | extern long long atomic64_inc_return(atomic64_t *v); | ||
| 151 | extern long long atomic64_dec_return(atomic64_t *v); | ||
| 152 | extern long long atomic64_add_return(long long i, atomic64_t *v); | ||
| 153 | extern long long atomic64_sub_return(long long i, atomic64_t *v); | ||
| 154 | |||
| 155 | static inline long long atomic64_add_negative(long long i, atomic64_t *v) | ||
| 156 | { | ||
| 157 | return atomic64_add_return(i, v) < 0; | ||
| 158 | } | ||
| 159 | |||
| 160 | static inline void atomic64_add(long long i, atomic64_t *v) | ||
| 161 | { | ||
| 162 | atomic64_add_return(i, v); | ||
| 163 | } | ||
| 164 | |||
| 165 | static inline void atomic64_sub(long long i, atomic64_t *v) | ||
| 166 | { | ||
| 167 | atomic64_sub_return(i, v); | ||
| 168 | } | ||
| 169 | |||
| 170 | static inline void atomic64_inc(atomic64_t *v) | ||
| 171 | { | ||
| 172 | atomic64_inc_return(v); | ||
| 173 | } | ||
| 174 | |||
| 175 | static inline void atomic64_dec(atomic64_t *v) | ||
| 176 | { | ||
| 177 | atomic64_dec_return(v); | ||
| 178 | } | ||
| 179 | |||
| 180 | #define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0) | ||
| 181 | #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0) | ||
| 182 | #define atomic64_inc_and_test(v) (atomic64_inc_return((v)) == 0) | ||
| 183 | |||
| 124 | /*****************************************************************************/ | 184 | /*****************************************************************************/ |
| 125 | /* | 185 | /* |
| 126 | * exchange value with memory | 186 | * exchange value with memory |
| 127 | */ | 187 | */ |
| 188 | extern uint64_t __xchg_64(uint64_t i, volatile void *v); | ||
| 189 | |||
| 128 | #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS | 190 | #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS |
| 129 | 191 | ||
| 130 | #define xchg(ptr, x) \ | 192 | #define xchg(ptr, x) \ |
| @@ -174,8 +236,10 @@ extern uint32_t __xchg_32(uint32_t i, volatile void *v); · 43 unmodified lines | |||
| 174 | 236 | ||
| 175 | #define tas(ptr) (xchg((ptr), 1)) | 237 | #define tas(ptr) (xchg((ptr), 1)) |
| 176 | 238 | ||
| 177 | #define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new)) | 239 | #define atomic_cmpxchg(v, old, new) (cmpxchg(&(v)->counter, old, new)) |
| 178 | #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) | 240 | #define atomic_xchg(v, new) (xchg(&(v)->counter, new)) |
| 241 | #define atomic64_cmpxchg(v, old, new) (__cmpxchg_64(old, new, &(v)->counter)) | ||
| 242 | #define atomic64_xchg(v, new) (__xchg_64(new, &(v)->counter)) | ||
| 179 | 243 | ||
| 180 | static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) | 244 | static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) |
| 181 | { | 245 | { |
| @@ -0,0 +1,17 @@ | |||
| 1 | /* FRV performance counter support | ||
| 2 | * | ||
| 3 | * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_PERF_COUNTER_H | ||
| 13 | #define _ASM_PERF_COUNTER_H | ||
| 14 | |||
| 15 | #define PERF_COUNTER_INDEX_OFFSET 0 | ||
| 16 | |||
| 17 | #endif /* _ASM_PERF_COUNTER_H */ | ||
| @@ -208,6 +208,8 @@ extern void free_initmem(void); · 207 unmodified lines | |||
| 208 | * - if (*ptr == test) then orig = *ptr; *ptr = test; | 208 | * - if (*ptr == test) then orig = *ptr; *ptr = test; |
| 209 | * - if (*ptr != test) then orig = *ptr; | 209 | * - if (*ptr != test) then orig = *ptr; |
| 210 | */ | 210 | */ |
| 211 | extern uint64_t __cmpxchg_64(uint64_t test, uint64_t new, volatile uint64_t *v); | ||
| 212 | |||
| 211 | #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS | 213 | #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS |
| 212 | 214 | ||
| 213 | #define cmpxchg(ptr, test, new) \ | 215 | #define cmpxchg(ptr, test, new) \ |
| @@ -341,10 +341,12 @@ · 340 unmodified lines | |||
| 341 | #define __NR_inotify_init1 332 | 341 | #define __NR_inotify_init1 332 |
| 342 | #define __NR_preadv 333 | 342 | #define __NR_preadv 333 |
| 343 | #define __NR_pwritev 334 | 343 | #define __NR_pwritev 334 |
| 344 | #define __NR_rt_tgsigqueueinfo 335 | ||
| 345 | #define __NR_perf_counter_open 336 | ||
| 344 | 346 | ||
| 345 | #ifdef __KERNEL__ | 347 | #ifdef __KERNEL__ |
| 346 | 348 | ||
| 347 | #define NR_syscalls 335 | 349 | #define NR_syscalls 337 |
| 348 | 350 | ||
| 349 | #define __ARCH_WANT_IPC_PARSE_VERSION | 351 | #define __ARCH_WANT_IPC_PARSE_VERSION |
| 350 | /* #define __ARCH_WANT_OLD_READDIR */ | 352 | /* #define __ARCH_WANT_OLD_READDIR */ |
| @@ -1524,5 +1524,7 @@ sys_call_table: · 1523 unmodified lines | |||
| 1524 | .long sys_inotify_init1 | 1524 | .long sys_inotify_init1 |
| 1525 | .long sys_preadv | 1525 | .long sys_preadv |
| 1526 | .long sys_pwritev | 1526 | .long sys_pwritev |
| 1527 | .long sys_rt_tgsigqueueinfo /* 335 */ | ||
| 1528 | .long sys_perf_counter_open | ||
| 1527 | 1529 | ||
| 1528 | syscall_table_size = (. - sys_call_table) | 1530 | syscall_table_size = (. - sys_call_table) |
| @@ -67,6 +67,10 @@ EXPORT_SYMBOL(atomic_sub_return); · 66 unmodified lines | |||
| 67 | EXPORT_SYMBOL(__xchg_32); | 67 | EXPORT_SYMBOL(__xchg_32); |
| 68 | EXPORT_SYMBOL(__cmpxchg_32); | 68 | EXPORT_SYMBOL(__cmpxchg_32); |
| 69 | #endif | 69 | #endif |
| 70 | EXPORT_SYMBOL(atomic64_add_return); | ||
| 71 | EXPORT_SYMBOL(atomic64_sub_return); | ||
| 72 | EXPORT_SYMBOL(__xchg_64); | ||
| 73 | EXPORT_SYMBOL(__cmpxchg_64); | ||
| 70 | 74 | ||
| 71 | EXPORT_SYMBOL(__debug_bug_printk); | 75 | EXPORT_SYMBOL(__debug_bug_printk); |
| 72 | EXPORT_SYMBOL(__delay_loops_MHz); | 76 | EXPORT_SYMBOL(__delay_loops_MHz); |
| @@ -4,5 +4,5 @@ · 3 unmodified lines | |||
| 4 | 4 | ||
| 5 | lib-y := \ | 5 | lib-y := \ |
| 6 | __ashldi3.o __lshrdi3.o __muldi3.o __ashrdi3.o __negdi2.o __ucmpdi2.o \ | 6 | __ashldi3.o __lshrdi3.o __muldi3.o __ashrdi3.o __negdi2.o __ucmpdi2.o \ |
| 7 | checksum.o memcpy.o memset.o atomic-ops.o \ | 7 | checksum.o memcpy.o memset.o atomic-ops.o atomic64-ops.o \ |
| 8 | outsl_ns.o outsl_sw.o insl_ns.o insl_sw.o cache.o | 8 | outsl_ns.o outsl_sw.o insl_ns.o insl_sw.o cache.o perf_counter.o |
| @@ -163,11 +163,10 @@ __cmpxchg_32: · 162 unmodified lines | |||
| 163 | ld.p @(gr11,gr0),gr8 | 163 | ld.p @(gr11,gr0),gr8 |
| 164 | orcr cc7,cc7,cc3 | 164 | orcr cc7,cc7,cc3 |
| 165 | subcc gr8,gr9,gr7,icc0 | 165 | subcc gr8,gr9,gr7,icc0 |
| 166 | bne icc0,#0,1f | 166 | bnelr icc0,#0 |
| 167 | cst.p gr10,@(gr11,gr0) ,cc3,#1 | 167 | cst.p gr10,@(gr11,gr0) ,cc3,#1 |
| 168 | corcc gr29,gr29,gr0 ,cc3,#1 | 168 | corcc gr29,gr29,gr0 ,cc3,#1 |
| 169 | beq icc3,#0,0b | 169 | beq icc3,#0,0b |
| 170 | 1: | ||
| 171 | bralr | 170 | bralr |
| 172 | 171 | ||
| 173 | .size __cmpxchg_32, .-__cmpxchg_32 | 172 | .size __cmpxchg_32, .-__cmpxchg_32 |
| @@ -0,0 +1,162 @@ | |||
| 1 | /* kernel atomic64 operations | ||
| 2 | * | ||
| 3 | * For an explanation of how atomic ops work in this arch, see: | ||
| 4 | * Documentation/frv/atomic-ops.txt | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved. | ||
| 7 | * Written by David Howells (dhowells@redhat.com) | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public License | ||
| 11 | * as published by the Free Software Foundation; either version | ||
| 12 | * 2 of the License, or (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <asm/spr-regs.h> | ||
| 16 | |||
| 17 | .text | ||
| 18 | .balign 4 | ||
| 19 | |||
| 20 | |||
| 21 | ############################################################################### | ||
| 22 | # | ||
| 23 | # long long atomic64_inc_return(atomic64_t *v) | ||
| 24 | # | ||
| 25 | ############################################################################### | ||
| 26 | .globl atomic64_inc_return | ||
| 27 | .type atomic64_inc_return,@function | ||
| 28 | atomic64_inc_return: | ||
| 29 | or.p gr8,gr8,gr10 | ||
| 30 | 0: | ||
| 31 | orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ | ||
| 32 | ckeq icc3,cc7 | ||
| 33 | ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */ | ||
| 34 | orcr cc7,cc7,cc3 /* set CC3 to true */ | ||
| 35 | addicc gr9,#1,gr9,icc0 | ||
| 36 | addxi gr8,#0,gr8,icc0 | ||
| 37 | cstd.p gr8,@(gr10,gr0) ,cc3,#1 | ||
| 38 | corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ | ||
| 39 | beq icc3,#0,0b | ||
| 40 | bralr | ||
| 41 | |||
| 42 | .size atomic64_inc_return, .-atomic64_inc_return | ||
| 43 | |||
| 44 | ############################################################################### | ||
| 45 | # | ||
| 46 | # long long atomic64_dec_return(atomic64_t *v) | ||
| 47 | # | ||
| 48 | ############################################################################### | ||
| 49 | .globl atomic64_dec_return | ||
| 50 | .type atomic64_dec_return,@function | ||
| 51 | atomic64_dec_return: | ||
| 52 | or.p gr8,gr8,gr10 | ||
| 53 | 0: | ||
| 54 | orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ | ||
| 55 | ckeq icc3,cc7 | ||
| 56 | ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */ | ||
| 57 | orcr cc7,cc7,cc3 /* set CC3 to true */ | ||
| 58 | subicc gr9,#1,gr9,icc0 | ||
| 59 | subxi gr8,#0,gr8,icc0 | ||
| 60 | cstd.p gr8,@(gr10,gr0) ,cc3,#1 | ||
| 61 | corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ | ||
| 62 | beq icc3,#0,0b | ||
| 63 | bralr | ||
| 64 | |||
| 65 | .size atomic64_dec_return, .-atomic64_dec_return | ||
| 66 | |||
| 67 | ############################################################################### | ||
| 68 | # | ||
| 69 | # long long atomic64_add_return(long long i, atomic64_t *v) | ||
| 70 | # | ||
| 71 | ############################################################################### | ||
| 72 | .globl atomic64_add_return | ||
| 73 | .type atomic64_add_return,@function | ||
| 74 | atomic64_add_return: | ||
| 75 | or.p gr8,gr8,gr4 | ||
| 76 | or gr9,gr9,gr5 | ||
| 77 | 0: | ||
| 78 | orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ | ||
| 79 | ckeq icc3,cc7 | ||
| 80 | ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */ | ||
| 81 | orcr cc7,cc7,cc3 /* set CC3 to true */ | ||
| 82 | addcc gr9,gr5,gr9,icc0 | ||
| 83 | addx gr8,gr4,gr8,icc0 | ||
| 84 | cstd.p gr8,@(gr10,gr0) ,cc3,#1 | ||
| 85 | corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ | ||
| 86 | beq icc3,#0,0b | ||
| 87 | bralr | ||
| 88 | |||
| 89 | .size atomic64_add_return, .-atomic64_add_return | ||
| 90 | |||
| 91 | ############################################################################### | ||
| 92 | # | ||
| 93 | # long long atomic64_sub_return(long long i, atomic64_t *v) | ||
| 94 | # | ||
| 95 | ############################################################################### | ||
| 96 | .globl atomic64_sub_return | ||
| 97 | .type atomic64_sub_return,@function | ||
| 98 | atomic64_sub_return: | ||
| 99 | or.p gr8,gr8,gr4 | ||
| 100 | or gr9,gr9,gr5 | ||
| 101 | 0: | ||
| 102 | orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ | ||
| 103 | ckeq icc3,cc7 | ||
| 104 | ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */ | ||
| 105 | orcr cc7,cc7,cc3 /* set CC3 to true */ | ||
| 106 | subcc gr9,gr5,gr9,icc0 | ||
| 107 | subx gr8,gr4,gr8,icc0 | ||
| 108 | cstd.p gr8,@(gr10,gr0) ,cc3,#1 | ||
| 109 | corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ | ||
| 110 | beq icc3,#0,0b | ||
| 111 | bralr | ||
| 112 | |||
| 113 | .size atomic64_sub_return, .-atomic64_sub_return | ||
| 114 | |||
| 115 | ############################################################################### | ||
| 116 | # | ||
| 117 | # uint64_t __xchg_64(uint64_t i, uint64_t *v) | ||
| 118 | # | ||
| 119 | ############################################################################### | ||
| 120 | .globl __xchg_64 | ||
| 121 | .type __xchg_64,@function | ||
| 122 | __xchg_64: | ||
| 123 | or.p gr8,gr8,gr4 | ||
| 124 | or gr9,gr9,gr5 | ||
| 125 | 0: | ||
| 126 | orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ | ||
| 127 | ckeq icc3,cc7 | ||
| 128 | ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */ | ||
| 129 | orcr cc7,cc7,cc3 /* set CC3 to true */ | ||
| 130 | cstd.p gr4,@(gr10,gr0) ,cc3,#1 | ||
| 131 | corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ | ||
| 132 | beq icc3,#0,0b | ||
| 133 | bralr | ||
| 134 | |||
| 135 | .size __xchg_64, .-__xchg_64 | ||
| 136 | |||
| 137 | ############################################################################### | ||
| 138 | # | ||
| 139 | # uint64_t __cmpxchg_64(uint64_t test, uint64_t new, uint64_t *v) | ||
| 140 | # | ||
| 141 | ############################################################################### | ||
| 142 | .globl __cmpxchg_64 | ||
| 143 | .type __cmpxchg_64,@function | ||
| 144 | __cmpxchg_64: | ||
| 145 | or.p gr8,gr8,gr4 | ||
| 146 | or gr9,gr9,gr5 | ||
| 147 | 0: | ||
| 148 | orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */ | ||
| 149 | ckeq icc3,cc7 | ||
| 150 | ldd.p @(gr12,gr0),gr8 /* LDD.P/ORCR must be atomic */ | ||
| 151 | orcr cc7,cc7,cc3 | ||
| 152 | subcc gr8,gr4,gr0,icc0 | ||
| 153 | subcc.p gr9,gr5,gr0,icc1 | ||
| 154 | bnelr icc0,#0 | ||
| 155 | bnelr icc1,#0 | ||
| 156 | cstd.p gr10,@(gr12,gr0) ,cc3,#1 | ||
| 157 | corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */ | ||
| 158 | beq icc3,#0,0b | ||
| 159 | bralr | ||
| 160 | |||
| 161 | .size __cmpxchg_64, .-__cmpxchg_64 | ||
| 162 | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* Performance counter handling | ||
| 2 | * | ||
| 3 | * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/perf_counter.h> | ||
| 13 | |||
| 14 | /* | ||
| 15 | * mark the performance counter as pending | ||
| 16 | */ | ||
| 17 | void set_perf_counter_pending(void) | ||
| 18 | { | ||
| 19 | } | ||
| @@ -13,7 +13,7 @@ config H8300H_GENERIC · 12 unmodified lines | |||
| 13 | 13 | ||
| 14 | config H8300H_AKI3068NET | 14 | config H8300H_AKI3068NET |
| 15 | bool "AE-3068/69" | 15 | bool "AE-3068/69" |
| 16 | select CONFIG_H83068 | 16 | select H83068 |
| 17 | help | 17 | help |
| 18 | AKI-H8/3068F / AKI-H8/3069F Flashmicom LAN Board Support | 18 | AKI-H8/3068F / AKI-H8/3069F Flashmicom LAN Board Support |
| 19 | More Information. (Japanese Only) | 19 | More Information. (Japanese Only) |
| @@ -24,7 +24,7 @@ config H8300H_AKI3068NET · 4 unmodified lines | |||
| 24 | 24 | ||
| 25 | config H8300H_H8MAX | 25 | config H8300H_H8MAX |
| 26 | bool "H8MAX" | 26 | bool "H8MAX" |
| 27 | select CONFIG_H83068 | 27 | select H83068 |
| 28 | help | 28 | help |
| 29 | H8MAX Evaluation Board Support | 29 | H8MAX Evaluation Board Support |
| 30 | More Information. (Japanese Only) | 30 | More Information. (Japanese Only) |
| @@ -32,7 +32,7 @@ config H8300H_H8MAX · 1 unmodified line | |||
| 32 | 32 | ||
| 33 | config H8300H_SIM | 33 | config H8300H_SIM |
| 34 | bool "H8/300H Simulator" | 34 | bool "H8/300H Simulator" |
| 35 | select CONFIG_H83007 | 35 | select H83007 |
| 36 | help | 36 | help |
| 37 | GDB Simulator Support | 37 | GDB Simulator Support |
| 38 | More Information. | 38 | More Information. |
| @@ -45,7 +45,7 @@ config H8S_GENERIC · 6 unmodified lines | |||
| 45 | 45 | ||
| 46 | config H8S_EDOSK2674 | 46 | config H8S_EDOSK2674 |
| 47 | bool "EDOSK-2674" | 47 | bool "EDOSK-2674" |
| 48 | select CONFIG_H8S2768 | 48 | select H8S2678 |
| 49 | help | 49 | help |
| 50 | Renesas EDOSK-2674 Evaluation Board Support | 50 | Renesas EDOSK-2674 Evaluation Board Support |
| 51 | More Information. | 51 | More Information. |
| @@ -9,6 +9,11 @@ extern void pci_iommu_shutdown(void); · 8 unmodified lines | |||
| 9 | extern void no_iommu_init(void); | 9 | extern void no_iommu_init(void); |
| 10 | extern int force_iommu, no_iommu; | 10 | extern int force_iommu, no_iommu; |
| 11 | extern int iommu_detected; | 11 | extern int iommu_detected; |
| 12 | #ifdef CONFIG_DMAR | ||
| 13 | extern int iommu_pass_through; | ||
| 14 | #else | ||
| 15 | #define iommu_pass_through (0) | ||
| 16 | #endif | ||
| 12 | extern void iommu_dma_init(void); | 17 | extern void iommu_dma_init(void); |
| 13 | extern void machvec_init(const char *name); | 18 | extern void machvec_init(const char *name); |
| 14 | 19 | ||
| @@ -71,3 +71,15 @@ void arch_acpi_processor_init_pdc(struct acpi_processor *pr) · 70 unmodified lines | |||
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | EXPORT_SYMBOL(arch_acpi_processor_init_pdc); | 73 | EXPORT_SYMBOL(arch_acpi_processor_init_pdc); |
| 74 | |||
| 75 | void arch_acpi_processor_cleanup_pdc(struct acpi_processor *pr) | ||
| 76 | { | ||
| 77 | if (pr->pdc) { | ||
| 78 | kfree(pr->pdc->pointer->buffer.pointer); | ||
| 79 | kfree(pr->pdc->pointer); | ||
| 80 | kfree(pr->pdc); | ||
| 81 | pr->pdc = NULL; | ||
| 82 | } | ||
| 83 | } | ||
| 84 | |||
| 85 | EXPORT_SYMBOL(arch_acpi_processor_cleanup_pdc); | ||
| @@ -65,7 +65,7 @@ static int __init esi_init (void) · 64 unmodified lines | |||
| 65 | } | 65 | } |
| 66 | 66 | ||
| 67 | if (!esi) | 67 | if (!esi) |
| 68 | return -ENODEV;; | 68 | return -ENODEV; |
| 69 | 69 | ||
| 70 | systab = __va(esi); | 70 | systab = __va(esi); |
| 71 | 71 | ||
| @@ -32,6 +32,8 @@ int force_iommu __read_mostly = 1; · 31 unmodified lines | |||
| 32 | int force_iommu __read_mostly; | 32 | int force_iommu __read_mostly; |
| 33 | #endif | 33 | #endif |
| 34 | 34 | ||
| 35 | int iommu_pass_through; | ||
| 36 | |||
| 35 | /* Dummy device used for NULL arguments (normally ISA). Better would | 37 | /* Dummy device used for NULL arguments (normally ISA). Better would |
| 36 | be probably a smaller DMA mask, but this is bug-to-bug compatible | 38 | be probably a smaller DMA mask, but this is bug-to-bug compatible |
| 37 | to i386. */ | 39 | to i386. */ |
| @@ -46,7 +46,7 @@ void __init swiotlb_dma_init(void) · 45 unmodified lines | |||
| 46 | 46 | ||
| 47 | void __init pci_swiotlb_init(void) | 47 | void __init pci_swiotlb_init(void) |
| 48 | { | 48 | { |
| 49 | if (!iommu_detected) { | 49 | if (!iommu_detected || iommu_pass_through) { |
| 50 | #ifdef CONFIG_IA64_GENERIC | 50 | #ifdef CONFIG_IA64_GENERIC |
| 51 | swiotlb = 1; | 51 | swiotlb = 1; |
| 52 | printk(KERN_INFO "PCI-DMA: Re-initialize machine vector.\n"); | 52 | printk(KERN_INFO "PCI-DMA: Re-initialize machine vector.\n"); |
| @@ -5603,7 +5603,7 @@ pfm_interrupt_handler(int irq, void *arg) · 5602 unmodified lines | |||
| 5603 | * /proc/perfmon interface, for debug only | 5603 | * /proc/perfmon interface, for debug only |
| 5604 | */ | 5604 | */ |
| 5605 | 5605 | ||
| 5606 | #define PFM_PROC_SHOW_HEADER ((void *)nr_cpu_ids+1) | 5606 | #define PFM_PROC_SHOW_HEADER ((void *)(long)nr_cpu_ids+1) |
| 5607 | 5607 | ||
| 5608 | static void * | 5608 | static void * |
| 5609 | pfm_proc_start(struct seq_file *m, loff_t *pos) | 5609 | pfm_proc_start(struct seq_file *m, loff_t *pos) |
| @@ -192,7 +192,7 @@ struct salinfo_platform_oemdata_parms { · 191 unmodified lines | |||
| 192 | static void | 192 | static void |
| 193 | salinfo_work_to_do(struct salinfo_data *data) | 193 | salinfo_work_to_do(struct salinfo_data *data) |
| 194 | { | 194 | { |
| 195 | down_trylock(&data->mutex); | 195 | (void)(down_trylock(&data->mutex) ?: 0); |
| 196 | up(&data->mutex); | 196 | up(&data->mutex); |
| 197 | } | 197 | } |
| 198 | 198 | ||
| @@ -11,5 +11,11 @@ · 10 unmodified lines | |||
| 11 | * | 11 | * |
| 12 | */ | 12 | */ |
| 13 | #undef CONFIG_MODULES | 13 | #undef CONFIG_MODULES |
| 14 | #include <linux/module.h> | ||
| 15 | #undef CONFIG_KALLSYMS | ||
| 16 | #undef EXPORT_SYMBOL | ||
| 17 | #undef EXPORT_SYMBOL_GPL | ||
| 18 | #define EXPORT_SYMBOL(sym) | ||
| 19 | #define EXPORT_SYMBOL_GPL(sym) | ||
| 14 | #include "../../../lib/vsprintf.c" | 20 | #include "../../../lib/vsprintf.c" |
| 15 | #include "../../../lib/ctype.c" | 21 | #include "../../../lib/ctype.c" |
| @@ -130,7 +130,7 @@ static void collect_interruption(struct kvm_vcpu *vcpu) · 129 unmodified lines | |||
| 130 | if (vdcr & IA64_DCR_PP) { | 130 | if (vdcr & IA64_DCR_PP) { |
| 131 | vpsr |= IA64_PSR_PP; | 131 | vpsr |= IA64_PSR_PP; |
| 132 | } else { | 132 | } else { |
| 133 | vpsr &= ~IA64_PSR_PP;; | 133 | vpsr &= ~IA64_PSR_PP; |
| 134 | } | 134 | } |
| 135 | 135 | ||
| 136 | vcpu_set_psr(vcpu, vpsr); | 136 | vcpu_set_psr(vcpu, vpsr); |
| @@ -594,11 +594,11 @@ static void set_pal_call_data(struct kvm_vcpu *vcpu) · 457 unmodified lines | |||
| 594 | p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); | 594 | p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); |
| 595 | break; | 595 | break; |
| 596 | case PAL_BRAND_INFO: | 596 | case PAL_BRAND_INFO: |
| 597 | p->u.pal_data.gr29 = gr29;; | 597 | p->u.pal_data.gr29 = gr29; |
| 598 | p->u.pal_data.gr30 = kvm_trans_pal_call_args(vcpu, gr30); | 598 | p->u.pal_data.gr30 = kvm_trans_pal_call_args(vcpu, gr30); |
| 599 | break; | 599 | break; |
| 600 | default: | 600 | default: |
| 601 | p->u.pal_data.gr29 = gr29;; | 601 | p->u.pal_data.gr29 = gr29; |
| 602 | p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); | 602 | p->u.pal_data.gr30 = vcpu_get_gr(vcpu, 30); |
| 603 | } | 603 | } |
| 604 | p->u.pal_data.gr28 = gr28; | 604 | p->u.pal_data.gr28 = gr28; |
| @@ -406,7 +406,7 @@ void getreg(unsigned long regnum, unsigned long *val, · 405 unmodified lines | |||
| 406 | * Now look at registers in [0-31] range and init correct UNAT | 406 | * Now look at registers in [0-31] range and init correct UNAT |
| 407 | */ | 407 | */ |
| 408 | addr = (unsigned long)regs; | 408 | addr = (unsigned long)regs; |
| 409 | unat = ®s->eml_unat;; | 409 | unat = ®s->eml_unat; |
| 410 | 410 | ||
| 411 | addr += gr_info[regnum]; | 411 | addr += gr_info[regnum]; |
| 412 | 412 | ||
| @@ -135,7 +135,7 @@ struct thash_data *__vtr_lookup(struct kvm_vcpu *vcpu, u64 va, int type) · 134 unmodified lines | |||
| 135 | u64 rid; | 135 | u64 rid; |
| 136 | 136 | ||
| 137 | rid = vcpu_get_rr(vcpu, va); | 137 | rid = vcpu_get_rr(vcpu, va); |
| 138 | rid = rid & RR_RID_MASK;; | 138 | rid = rid & RR_RID_MASK; |
| 139 | if (type == D_TLB) { | 139 | if (type == D_TLB) { |
| 140 | if (vcpu_quick_region_check(vcpu->arch.dtr_regions, va)) { | 140 | if (vcpu_quick_region_check(vcpu->arch.dtr_regions, va)) { |
| 141 | for (trp = (struct thash_data *)&vcpu->arch.dtrs, i = 0; | 141 | for (trp = (struct thash_data *)&vcpu->arch.dtrs, i = 0; |
| @@ -518,7 +518,7 @@ struct thash_data *vtlb_lookup(struct kvm_vcpu *v, u64 va, int is_data) · 376 unmodified lines | |||
| 518 | 518 | ||
| 519 | struct thash_cb *hcb = &v->arch.vtlb; | 519 | struct thash_cb *hcb = &v->arch.vtlb; |
| 520 | 520 | ||
| 521 | cch = __vtr_lookup(v, va, is_data);; | 521 | cch = __vtr_lookup(v, va, is_data); |
| 522 | if (cch) | 522 | if (cch) |
| 523 | return cch; | 523 | return cch; |
| 524 | 524 | ||
| @@ -435,7 +435,8 @@ void sn_generate_path(struct pci_bus *pci_bus, char *address) · 434 unmodified lines | |||
| 435 | bricktype = MODULE_GET_BTYPE(moduleid); | 435 | bricktype = MODULE_GET_BTYPE(moduleid); |
| 436 | if ((bricktype == L1_BRICKTYPE_191010) || | 436 | if ((bricktype == L1_BRICKTYPE_191010) || |
| 437 | (bricktype == L1_BRICKTYPE_1932)) | 437 | (bricktype == L1_BRICKTYPE_1932)) |
| 438 | sprintf(address, "%s^%d", address, geo_slot(geoid)); | 438 | sprintf(address + strlen(address), "^%d", |
| 439 | geo_slot(geoid)); | ||
| 439 | } | 440 | } |
| 440 | 441 | ||
| 441 | void __devinit | 442 | void __devinit |
| @@ -601,6 +601,7 @@ config CAVIUM_OCTEON_SIMULATOR · 600 unmodified lines | |||
| 601 | select SYS_SUPPORTS_64BIT_KERNEL | 601 | select SYS_SUPPORTS_64BIT_KERNEL |
| 602 | select SYS_SUPPORTS_BIG_ENDIAN | 602 | select SYS_SUPPORTS_BIG_ENDIAN |
| 603 | select SYS_SUPPORTS_HIGHMEM | 603 | select SYS_SUPPORTS_HIGHMEM |
| 604 | select SYS_SUPPORTS_HOTPLUG_CPU | ||
| 604 | select SYS_HAS_CPU_CAVIUM_OCTEON | 605 | select SYS_HAS_CPU_CAVIUM_OCTEON |
| 605 | help | 606 | help |
| 606 | The Octeon simulator is software performance model of the Cavium | 607 | The Octeon simulator is software performance model of the Cavium |
| @@ -615,6 +616,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD · 8 unmodified lines | |||
| 615 | select SYS_SUPPORTS_64BIT_KERNEL | 616 | select SYS_SUPPORTS_64BIT_KERNEL |
| 616 | select SYS_SUPPORTS_BIG_ENDIAN | 617 | select SYS_SUPPORTS_BIG_ENDIAN |
| 617 | select SYS_SUPPORTS_HIGHMEM | 618 | select SYS_SUPPORTS_HIGHMEM |
| 619 | select SYS_SUPPORTS_HOTPLUG_CPU | ||
| 618 | select SYS_HAS_EARLY_PRINTK | 620 | select SYS_HAS_EARLY_PRINTK |
| 619 | select SYS_HAS_CPU_CAVIUM_OCTEON | 621 | select SYS_HAS_CPU_CAVIUM_OCTEON |
| 620 | select SWAP_IO_SPACE | 622 | select SWAP_IO_SPACE |
| @@ -784,8 +786,17 @@ config SYS_HAS_EARLY_PRINTK · 163 unmodified lines | |||
| 784 | bool | 786 | bool |
| 785 | 787 | ||
| 786 | config HOTPLUG_CPU | 788 | config HOTPLUG_CPU |
| 789 | bool "Support for hot-pluggable CPUs" | ||
| 790 | depends on SMP && HOTPLUG && SYS_SUPPORTS_HOTPLUG_CPU | ||
| 791 | help | ||
| 792 | Say Y here to allow turning CPUs off and on. CPUs can be | ||
| 793 | controlled through /sys/devices/system/cpu. | ||
| 794 | (Note: power management support will enable this option | ||
| 795 | automatically on SMP systems. ) | ||
| 796 | Say N if you want to disable CPU hotplug. | ||
| 797 | |||
| 798 | config SYS_SUPPORTS_HOTPLUG_CPU | ||
| 787 | bool | 799 | bool |
| 788 | default n | ||
| 789 | 800 | ||
| 790 | config I8259 | 801 | config I8259 |
| 791 | bool | 802 | bool |
| @@ -2136,11 +2147,11 @@ menu "Power management options" · 1344 unmodified lines | |||
| 2136 | 2147 | ||
| 2137 | config ARCH_HIBERNATION_POSSIBLE | 2148 | config ARCH_HIBERNATION_POSSIBLE |
| 2138 | def_bool y | 2149 | def_bool y |
| 2139 | depends on !SMP | 2150 | depends on SYS_SUPPORTS_HOTPLUG_CPU |
| 2140 | 2151 | ||
| 2141 | config ARCH_SUSPEND_POSSIBLE | 2152 | config ARCH_SUSPEND_POSSIBLE |
| 2142 | def_bool y | 2153 | def_bool y |
| 2143 | depends on !SMP | 2154 | depends on SYS_SUPPORTS_HOTPLUG_CPU |
| 2144 | 2155 | ||
| 2145 | source "kernel/power/Kconfig" | 2156 | source "kernel/power/Kconfig" |
| 2146 | 2157 | ||
| @@ -7,7 +7,7 @@ · 6 unmodified lines | |||
| 7 | */ | 7 | */ |
| 8 | #include <linux/irq.h> | 8 | #include <linux/irq.h> |
| 9 | #include <linux/interrupt.h> | 9 | #include <linux/interrupt.h> |
| 10 | #include <linux/hardirq.h> | 10 | #include <linux/smp.h> |
| 11 | 11 | ||
| 12 | #include <asm/octeon/octeon.h> | 12 | #include <asm/octeon/octeon.h> |
| 13 | #include <asm/octeon/cvmx-pexp-defs.h> | 13 | #include <asm/octeon/cvmx-pexp-defs.h> |
| @@ -501,3 +501,62 @@ asmlinkage void plat_irq_dispatch(void) · 487 unmodified lines | |||
| 501 | } | 501 | } |
| 502 | } | 502 | } |
| 503 | } | 503 | } |
| 504 | |||
| 505 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 506 | static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu) | ||
| 507 | { | ||
| 508 | unsigned int isset; | ||
| 509 | #ifdef CONFIG_SMP | ||
| 510 | int coreid = cpu_logical_map(cpu); | ||
| 511 | #else | ||
| 512 | int coreid = cvmx_get_core_num(); | ||
| 513 | #endif | ||
| 514 | int bit = (irq < OCTEON_IRQ_WDOG0) ? | ||
| 515 | irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0; | ||
| 516 | if (irq < 64) { | ||
| 517 | isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) & | ||
| 518 | (1ull << bit)) >> bit; | ||
| 519 | } else { | ||
| 520 | isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) & | ||
| 521 | (1ull << bit)) >> bit; | ||
| 522 | } | ||
| 523 | return isset; | ||
| 524 | } | ||
| 525 | |||
| 526 | void fixup_irqs(void) | ||
| 527 | { | ||
| 528 | int irq; | ||
| 529 | |||
| 530 | for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) | ||
| 531 | octeon_irq_core_disable_local(irq); | ||
| 532 | |||
| 533 | for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) { | ||
| 534 | if (is_irq_enabled_on_cpu(irq, smp_processor_id())) { | ||
| 535 | /* ciu irq migrates to next cpu */ | ||
| 536 | octeon_irq_chip_ciu0.disable(irq); | ||
| 537 | octeon_irq_ciu0_set_affinity(irq, &cpu_online_map); | ||
| 538 | } | ||
| 539 | } | ||
| 540 | |||
| 541 | #if 0 | ||
| 542 | for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++) | ||
| 543 | octeon_irq_mailbox_mask(irq); | ||
| 544 | #endif | ||
| 545 | for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { | ||
| 546 | if (is_irq_enabled_on_cpu(irq, smp_processor_id())) { | ||
| 547 | /* ciu irq migrates to next cpu */ | ||
| 548 | octeon_irq_chip_ciu0.disable(irq); | ||
| 549 | octeon_irq_ciu0_set_affinity(irq, &cpu_online_map); | ||
| 550 | } | ||
| 551 | } | ||
| 552 | |||
| 553 | for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) { | ||
| 554 | if (is_irq_enabled_on_cpu(irq, smp_processor_id())) { | ||
| 555 | /* ciu irq migrates to next cpu */ | ||
| 556 | octeon_irq_chip_ciu1.disable(irq); | ||
| 557 | octeon_irq_ciu1_set_affinity(irq, &cpu_online_map); | ||
| 558 | } | ||
| 559 | } | ||
| 560 | } | ||
| 561 | |||
| 562 | #endif /* CONFIG_HOTPLUG_CPU */ | ||
| @@ -0,0 +1,70 @@ | |||
| 1 | /* | ||
| 2 | * (C) Copyright 2004, 2005 Cavium Networks | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License as | ||
| 6 | * published by the Free Software Foundation; either version 2 of | ||
| 7 | * the License, or (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 17 | * MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __OCTEON_BOOT_H__ | ||
| 21 | #define __OCTEON_BOOT_H__ | ||
| 22 | |||
| 23 | #include <linux/types.h> | ||
| 24 | |||
| 25 | struct boot_init_vector { | ||
| 26 | uint32_t stack_addr; | ||
| 27 | uint32_t code_addr; | ||
| 28 | uint32_t app_start_func_addr; | ||
| 29 | uint32_t k0_val; | ||
| 30 | uint32_t flags; | ||
| 31 | uint32_t boot_info_addr; | ||
| 32 | uint32_t pad; | ||
| 33 | uint32_t pad2; | ||
| 34 | }; | ||
| 35 | |||
| 36 | /* similar to bootloader's linux_app_boot_info but without global data */ | ||
| 37 | struct linux_app_boot_info { | ||
| 38 | uint32_t labi_signature; | ||
| 39 | uint32_t start_core0_addr; | ||
| 40 | uint32_t avail_coremask; | ||
| 41 | uint32_t pci_console_active; | ||
| 42 | uint32_t icache_prefetch_disable; | ||
| 43 | uint32_t InitTLBStart_addr; | ||
| 44 | uint32_t start_app_addr; | ||
| 45 | uint32_t cur_exception_base; | ||
| 46 | uint32_t no_mark_private_data; | ||
| 47 | uint32_t compact_flash_common_base_addr; | ||
| 48 | uint32_t compact_flash_attribute_base_addr; | ||
| 49 | uint32_t led_display_base_addr; | ||
| 50 | }; | ||
| 51 | |||
| 52 | /* If not to copy a lot of bootloader's structures | ||
| 53 | here is only offset of requested member */ | ||
| 54 | #define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK 0x765c | ||
| 55 | |||
| 56 | /* hardcoded in bootloader */ | ||
| 57 | #define LABI_ADDR_IN_BOOTLOADER 0x700 | ||
| 58 | |||
| 59 | #define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot" | ||
| 60 | |||
| 61 | #define LABI_SIGNATURE 0xAABBCCDD | ||
| 62 | |||
| 63 | /* from uboot-headers/octeon_mem_map.h */ | ||
| 64 | #define EXCEPTION_BASE_INCR (4 * 1024) | ||
| 65 | /* Increment size for exception base addresses (4k minimum) */ | ||
| 66 | #define EXCEPTION_BASE_BASE 0 | ||
| 67 | #define BOOTLOADER_PRIV_DATA_BASE (EXCEPTION_BASE_BASE + 0x800) | ||
| 68 | #define BOOTLOADER_BOOT_VECTOR (BOOTLOADER_PRIV_DATA_BASE) | ||
| 69 | |||
| 70 | #endif /* __OCTEON_BOOT_H__ */ | ||
| @@ -13,6 +13,7 @@ · 12 unmodified lines | |||
| 13 | #include <linux/io.h> | 13 | #include <linux/io.h> |
| 14 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
| 15 | #include <linux/serial.h> | 15 | #include <linux/serial.h> |
| 16 | #include <linux/smp.h> | ||
| 16 | #include <linux/types.h> | 17 | #include <linux/types.h> |
| 17 | #include <linux/string.h> /* for memset */ | 18 | #include <linux/string.h> /* for memset */ |
| 18 | #include <linux/tty.h> | 19 | #include <linux/tty.h> |
| @@ -5,6 +5,7 @@ · 4 unmodified lines | |||
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2004-2008 Cavium Networks | 6 | * Copyright (C) 2004-2008 Cavium Networks |
| 7 | */ | 7 | */ |
| 8 | #include <linux/cpu.h> | ||
| 8 | #include <linux/init.h> | 9 | #include <linux/init.h> |
| 9 | #include <linux/delay.h> | 10 | #include <linux/delay.h> |
| 10 | #include <linux/smp.h> | 11 | #include <linux/smp.h> |
| @@ -19,10 +20,16 @@ · 8 unmodified lines | |||
| 19 | 20 | ||
| 20 | #include <asm/octeon/octeon.h> | 21 | #include <asm/octeon/octeon.h> |
| 21 | 22 | ||
| 23 | #include "octeon_boot.h" | ||
| 24 | |||
| 22 | volatile unsigned long octeon_processor_boot = 0xff; | 25 | volatile unsigned long octeon_processor_boot = 0xff; |
| 23 | volatile unsigned long octeon_processor_sp; | 26 | volatile unsigned long octeon_processor_sp; |
| 24 | volatile unsigned long octeon_processor_gp; | 27 | volatile unsigned long octeon_processor_gp; |
| 25 | 28 | ||
| 29 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 30 | static unsigned int InitTLBStart_addr; | ||
| 31 | #endif | ||
| 32 | |||
| 26 | static irqreturn_t mailbox_interrupt(int irq, void *dev_id) | 33 | static irqreturn_t mailbox_interrupt(int irq, void *dev_id) |
| 27 | { | 34 | { |
| 28 | const int coreid = cvmx_get_core_num(); | 35 | const int coreid = cvmx_get_core_num(); |
| @@ -67,8 +74,28 @@ static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action) · 38 unmodified lines | |||
| 67 | } | 74 | } |
| 68 | 75 | ||
| 69 | /** | 76 | /** |
| 70 | * Detect available CPUs, populate phys_cpu_present_map | 77 | * Detect available CPUs, populate cpu_possible_map |
| 71 | */ | 78 | */ |
| 79 | static void octeon_smp_hotplug_setup(void) | ||
| 80 | { | ||
| 81 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 82 | uint32_t labi_signature; | ||
| 83 | |||
| 84 | labi_signature = | ||
| 85 | cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, | ||
| 86 | LABI_ADDR_IN_BOOTLOADER + | ||
| 87 | offsetof(struct linux_app_boot_info, | ||
| 88 | labi_signature))); | ||
| 89 | if (labi_signature != LABI_SIGNATURE) | ||
| 90 | pr_err("The bootloader version on this board is incorrect\n"); | ||
| 91 | InitTLBStart_addr = | ||
| 92 | cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, | ||
| 93 | LABI_ADDR_IN_BOOTLOADER + | ||
| 94 | offsetof(struct linux_app_boot_info, | ||
| 95 | InitTLBStart_addr))); | ||
| 96 | #endif | ||
| 97 | } | ||
| 98 | |||
| 72 | static void octeon_smp_setup(void) | 99 | static void octeon_smp_setup(void) |
| 73 | { | 100 | { |
| 74 | const int coreid = cvmx_get_core_num(); | 101 | const int coreid = cvmx_get_core_num(); |
| @@ -91,6 +118,9 @@ static void octeon_smp_setup(void) · 16 unmodified lines | |||
| 91 | cpus++; | 118 | cpus++; |
| 92 | } | 119 | } |
| 93 | } | 120 | } |
| 121 | cpu_present_map = cpu_possible_map; | ||
| 122 | |||
| 123 | octeon_smp_hotplug_setup(); | ||
| 94 | } | 124 | } |
| 95 | 125 | ||
| 96 | /** | 126 | /** |
| @@ -128,6 +158,17 @@ static void octeon_init_secondary(void) · 31 unmodified lines | |||
| 128 | const int coreid = cvmx_get_core_num(); | 158 | const int coreid = cvmx_get_core_num(); |
| 129 | union cvmx_ciu_intx_sum0 interrupt_enable; | 159 | union cvmx_ciu_intx_sum0 interrupt_enable; |
| 130 | 160 | ||
| 161 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 162 | unsigned int cur_exception_base; | ||
| 163 | |||
| 164 | cur_exception_base = cvmx_read64_uint32( | ||
| 165 | CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, | ||
| 166 | LABI_ADDR_IN_BOOTLOADER + | ||
| 167 | offsetof(struct linux_app_boot_info, | ||
| 168 | cur_exception_base))); | ||
| 169 | /* cur_exception_base is incremented in bootloader after setting */ | ||
| 170 | write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR)); | ||
| 171 | #endif | ||
| 131 | octeon_check_cpu_bist(); | 172 | octeon_check_cpu_bist(); |
| 132 | octeon_init_cvmcount(); | 173 | octeon_init_cvmcount(); |
| 133 | /* | 174 | /* |
| @@ -199,6 +240,193 @@ static void octeon_cpus_done(void) · 65 unmodified lines | |||
| 199 | #endif | 240 | #endif |
| 200 | } | 241 | } |
| 201 | 242 | ||
| 243 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 244 | |||
| 245 | /* State of each CPU. */ | ||
| 246 | DEFINE_PER_CPU(int, cpu_state); | ||
| 247 | |||
| 248 | extern void fixup_irqs(void); | ||
| 249 | |||
| 250 | static DEFINE_SPINLOCK(smp_reserve_lock); | ||
| 251 | |||
| 252 | static int octeon_cpu_disable(void) | ||
| 253 | { | ||
| 254 | unsigned int cpu = smp_processor_id(); | ||
| 255 | |||
| 256 | if (cpu == 0) | ||
| 257 | return -EBUSY; | ||
| 258 | |||
| 259 | spin_lock(&smp_reserve_lock); | ||
| 260 | |||
| 261 | cpu_clear(cpu, cpu_online_map); | ||
| 262 | cpu_clear(cpu, cpu_callin_map); | ||
| 263 | local_irq_disable(); | ||
| 264 | fixup_irqs(); | ||
| 265 | local_irq_enable(); | ||
| 266 | |||
| 267 | flush_cache_all(); | ||
| 268 | local_flush_tlb_all(); | ||
| 269 | |||
| 270 | spin_unlock(&smp_reserve_lock); | ||
| 271 | |||
| 272 | return 0; | ||
| 273 | } | ||
| 274 | |||
| 275 | static void octeon_cpu_die(unsigned int cpu) | ||
| 276 | { | ||
| 277 | int coreid = cpu_logical_map(cpu); | ||
| 278 | uint32_t avail_coremask; | ||
| 279 | struct cvmx_bootmem_named_block_desc *block_desc; | ||
| 280 | |||
| 281 | #ifdef CONFIG_CAVIUM_OCTEON_WATCHDOG | ||
| 282 | /* Disable the watchdog */ | ||
| 283 | cvmx_ciu_wdogx_t ciu_wdog; | ||
| 284 | ciu_wdog.u64 = cvmx_read_csr(CVMX_CIU_WDOGX(cpu)); | ||
| 285 | ciu_wdog.s.mode = 0; | ||
| 286 | cvmx_write_csr(CVMX_CIU_WDOGX(cpu), ciu_wdog.u64); | ||
| 287 | #endif | ||
| 288 | |||
| 289 | while (per_cpu(cpu_state, cpu) != CPU_DEAD) | ||
| 290 | cpu_relax(); | ||
| 291 | |||
| 292 | /* | ||
| 293 | * This is a bit complicated strategics of getting/settig available | ||
| 294 | * cores mask, copied from bootloader | ||
| 295 | */ | ||
| 296 | /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */ | ||
| 297 | block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); | ||
| 298 | |||
| 299 | if (!block_desc) { | ||
| 300 | avail_coremask = | ||
| 301 | cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, | ||
| 302 | LABI_ADDR_IN_BOOTLOADER + | ||
| 303 | offsetof | ||
| 304 | (struct linux_app_boot_info, | ||
| 305 | avail_coremask))); | ||
| 306 | } else { /* alternative, already initialized */ | ||
| 307 | avail_coremask = | ||
| 308 | cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, | ||
| 309 | block_desc->base_addr + | ||
| 310 | AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK)); | ||
| 311 | } | ||
| 312 | |||
| 313 | avail_coremask |= 1 << coreid; | ||
| 314 | |||
| 315 | /* Setting avail_coremask for bootoct binary */ | ||
| 316 | if (!block_desc) { | ||
| 317 | cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, | ||
| 318 | LABI_ADDR_IN_BOOTLOADER + | ||
| 319 | offsetof(struct linux_app_boot_info, | ||
| 320 | avail_coremask)), | ||
| 321 | avail_coremask); | ||
| 322 | } else { | ||
| 323 | cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, | ||
| 324 | block_desc->base_addr + | ||
| 325 | AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK), | ||
| 326 | avail_coremask); | ||
| 327 | } | ||
| 328 | |||
| 329 | pr_info("Reset core %d. Available Coremask = %x \n", coreid, | ||
| 330 | avail_coremask); | ||
| 331 | cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); | ||
| 332 | cvmx_write_csr(CVMX_CIU_PP_RST, 0); | ||
| 333 | } | ||
| 334 | |||
| 335 | void play_dead(void) | ||
| 336 | { | ||
| 337 | int coreid = cvmx_get_core_num(); | ||
| 338 | |||
| 339 | idle_task_exit(); | ||
| 340 | octeon_processor_boot = 0xff; | ||
| 341 | per_cpu(cpu_state, coreid) = CPU_DEAD; | ||
| 342 | |||
| 343 | while (1) /* core will be reset here */ | ||
| 344 | ; | ||
| 345 | } | ||
| 346 | |||
| 347 | extern void kernel_entry(unsigned long arg1, ...); | ||
| 348 | |||
| 349 | static void start_after_reset(void) | ||
| 350 | { | ||
| 351 | kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ | ||
| 352 | } | ||
| 353 | |||
| 354 | int octeon_update_boot_vector(unsigned int cpu) | ||
| 355 | { | ||
| 356 | |||
| 357 | int coreid = cpu_logical_map(cpu); | ||
| 358 | unsigned int avail_coremask; | ||
| 359 | struct cvmx_bootmem_named_block_desc *block_desc; | ||
| 360 | struct boot_init_vector *boot_vect = | ||
| 361 | (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 + | ||
| 362 | BOOTLOADER_BOOT_VECTOR); | ||
| 363 | |||
| 364 | block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); | ||
| 365 | |||
| 366 | if (!block_desc) { | ||
| 367 | avail_coremask = | ||
| 368 | cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, | ||
| 369 | LABI_ADDR_IN_BOOTLOADER + | ||
| 370 | offsetof(struct linux_app_boot_info, | ||
| 371 | avail_coremask))); | ||
| 372 | } else { /* alternative, already initialized */ | ||
| 373 | avail_coremask = | ||
| 374 | cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, | ||
| 375 | block_desc->base_addr + | ||
| 376 | AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK)); | ||
| 377 | } | ||
| 378 | |||
| 379 | if (!(avail_coremask & (1 << coreid))) { | ||
| 380 | /* core not available, assume, that catched by simple-executive */ | ||
| 381 | cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); | ||
| 382 | cvmx_write_csr(CVMX_CIU_PP_RST, 0); | ||
| 383 | } | ||
| 384 | |||
| 385 | boot_vect[coreid].app_start_func_addr = | ||
| 386 | (uint32_t) (unsigned long) start_after_reset; | ||
| 387 | boot_vect[coreid].code_addr = InitTLBStart_addr; | ||
| 388 | |||
| 389 | CVMX_SYNC; | ||
| 390 | |||
| 391 | cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); | ||
| 392 | |||
| 393 | return 0; | ||
| 394 | } | ||
| 395 | |||
| 396 | static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb, | ||
| 397 | unsigned long action, void *hcpu) | ||
| 398 | { | ||
| 399 | unsigned int cpu = (unsigned long)hcpu; | ||
| 400 | |||
| 401 | switch (action) { | ||
| 402 | case CPU_UP_PREPARE: | ||
| 403 | octeon_update_boot_vector(cpu); | ||
| 404 | break; | ||
| 405 | case CPU_ONLINE: | ||
| 406 | pr_info("Cpu %d online\n", cpu); | ||
| 407 | break; | ||
| 408 | case CPU_DEAD: | ||
| 409 | break; | ||
| 410 | } | ||
| 411 | |||
| 412 | return NOTIFY_OK; | ||
| 413 | } | ||
| 414 | |||
| 415 | static struct notifier_block __cpuinitdata octeon_cpu_notifier = { | ||
| 416 | .notifier_call = octeon_cpu_callback, | ||
| 417 | }; | ||
| 418 | |||
| 419 | static int __cpuinit register_cavium_notifier(void) | ||
| 420 | { | ||
| 421 | register_hotcpu_notifier(&octeon_cpu_notifier); | ||
| 422 | |||
| 423 | return 0; | ||
| 424 | } | ||
| 425 | |||
| 426 | late_initcall(register_cavium_notifier); | ||
| 427 | |||
| 428 | #endif /* CONFIG_HOTPLUG_CPU */ | ||
| 429 | |||
| 202 | struct plat_smp_ops octeon_smp_ops = { | 430 | struct plat_smp_ops octeon_smp_ops = { |
| 203 | .send_ipi_single = octeon_send_ipi_single, | 431 | .send_ipi_single = octeon_send_ipi_single, |
| 204 | .send_ipi_mask = octeon_send_ipi_mask, | 432 | .send_ipi_mask = octeon_send_ipi_mask, |
| @@ -208,4 +436,8 @@ struct plat_smp_ops octeon_smp_ops = { · 3 unmodified lines | |||
| 208 | .boot_secondary = octeon_boot_secondary, | 436 | .boot_secondary = octeon_boot_secondary, |
| 209 | .smp_setup = octeon_smp_setup, | 437 | .smp_setup = octeon_smp_setup, |
| 210 | .prepare_cpus = octeon_prepare_cpus, | 438 | .prepare_cpus = octeon_prepare_cpus, |
| 439 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 440 | .cpu_disable = octeon_cpu_disable, | ||
| 441 | .cpu_die = octeon_cpu_die, | ||
| 442 | #endif | ||
| 211 | }; | 443 | }; |
| @@ -1,6 +1,7 @@ | |||
| 1 | #ifndef __ASM_BUG_H | 1 | #ifndef __ASM_BUG_H |
| 2 | #define __ASM_BUG_H | 2 | #define __ASM_BUG_H |
| 3 | 3 | ||
| 4 | #include <linux/compiler.h> | ||
| 4 | #include <asm/sgidefs.h> | 5 | #include <asm/sgidefs.h> |
| 5 | 6 | ||
| 6 | #ifdef CONFIG_BUG | 7 | #ifdef CONFIG_BUG |
| @@ -11,6 +11,7 @@ · 10 unmodified lines | |||
| 11 | 11 | ||
| 12 | #include <linux/bug.h> | 12 | #include <linux/bug.h> |
| 13 | #include <linux/delay.h> | 13 | #include <linux/delay.h> |
| 14 | #include <linux/smp.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/cpu.h> | 16 | #include <asm/cpu.h> |
| 16 | #include <asm/cpu-info.h> | 17 | #include <asm/cpu-info.h> |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | |||
| 10 | #define _ASM_IRQ_H | 10 | #define _ASM_IRQ_H |
| 11 | 11 | ||
| 12 | #include <linux/linkage.h> | 12 | #include <linux/linkage.h> |
| 13 | #include <linux/smp.h> | ||
| 13 | 14 | ||
| 14 | #include <asm/mipsmtregs.h> | 15 | #include <asm/mipsmtregs.h> |
| 15 | 16 | ||
| @@ -13,6 +13,7 @@ · 12 unmodified lines | |||
| 13 | 13 | ||
| 14 | #include <linux/errno.h> | 14 | #include <linux/errno.h> |
| 15 | #include <linux/sched.h> | 15 | #include <linux/sched.h> |
| 16 | #include <linux/smp.h> | ||
| 16 | #include <linux/slab.h> | 17 | #include <linux/slab.h> |
| 17 | #include <asm/cacheflush.h> | 18 | #include <asm/cacheflush.h> |
| 18 | #include <asm/tlbflush.h> | 19 | #include <asm/tlbflush.h> |
| @@ -26,6 +26,10 @@ struct plat_smp_ops { · 25 unmodified lines | |||
| 26 | void (*boot_secondary)(int cpu, struct task_struct *idle); | 26 | void (*boot_secondary)(int cpu, struct task_struct *idle); |
| 27 | void (*smp_setup)(void); | 27 | void (*smp_setup)(void); |
| 28 | void (*prepare_cpus)(unsigned int max_cpus); | 28 | void (*prepare_cpus)(unsigned int max_cpus); |
| 29 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 30 | int (*cpu_disable)(void); | ||
| 31 | void (*cpu_die)(unsigned int cpu); | ||
| 32 | #endif | ||
| 29 | }; | 33 | }; |
| 30 | 34 | ||
| 31 | extern void register_smp_ops(struct plat_smp_ops *ops); | 35 | extern void register_smp_ops(struct plat_smp_ops *ops); |
| @@ -13,6 +13,7 @@ · 12 unmodified lines | |||
| 13 | 13 | ||
| 14 | #include <linux/bitops.h> | 14 | #include <linux/bitops.h> |
| 15 | #include <linux/linkage.h> | 15 | #include <linux/linkage.h> |
| 16 | #include <linux/smp.h> | ||
| 16 | #include <linux/threads.h> | 17 | #include <linux/threads.h> |
| 17 | #include <linux/cpumask.h> | 18 | #include <linux/cpumask.h> |
| 18 | 19 | ||
| @@ -40,6 +41,7 @@ extern int __cpu_logical_map[NR_CPUS]; · 21 unmodified lines | |||
| 40 | /* Octeon - Tell another core to flush its icache */ | 41 | /* Octeon - Tell another core to flush its icache */ |
| 41 | #define SMP_ICACHE_FLUSH 0x4 | 42 | #define SMP_ICACHE_FLUSH 0x4 |
| 42 | 43 | ||
| 44 | extern volatile cpumask_t cpu_callin_map; | ||
| 43 | 45 | ||
| 44 | extern void asmlinkage smp_bootstrap(void); | 46 | extern void asmlinkage smp_bootstrap(void); |
| 45 | 47 | ||
| @@ -55,6 +57,24 @@ static inline void smp_send_reschedule(int cpu) · 9 unmodified lines | |||
| 55 | mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF); | 57 | mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF); |
| 56 | } | 58 | } |
| 57 | 59 | ||
| 60 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 61 | static inline int __cpu_disable(void) | ||
| 62 | { | ||
| 63 | extern struct plat_smp_ops *mp_ops; /* private */ | ||
| 64 | |||
| 65 | return mp_ops->cpu_disable(); | ||
| 66 | } | ||
| 67 | |||
| 68 | static inline void __cpu_die(unsigned int cpu) | ||
| 69 | { | ||
| 70 | extern struct plat_smp_ops *mp_ops; /* private */ | ||
| 71 | |||
| 72 | mp_ops->cpu_die(cpu); | ||
| 73 | } | ||
| 74 | |||
| 75 | extern void play_dead(void); | ||
| 76 | #endif | ||
| 77 | |||
| 58 | extern asmlinkage void smp_call_function_interrupt(void); | 78 | extern asmlinkage void smp_call_function_interrupt(void); |
| 59 | 79 | ||
| 60 | extern void arch_send_call_function_single_ipi(int cpu); | 80 | extern void arch_send_call_function_single_ipi(int cpu); |
| @@ -11,6 +11,7 @@ · 10 unmodified lines | |||
| 11 | 11 | ||
| 12 | 12 | ||
| 13 | #ifndef __ASSEMBLY__ | 13 | #ifndef __ASSEMBLY__ |
| 14 | #include <linux/smp.h> | ||
| 14 | #include <linux/types.h> | 15 | #include <linux/types.h> |
| 15 | #endif /* !__ASSEMBLY__ */ | 16 | #endif /* !__ASSEMBLY__ */ |
| 16 | 17 | ||
| @@ -10,6 +10,7 @@ · 9 unmodified lines | |||
| 10 | #include <linux/init.h> | 10 | #include <linux/init.h> |
| 11 | #include <linux/interrupt.h> | 11 | #include <linux/interrupt.h> |
| 12 | #include <linux/kernel.h> | 12 | #include <linux/kernel.h> |
| 13 | #include <linux/smp.h> | ||
| 13 | #include <linux/spinlock.h> | 14 | #include <linux/spinlock.h> |
| 14 | 15 | ||
| 15 | #include <asm/irq_cpu.h> | 16 | #include <asm/irq_cpu.h> |
| @@ -18,6 +18,7 @@ · 17 unmodified lines | |||
| 18 | #include <linux/clockchips.h> | 18 | #include <linux/clockchips.h> |
| 19 | #include <linux/interrupt.h> | 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/percpu.h> | 20 | #include <linux/percpu.h> |
| 21 | #include <linux/smp.h> | ||
| 21 | 22 | ||
| 22 | #include <asm/addrspace.h> | 23 | #include <asm/addrspace.h> |
| 23 | #include <asm/io.h> | 24 | #include <asm/io.h> |
| @@ -9,6 +9,7 @@ · 8 unmodified lines | |||
| 9 | #include <linux/clockchips.h> | 9 | #include <linux/clockchips.h> |
| 10 | #include <linux/interrupt.h> | 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/percpu.h> | 11 | #include <linux/percpu.h> |
| 12 | #include <linux/smp.h> | ||
| 12 | 13 | ||
| 13 | #include <asm/smtc_ipi.h> | 14 | #include <asm/smtc_ipi.h> |
| 14 | #include <asm/time.h> | 15 | #include <asm/time.h> |
| @@ -18,6 +18,7 @@ · 17 unmodified lines | |||
| 18 | #include <linux/clockchips.h> | 18 | #include <linux/clockchips.h> |
| 19 | #include <linux/interrupt.h> | 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/percpu.h> | 20 | #include <linux/percpu.h> |
| 21 | #include <linux/smp.h> | ||
| 21 | 22 | ||
| 22 | #include <asm/addrspace.h> | 23 | #include <asm/addrspace.h> |
| 23 | #include <asm/io.h> | 24 | #include <asm/io.h> |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | |||
| 10 | #include <linux/clockchips.h> | 10 | #include <linux/clockchips.h> |
| 11 | #include <linux/interrupt.h> | 11 | #include <linux/interrupt.h> |
| 12 | #include <linux/percpu.h> | 12 | #include <linux/percpu.h> |
| 13 | #include <linux/smp.h> | ||
| 13 | 14 | ||
| 14 | #include <asm/smtc_ipi.h> | 15 | #include <asm/smtc_ipi.h> |
| 15 | #include <asm/time.h> | 16 | #include <asm/time.h> |
| @@ -14,6 +14,7 @@ · 13 unmodified lines | |||
| 14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
| 15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
| 16 | #include <linux/ptrace.h> | 16 | #include <linux/ptrace.h> |
| 17 | #include <linux/smp.h> | ||
| 17 | #include <linux/stddef.h> | 18 | #include <linux/stddef.h> |
| 18 | 19 | ||
| 19 | #include <asm/bugs.h> | 20 | #include <asm/bugs.h> |
| @@ -7,6 +7,7 @@ · 6 unmodified lines | |||
| 7 | #include <linux/interrupt.h> | 7 | #include <linux/interrupt.h> |
| 8 | #include <linux/jiffies.h> | 8 | #include <linux/jiffies.h> |
| 9 | #include <linux/module.h> | 9 | #include <linux/module.h> |
| 10 | #include <linux/smp.h> | ||
| 10 | #include <linux/spinlock.h> | 11 | #include <linux/spinlock.h> |
| 11 | 12 | ||
| 12 | #include <asm/delay.h> | 13 | #include <asm/delay.h> |
| @@ -2,6 +2,7 @@ · 1 unmodified line | |||
| 2 | 2 | ||
| 3 | #include <linux/bitmap.h> | 3 | #include <linux/bitmap.h> |
| 4 | #include <linux/init.h> | 4 | #include <linux/init.h> |
| 5 | #include <linux/smp.h> | ||
| 5 | 6 | ||
| 6 | #include <asm/io.h> | 7 | #include <asm/io.h> |
| 7 | #include <asm/gic.h> | 8 | #include <asm/gic.h> |
| @@ -26,6 +26,7 @@ · 25 unmodified lines | |||
| 26 | #include <linux/kgdb.h> | 26 | #include <linux/kgdb.h> |
| 27 | #include <linux/kdebug.h> | 27 | #include <linux/kdebug.h> |
| 28 | #include <linux/sched.h> | 28 | #include <linux/sched.h> |
| 29 | #include <linux/smp.h> | ||
| 29 | #include <asm/inst.h> | 30 | #include <asm/inst.h> |
| 30 | #include <asm/fpu.h> | 31 | #include <asm/fpu.h> |
| 31 | #include <asm/cacheflush.h> | 32 | #include <asm/cacheflush.h> |
| @@ -50,10 +50,15 @@ · 49 unmodified lines | |||
| 50 | */ | 50 | */ |
| 51 | void __noreturn cpu_idle(void) | 51 | void __noreturn cpu_idle(void) |
| 52 | { | 52 | { |
| 53 | int cpu; | ||
| 54 | |||
| 55 | /* CPU is going idle. */ | ||
| 56 | cpu = smp_processor_id(); | ||
| 57 | |||
| 53 | /* endless idle loop with no priority at all */ | 58 | /* endless idle loop with no priority at all */ |
| 54 | while (1) { | 59 | while (1) { |
| 55 | tick_nohz_stop_sched_tick(1); | 60 | tick_nohz_stop_sched_tick(1); |
| 56 | while (!need_resched()) { | 61 | while (!need_resched() && cpu_online(cpu)) { |
| 57 | #ifdef CONFIG_MIPS_MT_SMTC | 62 | #ifdef CONFIG_MIPS_MT_SMTC |
| 58 | extern void smtc_idle_loop_hook(void); | 63 | extern void smtc_idle_loop_hook(void); |
| 59 | 64 | ||
| @@ -62,6 +67,12 @@ void __noreturn cpu_idle(void) · 2 unmodified lines | |||
| 62 | if (cpu_wait) | 67 | if (cpu_wait) |
| 63 | (*cpu_wait)(); | 68 | (*cpu_wait)(); |
| 64 | } | 69 | } |
| 70 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 71 | if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map) && | ||
| 72 | (system_state == SYSTEM_RUNNING || | ||
| 73 | system_state == SYSTEM_BOOTING)) | ||
| 74 | play_dead(); | ||
| 75 | #endif | ||
| 65 | tick_nohz_restart_sched_tick(); | 76 | tick_nohz_restart_sched_tick(); |
| 66 | preempt_enable_no_resched(); | 77 | preempt_enable_no_resched(); |
| 67 | schedule(); | 78 | schedule(); |
| @@ -20,6 +20,7 @@ · 19 unmodified lines | |||
| 20 | 20 | ||
| 21 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
| 22 | #include <linux/sched.h> | 22 | #include <linux/sched.h> |
| 23 | #include <linux/smp.h> | ||
| 23 | #include <linux/cpumask.h> | 24 | #include <linux/cpumask.h> |
| 24 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
| 25 | #include <linux/compiler.h> | 26 | #include <linux/compiler.h> |
| @@ -55,6 +55,18 @@ static void __init up_prepare_cpus(unsigned int max_cpus) · 54 unmodified lines | |||
| 55 | { | 55 | { |
| 56 | } | 56 | } |
| 57 | 57 | ||
| 58 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 59 | static int up_cpu_disable(void) | ||
| 60 | { | ||
| 61 | return -ENOSYS; | ||
| 62 | } | ||
| 63 | |||
| 64 | static void up_cpu_die(unsigned int cpu) | ||
| 65 | { | ||
| 66 | BUG(); | ||
| 67 | } | ||
| 68 | #endif | ||
| 69 | |||
| 58 | struct plat_smp_ops up_smp_ops = { | 70 | struct plat_smp_ops up_smp_ops = { |
| 59 | .send_ipi_single = up_send_ipi_single, | 71 | .send_ipi_single = up_send_ipi_single, |
| 60 | .send_ipi_mask = up_send_ipi_mask, | 72 | .send_ipi_mask = up_send_ipi_mask, |
| @@ -64,4 +76,8 @@ struct plat_smp_ops up_smp_ops = { · 3 unmodified lines | |||
| 64 | .boot_secondary = up_boot_secondary, | 76 | .boot_secondary = up_boot_secondary, |
| 65 | .smp_setup = up_smp_setup, | 77 | .smp_setup = up_smp_setup, |
| 66 | .prepare_cpus = up_prepare_cpus, | 78 | .prepare_cpus = up_prepare_cpus, |
| 79 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 80 | .cpu_disable = up_cpu_disable, | ||
| 81 | .cpu_die = up_cpu_die, | ||
| 82 | #endif | ||
| 67 | }; | 83 | }; |
| @@ -22,6 +22,7 @@ · 21 unmodified lines | |||
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| 24 | #include <linux/interrupt.h> | 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/smp.h> | ||
| 25 | #include <linux/spinlock.h> | 26 | #include <linux/spinlock.h> |
| 26 | #include <linux/threads.h> | 27 | #include <linux/threads.h> |
| 27 | #include <linux/module.h> | 28 | #include <linux/module.h> |
| @@ -44,7 +45,7 @@ · 16 unmodified lines | |||
| 44 | #include <asm/mipsmtregs.h> | 45 | #include <asm/mipsmtregs.h> |
| 45 | #endif /* CONFIG_MIPS_MT_SMTC */ | 46 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 46 | 47 | ||
| 47 | static volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ | 48 | volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ |
| 48 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ | 49 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
| 49 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ | 50 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ |
| 50 | 51 | ||
| @@ -200,6 +201,8 @@ void __devinit smp_prepare_boot_cpu(void) · 149 unmodified lines | |||
| 200 | * and keep control until "cpu_online(cpu)" is set. Note: cpu is | 201 | * and keep control until "cpu_online(cpu)" is set. Note: cpu is |
| 201 | * physical, not logical. | 202 | * physical, not logical. |
| 202 | */ | 203 | */ |
| 204 | static struct task_struct *cpu_idle_thread[NR_CPUS]; | ||
| 205 | |||
| 203 | int __cpuinit __cpu_up(unsigned int cpu) | 206 | int __cpuinit __cpu_up(unsigned int cpu) |
| 204 | { | 207 | { |
| 205 | struct task_struct *idle; | 208 | struct task_struct *idle; |
| @@ -209,9 +212,16 @@ int __cpuinit __cpu_up(unsigned int cpu) · 3 unmodified lines | |||
| 209 | * The following code is purely to make sure | 212 | * The following code is purely to make sure |
| 210 | * Linux can schedule processes on this slave. | 213 | * Linux can schedule processes on this slave. |
| 211 | */ | 214 | */ |
| 212 | idle = fork_idle(cpu); | 215 | if (!cpu_idle_thread[cpu]) { |
| 213 | if (IS_ERR(idle)) | 216 | idle = fork_idle(cpu); |
| 214 | panic(KERN_ERR "Fork failed for CPU %d", cpu); | 217 | cpu_idle_thread[cpu] = idle; |
| 218 | |||
| 219 | if (IS_ERR(idle)) | ||
| 220 | panic(KERN_ERR "Fork failed for CPU %d", cpu); | ||
| 221 | } else { | ||
| 222 | idle = cpu_idle_thread[cpu]; | ||
| 223 | init_idle(idle, cpu); | ||
| 224 | } | ||
| 215 | 225 | ||
| 216 | mp_ops->boot_secondary(cpu, idle); | 226 | mp_ops->boot_secondary(cpu, idle); |
| 217 | 227 | ||
| @@ -20,6 +20,7 @@ · 19 unmodified lines | |||
| 20 | #include <linux/clockchips.h> | 20 | #include <linux/clockchips.h> |
| 21 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
| 22 | #include <linux/sched.h> | 22 | #include <linux/sched.h> |
| 23 | #include <linux/smp.h> | ||
| 23 | #include <linux/cpumask.h> | 24 | #include <linux/cpumask.h> |
| 24 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
| 25 | #include <linux/kernel_stat.h> | 26 | #include <linux/kernel_stat.h> |
| @@ -17,7 +17,10 @@ static int __init topology_init(void) · 16 unmodified lines | |||
| 17 | #endif /* CONFIG_NUMA */ | 17 | #endif /* CONFIG_NUMA */ |
| 18 | 18 | ||
| 19 | for_each_present_cpu(i) { | 19 | for_each_present_cpu(i) { |
| 20 | ret = register_cpu(&per_cpu(cpu_devices, i), i); | 20 | struct cpu *c = &per_cpu(cpu_devices, i); |
| 21 | |||
| 22 | c->hotpluggable = 1; | ||
| 23 | ret = register_cpu(c, i); | ||
| 21 | if (ret) | 24 | if (ret) |
| 22 | printk(KERN_WARNING "topology_init: register_cpu %d " | 25 | printk(KERN_WARNING "topology_init: register_cpu %d " |
| 23 | "failed (%d)\n", i, ret); | 26 | "failed (%d)\n", i, ret); |
| @@ -91,6 +91,7 @@ unsigned __cpuinit get_c0_compare_int(void) · 90 unmodified lines | |||
| 91 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; | 91 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
| 92 | } else { | 92 | } else { |
| 93 | #endif | 93 | #endif |
| 94 | { | ||
| 94 | if (cpu_has_vint) | 95 | if (cpu_has_vint) |
| 95 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); | 96 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); |
| 96 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; | 97 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
| @@ -8,6 +8,7 @@ · 7 unmodified lines | |||
| 8 | #include <linux/init.h> | 8 | #include <linux/init.h> |
| 9 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| 10 | #include <linux/sched.h> | 10 | #include <linux/sched.h> |
| 11 | #include <linux/smp.h> | ||
| 11 | #include <linux/mm.h> | 12 | #include <linux/mm.h> |
| 12 | #include <linux/bitops.h> | 13 | #include <linux/bitops.h> |
| 13 | #include <linux/cpu.h> | 14 | #include <linux/cpu.h> |
| @@ -12,6 +12,7 @@ · 11 unmodified lines | |||
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/sched.h> | 14 | #include <linux/sched.h> |
| 15 | #include <linux/smp.h> | ||
| 15 | #include <linux/mm.h> | 16 | #include <linux/mm.h> |
| 16 | 17 | ||
| 17 | #include <asm/page.h> | 18 | #include <asm/page.h> |
| @@ -13,6 +13,7 @@ · 12 unmodified lines | |||
| 13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/linkage.h> | 14 | #include <linux/linkage.h> |
| 15 | #include <linux/sched.h> | 15 | #include <linux/sched.h> |
| 16 | #include <linux/smp.h> | ||
| 16 | #include <linux/mm.h> | 17 | #include <linux/mm.h> |
| 17 | #include <linux/module.h> | 18 | #include <linux/module.h> |
| 18 | #include <linux/bitops.h> | 19 | #include <linux/bitops.h> |
| @@ -11,6 +11,7 @@ · 10 unmodified lines | |||
| 11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 12 | #include <linux/kernel.h> | 12 | #include <linux/kernel.h> |
| 13 | #include <linux/sched.h> | 13 | #include <linux/sched.h> |
| 14 | #include <linux/smp.h> | ||
| 14 | #include <linux/mm.h> | 15 | #include <linux/mm.h> |
| 15 | 16 | ||
| 16 | #include <asm/cacheops.h> | 17 | #include <asm/cacheops.h> |
| @@ -1,5 +1,6 @@ | |||
| 1 | #include <linux/module.h> | 1 | #include <linux/module.h> |
| 2 | #include <linux/highmem.h> | 2 | #include <linux/highmem.h> |
| 3 | #include <linux/smp.h> | ||
| 3 | #include <asm/fixmap.h> | 4 | #include <asm/fixmap.h> |
| 4 | #include <asm/tlbflush.h> | 5 | #include <asm/tlbflush.h> |
| 5 | 6 | ||
| @@ -13,6 +13,7 @@ · 12 unmodified lines | |||
| 13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
| 14 | #include <linux/signal.h> | 14 | #include <linux/signal.h> |
| 15 | #include <linux/sched.h> | 15 | #include <linux/sched.h> |
| 16 | #include <linux/smp.h> | ||
| 16 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 17 | #include <linux/errno.h> | 18 | #include <linux/errno.h> |
| 18 | #include <linux/string.h> | 19 | #include <linux/string.h> |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | |||
| 10 | #include <linux/init.h> | 10 | #include <linux/init.h> |
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/sched.h> | 12 | #include <linux/sched.h> |
| 13 | #include <linux/smp.h> | ||
| 13 | #include <linux/mm.h> | 14 | #include <linux/mm.h> |
| 14 | #include <linux/module.h> | 15 | #include <linux/module.h> |
| 15 | #include <linux/proc_fs.h> | 16 | #include <linux/proc_fs.h> |
| @@ -13,6 +13,7 @@ · 12 unmodified lines | |||
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 15 | #include <linux/sched.h> | 15 | #include <linux/sched.h> |
| 16 | #include <linux/smp.h> | ||
| 16 | #include <linux/mm.h> | 17 | #include <linux/mm.h> |
| 17 | 18 | ||
| 18 | #include <asm/page.h> | 19 | #include <asm/page.h> |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | |||
| 10 | */ | 10 | */ |
| 11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 12 | #include <linux/sched.h> | 12 | #include <linux/sched.h> |
| 13 | #include <linux/smp.h> | ||
| 13 | #include <linux/mm.h> | 14 | #include <linux/mm.h> |
| 14 | #include <linux/hugetlb.h> | 15 | #include <linux/hugetlb.h> |
| 15 | 16 | ||
| @@ -10,6 +10,7 @@ · 9 unmodified lines | |||
| 10 | */ | 10 | */ |
| 11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 12 | #include <linux/sched.h> | 12 | #include <linux/sched.h> |
| 13 | #include <linux/smp.h> | ||
| 13 | #include <linux/mm.h> | 14 | #include <linux/mm.h> |
| 14 | 15 | ||
| 15 | #include <asm/cpu.h> | 16 | #include <asm/cpu.h> |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | |||
| 23 | #include <linux/bug.h> | 23 | #include <linux/bug.h> |
| 24 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
| 25 | #include <linux/types.h> | 25 | #include <linux/types.h> |
| 26 | #include <linux/smp.h> | ||
| 26 | #include <linux/string.h> | 27 | #include <linux/string.h> |
| 27 | #include <linux/init.h> | 28 | #include <linux/init.h> |
| 28 | 29 | ||
| @@ -24,6 +24,7 @@ · 23 unmodified lines | |||
| 24 | #include <linux/init.h> | 24 | #include <linux/init.h> |
| 25 | #include <linux/irq.h> | 25 | #include <linux/irq.h> |
| 26 | #include <linux/sched.h> | 26 | #include <linux/sched.h> |
| 27 | #include <linux/smp.h> | ||
| 27 | #include <linux/slab.h> | 28 | #include <linux/slab.h> |
| 28 | #include <linux/interrupt.h> | 29 | #include <linux/interrupt.h> |
| 29 | #include <linux/io.h> | 30 | #include <linux/io.h> |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | |||
| 10 | #include <linux/init.h> | 10 | #include <linux/init.h> |
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/pci.h> | 12 | #include <linux/pci.h> |
| 13 | #include <linux/smp.h> | ||
| 13 | #include <asm/sn/arch.h> | 14 | #include <asm/sn/arch.h> |
| 14 | #include <asm/pci/bridge.h> | 15 | #include <asm/pci/bridge.h> |
| 15 | #include <asm/paccess.h> | 16 | #include <asm/paccess.h> |
| @@ -1,5 +1,6 @@ | |||
| 1 | #include <linux/linkage.h> | 1 | #include <linux/linkage.h> |
| 2 | #include <linux/sched.h> | 2 | #include <linux/sched.h> |
| 3 | #include <linux/smp.h> | ||
| 3 | 4 | ||
| 4 | #include <asm/pmon.h> | 5 | #include <asm/pmon.h> |
| 5 | #include <asm/titan_dep.h> | 6 | #include <asm/titan_dep.h> |
| @@ -43,15 +43,6 @@ LEAF(swsusp_arch_resume) · 42 unmodified lines | |||
| 43 | bne t1, t3, 1b | 43 | bne t1, t3, 1b |
| 44 | PTR_L t0, PBE_NEXT(t0) | 44 | PTR_L t0, PBE_NEXT(t0) |
| 45 | bnez t0, 0b | 45 | bnez t0, 0b |
| 46 | /* flush caches to make sure context is in memory */ | ||
| 47 | PTR_L t0, __flush_cache_all | ||
| 48 | jalr t0 | ||
| 49 | /* flush tlb entries */ | ||
| 50 | #ifdef CONFIG_SMP | ||
| 51 | jal flush_tlb_all | ||
| 52 | #else | ||
| 53 | jal local_flush_tlb_all | ||
| 54 | #endif | ||
| 55 | PTR_LA t0, saved_regs | 46 | PTR_LA t0, saved_regs |
| 56 | PTR_L ra, PT_R31(t0) | 47 | PTR_L ra, PT_R31(t0) |
| 57 | PTR_L sp, PT_R29(t0) | 48 | PTR_L sp, PT_R29(t0) |
| @@ -9,6 +9,7 @@ · 8 unmodified lines | |||
| 9 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| 10 | #include <linux/init.h> | 10 | #include <linux/init.h> |
| 11 | #include <linux/sched.h> | 11 | #include <linux/sched.h> |
| 12 | #include <linux/smp.h> | ||
| 12 | #include <linux/mm.h> | 13 | #include <linux/mm.h> |
| 13 | #include <linux/module.h> | 14 | #include <linux/module.h> |
| 14 | #include <linux/cpumask.h> | 15 | #include <linux/cpumask.h> |
| @@ -18,6 +18,7 @@ · 17 unmodified lines | |||
| 18 | #include <linux/ioport.h> | 18 | #include <linux/ioport.h> |
| 19 | #include <linux/timex.h> | 19 | #include <linux/timex.h> |
| 20 | #include <linux/slab.h> | 20 | #include <linux/slab.h> |
| 21 | #include <linux/smp.h> | ||
| 21 | #include <linux/random.h> | 22 | #include <linux/random.h> |
| 22 | #include <linux/kernel.h> | 23 | #include <linux/kernel.h> |
| 23 | #include <linux/kernel_stat.h> | 24 | #include <linux/kernel_stat.h> |
| @@ -10,6 +10,7 @@ · 9 unmodified lines | |||
| 10 | #include <linux/interrupt.h> | 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/kernel_stat.h> | 11 | #include <linux/kernel_stat.h> |
| 12 | #include <linux/param.h> | 12 | #include <linux/param.h> |
| 13 | #include <linux/smp.h> | ||
| 13 | #include <linux/time.h> | 14 | #include <linux/time.h> |
| 14 | #include <linux/timex.h> | 15 | #include <linux/timex.h> |
| 15 | #include <linux/mm.h> | 16 | #include <linux/mm.h> |
| @@ -9,6 +9,7 @@ · 8 unmodified lines | |||
| 9 | 9 | ||
| 10 | #include <linux/init.h> | 10 | #include <linux/init.h> |
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/smp.h> | ||
| 12 | #include <asm/sn/types.h> | 13 | #include <asm/sn/types.h> |
| 13 | #include <asm/sn/klconfig.h> | 14 | #include <asm/sn/klconfig.h> |
| 14 | #include <asm/sn/hub.h> | 15 | #include <asm/sn/hub.h> |
| @@ -19,6 +19,7 @@ · 18 unmodified lines | |||
| 19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 20 | #include <linux/linkage.h> | 20 | #include <linux/linkage.h> |
| 21 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/smp.h> | ||
| 22 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
| 23 | #include <linux/mm.h> | 24 | #include <linux/mm.h> |
| 24 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
| @@ -51,12 +51,13 @@ static int cfe_console_setup(struct console *cons, char *str) · 50 unmodified lines | |||
| 51 | setleds("u0cn"); | 51 | setleds("u0cn"); |
| 52 | } else if (!strcmp(consdev, "uart1")) { | 52 | } else if (!strcmp(consdev, "uart1")) { |
| 53 | setleds("u1cn"); | 53 | setleds("u1cn"); |
| 54 | } else | ||
| 54 | #endif | 55 | #endif |
| 55 | #ifdef CONFIG_VGA_CONSOLE | 56 | #ifdef CONFIG_VGA_CONSOLE |
| 56 | } else if (!strcmp(consdev, "pcconsole0")) { | 57 | if (!strcmp(consdev, "pcconsole0")) { |
| 57 | setleds("pccn"); | 58 | setleds("pccn"); |
| 58 | #endif | ||
| 59 | } else | 59 | } else |
| 60 | #endif | ||
| 60 | return -ENODEV; | 61 | return -ENODEV; |
| 61 | } | 62 | } |
| 62 | return 0; | 63 | return 0; |
| @@ -1,5 +1,6 @@ | |||
| 1 | #include <linux/types.h> | 1 | #include <linux/types.h> |
| 2 | #include <linux/interrupt.h> | 2 | #include <linux/interrupt.h> |
| 3 | #include <linux/smp.h> | ||
| 3 | #include <linux/time.h> | 4 | #include <linux/time.h> |
| 4 | #include <linux/clockchips.h> | 5 | #include <linux/clockchips.h> |
| 5 | 6 | ||
| @@ -346,10 +346,12 @@ · 345 unmodified lines | |||
| 346 | #define __NR_inotify_init1 333 | 346 | #define __NR_inotify_init1 333 |
| 347 | #define __NR_preadv 334 | 347 | #define __NR_preadv 334 |
| 348 | #define __NR_pwritev 335 | 348 | #define __NR_pwritev 335 |
| 349 | #define __NR_rt_tgsigqueueinfo 336 | ||
| 350 | #define __NR_perf_counter_open 337 | ||
| 349 | 351 | ||
| 350 | #ifdef __KERNEL__ | 352 | #ifdef __KERNEL__ |
| 351 | 353 | ||
| 352 | #define NR_syscalls 326 | 354 | #define NR_syscalls 338 |
| 353 | 355 | ||
| 354 | /* | 356 | /* |
| 355 | * specify the deprecated syscalls we want to support on this arch | 357 | * specify the deprecated syscalls we want to support on this arch |
| @@ -722,6 +722,8 @@ ENTRY(sys_call_table) · 721 unmodified lines | |||
| 722 | .long sys_inotify_init1 | 722 | .long sys_inotify_init1 |
| 723 | .long sys_preadv | 723 | .long sys_preadv |
| 724 | .long sys_pwritev /* 335 */ | 724 | .long sys_pwritev /* 335 */ |
| 725 | .long sys_rt_tgsigqueueinfo | ||
| 726 | .long sys_perf_counter_open | ||
| 725 | 727 | ||
| 726 | 728 | ||
| 727 | nr_syscalls=(.-sys_call_table)/4 | 729 | nr_syscalls=(.-sys_call_table)/4 |
| @@ -38,14 +38,10 @@ SECTIONS · 37 unmodified lines | |||
| 38 | 38 | ||
| 39 | _etext = .; /* End of text section */ | 39 | _etext = .; /* End of text section */ |
| 40 | 40 | ||
| 41 | . = ALIGN(16); /* Exception table */ | 41 | EXCEPTION_TABLE(16) |
| 42 | __start___ex_table = .; | ||
| 43 | __ex_table : { *(__ex_table) } | ||
| 44 | __stop___ex_table = .; | ||
| 45 | |||
| 46 | BUG_TABLE | 42 | BUG_TABLE |
| 47 | 43 | ||
| 48 | RODATA | 44 | RO_DATA(PAGE_SIZE) |
| 49 | 45 | ||
| 50 | /* writeable */ | 46 | /* writeable */ |
| 51 | .data : { /* Data */ | 47 | .data : { /* Data */ |
| @@ -53,27 +49,19 @@ SECTIONS · 1 unmodified line | |||
| 53 | CONSTRUCTORS | 49 | CONSTRUCTORS |
| 54 | } | 50 | } |
| 55 | 51 | ||
| 56 | . = ALIGN(PAGE_SIZE); | 52 | .data_nosave : { NOSAVE_DATA; } |
| 57 | __nosave_begin = .; | ||
| 58 | .data_nosave : { *(.data.nosave) } | ||
| 59 | . = ALIGN(PAGE_SIZE); | ||
| 60 | __nosave_end = .; | ||
| 61 | |||
| 62 | . = ALIGN(PAGE_SIZE); | ||
| 63 | .data.page_aligned : { *(.data.idt) } | ||
| 64 | 53 | ||
| 65 | . = ALIGN(32); | 54 | .data.page_aligned : { PAGE_ALIGNED_DATA(PAGE_SIZE); } |
| 66 | .data.cacheline_aligned : { *(.data.cacheline_aligned) } | 55 | .data.cacheline_aligned : { CACHELINE_ALIGNED_DATA(32); } |
| 67 | 56 | ||
| 68 | /* rarely changed data like cpu maps */ | 57 | /* rarely changed data like cpu maps */ |
| 69 | . = ALIGN(32); | 58 | . = ALIGN(32); |
| 70 | .data.read_mostly : AT(ADDR(.data.read_mostly)) { | 59 | .data.read_mostly : AT(ADDR(.data.read_mostly)) { |
| 71 | *(.data.read_mostly) | 60 | READ_MOSTLY_DATA(32); |
| 72 | _edata = .; /* End of data section */ | 61 | _edata = .; /* End of data section */ |
| 73 | } | 62 | } |
| 74 | 63 | ||
| 75 | . = ALIGN(THREAD_SIZE); /* init_task */ | 64 | .data.init_task : { INIT_TASK(THREAD_SIZE); } |
| 76 | .data.init_task : { *(.data.init_task) } | ||
| 77 | 65 | ||
| 78 | /* might get freed after init */ | 66 | /* might get freed after init */ |
| 79 | . = ALIGN(PAGE_SIZE); | 67 | . = ALIGN(PAGE_SIZE); |
| @@ -88,23 +76,18 @@ SECTIONS · 8 unmodified lines | |||
| 88 | __init_begin = .; | 76 | __init_begin = .; |
| 89 | .init.text : { | 77 | .init.text : { |
| 90 | _sinittext = .; | 78 | _sinittext = .; |
| 91 | *(.init.text) | 79 | INIT_TEXT; |
| 92 | _einittext = .; | 80 | _einittext = .; |
| 93 | } | 81 | } |
| 94 | .init.data : { *(.init.data) } | 82 | .init.data : { INIT_DATA; } |
| 95 | . = ALIGN(16); | 83 | .setup.init : { INIT_SETUP(16); } |
| 96 | __setup_start = .; | ||
| 97 | .setup.init : { KEEP(*(.init.setup)) } | ||
| 98 | __setup_end = .; | ||
| 99 | 84 | ||
| 100 | __initcall_start = .; | 85 | __initcall_start = .; |
| 101 | .initcall.init : { | 86 | .initcall.init : { |
| 102 | INITCALLS | 87 | INITCALLS |
| 103 | } | 88 | } |
| 104 | __initcall_end = .; | 89 | __initcall_end = .; |
| 105 | __con_initcall_start = .; | 90 | .con_initcall.init : { CON_INITCALL; } |
| 106 | .con_initcall.init : { *(.con_initcall.init) } | ||
| 107 | __con_initcall_end = .; | ||
| 108 | 91 | ||
| 109 | SECURITY_INIT | 92 | SECURITY_INIT |
| 110 | . = ALIGN(4); | 93 | . = ALIGN(4); |
| @@ -114,28 +97,17 @@ SECTIONS · 3 unmodified lines | |||
| 114 | .altinstr_replacement : { *(.altinstr_replacement) } | 97 | .altinstr_replacement : { *(.altinstr_replacement) } |
| 115 | /* .exit.text is discard at runtime, not link time, to deal with references | 98 | /* .exit.text is discard at runtime, not link time, to deal with references |
| 116 | from .altinstructions and .eh_frame */ | 99 | from .altinstructions and .eh_frame */ |
| 117 | .exit.text : { *(.exit.text) } | 100 | .exit.text : { EXIT_TEXT; } |
| 118 | .exit.data : { *(.exit.data) } | 101 | .exit.data : { EXIT_DATA; } |
| 119 | 102 | ||
| 120 | #ifdef CONFIG_BLK_DEV_INITRD | 103 | .init.ramfs : { INIT_RAM_FS; } |
| 121 | . = ALIGN(PAGE_SIZE); | ||
| 122 | __initramfs_start = .; | ||
| 123 | .init.ramfs : { *(.init.ramfs) } | ||
| 124 | __initramfs_end = .; | ||
| 125 | #endif | ||
| 126 | 104 | ||
| 127 | PERCPU(32) | 105 | PERCPU(32) |
| 128 | . = ALIGN(PAGE_SIZE); | 106 | . = ALIGN(PAGE_SIZE); |
| 129 | __init_end = .; | 107 | __init_end = .; |
| 130 | /* freed after init ends here */ | 108 | /* freed after init ends here */ |
| 131 | 109 | ||
| 132 | __bss_start = .; /* BSS */ | 110 | BSS(4) |
| 133 | .bss : { | ||
| 134 | *(.bss.page_aligned) | ||
| 135 | *(.bss) | ||
| 136 | } | ||
| 137 | . = ALIGN(4); | ||
| 138 | __bss_stop = .; | ||
| 139 | 111 | ||
| 140 | _end = . ; | 112 | _end = . ; |
| 141 | 113 | ||
| @@ -145,7 +117,7 @@ SECTIONS · 3 unmodified lines | |||
| 145 | 117 | ||
| 146 | /* Sections to be discarded */ | 118 | /* Sections to be discarded */ |
| 147 | /DISCARD/ : { | 119 | /DISCARD/ : { |
| 148 | *(.exitcall.exit) | 120 | EXIT_CALL |
| 149 | *(.discard) | 121 | *(.discard) |
| 150 | } | 122 | } |
| 151 | 123 | ||
| @@ -65,7 +65,6 @@ config HAVE_LATENCYTOP_SUPPORT · 64 unmodified lines | |||
| 65 | 65 | ||
| 66 | config TRACE_IRQFLAGS_SUPPORT | 66 | config TRACE_IRQFLAGS_SUPPORT |
| 67 | bool | 67 | bool |
| 68 | depends on PPC64 | ||
| 69 | default y | 68 | default y |
| 70 | 69 | ||
| 71 | config LOCKDEP_SUPPORT | 70 | config LOCKDEP_SUPPORT |
| @@ -36,3 +36,13 @@ zImage.pseries · 35 unmodified lines | |||
| 36 | zconf.h | 36 | zconf.h |
| 37 | zlib.h | 37 | zlib.h |
| 38 | zutil.h | 38 | zutil.h |
| 39 | fdt.c | ||
| 40 | fdt.h | ||
| 41 | fdt_ro.c | ||
| 42 | fdt_rw.c | ||
| 43 | fdt_strerror.c | ||
| 44 | fdt_sw.c | ||
| 45 | fdt_wip.c | ||
| 46 | libfdt.h | ||
| 47 | libfdt_internal.h | ||
| 48 | |||
| @@ -70,8 +70,8 @@ · 69 unmodified lines | |||
| 70 | devsel-speed = <0x00000001>; | 70 | devsel-speed = <0x00000001>; |
| 71 | min-grant = <0>; | 71 | min-grant = <0>; |
| 72 | max-latency = <0>; | 72 | max-latency = <0>; |
| 73 | /* First 64k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */ | 73 | /* First 4k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */ |
| 74 | ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00010000>; | 74 | ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>; |
| 75 | interrupt-parent = <&i8259>; | 75 | interrupt-parent = <&i8259>; |
| 76 | #interrupt-cells = <2>; | 76 | #interrupt-cells = <2>; |
| 77 | #address-cells = <2>; | 77 | #address-cells = <2>; |
| @@ -253,6 +253,7 @@ · 252 unmodified lines | |||
| 253 | /* Filled in by U-Boot */ | 253 | /* Filled in by U-Boot */ |
| 254 | clock-frequency = <0>; | 254 | clock-frequency = <0>; |
| 255 | status = "disabled"; | 255 | status = "disabled"; |
| 256 | sdhci,1-bit-only; | ||
| 256 | }; | 257 | }; |
| 257 | 258 | ||
| 258 | crypto@30000 { | 259 | crypto@30000 { |
| @@ -598,8 +598,6 @@ typedef struct risc_timer_pram { · 597 unmodified lines | |||
| 598 | #define CICR_IEN ((uint)0x00000080) /* Int. enable */ | 598 | #define CICR_IEN ((uint)0x00000080) /* Int. enable */ |
| 599 | #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ | 599 | #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ |
| 600 | 600 | ||
| 601 | #define IMAP_ADDR (get_immrbase()) | ||
| 602 | |||
| 603 | #define CPM_PIN_INPUT 0 | 601 | #define CPM_PIN_INPUT 0 |
| 604 | #define CPM_PIN_OUTPUT 1 | 602 | #define CPM_PIN_OUTPUT 1 |
| 605 | #define CPM_PIN_PRIMARY 0 | 603 | #define CPM_PIN_PRIMARY 0 |
| @@ -309,7 +309,9 @@ static inline void dma_sync_single_for_cpu(struct device *dev, · 308 unmodified lines | |||
| 309 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | 309 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); |
| 310 | 310 | ||
| 311 | BUG_ON(!dma_ops); | 311 | BUG_ON(!dma_ops); |
| 312 | dma_ops->sync_single_range_for_cpu(dev, dma_handle, 0, | 312 | |
| 313 | if (dma_ops->sync_single_range_for_cpu) | ||
| 314 | dma_ops->sync_single_range_for_cpu(dev, dma_handle, 0, | ||
| 313 | size, direction); | 315 | size, direction); |
| 314 | } | 316 | } |
| 315 | 317 | ||
| @@ -320,7 +322,9 @@ static inline void dma_sync_single_for_device(struct device *dev, · 4 unmodified lines | |||
| 320 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | 322 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); |
| 321 | 323 | ||
| 322 | BUG_ON(!dma_ops); | 324 | BUG_ON(!dma_ops); |
| 323 | dma_ops->sync_single_range_for_device(dev, dma_handle, | 325 | |
| 326 | if (dma_ops->sync_single_range_for_device) | ||
| 327 | dma_ops->sync_single_range_for_device(dev, dma_handle, | ||
| 324 | 0, size, direction); | 328 | 0, size, direction); |
| 325 | } | 329 | } |
| 326 | 330 | ||
| @@ -331,7 +335,9 @@ static inline void dma_sync_sg_for_cpu(struct device *dev, · 4 unmodified lines | |||
| 331 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | 335 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); |
| 332 | 336 | ||
| 333 | BUG_ON(!dma_ops); | 337 | BUG_ON(!dma_ops); |
| 334 | dma_ops->sync_sg_for_cpu(dev, sgl, nents, direction); | 338 | |
| 339 | if (dma_ops->sync_sg_for_cpu) | ||
| 340 | dma_ops->sync_sg_for_cpu(dev, sgl, nents, direction); | ||
| 335 | } | 341 | } |
| 336 | 342 | ||
| 337 | static inline void dma_sync_sg_for_device(struct device *dev, | 343 | static inline void dma_sync_sg_for_device(struct device *dev, |
| @@ -341,7 +347,9 @@ static inline void dma_sync_sg_for_device(struct device *dev, · 3 unmodified lines | |||
| 341 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | 347 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); |
| 342 | 348 | ||
| 343 | BUG_ON(!dma_ops); | 349 | BUG_ON(!dma_ops); |
| 344 | dma_ops->sync_sg_for_device(dev, sgl, nents, direction); | 350 | |
| 351 | if (dma_ops->sync_sg_for_device) | ||
| 352 | dma_ops->sync_sg_for_device(dev, sgl, nents, direction); | ||
| 345 | } | 353 | } |
| 346 | 354 | ||
| 347 | static inline void dma_sync_single_range_for_cpu(struct device *dev, | 355 | static inline void dma_sync_single_range_for_cpu(struct device *dev, |
| @@ -351,7 +359,9 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev, · 3 unmodified lines | |||
| 351 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | 359 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); |
| 352 | 360 | ||
| 353 | BUG_ON(!dma_ops); | 361 | BUG_ON(!dma_ops); |
| 354 | dma_ops->sync_single_range_for_cpu(dev, dma_handle, | 362 | |
| 363 | if (dma_ops->sync_single_range_for_cpu) | ||
| 364 | dma_ops->sync_single_range_for_cpu(dev, dma_handle, | ||
| 355 | offset, size, direction); | 365 | offset, size, direction); |
| 356 | } | 366 | } |
| 357 | 367 | ||
| @@ -362,7 +372,9 @@ static inline void dma_sync_single_range_for_device(struct device *dev, · 4 unmodified lines | |||
| 362 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); | 372 | struct dma_mapping_ops *dma_ops = get_dma_ops(dev); |
| 363 | 373 | ||
| 364 | BUG_ON(!dma_ops); | 374 | BUG_ON(!dma_ops); |
| 365 | dma_ops->sync_single_range_for_device(dev, dma_handle, offset, | 375 | |
| 376 | if (dma_ops->sync_single_range_for_device) | ||
| 377 | dma_ops->sync_single_range_for_device(dev, dma_handle, offset, | ||
| 366 | size, direction); | 378 | size, direction); |
| 367 | } | 379 | } |
| 368 | #else /* CONFIG_PPC_NEED_DMA_SYNC_OPS */ | 380 | #else /* CONFIG_PPC_NEED_DMA_SYNC_OPS */ |
| @@ -22,9 +22,7 @@ · 21 unmodified lines | |||
| 22 | 22 | ||
| 23 | #ifdef __KERNEL__ | 23 | #ifdef __KERNEL__ |
| 24 | 24 | ||
| 25 | #include <linux/init.h> | ||
| 26 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
| 27 | #include <linux/highmem.h> | ||
| 28 | #include <asm/kmap_types.h> | 26 | #include <asm/kmap_types.h> |
| 29 | #include <asm/tlbflush.h> | 27 | #include <asm/tlbflush.h> |
| 30 | #include <asm/page.h> | 28 | #include <asm/page.h> |
| @@ -62,6 +60,9 @@ extern pte_t *pkmap_page_table; · 31 unmodified lines | |||
| 62 | 60 | ||
| 63 | extern void *kmap_high(struct page *page); | 61 | extern void *kmap_high(struct page *page); |
| 64 | extern void kunmap_high(struct page *page); | 62 | extern void kunmap_high(struct page *page); |
| 63 | extern void *kmap_atomic_prot(struct page *page, enum km_type type, | ||
| 64 | pgprot_t prot); | ||
| 65 | extern void kunmap_atomic(void *kvaddr, enum km_type type); | ||
| 65 | 66 | ||
| 66 | static inline void *kmap(struct page *page) | 67 | static inline void *kmap(struct page *page) |
| 67 | { | 68 | { |
| @@ -79,62 +80,11 @@ static inline void kunmap(struct page *page) · 11 unmodified lines | |||
| 79 | kunmap_high(page); | 80 | kunmap_high(page); |
| 80 | } | 81 | } |
| 81 | 82 | ||
| 82 | /* | ||
| 83 | * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap | ||
| 84 | * gives a more generic (and caching) interface. But kmap_atomic can | ||
| 85 | * be used in IRQ contexts, so in some (very limited) cases we need | ||
| 86 | * it. | ||
| 87 | */ | ||
| 88 | static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot) | ||
| 89 | { | ||
| 90 | unsigned int idx; | ||
| 91 | unsigned long vaddr; | ||
| 92 | |||
| 93 | /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ | ||
| 94 | pagefault_disable(); | ||
| 95 | if (!PageHighMem(page)) | ||
| 96 | return page_address(page); | ||
| 97 | |||
| 98 | debug_kmap_atomic(type); | ||
| 99 | idx = type + KM_TYPE_NR*smp_processor_id(); | ||
| 100 | vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
| 101 | #ifdef CONFIG_DEBUG_HIGHMEM | ||
| 102 | BUG_ON(!pte_none(*(kmap_pte-idx))); | ||
| 103 | #endif | ||
| 104 | __set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot), 1); | ||
| 105 | local_flush_tlb_page(NULL, vaddr); | ||
| 106 | |||
| 107 | return (void*) vaddr; | ||
| 108 | } | ||
| 109 | |||
| 110 | static inline void *kmap_atomic(struct page *page, enum km_type type) | 83 | static inline void *kmap_atomic(struct page *page, enum km_type type) |
| 111 | { | 84 | { |
| 112 | return kmap_atomic_prot(page, type, kmap_prot); | 85 | return kmap_atomic_prot(page, type, kmap_prot); |
| 113 | } | 86 | } |
| 114 | 87 | ||
| 115 | static inline void kunmap_atomic(void *kvaddr, enum km_type type) | ||
| 116 | { | ||
| 117 | #ifdef CONFIG_DEBUG_HIGHMEM | ||
| 118 | unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; | ||
| 119 | enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); | ||
| 120 | |||
| 121 | if (vaddr < __fix_to_virt(FIX_KMAP_END)) { | ||
| 122 | pagefault_enable(); | ||
| 123 | return; | ||
| 124 | } | ||
| 125 | |||
| 126 | BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); | ||
| 127 | |||
| 128 | /* | ||
| 129 | * force other mappings to Oops if they'll try to access | ||
| 130 | * this pte without first remap it | ||
| 131 | */ | ||
| 132 | pte_clear(&init_mm, vaddr, kmap_pte-idx); | ||
| 133 | local_flush_tlb_page(NULL, vaddr); | ||
| 134 | #endif | ||
| 135 | pagefault_enable(); | ||
| 136 | } | ||
| 137 | |||
| 138 | static inline struct page *kmap_atomic_to_page(void *ptr) | 88 | static inline struct page *kmap_atomic_to_page(void *ptr) |
| 139 | { | 89 | { |
| 140 | unsigned long idx, vaddr = (unsigned long) ptr; | 90 | unsigned long idx, vaddr = (unsigned long) ptr; |
| @@ -148,6 +98,7 @@ static inline struct page *kmap_atomic_to_page(void *ptr) · 7 unmodified lines | |||
| 148 | return pte_page(*pte); | 98 | return pte_page(*pte); |
| 149 | } | 99 | } |
| 150 | 100 | ||
| 101 | |||
| 151 | #define flush_cache_kmaps() flush_cache_all() | 102 | #define flush_cache_kmaps() flush_cache_all() |
| 152 | 103 | ||
| 153 | #endif /* __KERNEL__ */ | 104 | #endif /* __KERNEL__ */ |
| @@ -68,13 +68,13 @@ static inline int irqs_disabled_flags(unsigned long flags) · 67 unmodified lines | |||
| 68 | 68 | ||
| 69 | #if defined(CONFIG_BOOKE) | 69 | #if defined(CONFIG_BOOKE) |
| 70 | #define SET_MSR_EE(x) mtmsr(x) | 70 | #define SET_MSR_EE(x) mtmsr(x) |
| 71 | #define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory") | 71 | #define raw_local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory") |
| 72 | #else | 72 | #else |
| 73 | #define SET_MSR_EE(x) mtmsr(x) | 73 | #define SET_MSR_EE(x) mtmsr(x) |
| 74 | #define local_irq_restore(flags) mtmsr(flags) | 74 | #define raw_local_irq_restore(flags) mtmsr(flags) |
| 75 | #endif | 75 | #endif |
| 76 | 76 | ||
| 77 | static inline void local_irq_disable(void) | 77 | static inline void raw_local_irq_disable(void) |
| 78 | { | 78 | { |
| 79 | #ifdef CONFIG_BOOKE | 79 | #ifdef CONFIG_BOOKE |
| 80 | __asm__ __volatile__("wrteei 0": : :"memory"); | 80 | __asm__ __volatile__("wrteei 0": : :"memory"); |
| @@ -86,7 +86,7 @@ static inline void local_irq_disable(void) · 5 unmodified lines | |||
| 86 | #endif | 86 | #endif |
| 87 | } | 87 | } |
| 88 | 88 | ||
| 89 | static inline void local_irq_enable(void) | 89 | static inline void raw_local_irq_enable(void) |
| 90 | { | 90 | { |
| 91 | #ifdef CONFIG_BOOKE | 91 | #ifdef CONFIG_BOOKE |
| 92 | __asm__ __volatile__("wrteei 1": : :"memory"); | 92 | __asm__ __volatile__("wrteei 1": : :"memory"); |
| @@ -98,7 +98,7 @@ static inline void local_irq_enable(void) · 5 unmodified lines | |||
| 98 | #endif | 98 | #endif |
| 99 | } | 99 | } |
| 100 | 100 | ||
| 101 | static inline void local_irq_save_ptr(unsigned long *flags) | 101 | static inline void raw_local_irq_save_ptr(unsigned long *flags) |
| 102 | { | 102 | { |
| 103 | unsigned long msr; | 103 | unsigned long msr; |
| 104 | msr = mfmsr(); | 104 | msr = mfmsr(); |
| @@ -110,12 +110,12 @@ static inline void local_irq_save_ptr(unsigned long *flags) · 5 unmodified lines | |||
| 110 | #endif | 110 | #endif |
| 111 | } | 111 | } |
| 112 | 112 | ||
| 113 | #define local_save_flags(flags) ((flags) = mfmsr()) | 113 | #define raw_local_save_flags(flags) ((flags) = mfmsr()) |
| 114 | #define local_irq_save(flags) local_irq_save_ptr(&flags) | 114 | #define raw_local_irq_save(flags) raw_local_irq_save_ptr(&flags) |
| 115 | #define irqs_disabled() ((mfmsr() & MSR_EE) == 0) | 115 | #define raw_irqs_disabled() ((mfmsr() & MSR_EE) == 0) |
| 116 | #define raw_irqs_disabled_flags(flags) (((flags) & MSR_EE) == 0) | ||
| 116 | 117 | ||
| 117 | #define hard_irq_enable() local_irq_enable() | 118 | #define hard_irq_disable() raw_local_irq_disable() |
| 118 | #define hard_irq_disable() local_irq_disable() | ||
| 119 | 119 | ||
| 120 | static inline int irqs_disabled_flags(unsigned long flags) | 120 | static inline int irqs_disabled_flags(unsigned long flags) |
| 121 | { | 121 | { |
| @@ -61,6 +61,8 @@ struct pt_regs; · 60 unmodified lines | |||
| 61 | extern unsigned long perf_misc_flags(struct pt_regs *regs); | 61 | extern unsigned long perf_misc_flags(struct pt_regs *regs); |
| 62 | extern unsigned long perf_instruction_pointer(struct pt_regs *regs); | 62 | extern unsigned long perf_instruction_pointer(struct pt_regs *regs); |
| 63 | 63 | ||
| 64 | #define PERF_COUNTER_INDEX_OFFSET 1 | ||
| 65 | |||
| 64 | /* | 66 | /* |
| 65 | * Only override the default definitions in include/linux/perf_counter.h | 67 | * Only override the default definitions in include/linux/perf_counter.h |
| 66 | * if we have hardware PMU support. | 68 | * if we have hardware PMU support. |
| @@ -47,7 +47,8 @@ · 46 unmodified lines | |||
| 47 | * generic accessors and iterators here | 47 | * generic accessors and iterators here |
| 48 | */ | 48 | */ |
| 49 | #define __real_pte(e,p) ((real_pte_t) { \ | 49 | #define __real_pte(e,p) ((real_pte_t) { \ |
| 50 | (e), pte_val(*((p) + PTRS_PER_PTE)) }) | 50 | (e), ((e) & _PAGE_COMBO) ? \ |
| 51 | (pte_val(*((p) + PTRS_PER_PTE))) : 0 }) | ||
| 51 | #define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \ | 52 | #define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \ |
| 52 | (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf)) | 53 | (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf)) |
| 53 | #define __rpte_to_pte(r) ((r).pte) | 54 | #define __rpte_to_pte(r) ((r).pte) |
| @@ -58,7 +58,7 @@ struct rtas_t { · 57 unmodified lines | |||
| 58 | unsigned long entry; /* physical address pointer */ | 58 | unsigned long entry; /* physical address pointer */ |
| 59 | unsigned long base; /* physical address pointer */ | 59 | unsigned long base; /* physical address pointer */ |
| 60 | unsigned long size; | 60 | unsigned long size; |
| 61 | spinlock_t lock; | 61 | raw_spinlock_t lock; |
| 62 | struct rtas_args args; | 62 | struct rtas_args args; |
| 63 | struct device_node *dev; /* virtual address pointer */ | 63 | struct device_node *dev; /* virtual address pointer */ |
| 64 | }; | 64 | }; |
| @@ -245,5 +245,8 @@ static inline u32 rtas_config_addr(int busno, int devfn, int reg) · 180 unmodified lines | |||
| 245 | (devfn << 8) | (reg & 0xff); | 245 | (devfn << 8) | (reg & 0xff); |
| 246 | } | 246 | } |
| 247 | 247 | ||
| 248 | extern void __cpuinit rtas_give_timebase(void); | ||
| 249 | extern void __cpuinit rtas_take_timebase(void); | ||
| 250 | |||
| 248 | #endif /* __KERNEL__ */ | 251 | #endif /* __KERNEL__ */ |
| 249 | #endif /* _POWERPC_RTAS_H */ | 252 | #endif /* _POWERPC_RTAS_H */ |
| @@ -191,11 +191,49 @@ transfer_to_handler_cont: · 190 unmodified lines | |||
| 191 | mflr r9 | 191 | mflr r9 |
| 192 | lwz r11,0(r9) /* virtual address of handler */ | 192 | lwz r11,0(r9) /* virtual address of handler */ |
| 193 | lwz r9,4(r9) /* where to go when done */ | 193 | lwz r9,4(r9) /* where to go when done */ |
| 194 | #ifdef CONFIG_TRACE_IRQFLAGS | ||
| 195 | lis r12,reenable_mmu@h | ||
| 196 | ori r12,r12,reenable_mmu@l | ||
| 197 | mtspr SPRN_SRR0,r12 | ||
| 198 | mtspr SPRN_SRR1,r10 | ||
| 199 | SYNC | ||
| 200 | RFI | ||
| 201 | reenable_mmu: /* re-enable mmu so we can */ | ||
| 202 | mfmsr r10 | ||
| 203 | lwz r12,_MSR(r1) | ||
| 204 | xor r10,r10,r12 | ||
| 205 | andi. r10,r10,MSR_EE /* Did EE change? */ | ||
| 206 | beq 1f | ||
| 207 | |||
| 208 | /* Save handler and return address into the 2 unused words | ||
| 209 | * of the STACK_FRAME_OVERHEAD (sneak sneak sneak). Everything | ||
| 210 | * else can be recovered from the pt_regs except r3 which for | ||
| 211 | * normal interrupts has been set to pt_regs and for syscalls | ||
| 212 | * is an argument, so we temporarily use ORIG_GPR3 to save it | ||
| 213 | */ | ||
| 214 | stw r9,8(r1) | ||
| 215 | stw r11,12(r1) | ||
| 216 | stw r3,ORIG_GPR3(r1) | ||
| 217 | bl trace_hardirqs_off | ||
| 218 | lwz r0,GPR0(r1) | ||
| 219 | lwz r3,ORIG_GPR3(r1) | ||
| 220 | lwz r4,GPR4(r1) | ||
| 221 | lwz r5,GPR5(r1) | ||
| 222 | lwz r6,GPR6(r1) | ||
| 223 | lwz r7,GPR7(r1) | ||
| 224 | lwz r8,GPR8(r1) | ||
| 225 | lwz r9,8(r1) | ||
| 226 | lwz r11,12(r1) | ||
| 227 | 1: mtctr r11 | ||
| 228 | mtlr r9 | ||
| 229 | bctr /* jump to handler */ | ||
| 230 | #else /* CONFIG_TRACE_IRQFLAGS */ | ||
| 194 | mtspr SPRN_SRR0,r11 | 231 | mtspr SPRN_SRR0,r11 |
| 195 | mtspr SPRN_SRR1,r10 | 232 | mtspr SPRN_SRR1,r10 |
| 196 | mtlr r9 | 233 | mtlr r9 |
| 197 | SYNC | 234 | SYNC |
| 198 | RFI /* jump to handler, enable MMU */ | 235 | RFI /* jump to handler, enable MMU */ |
| 236 | #endif /* CONFIG_TRACE_IRQFLAGS */ | ||
| 199 | 237 | ||
| 200 | #if defined (CONFIG_6xx) || defined(CONFIG_E500) | 238 | #if defined (CONFIG_6xx) || defined(CONFIG_E500) |
| 201 | 4: rlwinm r12,r12,0,~_TLF_NAPPING | 239 | 4: rlwinm r12,r12,0,~_TLF_NAPPING |
| @@ -251,6 +289,31 @@ _GLOBAL(DoSyscall) · 49 unmodified lines | |||
| 251 | #ifdef SHOW_SYSCALLS | 289 | #ifdef SHOW_SYSCALLS |
| 252 | bl do_show_syscall | 290 | bl do_show_syscall |
| 253 | #endif /* SHOW_SYSCALLS */ | 291 | #endif /* SHOW_SYSCALLS */ |
| 292 | #ifdef CONFIG_TRACE_IRQFLAGS | ||
| 293 | /* Return from syscalls can (and generally will) hard enable | ||
| 294 | * interrupts. You aren't supposed to call a syscall with | ||
| 295 | * interrupts disabled in the first place. However, to ensure | ||
| 296 | * that we get it right vs. lockdep if it happens, we force | ||
| 297 | * that hard enable here with appropriate tracing if we see | ||
| 298 | * that we have been called with interrupts off | ||
| 299 | */ | ||
| 300 | mfmsr r11 | ||
| 301 | andi. r12,r11,MSR_EE | ||
| 302 | bne+ 1f | ||
| 303 | /* We came in with interrupts disabled, we enable them now */ | ||
| 304 | bl trace_hardirqs_on | ||
| 305 | mfmsr r11 | ||
| 306 | lwz r0,GPR0(r1) | ||
| 307 | lwz r3,GPR3(r1) | ||
| 308 | lwz r4,GPR4(r1) | ||
| 309 | ori r11,r11,MSR_EE | ||
| 310 | lwz r5,GPR5(r1) | ||
| 311 | lwz r6,GPR6(r1) | ||
| 312 | lwz r7,GPR7(r1) | ||
| 313 | lwz r8,GPR8(r1) | ||
| 314 | mtmsr r11 | ||
| 315 | 1: | ||
| 316 | #endif /* CONFIG_TRACE_IRQFLAGS */ | ||
| 254 | rlwinm r10,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ | 317 | rlwinm r10,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ |
| 255 | lwz r11,TI_FLAGS(r10) | 318 | lwz r11,TI_FLAGS(r10) |
| 256 | andi. r11,r11,_TIF_SYSCALL_T_OR_A | 319 | andi. r11,r11,_TIF_SYSCALL_T_OR_A |
| @@ -275,6 +338,7 @@ ret_from_syscall: · 18 unmodified lines | |||
| 275 | rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ | 338 | rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ |
| 276 | /* disable interrupts so current_thread_info()->flags can't change */ | 339 | /* disable interrupts so current_thread_info()->flags can't change */ |
| 277 | LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */ | 340 | LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */ |
| 341 | /* Note: We don't bother telling lockdep about it */ | ||
| 278 | SYNC | 342 | SYNC |
| 279 | MTMSRD(r10) | 343 | MTMSRD(r10) |
| 280 | lwz r9,TI_FLAGS(r12) | 344 | lwz r9,TI_FLAGS(r12) |
| @@ -288,6 +352,19 @@ ret_from_syscall: · 7 unmodified lines | |||
| 288 | oris r11,r11,0x1000 /* Set SO bit in CR */ | 352 | oris r11,r11,0x1000 /* Set SO bit in CR */ |
| 289 | stw r11,_CCR(r1) | 353 | stw r11,_CCR(r1) |
| 290 | syscall_exit_cont: | 354 | syscall_exit_cont: |
| 355 | lwz r8,_MSR(r1) | ||
| 356 | #ifdef CONFIG_TRACE_IRQFLAGS | ||
| 357 | /* If we are going to return from the syscall with interrupts | ||
| 358 | * off, we trace that here. It shouldn't happen though but we | ||
| 359 | * want to catch the bugger if it does right ? | ||
| 360 | */ | ||
| 361 | andi. r10,r8,MSR_EE | ||
| 362 | bne+ 1f | ||
| 363 | stw r3,GPR3(r1) | ||
| 364 | bl trace_hardirqs_off | ||
| 365 | lwz r3,GPR3(r1) | ||
| 366 | 1: | ||
| 367 | #endif /* CONFIG_TRACE_IRQFLAGS */ | ||
| 291 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | 368 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) |
| 292 | /* If the process has its own DBCR0 value, load it up. The internal | 369 | /* If the process has its own DBCR0 value, load it up. The internal |
| 293 | debug mode bit tells us that dbcr0 should be loaded. */ | 370 | debug mode bit tells us that dbcr0 should be loaded. */ |
| @@ -311,7 +388,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) · 17 unmodified lines | |||
| 311 | mtlr r4 | 388 | mtlr r4 |
| 312 | mtcr r5 | 389 | mtcr r5 |
| 313 | lwz r7,_NIP(r1) | 390 | lwz r7,_NIP(r1) |
| 314 | lwz r8,_MSR(r1) | ||
| 315 | FIX_SRR1(r8, r0) | 391 | FIX_SRR1(r8, r0) |
| 316 | lwz r2,GPR2(r1) | 392 | lwz r2,GPR2(r1) |
| 317 | lwz r1,GPR1(r1) | 393 | lwz r1,GPR1(r1) |
| @@ -394,7 +470,9 @@ syscall_exit_work: · 76 unmodified lines | |||
| 394 | andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) | 470 | andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) |
| 395 | beq ret_from_except | 471 | beq ret_from_except |
| 396 | 472 | ||
| 397 | /* Re-enable interrupts */ | 473 | /* Re-enable interrupts. There is no need to trace that with |
| 474 | * lockdep as we are supposed to have IRQs on at this point | ||
| 475 | */ | ||
| 398 | ori r10,r10,MSR_EE | 476 | ori r10,r10,MSR_EE |
| 399 | SYNC | 477 | SYNC |
| 400 | MTMSRD(r10) | 478 | MTMSRD(r10) |
| @@ -705,6 +783,7 @@ ret_from_except: · 304 unmodified lines | |||
| 705 | /* Hard-disable interrupts so that current_thread_info()->flags | 783 | /* Hard-disable interrupts so that current_thread_info()->flags |
| 706 | * can't change between when we test it and when we return | 784 | * can't change between when we test it and when we return |
| 707 | * from the interrupt. */ | 785 | * from the interrupt. */ |
| 786 | /* Note: We don't bother telling lockdep about it */ | ||
| 708 | LOAD_MSR_KERNEL(r10,MSR_KERNEL) | 787 | LOAD_MSR_KERNEL(r10,MSR_KERNEL) |
| 709 | SYNC /* Some chip revs have problems here... */ | 788 | SYNC /* Some chip revs have problems here... */ |
| 710 | MTMSRD(r10) /* disable interrupts */ | 789 | MTMSRD(r10) /* disable interrupts */ |
| @@ -744,11 +823,24 @@ resume_kernel: · 33 unmodified lines | |||
| 744 | beq+ restore | 823 | beq+ restore |
| 745 | andi. r0,r3,MSR_EE /* interrupts off? */ | 824 | andi. r0,r3,MSR_EE /* interrupts off? */ |
| 746 | beq restore /* don't schedule if so */ | 825 | beq restore /* don't schedule if so */ |
| 826 | #ifdef CONFIG_TRACE_IRQFLAGS | ||
| 827 | /* Lockdep thinks irqs are enabled, we need to call | ||
| 828 | * preempt_schedule_irq with IRQs off, so we inform lockdep | ||
| 829 | * now that we -did- turn them off already | ||
| 830 | */ | ||
| 831 | bl trace_hardirqs_off | ||
| 832 | #endif | ||
| 747 | 1: bl preempt_schedule_irq | 833 | 1: bl preempt_schedule_irq |
| 748 | rlwinm r9,r1,0,0,(31-THREAD_SHIFT) | 834 | rlwinm r9,r1,0,0,(31-THREAD_SHIFT) |
| 749 | lwz r3,TI_FLAGS(r9) | 835 | lwz r3,TI_FLAGS(r9) |
| 750 | andi. r0,r3,_TIF_NEED_RESCHED | 836 | andi. r0,r3,_TIF_NEED_RESCHED |
| 751 | bne- 1b | 837 | bne- 1b |
| 838 | #ifdef CONFIG_TRACE_IRQFLAGS | ||
| 839 | /* And now, to properly rebalance the above, we tell lockdep they | ||
| 840 | * are being turned back on, which will happen when we return | ||
| 841 | */ | ||
| 842 | bl trace_hardirqs_on | ||
| 843 | #endif | ||
| 752 | #else | 844 | #else |
| 753 | resume_kernel: | 845 | resume_kernel: |
| 754 | #endif /* CONFIG_PREEMPT */ | 846 | #endif /* CONFIG_PREEMPT */ |
| @@ -765,6 +857,28 @@ restore: · 10 unmodified lines | |||
| 765 | stw r6,icache_44x_need_flush@l(r4) | 857 | stw r6,icache_44x_need_flush@l(r4) |
| 766 | 1: | 858 | 1: |
| 767 | #endif /* CONFIG_44x */ | 859 | #endif /* CONFIG_44x */ |
| 860 | |||
| 861 | lwz r9,_MSR(r1) | ||
| 862 | #ifdef CONFIG_TRACE_IRQFLAGS | ||
| 863 | /* Lockdep doesn't know about the fact that IRQs are temporarily turned | ||
| 864 | * off in this assembly code while peeking at TI_FLAGS() and such. However | ||
| 865 | * we need to inform it if the exception turned interrupts off, and we | ||
| 866 | * are about to trun them back on. | ||
| 867 | * | ||
| 868 | * The problem here sadly is that we don't know whether the exceptions was | ||
| 869 | * one that turned interrupts off or not. So we always tell lockdep about | ||
| 870 | * turning them on here when we go back to wherever we came from with EE | ||
| 871 | * on, even if that may meen some redudant calls being tracked. Maybe later | ||
| 872 | * we could encode what the exception did somewhere or test the exception | ||
| 873 | * type in the pt_regs but that sounds overkill | ||
| 874 | */ | ||
| 875 | andi. r10,r9,MSR_EE | ||
| 876 | beq 1f | ||
| 877 | bl trace_hardirqs_on | ||
| 878 | lwz r9,_MSR(r1) | ||
| 879 | 1: | ||
| 880 | #endif /* CONFIG_TRACE_IRQFLAGS */ | ||
| 881 | |||
| 768 | lwz r0,GPR0(r1) | 882 | lwz r0,GPR0(r1) |
| 769 | lwz r2,GPR2(r1) | 883 | lwz r2,GPR2(r1) |
| 770 | REST_4GPRS(3, r1) | 884 | REST_4GPRS(3, r1) |
| @@ -782,7 +896,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) · 11 unmodified lines | |||
| 782 | stwcx. r0,0,r1 /* to clear the reservation */ | 896 | stwcx. r0,0,r1 /* to clear the reservation */ |
| 783 | 897 | ||
| 784 | #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) | 898 | #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) |
| 785 | lwz r9,_MSR(r1) | ||
| 786 | andi. r10,r9,MSR_RI /* check if this exception occurred */ | 899 | andi. r10,r9,MSR_RI /* check if this exception occurred */ |
| 787 | beql nonrecoverable /* at a bad place (MSR:RI = 0) */ | 900 | beql nonrecoverable /* at a bad place (MSR:RI = 0) */ |
| 788 | 901 | ||
| @@ -805,7 +918,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) · 16 unmodified lines | |||
| 805 | MTMSRD(r10) /* clear the RI bit */ | 918 | MTMSRD(r10) /* clear the RI bit */ |
| 806 | .globl exc_exit_restart | 919 | .globl exc_exit_restart |
| 807 | exc_exit_restart: | 920 | exc_exit_restart: |
| 808 | lwz r9,_MSR(r1) | ||
| 809 | lwz r12,_NIP(r1) | 921 | lwz r12,_NIP(r1) |
| 810 | FIX_SRR1(r9,r10) | 922 | FIX_SRR1(r9,r10) |
| 811 | mtspr SPRN_SRR0,r12 | 923 | mtspr SPRN_SRR0,r12 |
| @@ -1035,11 +1147,18 @@ do_work: /* r10 contains MSR_KERNEL here */ · 223 unmodified lines | |||
| 1035 | beq do_user_signal | 1147 | beq do_user_signal |
| 1036 | 1148 | ||
| 1037 | do_resched: /* r10 contains MSR_KERNEL here */ | 1149 | do_resched: /* r10 contains MSR_KERNEL here */ |
| 1150 | /* Note: We don't need to inform lockdep that we are enabling | ||
| 1151 | * interrupts here. As far as it knows, they are already enabled | ||
| 1152 | */ | ||
| 1038 | ori r10,r10,MSR_EE | 1153 | ori r10,r10,MSR_EE |
| 1039 | SYNC | 1154 | SYNC |
| 1040 | MTMSRD(r10) /* hard-enable interrupts */ | 1155 | MTMSRD(r10) /* hard-enable interrupts */ |
| 1041 | bl schedule | 1156 | bl schedule |
| 1042 | recheck: | 1157 | recheck: |
| 1158 | /* Note: And we don't tell it we are disabling them again | ||
| 1159 | * neither. Those disable/enable cycles used to peek at | ||
| 1160 | * TI_FLAGS aren't advertised. | ||
| 1161 | */ | ||
| 1043 | LOAD_MSR_KERNEL(r10,MSR_KERNEL) | 1162 | LOAD_MSR_KERNEL(r10,MSR_KERNEL) |
| 1044 | SYNC | 1163 | SYNC |
| 1045 | MTMSRD(r10) /* disable interrupts */ | 1164 | MTMSRD(r10) /* disable interrupts */ |
| @@ -1124,9 +1124,8 @@ mmu_off: · 1123 unmodified lines | |||
| 1124 | RFI | 1124 | RFI |
| 1125 | 1125 | ||
| 1126 | /* | 1126 | /* |
| 1127 | * Use the first pair of BAT registers to map the 1st 16MB | 1127 | * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET |
| 1128 | * of RAM to PAGE_OFFSET. From this point on we can't safely | 1128 | * (we keep one for debugging) and on others, we use one 256M BAT. |
| 1129 | * call OF any more. | ||
| 1130 | */ | 1129 | */ |
| 1131 | initial_bats: | 1130 | initial_bats: |
| 1132 | lis r11,PAGE_OFFSET@h | 1131 | lis r11,PAGE_OFFSET@h |
| @@ -1136,12 +1135,16 @@ initial_bats: · 3 unmodified lines | |||
| 1136 | bne 4f | 1135 | bne 4f |
| 1137 | ori r11,r11,4 /* set up BAT registers for 601 */ | 1136 | ori r11,r11,4 /* set up BAT registers for 601 */ |
| 1138 | li r8,0x7f /* valid, block length = 8MB */ | 1137 | li r8,0x7f /* valid, block length = 8MB */ |
| 1139 | oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */ | ||
| 1140 | oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */ | ||
| 1141 | mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */ | 1138 | mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */ |
| 1142 | mtspr SPRN_IBAT0L,r8 /* lower BAT register */ | 1139 | mtspr SPRN_IBAT0L,r8 /* lower BAT register */ |
| 1143 | mtspr SPRN_IBAT1U,r9 | 1140 | addis r11,r11,0x800000@h |
| 1144 | mtspr SPRN_IBAT1L,r10 | 1141 | addis r8,r8,0x800000@h |
| 1142 | mtspr SPRN_IBAT1U,r11 | ||
| 1143 | mtspr SPRN_IBAT1L,r8 | ||
| 1144 | addis r11,r11,0x800000@h | ||
| 1145 | addis r8,r8,0x800000@h | ||
| 1146 | mtspr SPRN_IBAT2U,r11 | ||
| 1147 | mtspr SPRN_IBAT2L,r8 | ||
| 1145 | isync | 1148 | isync |
| 1146 | blr | 1149 | blr |
| 1147 | 1150 | ||
| @@ -76,7 +76,7 @@ struct of_device *of_device_alloc(struct device_node *np, · 75 unmodified lines | |||
| 76 | dev->dev.archdata.of_node = np; | 76 | dev->dev.archdata.of_node = np; |
| 77 | 77 | ||
| 78 | if (bus_id) | 78 | if (bus_id) |
| 79 | dev_set_name(&dev->dev, bus_id); | 79 | dev_set_name(&dev->dev, "%s", bus_id); |
| 80 | else | 80 | else |
| 81 | of_device_make_bus_id(dev); | 81 | of_device_make_bus_id(dev); |
| 82 | 82 | ||
| @@ -528,7 +528,7 @@ void show_regs(struct pt_regs * regs) · 527 unmodified lines | |||
| 528 | 528 | ||
| 529 | for (i = 0; i < 32; i++) { | 529 | for (i = 0; i < 32; i++) { |
| 530 | if ((i % REGS_PER_LINE) == 0) | 530 | if ((i % REGS_PER_LINE) == 0) |
| 531 | printk("\n" KERN_INFO "GPR%02d: ", i); | 531 | printk("\nGPR%02d: ", i); |
| 532 | printk(REG " ", regs->gpr[i]); | 532 | printk(REG " ", regs->gpr[i]); |
| 533 | if (i == LAST_VOLATILE && !FULL_REGS(regs)) | 533 | if (i == LAST_VOLATILE && !FULL_REGS(regs)) |
| 534 | break; | 534 | break; |
| @@ -38,9 +38,10 @@ · 37 unmodified lines | |||
| 38 | #include <asm/syscalls.h> | 38 | #include <asm/syscalls.h> |
| 39 | #include <asm/smp.h> | 39 | #include <asm/smp.h> |
| 40 | #include <asm/atomic.h> | 40 | #include <asm/atomic.h> |
| 41 | #include <asm/time.h> | ||
| 41 | 42 | ||
| 42 | struct rtas_t rtas = { | 43 | struct rtas_t rtas = { |
| 43 | .lock = SPIN_LOCK_UNLOCKED | 44 | .lock = __RAW_SPIN_LOCK_UNLOCKED |
| 44 | }; | 45 | }; |
| 45 | EXPORT_SYMBOL(rtas); | 46 | EXPORT_SYMBOL(rtas); |
| 46 | 47 | ||
| @@ -67,6 +68,28 @@ unsigned long rtas_rmo_buf; · 20 unmodified lines | |||
| 67 | void (*rtas_flash_term_hook)(int); | 68 | void (*rtas_flash_term_hook)(int); |
| 68 | EXPORT_SYMBOL(rtas_flash_term_hook); | 69 | EXPORT_SYMBOL(rtas_flash_term_hook); |
| 69 | 70 | ||
| 71 | /* RTAS use home made raw locking instead of spin_lock_irqsave | ||
| 72 | * because those can be called from within really nasty contexts | ||
| 73 | * such as having the timebase stopped which would lockup with | ||
| 74 | * normal locks and spinlock debugging enabled | ||
| 75 | */ | ||
| 76 | static unsigned long lock_rtas(void) | ||
| 77 | { | ||
| 78 | unsigned long flags; | ||
| 79 | |||
| 80 | local_irq_save(flags); | ||
| 81 | preempt_disable(); | ||
| 82 | __raw_spin_lock_flags(&rtas.lock, flags); | ||
| 83 | return flags; | ||
| 84 | } | ||
| 85 | |||
| 86 | static void unlock_rtas(unsigned long flags) | ||
| 87 | { | ||
| 88 | __raw_spin_unlock(&rtas.lock); | ||
| 89 | local_irq_restore(flags); | ||
| 90 | preempt_enable(); | ||
| 91 | } | ||
| 92 | |||
| 70 | /* | 93 | /* |
| 71 | * call_rtas_display_status and call_rtas_display_status_delay | 94 | * call_rtas_display_status and call_rtas_display_status_delay |
| 72 | * are designed only for very early low-level debugging, which | 95 | * are designed only for very early low-level debugging, which |
| @@ -79,7 +102,7 @@ static void call_rtas_display_status(char c) · 6 unmodified lines | |||
| 79 | 102 | ||
| 80 | if (!rtas.base) | 103 | if (!rtas.base) |
| 81 | return; | 104 | return; |
| 82 | spin_lock_irqsave(&rtas.lock, s); | 105 | s = lock_rtas(); |
| 83 | 106 | ||
| 84 | args->token = 10; | 107 | args->token = 10; |
| 85 | args->nargs = 1; | 108 | args->nargs = 1; |
| @@ -89,7 +112,7 @@ static void call_rtas_display_status(char c) · 3 unmodified lines | |||
| 89 | 112 | ||
| 90 | enter_rtas(__pa(args)); | 113 | enter_rtas(__pa(args)); |
| 91 | 114 | ||
| 92 | spin_unlock_irqrestore(&rtas.lock, s); | 115 | unlock_rtas(s); |
| 93 | } | 116 | } |
| 94 | 117 | ||
| 95 | static void call_rtas_display_status_delay(char c) | 118 | static void call_rtas_display_status_delay(char c) |
| @@ -411,8 +434,7 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...) · 315 unmodified lines | |||
| 411 | if (!rtas.entry || token == RTAS_UNKNOWN_SERVICE) | 434 | if (!rtas.entry || token == RTAS_UNKNOWN_SERVICE) |
| 412 | return -1; | 435 | return -1; |
| 413 | 436 | ||
| 414 | /* Gotta do something different here, use global lock for now... */ | 437 | s = lock_rtas(); |
| 415 | spin_lock_irqsave(&rtas.lock, s); | ||
| 416 | rtas_args = &rtas.args; | 438 | rtas_args = &rtas.args; |
| 417 | 439 | ||
| 418 | rtas_args->token = token; | 440 | rtas_args->token = token; |
| @@ -439,8 +461,7 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...) · 20 unmodified lines | |||
| 439 | outputs[i] = rtas_args->rets[i+1]; | 461 | outputs[i] = rtas_args->rets[i+1]; |
| 440 | ret = (nret > 0)? rtas_args->rets[0]: 0; | 462 | ret = (nret > 0)? rtas_args->rets[0]: 0; |
| 441 | 463 | ||
| 442 | /* Gotta do something different here, use global lock for now... */ | 464 | unlock_rtas(s); |
| 443 | spin_unlock_irqrestore(&rtas.lock, s); | ||
| 444 | 465 | ||
| 445 | if (buff_copy) { | 466 | if (buff_copy) { |
| 446 | log_error(buff_copy, ERR_TYPE_RTAS_LOG, 0); | 467 | log_error(buff_copy, ERR_TYPE_RTAS_LOG, 0); |
| @@ -837,7 +858,7 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs) · 390 unmodified lines | |||
| 837 | 858 | ||
| 838 | buff_copy = get_errorlog_buffer(); | 859 | buff_copy = get_errorlog_buffer(); |
| 839 | 860 | ||
| 840 | spin_lock_irqsave(&rtas.lock, flags); | 861 | flags = lock_rtas(); |
| 841 | 862 | ||
| 842 | rtas.args = args; | 863 | rtas.args = args; |
| 843 | enter_rtas(__pa(&rtas.args)); | 864 | enter_rtas(__pa(&rtas.args)); |
| @@ -848,7 +869,7 @@ asmlinkage int ppc_rtas(struct rtas_args __user *uargs) · 4 unmodified lines | |||
| 848 | if (args.rets[0] == -1) | 869 | if (args.rets[0] == -1) |
| 849 | errbuf = __fetch_rtas_last_error(buff_copy); | 870 | errbuf = __fetch_rtas_last_error(buff_copy); |
| 850 | 871 | ||
| 851 | spin_unlock_irqrestore(&rtas.lock, flags); | 872 | unlock_rtas(flags); |
| 852 | 873 | ||
| 853 | if (buff_copy) { | 874 | if (buff_copy) { |
| 854 | if (errbuf) | 875 | if (errbuf) |
| @@ -951,3 +972,33 @@ int __init early_init_dt_scan_rtas(unsigned long node, · 96 unmodified lines | |||
| 951 | /* break now */ | 972 | /* break now */ |
| 952 | return 1; | 973 | return 1; |
| 953 | } | 974 | } |
| 975 | |||
| 976 | static raw_spinlock_t timebase_lock; | ||
| 977 | static u64 timebase = 0; | ||
| 978 | |||
| 979 | void __cpuinit rtas_give_timebase(void) | ||
| 980 | { | ||
| 981 | unsigned long flags; | ||
| 982 | |||
| 983 | local_irq_save(flags); | ||
| 984 | hard_irq_disable(); | ||
| 985 | __raw_spin_lock(&timebase_lock); | ||
| 986 | rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); | ||
| 987 | timebase = get_tb(); | ||
| 988 | __raw_spin_unlock(&timebase_lock); | ||
| 989 | |||
| 990 | while (timebase) | ||
| 991 | barrier(); | ||
| 992 | rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); | ||
| 993 | local_irq_restore(flags); | ||
| 994 | } | ||
| 995 | |||
| 996 | void __cpuinit rtas_take_timebase(void) | ||
| 997 | { | ||
| 998 | while (!timebase) | ||
| 999 | barrier(); | ||
| 1000 | __raw_spin_lock(&timebase_lock); | ||
| 1001 | set_tb(timebase >> 32, timebase & 0xffffffff); | ||
| 1002 | timebase = 0; | ||
| 1003 | __raw_spin_unlock(&timebase_lock); | ||
| 1004 | } | ||
| @@ -119,6 +119,8 @@ notrace unsigned long __init early_init(unsigned long dt_ptr) · 118 unmodified lines | |||
| 119 | */ | 119 | */ |
| 120 | notrace void __init machine_init(unsigned long dt_ptr) | 120 | notrace void __init machine_init(unsigned long dt_ptr) |
| 121 | { | 121 | { |
| 122 | lockdep_init(); | ||
| 123 | |||
| 122 | /* Enable early debugging if any specified (see udbg.h) */ | 124 | /* Enable early debugging if any specified (see udbg.h) */ |
| 123 | udbg_early_init(); | 125 | udbg_early_init(); |
| 124 | 126 | ||
| @@ -68,7 +68,8 @@ EXPORT_PER_CPU_SYMBOL(cpu_core_map); · 67 unmodified lines | |||
| 68 | /* SMP operations for this machine */ | 68 | /* SMP operations for this machine */ |
| 69 | struct smp_ops_t *smp_ops; | 69 | struct smp_ops_t *smp_ops; |
| 70 | 70 | ||
| 71 | static volatile unsigned int cpu_callin_map[NR_CPUS]; | 71 | /* Can't be static due to PowerMac hackery */ |
| 72 | volatile unsigned int cpu_callin_map[NR_CPUS]; | ||
| 72 | 73 | ||
| 73 | int smt_enabled_at_boot = 1; | 74 | int smt_enabled_at_boot = 1; |
| 74 | 75 | ||
| @@ -219,7 +219,7 @@ void udbg_init_pas_realmode(void) · 218 unmodified lines | |||
| 219 | #ifdef CONFIG_PPC_EARLY_DEBUG_44x | 219 | #ifdef CONFIG_PPC_EARLY_DEBUG_44x |
| 220 | #include <platforms/44x/44x.h> | 220 | #include <platforms/44x/44x.h> |
| 221 | 221 | ||
| 222 | static int udbg_44x_as1_flush(void) | 222 | static void udbg_44x_as1_flush(void) |
| 223 | { | 223 | { |
| 224 | if (udbg_comport) { | 224 | if (udbg_comport) { |
| 225 | while ((as1_readb(&udbg_comport->lsr) & LSR_THRE) == 0) | 225 | while ((as1_readb(&udbg_comport->lsr) & LSR_THRE) == 0) |
| @@ -30,3 +30,4 @@ obj-$(CONFIG_PPC_MM_SLICES) += slice.o · 29 unmodified lines | |||
| 30 | obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o | 30 | obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o |
| 31 | obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o | 31 | obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o |
| 32 | obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o | 32 | obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o |
| 33 | obj-$(CONFIG_HIGHMEM) += highmem.o | ||
| @@ -0,0 +1,77 @@ | |||
| 1 | /* | ||
| 2 | * highmem.c: virtual kernel memory mappings for high memory | ||
| 3 | * | ||
| 4 | * PowerPC version, stolen from the i386 version. | ||
| 5 | * | ||
| 6 | * Used in CONFIG_HIGHMEM systems for memory pages which | ||
| 7 | * are not addressable by direct kernel virtual addresses. | ||
| 8 | * | ||
| 9 | * Copyright (C) 1999 Gerhard Wichert, Siemens AG | ||
| 10 | * Gerhard.Wichert@pdb.siemens.de | ||
| 11 | * | ||
| 12 | * | ||
| 13 | * Redesigned the x86 32-bit VM architecture to deal with | ||
| 14 | * up to 16 Terrabyte physical memory. With current x86 CPUs | ||
| 15 | * we now support up to 64 Gigabytes physical RAM. | ||
| 16 | * | ||
| 17 | * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> | ||
| 18 | * | ||
| 19 | * Reworked for PowerPC by various contributors. Moved from | ||
| 20 | * highmem.h by Benjamin Herrenschmidt (c) 2009 IBM Corp. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/highmem.h> | ||
| 24 | #include <linux/module.h> | ||
| 25 | |||
| 26 | /* | ||
| 27 | * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap | ||
| 28 | * gives a more generic (and caching) interface. But kmap_atomic can | ||
| 29 | * be used in IRQ contexts, so in some (very limited) cases we need | ||
| 30 | * it. | ||
| 31 | */ | ||
| 32 | void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot) | ||
| 33 | { | ||
| 34 | unsigned int idx; | ||
| 35 | unsigned long vaddr; | ||
| 36 | |||
| 37 | /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ | ||
| 38 | pagefault_disable(); | ||
| 39 | if (!PageHighMem(page)) | ||
| 40 | return page_address(page); | ||
| 41 | |||
| 42 | debug_kmap_atomic(type); | ||
| 43 | idx = type + KM_TYPE_NR*smp_processor_id(); | ||
| 44 | vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
| 45 | #ifdef CONFIG_DEBUG_HIGHMEM | ||
| 46 | BUG_ON(!pte_none(*(kmap_pte-idx))); | ||
| 47 | #endif | ||
| 48 | __set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot), 1); | ||
| 49 | local_flush_tlb_page(NULL, vaddr); | ||
| 50 | |||
| 51 | return (void*) vaddr; | ||
| 52 | } | ||
| 53 | EXPORT_SYMBOL(kmap_atomic_prot); | ||
| 54 | |||
| 55 | void kunmap_atomic(void *kvaddr, enum km_type type) | ||
| 56 | { | ||
| 57 | #ifdef CONFIG_DEBUG_HIGHMEM | ||
| 58 | unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; | ||
| 59 | enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); | ||
| 60 | |||
| 61 | if (vaddr < __fix_to_virt(FIX_KMAP_END)) { | ||
| 62 | pagefault_enable(); | ||
| 63 | return; | ||
| 64 | } | ||
| 65 | |||
| 66 | BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); | ||
| 67 | |||
| 68 | /* | ||
| 69 | * force other mappings to Oops if they'll try to access | ||
| 70 | * this pte without first remap it | ||
| 71 | */ | ||
| 72 | pte_clear(&init_mm, vaddr, kmap_pte-idx); | ||
| 73 | local_flush_tlb_page(NULL, vaddr); | ||
| 74 | #endif | ||
| 75 | pagefault_enable(); | ||
| 76 | } | ||
| 77 | EXPORT_SYMBOL(kunmap_atomic); | ||
| @@ -16,6 +16,7 @@ · 15 unmodified lines | |||
| 16 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/delay.h> | 17 | #include <linux/delay.h> |
| 18 | #include <linux/of_gpio.h> | 18 | #include <linux/of_gpio.h> |
| 19 | #include <linux/of_i2c.h> | ||
| 19 | 20 | ||
| 20 | #include <asm/machdep.h> | 21 | #include <asm/machdep.h> |
| 21 | #include <asm/prom.h> | 22 | #include <asm/prom.h> |
| @@ -65,7 +66,6 @@ define_machine(warp) { · 43 unmodified lines | |||
| 65 | 66 | ||
| 66 | static u32 post_info; | 67 | static u32 post_info; |
| 67 | 68 | ||
| 68 | /* I am not sure this is the best place for this... */ | ||
| 69 | static int __init warp_post_info(void) | 69 | static int __init warp_post_info(void) |
| 70 | { | 70 | { |
| 71 | struct device_node *np; | 71 | struct device_node *np; |
| @@ -194,9 +194,9 @@ static int pika_setup_leds(void) · 122 unmodified lines | |||
| 194 | return 0; | 194 | return 0; |
| 195 | } | 195 | } |
| 196 | 196 | ||
| 197 | static void pika_setup_critical_temp(struct i2c_client *client) | 197 | static void pika_setup_critical_temp(struct device_node *np, |
| 198 | struct i2c_client *client) | ||
| 198 | { | 199 | { |
| 199 | struct device_node *np; | ||
| 200 | int irq, rc; | 200 | int irq, rc; |
| 201 | 201 | ||
| 202 | /* Do this before enabling critical temp interrupt since we | 202 | /* Do this before enabling critical temp interrupt since we |
| @@ -208,14 +208,7 @@ static void pika_setup_critical_temp(struct i2c_client *client) · 5 unmodified lines | |||
| 208 | i2c_smbus_write_byte_data(client, 2, 65); /* Thigh */ | 208 | i2c_smbus_write_byte_data(client, 2, 65); /* Thigh */ |
| 209 | i2c_smbus_write_byte_data(client, 3, 0); /* Tlow */ | 209 | i2c_smbus_write_byte_data(client, 3, 0); /* Tlow */ |
| 210 | 210 | ||
| 211 | np = of_find_compatible_node(NULL, NULL, "adi,ad7414"); | ||
| 212 | if (np == NULL) { | ||
| 213 | printk(KERN_ERR __FILE__ ": Unable to find ad7414\n"); | ||
| 214 | return; | ||
| 215 | } | ||
| 216 | |||
| 217 | irq = irq_of_parse_and_map(np, 0); | 211 | irq = irq_of_parse_and_map(np, 0); |
| 218 | of_node_put(np); | ||
| 219 | if (irq == NO_IRQ) { | 212 | if (irq == NO_IRQ) { |
| 220 | printk(KERN_ERR __FILE__ ": Unable to get ad7414 irq\n"); | 213 | printk(KERN_ERR __FILE__ ": Unable to get ad7414 irq\n"); |
| 221 | return; | 214 | return; |
| @@ -244,32 +237,24 @@ static inline void pika_dtm_check_fan(void __iomem *fpga) · 22 unmodified lines | |||
| 244 | 237 | ||
| 245 | static int pika_dtm_thread(void __iomem *fpga) | 238 | static int pika_dtm_thread(void __iomem *fpga) |
| 246 | { | 239 | { |
| 247 | struct i2c_adapter *adap; | 240 | struct device_node *np; |
| 248 | struct i2c_client *client; | 241 | struct i2c_client *client; |
| 249 | 242 | ||
| 250 | /* We loop in case either driver was compiled as a module and | 243 | np = of_find_compatible_node(NULL, NULL, "adi,ad7414"); |
| 251 | * has not been insmoded yet. | 244 | if (np == NULL) |
| 252 | */ | 245 | return -ENOENT; |
| 253 | while (!(adap = i2c_get_adapter(0))) { | ||
| 254 | set_current_state(TASK_INTERRUPTIBLE); | ||
| 255 | schedule_timeout(HZ); | ||
| 256 | } | ||
| 257 | |||
| 258 | while (1) { | ||
| 259 | list_for_each_entry(client, &adap->clients, list) | ||
| 260 | if (client->addr == 0x4a) | ||
| 261 | goto found_it; | ||
| 262 | 246 | ||
| 263 | set_current_state(TASK_INTERRUPTIBLE); | 247 | client = of_find_i2c_device_by_node(np); |
| 264 | schedule_timeout(HZ); | 248 | if (client == NULL) { |
| 249 | of_node_put(np); | ||
| 250 | return -ENOENT; | ||
| 265 | } | 251 | } |
| 266 | 252 | ||
| 267 | found_it: | 253 | pika_setup_critical_temp(np, client); |
| 268 | pika_setup_critical_temp(client); | ||
| 269 | 254 | ||
| 270 | i2c_put_adapter(adap); | 255 | of_node_put(np); |
| 271 | 256 | ||
| 272 | printk(KERN_INFO "PIKA DTM thread running.\n"); | 257 | printk(KERN_INFO "Warp DTM thread running.\n"); |
| 273 | 258 | ||
| 274 | while (!kthread_should_stop()) { | 259 | while (!kthread_should_stop()) { |
| 275 | int val; | 260 | int val; |
| @@ -291,7 +276,6 @@ found_it: · 15 unmodified lines | |||
| 291 | return 0; | 276 | return 0; |
| 292 | } | 277 | } |
| 293 | 278 | ||
| 294 | |||
| 295 | static int __init pika_dtm_start(void) | 279 | static int __init pika_dtm_start(void) |
| 296 | { | 280 | { |
| 297 | struct task_struct *dtm_thread; | 281 | struct task_struct *dtm_thread; |
| @@ -285,6 +285,7 @@ static struct of_device_id mpc85xx_ids[] = { · 284 unmodified lines | |||
| 285 | { .type = "qe", }, | 285 | { .type = "qe", }, |
| 286 | { .compatible = "fsl,qe", }, | 286 | { .compatible = "fsl,qe", }, |
| 287 | { .compatible = "gianfar", }, | 287 | { .compatible = "gianfar", }, |
| 288 | { .compatible = "fsl,rapidio-delta", }, | ||
| 288 | {}, | 289 | {}, |
| 289 | }; | 290 | }; |
| 290 | 291 | ||
| @@ -52,20 +52,19 @@ smp_85xx_kick_cpu(int nr) · 51 unmodified lines | |||
| 52 | 52 | ||
| 53 | pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr); | 53 | pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr); |
| 54 | 54 | ||
| 55 | local_irq_save(flags); | ||
| 56 | |||
| 57 | np = of_get_cpu_node(nr, NULL); | 55 | np = of_get_cpu_node(nr, NULL); |
| 58 | cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL); | 56 | cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL); |
| 59 | 57 | ||
| 60 | if (cpu_rel_addr == NULL) { | 58 | if (cpu_rel_addr == NULL) { |
| 61 | printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr); | 59 | printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr); |
| 62 | local_irq_restore(flags); | ||
| 63 | return; | 60 | return; |
| 64 | } | 61 | } |
| 65 | 62 | ||
| 66 | /* Map the spin table */ | 63 | /* Map the spin table */ |
| 67 | bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY); | 64 | bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY); |
| 68 | 65 | ||
| 66 | local_irq_save(flags); | ||
| 67 | |||
| 69 | out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr); | 68 | out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr); |
| 70 | out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start)); | 69 | out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start)); |
| 71 | 70 | ||
| @@ -73,10 +72,10 @@ smp_85xx_kick_cpu(int nr) · 1 unmodified line | |||
| 73 | while ((__secondary_hold_acknowledge != nr) && (++n < 1000)) | 72 | while ((__secondary_hold_acknowledge != nr) && (++n < 1000)) |
| 74 | mdelay(1); | 73 | mdelay(1); |
| 75 | 74 | ||
| 76 | iounmap(bptr_vaddr); | ||
| 77 | |||
| 78 | local_irq_restore(flags); | 75 | local_irq_restore(flags); |
| 79 | 76 | ||
| 77 | iounmap(bptr_vaddr); | ||
| 78 | |||
| 80 | pr_debug("waited %d msecs for CPU #%d.\n", n, nr); | 79 | pr_debug("waited %d msecs for CPU #%d.\n", n, nr); |
| 81 | } | 80 | } |
| 82 | 81 | ||
| @@ -102,10 +102,11 @@ static struct of_device_id __initdata socrates_of_bus_ids[] = { · 101 unmodified lines | |||
| 102 | {}, | 102 | {}, |
| 103 | }; | 103 | }; |
| 104 | 104 | ||
| 105 | static void __init socrates_init(void) | 105 | static int __init socrates_publish_devices(void) |
| 106 | { | 106 | { |
| 107 | of_platform_bus_probe(NULL, socrates_of_bus_ids, NULL); | 107 | return of_platform_bus_probe(NULL, socrates_of_bus_ids, NULL); |
| 108 | } | 108 | } |
| 109 | machine_device_initcall(socrates, socrates_publish_devices); | ||
| 109 | 110 | ||
| 110 | /* | 111 | /* |
| 111 | * Called very early, device-tree isn't unflattened | 112 | * Called very early, device-tree isn't unflattened |
| @@ -124,7 +125,6 @@ define_machine(socrates) { · 12 unmodified lines | |||
| 124 | .name = "Socrates", | 125 | .name = "Socrates", |
| 125 | .probe = socrates_probe, | 126 | .probe = socrates_probe, |
| 126 | .setup_arch = socrates_setup_arch, | 127 | .setup_arch = socrates_setup_arch, |
| 127 | .init = socrates_init, | ||
| 128 | .init_IRQ = socrates_pic_init, | 128 | .init_IRQ = socrates_pic_init, |
| 129 | .get_irq = mpic_get_irq, | 129 | .get_irq = mpic_get_irq, |
| 130 | .restart = fsl_rstcr_restart, | 130 | .restart = fsl_rstcr_restart, |
| @@ -32,7 +32,6 @@ · 31 unmodified lines | |||
| 32 | 32 | ||
| 33 | #include <sysdev/fsl_soc.h> | 33 | #include <sysdev/fsl_soc.h> |
| 34 | #include <sysdev/fsl_pci.h> | 34 | #include <sysdev/fsl_pci.h> |
| 35 | #include <linux/of_platform.h> | ||
| 36 | 35 | ||
| 37 | /* A few bit definitions needed for fixups on some boards */ | 36 | /* A few bit definitions needed for fixups on some boards */ |
| 38 | #define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */ | 37 | #define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */ |
| @@ -36,7 +36,6 @@ · 35 unmodified lines | |||
| 36 | #include <asm/prom.h> | 36 | #include <asm/prom.h> |
| 37 | #include <asm/smp.h> | 37 | #include <asm/smp.h> |
| 38 | #include <asm/paca.h> | 38 | #include <asm/paca.h> |
| 39 | #include <asm/time.h> | ||
| 40 | #include <asm/machdep.h> | 39 | #include <asm/machdep.h> |
| 41 | #include <asm/cputable.h> | 40 | #include <asm/cputable.h> |
| 42 | #include <asm/firmware.h> | 41 | #include <asm/firmware.h> |
| @@ -140,31 +139,6 @@ static void __devinit smp_cell_setup_cpu(int cpu) · 97 unmodified lines | |||
| 140 | mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); | 139 | mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); |
| 141 | } | 140 | } |
| 142 | 141 | ||
| 143 | static DEFINE_SPINLOCK(timebase_lock); | ||
| 144 | static unsigned long timebase = 0; | ||
| 145 | |||
| 146 | static void __devinit cell_give_timebase(void) | ||
| 147 | { | ||
| 148 | spin_lock(&timebase_lock); | ||
| 149 | rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); | ||
| 150 | timebase = get_tb(); | ||
| 151 | spin_unlock(&timebase_lock); | ||
| 152 | |||
| 153 | while (timebase) | ||
| 154 | barrier(); | ||
| 155 | rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); | ||
| 156 | } | ||
| 157 | |||
| 158 | static void __devinit cell_take_timebase(void) | ||
| 159 | { | ||
| 160 | while (!timebase) | ||
| 161 | barrier(); | ||
| 162 | spin_lock(&timebase_lock); | ||
| 163 | set_tb(timebase >> 32, timebase & 0xffffffff); | ||
| 164 | timebase = 0; | ||
| 165 | spin_unlock(&timebase_lock); | ||
| 166 | } | ||
| 167 | |||
| 168 | static void __devinit smp_cell_kick_cpu(int nr) | 142 | static void __devinit smp_cell_kick_cpu(int nr) |
| 169 | { | 143 | { |
| 170 | BUG_ON(nr < 0 || nr >= NR_CPUS); | 144 | BUG_ON(nr < 0 || nr >= NR_CPUS); |
| @@ -224,8 +198,8 @@ void __init smp_init_cell(void) · 53 unmodified lines | |||
| 224 | 198 | ||
| 225 | /* Non-lpar has additional take/give timebase */ | 199 | /* Non-lpar has additional take/give timebase */ |
| 226 | if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { | 200 | if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { |
| 227 | smp_ops->give_timebase = cell_give_timebase; | 201 | smp_ops->give_timebase = rtas_give_timebase; |
| 228 | smp_ops->take_timebase = cell_take_timebase; | 202 | smp_ops->take_timebase = rtas_take_timebase; |
| 229 | } | 203 | } |
| 230 | 204 | ||
| 231 | DBG(" <- smp_init_cell()\n"); | 205 | DBG(" <- smp_init_cell()\n"); |
| @@ -26,7 +26,6 @@ · 25 unmodified lines | |||
| 26 | #include <asm/io.h> | 26 | #include <asm/io.h> |
| 27 | #include <asm/prom.h> | 27 | #include <asm/prom.h> |
| 28 | #include <asm/smp.h> | 28 | #include <asm/smp.h> |
| 29 | #include <asm/time.h> | ||
| 30 | #include <asm/machdep.h> | 29 | #include <asm/machdep.h> |
| 31 | #include <asm/mpic.h> | 30 | #include <asm/mpic.h> |
| 32 | #include <asm/rtas.h> | 31 | #include <asm/rtas.h> |
| @@ -42,40 +41,12 @@ static void __devinit smp_chrp_setup_cpu(int cpu_nr) · 9 unmodified lines | |||
| 42 | mpic_setup_this_cpu(); | 41 | mpic_setup_this_cpu(); |
| 43 | } | 42 | } |
| 44 | 43 | ||
| 45 | static DEFINE_SPINLOCK(timebase_lock); | ||
| 46 | static unsigned int timebase_upper = 0, timebase_lower = 0; | ||
| 47 | |||
| 48 | void __devinit smp_chrp_give_timebase(void) | ||
| 49 | { | ||
| 50 | spin_lock(&timebase_lock); | ||
| 51 | rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); | ||
| 52 | timebase_upper = get_tbu(); | ||
| 53 | timebase_lower = get_tbl(); | ||
| 54 | spin_unlock(&timebase_lock); | ||
| 55 | |||
| 56 | while (timebase_upper || timebase_lower) | ||
| 57 | barrier(); | ||
| 58 | rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); | ||
| 59 | } | ||
| 60 | |||
| 61 | void __devinit smp_chrp_take_timebase(void) | ||
| 62 | { | ||
| 63 | while (!(timebase_upper || timebase_lower)) | ||
| 64 | barrier(); | ||
| 65 | spin_lock(&timebase_lock); | ||
| 66 | set_tb(timebase_upper, timebase_lower); | ||
| 67 | timebase_upper = 0; | ||
| 68 | timebase_lower = 0; | ||
| 69 | spin_unlock(&timebase_lock); | ||
| 70 | printk("CPU %i taken timebase\n", smp_processor_id()); | ||
| 71 | } | ||
| 72 | |||
| 73 | /* CHRP with openpic */ | 44 | /* CHRP with openpic */ |
| 74 | struct smp_ops_t chrp_smp_ops = { | 45 | struct smp_ops_t chrp_smp_ops = { |
| 75 | .message_pass = smp_mpic_message_pass, | 46 | .message_pass = smp_mpic_message_pass, |
| 76 | .probe = smp_mpic_probe, | 47 | .probe = smp_mpic_probe, |
| 77 | .kick_cpu = smp_chrp_kick_cpu, | 48 | .kick_cpu = smp_chrp_kick_cpu, |
| 78 | .setup_cpu = smp_chrp_setup_cpu, | 49 | .setup_cpu = smp_chrp_setup_cpu, |
| 79 | .give_timebase = smp_chrp_give_timebase, | 50 | .give_timebase = rtas_give_timebase, |
| 80 | .take_timebase = smp_chrp_take_timebase, | 51 | .take_timebase = rtas_take_timebase, |
| 81 | }; | 52 | }; |
| @@ -71,20 +71,25 @@ static void pas_restart(char *cmd) · 70 unmodified lines | |||
| 71 | } | 71 | } |
| 72 | 72 | ||
| 73 | #ifdef CONFIG_SMP | 73 | #ifdef CONFIG_SMP |
| 74 | static DEFINE_SPINLOCK(timebase_lock); | 74 | static raw_spinlock_t timebase_lock; |
| 75 | static unsigned long timebase; | 75 | static unsigned long timebase; |
| 76 | 76 | ||
| 77 | static void __devinit pas_give_timebase(void) | 77 | static void __devinit pas_give_timebase(void) |
| 78 | { | 78 | { |
| 79 | spin_lock(&timebase_lock); | 79 | unsigned long flags; |
| 80 | |||
| 81 | local_irq_save(flags); | ||
| 82 | hard_irq_disable(); | ||
| 83 | __raw_spin_lock(&timebase_lock); | ||
| 80 | mtspr(SPRN_TBCTL, TBCTL_FREEZE); | 84 | mtspr(SPRN_TBCTL, TBCTL_FREEZE); |
| 81 | isync(); | 85 | isync(); |
| 82 | timebase = get_tb(); | 86 | timebase = get_tb(); |
| 83 | spin_unlock(&timebase_lock); | 87 | __raw_spin_unlock(&timebase_lock); |
| 84 | 88 | ||
| 85 | while (timebase) | 89 | while (timebase) |
| 86 | barrier(); | 90 | barrier(); |
| 87 | mtspr(SPRN_TBCTL, TBCTL_RESTART); | 91 | mtspr(SPRN_TBCTL, TBCTL_RESTART); |
| 92 | local_irq_restore(flags); | ||
| 88 | } | 93 | } |
| 89 | 94 | ||
| 90 | static void __devinit pas_take_timebase(void) | 95 | static void __devinit pas_take_timebase(void) |
| @@ -92,10 +97,10 @@ static void __devinit pas_take_timebase(void) · 1 unmodified line | |||
| 92 | while (!timebase) | 97 | while (!timebase) |
| 93 | smp_rmb(); | 98 | smp_rmb(); |
| 94 | 99 | ||
| 95 | spin_lock(&timebase_lock); | 100 | __raw_spin_lock(&timebase_lock); |
| 96 | set_tb(timebase >> 32, timebase & 0xffffffff); | 101 | set_tb(timebase >> 32, timebase & 0xffffffff); |
| 97 | timebase = 0; | 102 | timebase = 0; |
| 98 | spin_unlock(&timebase_lock); | 103 | __raw_spin_unlock(&timebase_lock); |
| 99 | } | 104 | } |
| 100 | 105 | ||
| 101 | struct smp_ops_t pas_smp_ops = { | 106 | struct smp_ops_t pas_smp_ops = { |
| @@ -103,11 +103,6 @@ unsigned long smu_cmdbuf_abs; · 102 unmodified lines | |||
| 103 | EXPORT_SYMBOL(smu_cmdbuf_abs); | 103 | EXPORT_SYMBOL(smu_cmdbuf_abs); |
| 104 | #endif | 104 | #endif |
| 105 | 105 | ||
| 106 | #ifdef CONFIG_SMP | ||
| 107 | extern struct smp_ops_t psurge_smp_ops; | ||
| 108 | extern struct smp_ops_t core99_smp_ops; | ||
| 109 | #endif /* CONFIG_SMP */ | ||
| 110 | |||
| 111 | static void pmac_show_cpuinfo(struct seq_file *m) | 106 | static void pmac_show_cpuinfo(struct seq_file *m) |
| 112 | { | 107 | { |
| 113 | struct device_node *np; | 108 | struct device_node *np; |
| @@ -341,34 +336,6 @@ static void __init pmac_setup_arch(void) · 227 unmodified lines | |||
| 341 | ROOT_DEV = DEFAULT_ROOT_DEVICE; | 336 | ROOT_DEV = DEFAULT_ROOT_DEVICE; |
| 342 | #endif | 337 | #endif |
| 343 | 338 | ||
| 344 | #ifdef CONFIG_SMP | ||
| 345 | /* Check for Core99 */ | ||
| 346 | ic = of_find_node_by_name(NULL, "uni-n"); | ||
| 347 | if (!ic) | ||
| 348 | ic = of_find_node_by_name(NULL, "u3"); | ||
| 349 | if (!ic) | ||
| 350 | ic = of_find_node_by_name(NULL, "u4"); | ||
| 351 | if (ic) { | ||
| 352 | of_node_put(ic); | ||
| 353 | smp_ops = &core99_smp_ops; | ||
| 354 | } | ||
| 355 | #ifdef CONFIG_PPC32 | ||
| 356 | else { | ||
| 357 | /* | ||
| 358 | * We have to set bits in cpu_possible_map here since the | ||
| 359 | * secondary CPU(s) aren't in the device tree, and | ||
| 360 | * setup_per_cpu_areas only allocates per-cpu data for | ||
| 361 | * CPUs in the cpu_possible_map. | ||
| 362 | */ | ||
| 363 | int cpu; | ||
| 364 | |||
| 365 | for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) | ||
| 366 | cpu_set(cpu, cpu_possible_map); | ||
| 367 | smp_ops = &psurge_smp_ops; | ||
| 368 | } | ||
| 369 | #endif | ||
| 370 | #endif /* CONFIG_SMP */ | ||
| 371 | |||
| 372 | #ifdef CONFIG_ADB | 339 | #ifdef CONFIG_ADB |
| 373 | if (strstr(cmd_line, "adb_sync")) { | 340 | if (strstr(cmd_line, "adb_sync")) { |
| 374 | extern int __adb_probe_sync; | 341 | extern int __adb_probe_sync; |
| @@ -512,6 +479,14 @@ static void __init pmac_init_early(void) · 137 unmodified lines | |||
| 512 | #ifdef CONFIG_PPC64 | 479 | #ifdef CONFIG_PPC64 |
| 513 | iommu_init_early_dart(); | 480 | iommu_init_early_dart(); |
| 514 | #endif | 481 | #endif |
| 482 | |||
| 483 | /* SMP Init has to be done early as we need to patch up | ||
| 484 | * cpu_possible_map before interrupt stacks are allocated | ||
| 485 | * or kaboom... | ||
| 486 | */ | ||
| 487 | #ifdef CONFIG_SMP | ||
| 488 | pmac_setup_smp(); | ||
| 489 | #endif | ||
| 515 | } | 490 | } |
| 516 | 491 | ||
| 517 | static int __init pmac_declare_of_platform_devices(void) | 492 | static int __init pmac_declare_of_platform_devices(void) |
| @@ -64,10 +64,11 @@ · 63 unmodified lines | |||
| 64 | extern void __secondary_start_pmac_0(void); | 64 | extern void __secondary_start_pmac_0(void); |
| 65 | extern int pmac_pfunc_base_install(void); | 65 | extern int pmac_pfunc_base_install(void); |
| 66 | 66 | ||
| 67 | #ifdef CONFIG_PPC32 | 67 | static void (*pmac_tb_freeze)(int freeze); |
| 68 | static u64 timebase; | ||
| 69 | static int tb_req; | ||
| 68 | 70 | ||
| 69 | /* Sync flag for HW tb sync */ | 71 | #ifdef CONFIG_PPC32 |
| 70 | static volatile int sec_tb_reset = 0; | ||
| 71 | 72 | ||
| 72 | /* | 73 | /* |
| 73 | * Powersurge (old powermac SMP) support. | 74 | * Powersurge (old powermac SMP) support. |
| @@ -294,6 +295,9 @@ static int __init smp_psurge_probe(void) · 220 unmodified lines | |||
| 294 | psurge_quad_init(); | 295 | psurge_quad_init(); |
| 295 | /* All released cards using this HW design have 4 CPUs */ | 296 | /* All released cards using this HW design have 4 CPUs */ |
| 296 | ncpus = 4; | 297 | ncpus = 4; |
| 298 | /* No sure how timebase sync works on those, let's use SW */ | ||
| 299 | smp_ops->give_timebase = smp_generic_give_timebase; | ||
| 300 | smp_ops->take_timebase = smp_generic_take_timebase; | ||
| 297 | } else { | 301 | } else { |
| 298 | iounmap(quad_base); | 302 | iounmap(quad_base); |
| 299 | if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { | 303 | if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { |
| @@ -308,18 +312,15 @@ static int __init smp_psurge_probe(void) · 8 unmodified lines | |||
| 308 | psurge_start = ioremap(PSURGE_START, 4); | 312 | psurge_start = ioremap(PSURGE_START, 4); |
| 309 | psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); | 313 | psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); |
| 310 | 314 | ||
| 311 | /* | 315 | /* This is necessary because OF doesn't know about the |
| 312 | * This is necessary because OF doesn't know about the | ||
| 313 | * secondary cpu(s), and thus there aren't nodes in the | 316 | * secondary cpu(s), and thus there aren't nodes in the |
| 314 | * device tree for them, and smp_setup_cpu_maps hasn't | 317 | * device tree for them, and smp_setup_cpu_maps hasn't |
| 315 | * set their bits in cpu_possible_map and cpu_present_map. | 318 | * set their bits in cpu_present_map. |
| 316 | */ | 319 | */ |
| 317 | if (ncpus > NR_CPUS) | 320 | if (ncpus > NR_CPUS) |
| 318 | ncpus = NR_CPUS; | 321 | ncpus = NR_CPUS; |
| 319 | for (i = 1; i < ncpus ; ++i) { | 322 | for (i = 1; i < ncpus ; ++i) |
| 320 | cpu_set(i, cpu_present_map); | 323 | cpu_set(i, cpu_present_map); |
| 321 | set_hard_smp_processor_id(i, i); | ||
| 322 | } | ||
| 323 | 324 | ||
| 324 | if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); | 325 | if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); |
| 325 | 326 | ||
| @@ -329,8 +330,14 @@ static int __init smp_psurge_probe(void) · 3 unmodified lines | |||
| 329 | static void __init smp_psurge_kick_cpu(int nr) | 330 | static void __init smp_psurge_kick_cpu(int nr) |
| 330 | { | 331 | { |
| 331 | unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; | 332 | unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; |
| 332 | unsigned long a; | 333 | unsigned long a, flags; |
| 333 | int i; | 334 | int i, j; |
| 335 | |||
| 336 | /* Defining this here is evil ... but I prefer hiding that | ||
| 337 | * crap to avoid giving people ideas that they can do the | ||
| 338 | * same. | ||
| 339 | */ | ||
| 340 | extern volatile unsigned int cpu_callin_map[NR_CPUS]; | ||
| 334 | 341 | ||
| 335 | /* may need to flush here if secondary bats aren't setup */ | 342 | /* may need to flush here if secondary bats aren't setup */ |
| 336 | for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) | 343 | for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) |
| @@ -339,47 +346,52 @@ static void __init smp_psurge_kick_cpu(int nr) · 2 unmodified lines | |||
| 339 | 346 | ||
| 340 | if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); | 347 | if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); |
| 341 | 348 | ||
| 349 | /* This is going to freeze the timeebase, we disable interrupts */ | ||
| 350 | local_irq_save(flags); | ||
| 351 | |||
| 342 | out_be32(psurge_start, start); | 352 | out_be32(psurge_start, start); |
| 343 | mb(); | 353 | mb(); |
| 344 | 354 | ||
| 345 | psurge_set_ipi(nr); | 355 | psurge_set_ipi(nr); |
| 356 | |||
| 346 | /* | 357 | /* |
| 347 | * We can't use udelay here because the timebase is now frozen. | 358 | * We can't use udelay here because the timebase is now frozen. |
| 348 | */ | 359 | */ |
| 349 | for (i = 0; i < 2000; ++i) | 360 | for (i = 0; i < 2000; ++i) |
| 350 | barrier(); | 361 | asm volatile("nop" : : : "memory"); |
| 351 | psurge_clr_ipi(nr); | 362 | psurge_clr_ipi(nr); |
| 352 | 363 | ||
| 353 | if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); | 364 | /* |
| 354 | } | 365 | * Also, because the timebase is frozen, we must not return to the |
| 355 | 366 | * caller which will try to do udelay's etc... Instead, we wait -here- | |
| 356 | /* | 367 | * for the CPU to callin. |
| 357 | * With the dual-cpu powersurge board, the decrementers and timebases | 368 | */ |
| 358 | * of both cpus are frozen after the secondary cpu is started up, | 369 | for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) { |
| 359 | * until we give the secondary cpu another interrupt. This routine | 370 | for (j = 1; j < 10000; j++) |
| 360 | * uses this to get the timebases synchronized. | 371 | asm volatile("nop" : : : "memory"); |
| 361 | * -- paulus. | 372 | asm volatile("sync" : : : "memory"); |
| 362 | */ | 373 | } |
| 363 | static void __init psurge_dual_sync_tb(int cpu_nr) | 374 | if (!cpu_callin_map[nr]) |
| 364 | { | 375 | goto stuck; |
| 365 | int t; | 376 | |
| 366 | 377 | /* And we do the TB sync here too for standard dual CPU cards */ | |
| 367 | set_dec(tb_ticks_per_jiffy); | 378 | if (psurge_type == PSURGE_DUAL) { |
| 368 | /* XXX fixme */ | 379 | while(!tb_req) |
| 369 | set_tb(0, 0); | 380 | barrier(); |
| 370 | 381 | tb_req = 0; | |
| 371 | if (cpu_nr > 0) { | 382 | mb(); |
| 383 | timebase = get_tb(); | ||
| 384 | mb(); | ||
| 385 | while (timebase) | ||
| 386 | barrier(); | ||
| 372 | mb(); | 387 | mb(); |
| 373 | sec_tb_reset = 1; | ||
| 374 | return; | ||
| 375 | } | 388 | } |
| 389 | stuck: | ||
| 390 | /* now interrupt the secondary, restarting both TBs */ | ||
| 391 | if (psurge_type == PSURGE_DUAL) | ||
| 392 | psurge_set_ipi(1); | ||
| 376 | 393 | ||
| 377 | /* wait for the secondary to have reset its TB before proceeding */ | 394 | if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); |
| 378 | for (t = 10000000; t > 0 && !sec_tb_reset; --t) | ||
| 379 | ; | ||
| 380 | |||
| 381 | /* now interrupt the secondary, starting both TBs */ | ||
| 382 | psurge_set_ipi(1); | ||
| 383 | } | 395 | } |
| 384 | 396 | ||
| 385 | static struct irqaction psurge_irqaction = { | 397 | static struct irqaction psurge_irqaction = { |
| @@ -390,36 +402,35 @@ static struct irqaction psurge_irqaction = { · 4 unmodified lines | |||
| 390 | 402 | ||
| 391 | static void __init smp_psurge_setup_cpu(int cpu_nr) | 403 | static void __init smp_psurge_setup_cpu(int cpu_nr) |
| 392 | { | 404 | { |
| 405 | if (cpu_nr != 0) | ||
| 406 | return; | ||
| 393 | 407 | ||
| 394 | if (cpu_nr == 0) { | 408 | /* reset the entry point so if we get another intr we won't |
| 395 | /* If we failed to start the second CPU, we should still | 409 | * try to startup again */ |
| 396 | * send it an IPI to start the timebase & DEC or we might | 410 | out_be32(psurge_start, 0x100); |
| 397 | * have them stuck. | 411 | if (setup_irq(30, &psurge_irqaction)) |
| 398 | */ | 412 | printk(KERN_ERR "Couldn't get primary IPI interrupt"); |
| 399 | if (num_online_cpus() < 2) { | ||
| 400 | if (psurge_type == PSURGE_DUAL) | ||
| 401 | psurge_set_ipi(1); | ||
| 402 | return; | ||
| 403 | } | ||
| 404 | /* reset the entry point so if we get another intr we won't | ||
| 405 | * try to startup again */ | ||
| 406 | out_be32(psurge_start, 0x100); | ||
| 407 | if (setup_irq(30, &psurge_irqaction)) | ||
| 408 | printk(KERN_ERR "Couldn't get primary IPI interrupt"); | ||
| 409 | } | ||
| 410 | |||
| 411 | if (psurge_type == PSURGE_DUAL) | ||
| 412 | psurge_dual_sync_tb(cpu_nr); | ||
| 413 | } | 413 | } |
| 414 | 414 | ||
| 415 | void __init smp_psurge_take_timebase(void) | 415 | void __init smp_psurge_take_timebase(void) |
| 416 | { | 416 | { |
| 417 | /* Dummy implementation */ | 417 | if (psurge_type != PSURGE_DUAL) |
| 418 | return; | ||
| 419 | |||
| 420 | tb_req = 1; | ||
| 421 | mb(); | ||
| 422 | while (!timebase) | ||
| 423 | barrier(); | ||
| 424 | mb(); | ||
| 425 | set_tb(timebase >> 32, timebase & 0xffffffff); | ||
| 426 | timebase = 0; | ||
| 427 | mb(); | ||
| 428 | set_dec(tb_ticks_per_jiffy/2); | ||
| 418 | } | 429 | } |
| 419 | 430 | ||
| 420 | void __init smp_psurge_give_timebase(void) | 431 | void __init smp_psurge_give_timebase(void) |
| 421 | { | 432 | { |
| 422 | /* Dummy implementation */ | 433 | /* Nothing to do here */ |
| 423 | } | 434 | } |
| 424 | 435 | ||
| 425 | /* PowerSurge-style Macs */ | 436 | /* PowerSurge-style Macs */ |
| @@ -437,9 +448,6 @@ struct smp_ops_t psurge_smp_ops = { · 11 unmodified lines | |||
| 437 | * Core 99 and later support | 448 | * Core 99 and later support |
| 438 | */ | 449 | */ |
| 439 | 450 | ||
| 440 | static void (*pmac_tb_freeze)(int freeze); | ||
| 441 | static u64 timebase; | ||
| 442 | static int tb_req; | ||
| 443 | 451 | ||
| 444 | static void smp_core99_give_timebase(void) | 452 | static void smp_core99_give_timebase(void) |
| 445 | { | 453 | { |
| @@ -478,7 +486,6 @@ static void __devinit smp_core99_take_timebase(void) · 32 unmodified lines | |||
| 478 | set_tb(timebase >> 32, timebase & 0xffffffff); | 486 | set_tb(timebase >> 32, timebase & 0xffffffff); |
| 479 | timebase = 0; | 487 | timebase = 0; |
| 480 | mb(); | 488 | mb(); |
| 481 | set_dec(tb_ticks_per_jiffy/2); | ||
| 482 | 489 | ||
| 483 | local_irq_restore(flags); | 490 | local_irq_restore(flags); |
| 484 | } | 491 | } |
| @@ -920,3 +927,34 @@ struct smp_ops_t core99_smp_ops = { · 435 unmodified lines | |||
| 920 | # endif | 927 | # endif |
| 921 | #endif | 928 | #endif |
| 922 | }; | 929 | }; |
| 930 | |||
| 931 | void __init pmac_setup_smp(void) | ||
| 932 | { | ||
| 933 | struct device_node *np; | ||
| 934 | |||
| 935 | /* Check for Core99 */ | ||
| 936 | np = of_find_node_by_name(NULL, "uni-n"); | ||
| 937 | if (!np) | ||
| 938 | np = of_find_node_by_name(NULL, "u3"); | ||
| 939 | if (!np) | ||
| 940 | np = of_find_node_by_name(NULL, "u4"); | ||
| 941 | if (np) { | ||
| 942 | of_node_put(np); | ||
| 943 | smp_ops = &core99_smp_ops; | ||
| 944 | } | ||
| 945 | #ifdef CONFIG_PPC32 | ||
| 946 | else { | ||
| 947 | /* We have to set bits in cpu_possible_map here since the | ||
| 948 | * secondary CPU(s) aren't in the device tree. Various | ||
| 949 | * things won't be initialized for CPUs not in the possible | ||
| 950 | * map, so we really need to fix it up here. | ||
| 951 | */ | ||
| 952 | int cpu; | ||
| 953 | |||
| 954 | for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) | ||
| 955 | cpu_set(cpu, cpu_possible_map); | ||
| 956 | smp_ops = &psurge_smp_ops; | ||
| 957 | } | ||
| 958 | #endif /* CONFIG_PPC32 */ | ||
| 959 | } | ||
| 960 | |||
| @@ -122,7 +122,7 @@ static void eeh_enable_irq(struct pci_dev *dev) · 121 unmodified lines | |||
| 122 | * passed back in "userdata". | 122 | * passed back in "userdata". |
| 123 | */ | 123 | */ |
| 124 | 124 | ||
| 125 | static void eeh_report_error(struct pci_dev *dev, void *userdata) | 125 | static int eeh_report_error(struct pci_dev *dev, void *userdata) |
| 126 | { | 126 | { |
| 127 | enum pci_ers_result rc, *res = userdata; | 127 | enum pci_ers_result rc, *res = userdata; |
| 128 | struct pci_driver *driver = dev->driver; | 128 | struct pci_driver *driver = dev->driver; |
| @@ -130,19 +130,21 @@ static void eeh_report_error(struct pci_dev *dev, void *userdata) · 1 unmodified line | |||
| 130 | dev->error_state = pci_channel_io_frozen; | 130 | dev->error_state = pci_channel_io_frozen; |
| 131 | 131 | ||
| 132 | if (!driver) | 132 | if (!driver) |
| 133 | return; | 133 | return 0; |
| 134 | 134 | ||
| 135 | eeh_disable_irq(dev); | 135 | eeh_disable_irq(dev); |
| 136 | 136 | ||
| 137 | if (!driver->err_handler || | 137 | if (!driver->err_handler || |
| 138 | !driver->err_handler->error_detected) | 138 | !driver->err_handler->error_detected) |
| 139 | return; | 139 | return 0; |
| 140 | 140 | ||
| 141 | rc = driver->err_handler->error_detected (dev, pci_channel_io_frozen); | 141 | rc = driver->err_handler->error_detected (dev, pci_channel_io_frozen); |
| 142 | 142 | ||
| 143 | /* A driver that needs a reset trumps all others */ | 143 | /* A driver that needs a reset trumps all others */ |
| 144 | if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; | 144 | if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; |
| 145 | if (*res == PCI_ERS_RESULT_NONE) *res = rc; | 145 | if (*res == PCI_ERS_RESULT_NONE) *res = rc; |
| 146 | |||
| 147 | return 0; | ||
| 146 | } | 148 | } |
| 147 | 149 | ||
| 148 | /** | 150 | /** |
| @@ -153,7 +155,7 @@ static void eeh_report_error(struct pci_dev *dev, void *userdata) · 4 unmodified lines | |||
| 153 | * Cumulative response passed back in "userdata". | 155 | * Cumulative response passed back in "userdata". |
| 154 | */ | 156 | */ |
| 155 | 157 | ||
| 156 | static void eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) | 158 | static int eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) |
| 157 | { | 159 | { |
| 158 | enum pci_ers_result rc, *res = userdata; | 160 | enum pci_ers_result rc, *res = userdata; |
| 159 | struct pci_driver *driver = dev->driver; | 161 | struct pci_driver *driver = dev->driver; |
| @@ -161,26 +163,28 @@ static void eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata) · 1 unmodified line | |||
| 161 | if (!driver || | 163 | if (!driver || |
| 162 | !driver->err_handler || | 164 | !driver->err_handler || |
| 163 | !driver->err_handler->mmio_enabled) | 165 | !driver->err_handler->mmio_enabled) |
| 164 | return; | 166 | return 0; |
| 165 | 167 | ||
| 166 | rc = driver->err_handler->mmio_enabled (dev); | 168 | rc = driver->err_handler->mmio_enabled (dev); |
| 167 | 169 | ||
| 168 | /* A driver that needs a reset trumps all others */ | 170 | /* A driver that needs a reset trumps all others */ |
| 169 | if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; | 171 | if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; |
| 170 | if (*res == PCI_ERS_RESULT_NONE) *res = rc; | 172 | if (*res == PCI_ERS_RESULT_NONE) *res = rc; |
| 173 | |||
| 174 | return 0; | ||
| 171 | } | 175 | } |
| 172 | 176 | ||
| 173 | /** | 177 | /** |
| 174 | * eeh_report_reset - tell device that slot has been reset | 178 | * eeh_report_reset - tell device that slot has been reset |
| 175 | */ | 179 | */ |
| 176 | 180 | ||
| 177 | static void eeh_report_reset(struct pci_dev *dev, void *userdata) | 181 | static int eeh_report_reset(struct pci_dev *dev, void *userdata) |
| 178 | { | 182 | { |
| 179 | enum pci_ers_result rc, *res = userdata; | 183 | enum pci_ers_result rc, *res = userdata; |
| 180 | struct pci_driver *driver = dev->driver; | 184 | struct pci_driver *driver = dev->driver; |
| 181 | 185 | ||
| 182 | if (!driver) | 186 | if (!driver) |
| 183 | return; | 187 | return 0; |
| 184 | 188 | ||
| 185 | dev->error_state = pci_channel_io_normal; | 189 | dev->error_state = pci_channel_io_normal; |
| 186 | 190 | ||
| @@ -188,35 +192,39 @@ static void eeh_report_reset(struct pci_dev *dev, void *userdata) · 1 unmodified line | |||
| 188 | 192 | ||
| 189 | if (!driver->err_handler || | 193 | if (!driver->err_handler || |
| 190 | !driver->err_handler->slot_reset) | 194 | !driver->err_handler->slot_reset) |
| 191 | return; | 195 | return 0; |
| 192 | 196 | ||
| 193 | rc = driver->err_handler->slot_reset(dev); | 197 | rc = driver->err_handler->slot_reset(dev); |
| 194 | if ((*res == PCI_ERS_RESULT_NONE) || | 198 | if ((*res == PCI_ERS_RESULT_NONE) || |
| 195 | (*res == PCI_ERS_RESULT_RECOVERED)) *res = rc; | 199 | (*res == PCI_ERS_RESULT_RECOVERED)) *res = rc; |
| 196 | if (*res == PCI_ERS_RESULT_DISCONNECT && | 200 | if (*res == PCI_ERS_RESULT_DISCONNECT && |
| 197 | rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; | 201 | rc == PCI_ERS_RESULT_NEED_RESET) *res = rc; |
| 202 | |||
| 203 | return 0; | ||
| 198 | } | 204 | } |
| 199 | 205 | ||
| 200 | /** | 206 | /** |
| 201 | * eeh_report_resume - tell device to resume normal operations | 207 | * eeh_report_resume - tell device to resume normal operations |
| 202 | */ | 208 | */ |
| 203 | 209 | ||
| 204 | static void eeh_report_resume(struct pci_dev *dev, void *userdata) | 210 | static int eeh_report_resume(struct pci_dev *dev, void *userdata) |
| 205 | { | 211 | { |
| 206 | struct pci_driver *driver = dev->driver; | 212 | struct pci_driver *driver = dev->driver; |
| 207 | 213 | ||
| 208 | dev->error_state = pci_channel_io_normal; | 214 | dev->error_state = pci_channel_io_normal; |
| 209 | 215 | ||
| 210 | if (!driver) | 216 | if (!driver) |
| 211 | return; | 217 | return 0; |
| 212 | 218 | ||
| 213 | eeh_enable_irq(dev); | 219 | eeh_enable_irq(dev); |
| 214 | 220 | ||
| 215 | if (!driver->err_handler || | 221 | if (!driver->err_handler || |
| 216 | !driver->err_handler->resume) | 222 | !driver->err_handler->resume) |
| 217 | return; | 223 | return 0; |
| 218 | 224 | ||
| 219 | driver->err_handler->resume(dev); | 225 | driver->err_handler->resume(dev); |
| 226 | |||
| 227 | return 0; | ||
| 220 | } | 228 | } |
| 221 | 229 | ||
| 222 | /** | 230 | /** |
| @@ -226,22 +234,24 @@ static void eeh_report_resume(struct pci_dev *dev, void *userdata) · 3 unmodified lines | |||
| 226 | * dead, and that no further recovery attempts will be made on it. | 234 | * dead, and that no further recovery attempts will be made on it. |
| 227 | */ | 235 | */ |
| 228 | 236 | ||
| 229 | static void eeh_report_failure(struct pci_dev *dev, void *userdata) | 237 | static int eeh_report_failure(struct pci_dev *dev, void *userdata) |
| 230 | { | 238 | { |
| 231 | struct pci_driver *driver = dev->driver; | 239 | struct pci_driver *driver = dev->driver; |
| 232 | 240 | ||
| 233 | dev->error_state = pci_channel_io_perm_failure; | 241 | dev->error_state = pci_channel_io_perm_failure; |
| 234 | 242 | ||
| 235 | if (!driver) | 243 | if (!driver) |
| 236 | return; | 244 | return 0; |
| 237 | 245 | ||
| 238 | eeh_disable_irq(dev); | 246 | eeh_disable_irq(dev); |
| 239 | 247 | ||
| 240 | if (!driver->err_handler || | 248 | if (!driver->err_handler || |
| 241 | !driver->err_handler->error_detected) | 249 | !driver->err_handler->error_detected) |
| 242 | return; | 250 | return 0; |
| 243 | 251 | ||
| 244 | driver->err_handler->error_detected(dev, pci_channel_io_perm_failure); | 252 | driver->err_handler->error_detected(dev, pci_channel_io_perm_failure); |
| 253 | |||
| 254 | return 0; | ||
| 245 | } | 255 | } |
| 246 | 256 | ||
| 247 | /* ------------------------------------------------------- */ | 257 | /* ------------------------------------------------------- */ |
| @@ -35,7 +35,6 @@ · 34 unmodified lines | |||
| 35 | #include <asm/prom.h> | 35 | #include <asm/prom.h> |
| 36 | #include <asm/smp.h> | 36 | #include <asm/smp.h> |
| 37 | #include <asm/paca.h> | 37 | #include <asm/paca.h> |
| 38 | #include <asm/time.h> | ||
| 39 | #include <asm/machdep.h> | 38 | #include <asm/machdep.h> |
| 40 | #include <asm/cputable.h> | 39 | #include <asm/cputable.h> |
| 41 | #include <asm/firmware.h> | 40 | #include <asm/firmware.h> |
| @@ -118,31 +117,6 @@ static void __devinit smp_xics_setup_cpu(int cpu) · 76 unmodified lines | |||
| 118 | } | 117 | } |
| 119 | #endif /* CONFIG_XICS */ | 118 | #endif /* CONFIG_XICS */ |
| 120 | 119 | ||
| 121 | static DEFINE_SPINLOCK(timebase_lock); | ||
| 122 | static unsigned long timebase = 0; | ||
| 123 | |||
| 124 | static void __devinit pSeries_give_timebase(void) | ||
| 125 | { | ||
| 126 | spin_lock(&timebase_lock); | ||
| 127 | rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); | ||
| 128 | timebase = get_tb(); | ||
| 129 | spin_unlock(&timebase_lock); | ||
| 130 | |||
| 131 | while (timebase) | ||
| 132 | barrier(); | ||
| 133 | rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); | ||
| 134 | } | ||
| 135 | |||
| 136 | static void __devinit pSeries_take_timebase(void) | ||
| 137 | { | ||
| 138 | while (!timebase) | ||
| 139 | barrier(); | ||
| 140 | spin_lock(&timebase_lock); | ||
| 141 | set_tb(timebase >> 32, timebase & 0xffffffff); | ||
| 142 | timebase = 0; | ||
| 143 | spin_unlock(&timebase_lock); | ||
| 144 | } | ||
| 145 | |||
| 146 | static void __devinit smp_pSeries_kick_cpu(int nr) | 120 | static void __devinit smp_pSeries_kick_cpu(int nr) |
| 147 | { | 121 | { |
| 148 | BUG_ON(nr < 0 || nr >= NR_CPUS); | 122 | BUG_ON(nr < 0 || nr >= NR_CPUS); |
| @@ -209,8 +183,8 @@ static void __init smp_init_pseries(void) · 60 unmodified lines | |||
| 209 | 183 | ||
| 210 | /* Non-lpar has additional take/give timebase */ | 184 | /* Non-lpar has additional take/give timebase */ |
| 211 | if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { | 185 | if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { |
| 212 | smp_ops->give_timebase = pSeries_give_timebase; | 186 | smp_ops->give_timebase = rtas_give_timebase; |
| 213 | smp_ops->take_timebase = pSeries_take_timebase; | 187 | smp_ops->take_timebase = rtas_take_timebase; |
| 214 | } | 188 | } |
| 215 | 189 | ||
| 216 | pr_debug(" <- smp_init_pSeries()\n"); | 190 | pr_debug(" <- smp_init_pSeries()\n"); |
| @@ -279,28 +279,29 @@ static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, · 278 unmodified lines | |||
| 279 | } | 279 | } |
| 280 | 280 | ||
| 281 | #ifdef CONFIG_PPC_DCR | 281 | #ifdef CONFIG_PPC_DCR |
| 282 | static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, | 282 | static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node, |
| 283 | struct mpic_reg_bank *rb, | ||
| 283 | unsigned int offset, unsigned int size) | 284 | unsigned int offset, unsigned int size) |
| 284 | { | 285 | { |
| 285 | const u32 *dbasep; | 286 | const u32 *dbasep; |
| 286 | 287 | ||
| 287 | dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL); | 288 | dbasep = of_get_property(node, "dcr-reg", NULL); |
| 288 | 289 | ||
| 289 | rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size); | 290 | rb->dhost = dcr_map(node, *dbasep + offset, size); |
| 290 | BUG_ON(!DCR_MAP_OK(rb->dhost)); | 291 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
| 291 | } | 292 | } |
| 292 | 293 | ||
| 293 | static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr, | 294 | static inline void mpic_map(struct mpic *mpic, struct device_node *node, |
| 294 | struct mpic_reg_bank *rb, unsigned int offset, | 295 | phys_addr_t phys_addr, struct mpic_reg_bank *rb, |
| 295 | unsigned int size) | 296 | unsigned int offset, unsigned int size) |
| 296 | { | 297 | { |
| 297 | if (mpic->flags & MPIC_USES_DCR) | 298 | if (mpic->flags & MPIC_USES_DCR) |
| 298 | _mpic_map_dcr(mpic, rb, offset, size); | 299 | _mpic_map_dcr(mpic, node, rb, offset, size); |
| 299 | else | 300 | else |
| 300 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); | 301 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); |
| 301 | } | 302 | } |
| 302 | #else /* CONFIG_PPC_DCR */ | 303 | #else /* CONFIG_PPC_DCR */ |
| 303 | #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) | 304 | #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
| 304 | #endif /* !CONFIG_PPC_DCR */ | 305 | #endif /* !CONFIG_PPC_DCR */ |
| 305 | 306 | ||
| 306 | 307 | ||
| @@ -1052,11 +1053,10 @@ struct mpic * __init mpic_alloc(struct device_node *node, · 745 unmodified lines | |||
| 1052 | int intvec_top; | 1053 | int intvec_top; |
| 1053 | u64 paddr = phys_addr; | 1054 | u64 paddr = phys_addr; |
| 1054 | 1055 | ||
| 1055 | mpic = alloc_bootmem(sizeof(struct mpic)); | 1056 | mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); |
| 1056 | if (mpic == NULL) | 1057 | if (mpic == NULL) |
| 1057 | return NULL; | 1058 | return NULL; |
| 1058 | 1059 | ||
| 1059 | memset(mpic, 0, sizeof(struct mpic)); | ||
| 1060 | mpic->name = name; | 1060 | mpic->name = name; |
| 1061 | 1061 | ||
| 1062 | mpic->hc_irq = mpic_irq_chip; | 1062 | mpic->hc_irq = mpic_irq_chip; |
| @@ -1152,8 +1152,8 @@ struct mpic * __init mpic_alloc(struct device_node *node, · 89 unmodified lines | |||
| 1152 | } | 1152 | } |
| 1153 | 1153 | ||
| 1154 | /* Map the global registers */ | 1154 | /* Map the global registers */ |
| 1155 | mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); | 1155 | mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
| 1156 | mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); | 1156 | mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); |
| 1157 | 1157 | ||
| 1158 | /* Reset */ | 1158 | /* Reset */ |
| 1159 | if (flags & MPIC_WANTS_RESET) { | 1159 | if (flags & MPIC_WANTS_RESET) { |
| @@ -1194,7 +1194,7 @@ struct mpic * __init mpic_alloc(struct device_node *node, · 34 unmodified lines | |||
| 1194 | 1194 | ||
| 1195 | /* Map the per-CPU registers */ | 1195 | /* Map the per-CPU registers */ |
| 1196 | for (i = 0; i < mpic->num_cpus; i++) { | 1196 | for (i = 0; i < mpic->num_cpus; i++) { |
| 1197 | mpic_map(mpic, paddr, &mpic->cpuregs[i], | 1197 | mpic_map(mpic, node, paddr, &mpic->cpuregs[i], |
| 1198 | MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), | 1198 | MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE), |
| 1199 | 0x1000); | 1199 | 0x1000); |
| 1200 | } | 1200 | } |
| @@ -1202,7 +1202,7 @@ struct mpic * __init mpic_alloc(struct device_node *node, · 1 unmodified line | |||
| 1202 | /* Initialize main ISU if none provided */ | 1202 | /* Initialize main ISU if none provided */ |
| 1203 | if (mpic->isu_size == 0) { | 1203 | if (mpic->isu_size == 0) { |
| 1204 | mpic->isu_size = mpic->num_sources; | 1204 | mpic->isu_size = mpic->num_sources; |
| 1205 | mpic_map(mpic, paddr, &mpic->isus[0], | 1205 | mpic_map(mpic, node, paddr, &mpic->isus[0], |
| 1206 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); | 1206 | MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
| 1207 | } | 1207 | } |
| 1208 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); | 1208 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); |
| @@ -1256,8 +1256,10 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, · 47 unmodified lines | |||
| 1256 | 1256 | ||
| 1257 | BUG_ON(isu_num >= MPIC_MAX_ISU); | 1257 | BUG_ON(isu_num >= MPIC_MAX_ISU); |
| 1258 | 1258 | ||
| 1259 | mpic_map(mpic, paddr, &mpic->isus[isu_num], 0, | 1259 | mpic_map(mpic, mpic->irqhost->of_node, |
| 1260 | paddr, &mpic->isus[isu_num], 0, | ||
| 1260 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); | 1261 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
| 1262 | |||
| 1261 | if ((isu_first + mpic->isu_size) > mpic->num_sources) | 1263 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
| 1262 | mpic->num_sources = isu_first + mpic->isu_size; | 1264 | mpic->num_sources = isu_first + mpic->isu_size; |
| 1263 | } | 1265 | } |
| @@ -112,6 +112,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) · 111 unmodified lines | |||
| 112 | { | 112 | { |
| 113 | unsigned long flags; | 113 | unsigned long flags; |
| 114 | u8 mcn_shift = 0, dev_shift = 0; | 114 | u8 mcn_shift = 0, dev_shift = 0; |
| 115 | u32 ret; | ||
| 115 | 116 | ||
| 116 | spin_lock_irqsave(&qe_lock, flags); | 117 | spin_lock_irqsave(&qe_lock, flags); |
| 117 | if (cmd == QE_RESET) { | 118 | if (cmd == QE_RESET) { |
| @@ -139,11 +140,13 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) · 21 unmodified lines | |||
| 139 | } | 140 | } |
| 140 | 141 | ||
| 141 | /* wait for the QE_CR_FLG to clear */ | 142 | /* wait for the QE_CR_FLG to clear */ |
| 142 | while(in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) | 143 | ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0, |
| 143 | cpu_relax(); | 144 | 100, 0); |
| 145 | /* On timeout (e.g. failure), the expression will be false (ret == 0), | ||
| 146 | otherwise it will be true (ret == 1). */ | ||
| 144 | spin_unlock_irqrestore(&qe_lock, flags); | 147 | spin_unlock_irqrestore(&qe_lock, flags); |
| 145 | 148 | ||
| 146 | return 0; | 149 | return ret == 1; |
| 147 | } | 150 | } |
| 148 | EXPORT_SYMBOL(qe_issue_cmd); | 151 | EXPORT_SYMBOL(qe_issue_cmd); |
| 149 | 152 | ||
| @@ -94,6 +94,7 @@ config S390 · 93 unmodified lines | |||
| 94 | select HAVE_KVM if 64BIT | 94 | select HAVE_KVM if 64BIT |
| 95 | select HAVE_ARCH_TRACEHOOK | 95 | select HAVE_ARCH_TRACEHOOK |
| 96 | select INIT_ALL_POSSIBLE | 96 | select INIT_ALL_POSSIBLE |
| 97 | select HAVE_PERF_COUNTERS | ||
| 97 | 98 | ||
| 98 | source "init/Kconfig" | 99 | source "init/Kconfig" |
| 99 | 100 | ||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.30-rc3 | 3 | # Linux kernel version: 2.6.30 |
| 4 | # Thu Apr 23 09:29:52 2009 | 4 | # Mon Jun 22 11:08:16 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_SCHED_MC=y | 6 | CONFIG_SCHED_MC=y |
| 7 | CONFIG_MMU=y | 7 | CONFIG_MMU=y |
| @@ -25,6 +25,7 @@ CONFIG_VIRT_CPU_ACCOUNTING=y · 17 unmodified lines | |||
| 25 | CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y | 25 | CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y |
| 26 | CONFIG_S390=y | 26 | CONFIG_S390=y |
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 28 | CONFIG_CONSTRUCTORS=y | ||
| 28 | 29 | ||
| 29 | # | 30 | # |
| 30 | # General setup | 31 | # General setup |
| @@ -90,7 +91,6 @@ CONFIG_SYSCTL_SYSCALL=y · 59 unmodified lines | |||
| 90 | CONFIG_KALLSYMS=y | 91 | CONFIG_KALLSYMS=y |
| 91 | # CONFIG_KALLSYMS_ALL is not set | 92 | # CONFIG_KALLSYMS_ALL is not set |
| 92 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 93 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 93 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 94 | CONFIG_HOTPLUG=y | 94 | CONFIG_HOTPLUG=y |
| 95 | CONFIG_PRINTK=y | 95 | CONFIG_PRINTK=y |
| 96 | CONFIG_BUG=y | 96 | CONFIG_BUG=y |
| @@ -103,7 +103,14 @@ CONFIG_TIMERFD=y · 6 unmodified lines | |||
| 103 | CONFIG_EVENTFD=y | 103 | CONFIG_EVENTFD=y |
| 104 | CONFIG_SHMEM=y | 104 | CONFIG_SHMEM=y |
| 105 | CONFIG_AIO=y | 105 | CONFIG_AIO=y |
| 106 | CONFIG_HAVE_PERF_COUNTERS=y | ||
| 107 | |||
| 108 | # | ||
| 109 | # Performance Counters | ||
| 110 | # | ||
| 111 | # CONFIG_PERF_COUNTERS is not set | ||
| 106 | CONFIG_VM_EVENT_COUNTERS=y | 112 | CONFIG_VM_EVENT_COUNTERS=y |
| 113 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 107 | # CONFIG_COMPAT_BRK is not set | 114 | # CONFIG_COMPAT_BRK is not set |
| 108 | CONFIG_SLAB=y | 115 | CONFIG_SLAB=y |
| 109 | # CONFIG_SLUB is not set | 116 | # CONFIG_SLUB is not set |
| @@ -119,6 +126,11 @@ CONFIG_HAVE_KRETPROBES=y · 9 unmodified lines | |||
| 119 | CONFIG_HAVE_ARCH_TRACEHOOK=y | 126 | CONFIG_HAVE_ARCH_TRACEHOOK=y |
| 120 | CONFIG_USE_GENERIC_SMP_HELPERS=y | 127 | CONFIG_USE_GENERIC_SMP_HELPERS=y |
| 121 | CONFIG_HAVE_DEFAULT_NO_SPIN_MUTEXES=y | 128 | CONFIG_HAVE_DEFAULT_NO_SPIN_MUTEXES=y |
| 129 | |||
| 130 | # | ||
| 131 | # GCOV-based kernel profiling | ||
| 132 | # | ||
| 133 | # CONFIG_GCOV_KERNEL is not set | ||
| 122 | # CONFIG_SLOW_WORK is not set | 134 | # CONFIG_SLOW_WORK is not set |
| 123 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 135 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 124 | CONFIG_SLABINFO=y | 136 | CONFIG_SLABINFO=y |
| @@ -150,7 +162,7 @@ CONFIG_DEFAULT_DEADLINE=y · 25 unmodified lines | |||
| 150 | # CONFIG_DEFAULT_NOOP is not set | 162 | # CONFIG_DEFAULT_NOOP is not set |
| 151 | CONFIG_DEFAULT_IOSCHED="deadline" | 163 | CONFIG_DEFAULT_IOSCHED="deadline" |
| 152 | CONFIG_PREEMPT_NOTIFIERS=y | 164 | CONFIG_PREEMPT_NOTIFIERS=y |
| 153 | # CONFIG_FREEZER is not set | 165 | CONFIG_FREEZER=y |
| 154 | 166 | ||
| 155 | # | 167 | # |
| 156 | # Base setup | 168 | # Base setup |
| @@ -199,6 +211,7 @@ CONFIG_ARCH_SPARSEMEM_DEFAULT=y · 42 unmodified lines | |||
| 199 | CONFIG_ARCH_SELECT_MEMORY_MODEL=y | 211 | CONFIG_ARCH_SELECT_MEMORY_MODEL=y |
| 200 | CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y | 212 | CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y |
| 201 | CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y | 213 | CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y |
| 214 | CONFIG_ARCH_HIBERNATION_POSSIBLE=y | ||
| 202 | CONFIG_SELECT_MEMORY_MODEL=y | 215 | CONFIG_SELECT_MEMORY_MODEL=y |
| 203 | # CONFIG_FLATMEM_MANUAL is not set | 216 | # CONFIG_FLATMEM_MANUAL is not set |
| 204 | # CONFIG_DISCONTIGMEM_MANUAL is not set | 217 | # CONFIG_DISCONTIGMEM_MANUAL is not set |
| @@ -218,9 +231,9 @@ CONFIG_PHYS_ADDR_T_64BIT=y · 13 unmodified lines | |||
| 218 | CONFIG_ZONE_DMA_FLAG=1 | 231 | CONFIG_ZONE_DMA_FLAG=1 |
| 219 | CONFIG_BOUNCE=y | 232 | CONFIG_BOUNCE=y |
| 220 | CONFIG_VIRT_TO_BUS=y | 233 | CONFIG_VIRT_TO_BUS=y |
| 221 | CONFIG_UNEVICTABLE_LRU=y | ||
| 222 | CONFIG_HAVE_MLOCK=y | 234 | CONFIG_HAVE_MLOCK=y |
| 223 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | 235 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y |
| 236 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 224 | 237 | ||
| 225 | # | 238 | # |
| 226 | # I/O subsystem configuration | 239 | # I/O subsystem configuration |
| @@ -257,6 +270,16 @@ CONFIG_KEXEC=y · 30 unmodified lines | |||
| 257 | # CONFIG_ZFCPDUMP is not set | 270 | # CONFIG_ZFCPDUMP is not set |
| 258 | CONFIG_S390_GUEST=y | 271 | CONFIG_S390_GUEST=y |
| 259 | CONFIG_SECCOMP=y | 272 | CONFIG_SECCOMP=y |
| 273 | |||
| 274 | # | ||
| 275 | # Power Management | ||
| 276 | # | ||
| 277 | CONFIG_PM=y | ||
| 278 | # CONFIG_PM_DEBUG is not set | ||
| 279 | CONFIG_PM_SLEEP_SMP=y | ||
| 280 | CONFIG_PM_SLEEP=y | ||
| 281 | CONFIG_HIBERNATION=y | ||
| 282 | CONFIG_PM_STD_PARTITION="" | ||
| 260 | CONFIG_NET=y | 283 | CONFIG_NET=y |
| 261 | 284 | ||
| 262 | # | 285 | # |
| @@ -384,6 +407,7 @@ CONFIG_SCTP_HMAC_MD5=y · 121 unmodified lines | |||
| 384 | # CONFIG_ECONET is not set | 407 | # CONFIG_ECONET is not set |
| 385 | # CONFIG_WAN_ROUTER is not set | 408 | # CONFIG_WAN_ROUTER is not set |
| 386 | # CONFIG_PHONET is not set | 409 | # CONFIG_PHONET is not set |
| 410 | # CONFIG_IEEE802154 is not set | ||
| 387 | CONFIG_NET_SCHED=y | 411 | CONFIG_NET_SCHED=y |
| 388 | 412 | ||
| 389 | # | 413 | # |
| @@ -446,6 +470,7 @@ CONFIG_CAN_BCM=m · 56 unmodified lines | |||
| 446 | # CAN Device Drivers | 470 | # CAN Device Drivers |
| 447 | # | 471 | # |
| 448 | CONFIG_CAN_VCAN=m | 472 | CONFIG_CAN_VCAN=m |
| 473 | # CONFIG_CAN_DEV is not set | ||
| 449 | # CONFIG_CAN_DEBUG_DEVICES is not set | 474 | # CONFIG_CAN_DEBUG_DEVICES is not set |
| 450 | # CONFIG_AF_RXRPC is not set | 475 | # CONFIG_AF_RXRPC is not set |
| 451 | # CONFIG_WIMAX is not set | 476 | # CONFIG_WIMAX is not set |
| @@ -524,10 +549,6 @@ CONFIG_BLK_DEV_SR=y · 72 unmodified lines | |||
| 524 | CONFIG_BLK_DEV_SR_VENDOR=y | 549 | CONFIG_BLK_DEV_SR_VENDOR=y |
| 525 | CONFIG_CHR_DEV_SG=y | 550 | CONFIG_CHR_DEV_SG=y |
| 526 | # CONFIG_CHR_DEV_SCH is not set | 551 | # CONFIG_CHR_DEV_SCH is not set |
| 527 | |||
| 528 | # | ||
| 529 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 530 | # | ||
| 531 | CONFIG_SCSI_MULTI_LUN=y | 552 | CONFIG_SCSI_MULTI_LUN=y |
| 532 | CONFIG_SCSI_CONSTANTS=y | 553 | CONFIG_SCSI_CONSTANTS=y |
| 533 | CONFIG_SCSI_LOGGING=y | 554 | CONFIG_SCSI_LOGGING=y |
| @@ -578,7 +599,6 @@ CONFIG_DM_MULTIPATH=m · 44 unmodified lines | |||
| 578 | # CONFIG_DM_DELAY is not set | 599 | # CONFIG_DM_DELAY is not set |
| 579 | # CONFIG_DM_UEVENT is not set | 600 | # CONFIG_DM_UEVENT is not set |
| 580 | CONFIG_NETDEVICES=y | 601 | CONFIG_NETDEVICES=y |
| 581 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 582 | # CONFIG_IFB is not set | 602 | # CONFIG_IFB is not set |
| 583 | CONFIG_DUMMY=m | 603 | CONFIG_DUMMY=m |
| 584 | CONFIG_BONDING=m | 604 | CONFIG_BONDING=m |
| @@ -595,6 +615,7 @@ CONFIG_NET_ETHERNET=y · 10 unmodified lines | |||
| 595 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | 615 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set |
| 596 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | 616 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set |
| 597 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | 617 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set |
| 618 | # CONFIG_KS8842 is not set | ||
| 598 | CONFIG_NETDEV_1000=y | 619 | CONFIG_NETDEV_1000=y |
| 599 | CONFIG_NETDEV_10000=y | 620 | CONFIG_NETDEV_10000=y |
| 600 | # CONFIG_TR is not set | 621 | # CONFIG_TR is not set |
| @@ -674,6 +695,11 @@ CONFIG_S390_TAPE_34XX=m · 73 unmodified lines | |||
| 674 | # CONFIG_MONREADER is not set | 695 | # CONFIG_MONREADER is not set |
| 675 | CONFIG_MONWRITER=m | 696 | CONFIG_MONWRITER=m |
| 676 | CONFIG_S390_VMUR=m | 697 | CONFIG_S390_VMUR=m |
| 698 | |||
| 699 | # | ||
| 700 | # PPS support | ||
| 701 | # | ||
| 702 | # CONFIG_PPS is not set | ||
| 677 | # CONFIG_POWER_SUPPLY is not set | 703 | # CONFIG_POWER_SUPPLY is not set |
| 678 | # CONFIG_THERMAL is not set | 704 | # CONFIG_THERMAL is not set |
| 679 | # CONFIG_THERMAL_HWMON is not set | 705 | # CONFIG_THERMAL_HWMON is not set |
| @@ -683,6 +709,10 @@ CONFIG_S390_VMUR=m · 3 unmodified lines | |||
| 683 | # CONFIG_NEW_LEDS is not set | 709 | # CONFIG_NEW_LEDS is not set |
| 684 | CONFIG_ACCESSIBILITY=y | 710 | CONFIG_ACCESSIBILITY=y |
| 685 | # CONFIG_AUXDISPLAY is not set | 711 | # CONFIG_AUXDISPLAY is not set |
| 712 | |||
| 713 | # | ||
| 714 | # TI VLYNQ | ||
| 715 | # | ||
| 686 | # CONFIG_STAGING is not set | 716 | # CONFIG_STAGING is not set |
| 687 | 717 | ||
| 688 | # | 718 | # |
| @@ -703,11 +733,12 @@ CONFIG_FS_MBCACHE=y · 14 unmodified lines | |||
| 703 | # CONFIG_REISERFS_FS is not set | 733 | # CONFIG_REISERFS_FS is not set |
| 704 | # CONFIG_JFS_FS is not set | 734 | # CONFIG_JFS_FS is not set |
| 705 | CONFIG_FS_POSIX_ACL=y | 735 | CONFIG_FS_POSIX_ACL=y |
| 706 | CONFIG_FILE_LOCKING=y | ||
| 707 | # CONFIG_XFS_FS is not set | 736 | # CONFIG_XFS_FS is not set |
| 708 | # CONFIG_GFS2_FS is not set | 737 | # CONFIG_GFS2_FS is not set |
| 709 | # CONFIG_OCFS2_FS is not set | 738 | # CONFIG_OCFS2_FS is not set |
| 710 | # CONFIG_BTRFS_FS is not set | 739 | # CONFIG_BTRFS_FS is not set |
| 740 | CONFIG_FILE_LOCKING=y | ||
| 741 | CONFIG_FSNOTIFY=y | ||
| 711 | CONFIG_DNOTIFY=y | 742 | CONFIG_DNOTIFY=y |
| 712 | CONFIG_INOTIFY=y | 743 | CONFIG_INOTIFY=y |
| 713 | CONFIG_INOTIFY_USER=y | 744 | CONFIG_INOTIFY_USER=y |
| @@ -865,19 +896,23 @@ CONFIG_DEBUG_MEMORY_INIT=y · 151 unmodified lines | |||
| 865 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 896 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 866 | # CONFIG_DEBUG_PAGEALLOC is not set | 897 | # CONFIG_DEBUG_PAGEALLOC is not set |
| 867 | CONFIG_HAVE_FUNCTION_TRACER=y | 898 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 899 | CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y | ||
| 900 | CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y | ||
| 901 | CONFIG_HAVE_DYNAMIC_FTRACE=y | ||
| 902 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y | ||
| 903 | CONFIG_HAVE_FTRACE_SYSCALLS=y | ||
| 868 | CONFIG_TRACING_SUPPORT=y | 904 | CONFIG_TRACING_SUPPORT=y |
| 869 | 905 | CONFIG_FTRACE=y | |
| 870 | # | ||
| 871 | # Tracers | ||
| 872 | # | ||
| 873 | # CONFIG_FUNCTION_TRACER is not set | 906 | # CONFIG_FUNCTION_TRACER is not set |
| 874 | # CONFIG_IRQSOFF_TRACER is not set | 907 | # CONFIG_IRQSOFF_TRACER is not set |
| 875 | # CONFIG_PREEMPT_TRACER is not set | 908 | # CONFIG_PREEMPT_TRACER is not set |
| 876 | # CONFIG_SCHED_TRACER is not set | 909 | # CONFIG_SCHED_TRACER is not set |
| 877 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 910 | # CONFIG_ENABLE_DEFAULT_TRACERS is not set |
| 878 | # CONFIG_EVENT_TRACER is not set | 911 | # CONFIG_FTRACE_SYSCALLS is not set |
| 879 | # CONFIG_BOOT_TRACER is not set | 912 | # CONFIG_BOOT_TRACER is not set |
| 880 | # CONFIG_TRACE_BRANCH_PROFILING is not set | 913 | CONFIG_BRANCH_PROFILE_NONE=y |
| 914 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set | ||
| 915 | # CONFIG_PROFILE_ALL_BRANCHES is not set | ||
| 881 | # CONFIG_STACK_TRACER is not set | 916 | # CONFIG_STACK_TRACER is not set |
| 882 | # CONFIG_KMEMTRACE is not set | 917 | # CONFIG_KMEMTRACE is not set |
| 883 | # CONFIG_WORKQUEUE_TRACER is not set | 918 | # CONFIG_WORKQUEUE_TRACER is not set |
| @@ -886,6 +921,7 @@ CONFIG_TRACING_SUPPORT=y · 2 unmodified lines | |||
| 886 | CONFIG_SAMPLES=y | 921 | CONFIG_SAMPLES=y |
| 887 | # CONFIG_SAMPLE_KOBJECT is not set | 922 | # CONFIG_SAMPLE_KOBJECT is not set |
| 888 | # CONFIG_SAMPLE_KPROBES is not set | 923 | # CONFIG_SAMPLE_KPROBES is not set |
| 924 | # CONFIG_KMEMCHECK is not set | ||
| 889 | 925 | ||
| 890 | # | 926 | # |
| 891 | # Security options | 927 | # Security options |
| @@ -178,7 +178,7 @@ cputime64_to_clock_t(cputime64_t cputime) · 177 unmodified lines | |||
| 178 | } | 178 | } |
| 179 | 179 | ||
| 180 | struct s390_idle_data { | 180 | struct s390_idle_data { |
| 181 | spinlock_t lock; | 181 | unsigned int sequence; |
| 182 | unsigned long long idle_count; | 182 | unsigned long long idle_count; |
| 183 | unsigned long long idle_enter; | 183 | unsigned long long idle_enter; |
| 184 | unsigned long long idle_time; | 184 | unsigned long long idle_time; |
| @@ -248,14 +248,5 @@ int debug_unregister_view(debug_info_t* id, struct debug_view* view); · 247 unmodified lines | |||
| 248 | #define PRINT_FATAL(x...) printk ( KERN_DEBUG PRINTK_HEADER x ) | 248 | #define PRINT_FATAL(x...) printk ( KERN_DEBUG PRINTK_HEADER x ) |
| 249 | #endif /* DASD_DEBUG */ | 249 | #endif /* DASD_DEBUG */ |
| 250 | 250 | ||
| 251 | #undef DEBUG_MALLOC | ||
| 252 | #ifdef DEBUG_MALLOC | ||
| 253 | void *b; | ||
| 254 | #define kmalloc(x...) (PRINT_INFO(" kmalloc %p\n",b=kmalloc(x)),b) | ||
| 255 | #define kfree(x) PRINT_INFO(" kfree %p\n",x);kfree(x) | ||
| 256 | #define get_zeroed_page(x...) (PRINT_INFO(" gfp %p\n",b=get_zeroed_page(x)),b) | ||
| 257 | #define __get_free_pages(x...) (PRINT_INFO(" gfps %p\n",b=__get_free_pages(x)),b) | ||
| 258 | #endif /* DEBUG_MALLOC */ | ||
| 259 | |||
| 260 | #endif /* __KERNEL__ */ | 251 | #endif /* __KERNEL__ */ |
| 261 | #endif /* DEBUG_H */ | 252 | #endif /* DEBUG_H */ |
| @@ -99,7 +99,9 @@ struct kvm_s390_sie_block { · 98 unmodified lines | |||
| 99 | __u8 reservedd0[48]; /* 0x00d0 */ | 99 | __u8 reservedd0[48]; /* 0x00d0 */ |
| 100 | __u64 gcr[16]; /* 0x0100 */ | 100 | __u64 gcr[16]; /* 0x0100 */ |
| 101 | __u64 gbea; /* 0x0180 */ | 101 | __u64 gbea; /* 0x0180 */ |
| 102 | __u8 reserved188[120]; /* 0x0188 */ | 102 | __u8 reserved188[24]; /* 0x0188 */ |
| 103 | __u32 fac; /* 0x01a0 */ | ||
| 104 | __u8 reserved1a4[92]; /* 0x01a4 */ | ||
| 103 | } __attribute__((packed)); | 105 | } __attribute__((packed)); |
| 104 | 106 | ||
| 105 | struct kvm_vcpu_stat { | 107 | struct kvm_vcpu_stat { |
| @@ -0,0 +1,8 @@ | |||
| 1 | /* | ||
| 2 | * Performance counter support - s390 specific definitions. | ||
| 3 | * | ||
| 4 | * Copyright 2009 Martin Schwidefsky, IBM Corporation. | ||
| 5 | */ | ||
| 6 | |||
| 7 | static inline void set_perf_counter_pending(void) {} | ||
| 8 | static inline void clear_perf_counter_pending(void) {} | ||
| @@ -380,7 +380,7 @@ extern int qdio_establish(struct qdio_initialize *); · 379 unmodified lines | |||
| 380 | extern int qdio_activate(struct ccw_device *); | 380 | extern int qdio_activate(struct ccw_device *); |
| 381 | 381 | ||
| 382 | extern int do_QDIO(struct ccw_device *cdev, unsigned int callflags, | 382 | extern int do_QDIO(struct ccw_device *cdev, unsigned int callflags, |
| 383 | int q_nr, int bufnr, int count); | 383 | int q_nr, unsigned int bufnr, unsigned int count); |
| 384 | extern int qdio_cleanup(struct ccw_device*, int); | 384 | extern int qdio_cleanup(struct ccw_device*, int); |
| 385 | extern int qdio_shutdown(struct ccw_device*, int); | 385 | extern int qdio_shutdown(struct ccw_device*, int); |
| 386 | extern int qdio_free(struct ccw_device *); | 386 | extern int qdio_free(struct ccw_device *); |
| @@ -154,39 +154,35 @@ void __kprobes get_instruction_type(struct arch_specific_insn *ainsn) · 153 unmodified lines | |||
| 154 | 154 | ||
| 155 | static int __kprobes swap_instruction(void *aref) | 155 | static int __kprobes swap_instruction(void *aref) |
| 156 | { | 156 | { |
| 157 | struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); | ||
| 158 | unsigned long status = kcb->kprobe_status; | ||
| 157 | struct ins_replace_args *args = aref; | 159 | struct ins_replace_args *args = aref; |
| 160 | int rc; | ||
| 158 | 161 | ||
| 159 | return probe_kernel_write(args->ptr, &args->new, sizeof(args->new)); | 162 | kcb->kprobe_status = KPROBE_SWAP_INST; |
| 163 | rc = probe_kernel_write(args->ptr, &args->new, sizeof(args->new)); | ||
| 164 | kcb->kprobe_status = status; | ||
| 165 | return rc; | ||
| 160 | } | 166 | } |
| 161 | 167 | ||
| 162 | void __kprobes arch_arm_kprobe(struct kprobe *p) | 168 | void __kprobes arch_arm_kprobe(struct kprobe *p) |
| 163 | { | 169 | { |
| 164 | struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); | ||
| 165 | unsigned long status = kcb->kprobe_status; | ||
| 166 | struct ins_replace_args args; | 170 | struct ins_replace_args args; |
| 167 | 171 | ||
| 168 | args.ptr = p->addr; | 172 | args.ptr = p->addr; |
| 169 | args.old = p->opcode; | 173 | args.old = p->opcode; |
| 170 | args.new = BREAKPOINT_INSTRUCTION; | 174 | args.new = BREAKPOINT_INSTRUCTION; |
| 171 | |||
| 172 | kcb->kprobe_status = KPROBE_SWAP_INST; | ||
| 173 | stop_machine(swap_instruction, &args, NULL); | 175 | stop_machine(swap_instruction, &args, NULL); |
| 174 | kcb->kprobe_status = status; | ||
| 175 | } | 176 | } |
| 176 | 177 | ||
| 177 | void __kprobes arch_disarm_kprobe(struct kprobe *p) | 178 | void __kprobes arch_disarm_kprobe(struct kprobe *p) |
| 178 | { | 179 | { |
| 179 | struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); | ||
| 180 | unsigned long status = kcb->kprobe_status; | ||
| 181 | struct ins_replace_args args; | 180 | struct ins_replace_args args; |
| 182 | 181 | ||
| 183 | args.ptr = p->addr; | 182 | args.ptr = p->addr; |
| 184 | args.old = BREAKPOINT_INSTRUCTION; | 183 | args.old = BREAKPOINT_INSTRUCTION; |
| 185 | args.new = p->opcode; | 184 | args.new = p->opcode; |
| 186 | |||
| 187 | kcb->kprobe_status = KPROBE_SWAP_INST; | ||
| 188 | stop_machine(swap_instruction, &args, NULL); | 185 | stop_machine(swap_instruction, &args, NULL); |
| 189 | kcb->kprobe_status = status; | ||
| 190 | } | 186 | } |
| 191 | 187 | ||
| 192 | void __kprobes arch_remove_kprobe(struct kprobe *p) | 188 | void __kprobes arch_remove_kprobe(struct kprobe *p) |
| @@ -856,13 +856,20 @@ static ssize_t show_idle_count(struct sys_device *dev, · 855 unmodified lines | |||
| 856 | { | 856 | { |
| 857 | struct s390_idle_data *idle; | 857 | struct s390_idle_data *idle; |
| 858 | unsigned long long idle_count; | 858 | unsigned long long idle_count; |
| 859 | unsigned int sequence; | ||
| 859 | 860 | ||
| 860 | idle = &per_cpu(s390_idle, dev->id); | 861 | idle = &per_cpu(s390_idle, dev->id); |
| 861 | spin_lock(&idle->lock); | 862 | repeat: |
| 863 | sequence = idle->sequence; | ||
| 864 | smp_rmb(); | ||
| 865 | if (sequence & 1) | ||
| 866 | goto repeat; | ||
| 862 | idle_count = idle->idle_count; | 867 | idle_count = idle->idle_count; |
| 863 | if (idle->idle_enter) | 868 | if (idle->idle_enter) |
| 864 | idle_count++; | 869 | idle_count++; |
| 865 | spin_unlock(&idle->lock); | 870 | smp_rmb(); |
| 871 | if (idle->sequence != sequence) | ||
| 872 | goto repeat; | ||
| 866 | return sprintf(buf, "%llu\n", idle_count); | 873 | return sprintf(buf, "%llu\n", idle_count); |
| 867 | } | 874 | } |
| 868 | static SYSDEV_ATTR(idle_count, 0444, show_idle_count, NULL); | 875 | static SYSDEV_ATTR(idle_count, 0444, show_idle_count, NULL); |
| @@ -872,15 +879,22 @@ static ssize_t show_idle_time(struct sys_device *dev, · 3 unmodified lines | |||
| 872 | { | 879 | { |
| 873 | struct s390_idle_data *idle; | 880 | struct s390_idle_data *idle; |
| 874 | unsigned long long now, idle_time, idle_enter; | 881 | unsigned long long now, idle_time, idle_enter; |
| 882 | unsigned int sequence; | ||
| 875 | 883 | ||
| 876 | idle = &per_cpu(s390_idle, dev->id); | 884 | idle = &per_cpu(s390_idle, dev->id); |
| 877 | spin_lock(&idle->lock); | ||
| 878 | now = get_clock(); | 885 | now = get_clock(); |
| 886 | repeat: | ||
| 887 | sequence = idle->sequence; | ||
| 888 | smp_rmb(); | ||
| 889 | if (sequence & 1) | ||
| 890 | goto repeat; | ||
| 879 | idle_time = idle->idle_time; | 891 | idle_time = idle->idle_time; |
| 880 | idle_enter = idle->idle_enter; | 892 | idle_enter = idle->idle_enter; |
| 881 | if (idle_enter != 0ULL && idle_enter < now) | 893 | if (idle_enter != 0ULL && idle_enter < now) |
| 882 | idle_time += now - idle_enter; | 894 | idle_time += now - idle_enter; |
| 883 | spin_unlock(&idle->lock); | 895 | smp_rmb(); |
| 896 | if (idle->sequence != sequence) | ||
| 897 | goto repeat; | ||
| 884 | return sprintf(buf, "%llu\n", idle_time >> 12); | 898 | return sprintf(buf, "%llu\n", idle_time >> 12); |
| 885 | } | 899 | } |
| 886 | static SYSDEV_ATTR(idle_time_us, 0444, show_idle_time, NULL); | 900 | static SYSDEV_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
| @@ -908,11 +922,7 @@ static int __cpuinit smp_cpu_notify(struct notifier_block *self, · 21 unmodified lines | |||
| 908 | case CPU_ONLINE: | 922 | case CPU_ONLINE: |
| 909 | case CPU_ONLINE_FROZEN: | 923 | case CPU_ONLINE_FROZEN: |
| 910 | idle = &per_cpu(s390_idle, cpu); | 924 | idle = &per_cpu(s390_idle, cpu); |
| 911 | spin_lock_irq(&idle->lock); | 925 | memset(idle, 0, sizeof(struct s390_idle_data)); |
| 912 | idle->idle_enter = 0; | ||
| 913 | idle->idle_time = 0; | ||
| 914 | idle->idle_count = 0; | ||
| 915 | spin_unlock_irq(&idle->lock); | ||
| 916 | if (sysfs_create_group(&s->kobj, &cpu_online_attr_group)) | 926 | if (sysfs_create_group(&s->kobj, &cpu_online_attr_group)) |
| 917 | return NOTIFY_BAD; | 927 | return NOTIFY_BAD; |
| 918 | break; | 928 | break; |
| @@ -36,7 +36,6 @@ · 35 unmodified lines | |||
| 36 | #include <linux/notifier.h> | 36 | #include <linux/notifier.h> |
| 37 | #include <linux/clocksource.h> | 37 | #include <linux/clocksource.h> |
| 38 | #include <linux/clockchips.h> | 38 | #include <linux/clockchips.h> |
| 39 | #include <linux/bootmem.h> | ||
| 40 | #include <asm/uaccess.h> | 39 | #include <asm/uaccess.h> |
| 41 | #include <asm/delay.h> | 40 | #include <asm/delay.h> |
| 42 | #include <asm/s390_ext.h> | 41 | #include <asm/s390_ext.h> |
| @@ -62,9 +61,6 @@ · 19 unmodified lines | |||
| 62 | 61 | ||
| 63 | u64 sched_clock_base_cc = -1; /* Force to data section. */ | 62 | u64 sched_clock_base_cc = -1; /* Force to data section. */ |
| 64 | 63 | ||
| 65 | static ext_int_info_t ext_int_info_cc; | ||
| 66 | static ext_int_info_t ext_int_etr_cc; | ||
| 67 | |||
| 68 | static DEFINE_PER_CPU(struct clock_event_device, comparators); | 64 | static DEFINE_PER_CPU(struct clock_event_device, comparators); |
| 69 | 65 | ||
| 70 | /* | 66 | /* |
| @@ -255,15 +251,11 @@ void __init time_init(void) · 184 unmodified lines | |||
| 255 | stp_reset(); | 251 | stp_reset(); |
| 256 | 252 | ||
| 257 | /* request the clock comparator external interrupt */ | 253 | /* request the clock comparator external interrupt */ |
| 258 | if (register_early_external_interrupt(0x1004, | 254 | if (register_external_interrupt(0x1004, clock_comparator_interrupt)) |
| 259 | clock_comparator_interrupt, | ||
| 260 | &ext_int_info_cc) != 0) | ||
| 261 | panic("Couldn't request external interrupt 0x1004"); | 255 | panic("Couldn't request external interrupt 0x1004"); |
| 262 | 256 | ||
| 263 | /* request the timing alert external interrupt */ | 257 | /* request the timing alert external interrupt */ |
| 264 | if (register_early_external_interrupt(0x1406, | 258 | if (register_external_interrupt(0x1406, timing_alert_interrupt)) |
| 265 | timing_alert_interrupt, | ||
| 266 | &ext_int_etr_cc) != 0) | ||
| 267 | panic("Couldn't request external interrupt 0x1406"); | 259 | panic("Couldn't request external interrupt 0x1406"); |
| 268 | 260 | ||
| 269 | if (clocksource_register(&clocksource_tod) != 0) | 261 | if (clocksource_register(&clocksource_tod) != 0) |
| @@ -1445,14 +1437,14 @@ static void __init stp_reset(void) · 1175 unmodified lines | |||
| 1445 | { | 1437 | { |
| 1446 | int rc; | 1438 | int rc; |
| 1447 | 1439 | ||
| 1448 | stp_page = alloc_bootmem_pages(PAGE_SIZE); | 1440 | stp_page = (void *) get_zeroed_page(GFP_ATOMIC); |
| 1449 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); | 1441 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); |
| 1450 | if (rc == 0) | 1442 | if (rc == 0) |
| 1451 | set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags); | 1443 | set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags); |
| 1452 | else if (stp_online) { | 1444 | else if (stp_online) { |
| 1453 | pr_warning("The real or virtual hardware system does " | 1445 | pr_warning("The real or virtual hardware system does " |
| 1454 | "not provide an STP interface\n"); | 1446 | "not provide an STP interface\n"); |
| 1455 | free_bootmem((unsigned long) stp_page, PAGE_SIZE); | 1447 | free_page((unsigned long) stp_page); |
| 1456 | stp_page = NULL; | 1448 | stp_page = NULL; |
| 1457 | stp_online = 0; | 1449 | stp_online = 0; |
| 1458 | } | 1450 | } |
| @@ -25,13 +25,9 @@ · 24 unmodified lines | |||
| 25 | #include <asm/irq_regs.h> | 25 | #include <asm/irq_regs.h> |
| 26 | #include <asm/cputime.h> | 26 | #include <asm/cputime.h> |
| 27 | 27 | ||
| 28 | static ext_int_info_t ext_int_info_timer; | ||
| 29 | |||
| 30 | static DEFINE_PER_CPU(struct vtimer_queue, virt_cpu_timer); | 28 | static DEFINE_PER_CPU(struct vtimer_queue, virt_cpu_timer); |
| 31 | 29 | ||
| 32 | DEFINE_PER_CPU(struct s390_idle_data, s390_idle) = { | 30 | DEFINE_PER_CPU(struct s390_idle_data, s390_idle); |
| 33 | .lock = __SPIN_LOCK_UNLOCKED(s390_idle.lock) | ||
| 34 | }; | ||
| 35 | 31 | ||
| 36 | static inline __u64 get_vtimer(void) | 32 | static inline __u64 get_vtimer(void) |
| 37 | { | 33 | { |
| @@ -153,11 +149,13 @@ void vtime_start_cpu(void) · 115 unmodified lines | |||
| 153 | vq->elapsed -= vq->idle - S390_lowcore.async_enter_timer; | 149 | vq->elapsed -= vq->idle - S390_lowcore.async_enter_timer; |
| 154 | } | 150 | } |
| 155 | 151 | ||
| 156 | spin_lock(&idle->lock); | 152 | idle->sequence++; |
| 153 | smp_wmb(); | ||
| 157 | idle->idle_time += idle_time; | 154 | idle->idle_time += idle_time; |
| 158 | idle->idle_enter = 0ULL; | 155 | idle->idle_enter = 0ULL; |
| 159 | idle->idle_count++; | 156 | idle->idle_count++; |
| 160 | spin_unlock(&idle->lock); | 157 | smp_wmb(); |
| 158 | idle->sequence++; | ||
| 161 | } | 159 | } |
| 162 | 160 | ||
| 163 | void vtime_stop_cpu(void) | 161 | void vtime_stop_cpu(void) |
| @@ -244,15 +242,23 @@ cputime64_t s390_get_idle_time(int cpu) · 80 unmodified lines | |||
| 244 | { | 242 | { |
| 245 | struct s390_idle_data *idle; | 243 | struct s390_idle_data *idle; |
| 246 | unsigned long long now, idle_time, idle_enter; | 244 | unsigned long long now, idle_time, idle_enter; |
| 245 | unsigned int sequence; | ||
| 247 | 246 | ||
| 248 | idle = &per_cpu(s390_idle, cpu); | 247 | idle = &per_cpu(s390_idle, cpu); |
| 249 | spin_lock(&idle->lock); | 248 | |
| 250 | now = get_clock(); | 249 | now = get_clock(); |
| 250 | repeat: | ||
| 251 | sequence = idle->sequence; | ||
| 252 | smp_rmb(); | ||
| 253 | if (sequence & 1) | ||
| 254 | goto repeat; | ||
| 251 | idle_time = 0; | 255 | idle_time = 0; |
| 252 | idle_enter = idle->idle_enter; | 256 | idle_enter = idle->idle_enter; |
| 253 | if (idle_enter != 0ULL && idle_enter < now) | 257 | if (idle_enter != 0ULL && idle_enter < now) |
| 254 | idle_time = now - idle_enter; | 258 | idle_time = now - idle_enter; |
| 255 | spin_unlock(&idle->lock); | 259 | smp_rmb(); |
| 260 | if (idle->sequence != sequence) | ||
| 261 | goto repeat; | ||
| 256 | return idle_time; | 262 | return idle_time; |
| 257 | } | 263 | } |
| 258 | 264 | ||
| @@ -557,8 +563,7 @@ void init_cpu_vtimer(void) · 298 unmodified lines | |||
| 557 | void __init vtime_init(void) | 563 | void __init vtime_init(void) |
| 558 | { | 564 | { |
| 559 | /* request the cpu timer external interrupt */ | 565 | /* request the cpu timer external interrupt */ |
| 560 | if (register_early_external_interrupt(0x1005, do_cpu_timer_interrupt, | 566 | if (register_external_interrupt(0x1005, do_cpu_timer_interrupt)) |
| 561 | &ext_int_info_timer) != 0) | ||
| 562 | panic("Couldn't request external interrupt 0x1005"); | 567 | panic("Couldn't request external interrupt 0x1005"); |
| 563 | 568 | ||
| 564 | /* Enable cpu timer interrupts on the boot cpu. */ | 569 | /* Enable cpu timer interrupts on the boot cpu. */ |
| @@ -25,6 +25,7 @@ · 24 unmodified lines | |||
| 25 | #include <asm/lowcore.h> | 25 | #include <asm/lowcore.h> |
| 26 | #include <asm/pgtable.h> | 26 | #include <asm/pgtable.h> |
| 27 | #include <asm/nmi.h> | 27 | #include <asm/nmi.h> |
| 28 | #include <asm/system.h> | ||
| 28 | #include "kvm-s390.h" | 29 | #include "kvm-s390.h" |
| 29 | #include "gaccess.h" | 30 | #include "gaccess.h" |
| 30 | 31 | ||
| @@ -69,6 +70,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { · 38 unmodified lines | |||
| 69 | { NULL } | 70 | { NULL } |
| 70 | }; | 71 | }; |
| 71 | 72 | ||
| 73 | static unsigned long long *facilities; | ||
| 72 | 74 | ||
| 73 | /* Section: not file related */ | 75 | /* Section: not file related */ |
| 74 | void kvm_arch_hardware_enable(void *garbage) | 76 | void kvm_arch_hardware_enable(void *garbage) |
| @@ -288,6 +290,7 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) · 213 unmodified lines | |||
| 288 | vcpu->arch.sie_block->gmsor = vcpu->kvm->arch.guest_origin; | 290 | vcpu->arch.sie_block->gmsor = vcpu->kvm->arch.guest_origin; |
| 289 | vcpu->arch.sie_block->ecb = 2; | 291 | vcpu->arch.sie_block->ecb = 2; |
| 290 | vcpu->arch.sie_block->eca = 0xC1002001U; | 292 | vcpu->arch.sie_block->eca = 0xC1002001U; |
| 293 | vcpu->arch.sie_block->fac = (int) (long) facilities; | ||
| 291 | hrtimer_init(&vcpu->arch.ckc_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); | 294 | hrtimer_init(&vcpu->arch.ckc_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); |
| 292 | tasklet_init(&vcpu->arch.tasklet, kvm_s390_tasklet, | 295 | tasklet_init(&vcpu->arch.tasklet, kvm_s390_tasklet, |
| 293 | (unsigned long) vcpu); | 296 | (unsigned long) vcpu); |
| @@ -739,11 +742,29 @@ gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) · 445 unmodified lines | |||
| 739 | 742 | ||
| 740 | static int __init kvm_s390_init(void) | 743 | static int __init kvm_s390_init(void) |
| 741 | { | 744 | { |
| 742 | return kvm_init(NULL, sizeof(struct kvm_vcpu), THIS_MODULE); | 745 | int ret; |
| 746 | ret = kvm_init(NULL, sizeof(struct kvm_vcpu), THIS_MODULE); | ||
| 747 | if (ret) | ||
| 748 | return ret; | ||
| 749 | |||
| 750 | /* | ||
| 751 | * guests can ask for up to 255+1 double words, we need a full page | ||
| 752 | * to hold the maximum amount of facilites. On the other hand, we | ||
| 753 | * only set facilities that are known to work in KVM. | ||
| 754 | */ | ||
| 755 | facilities = (unsigned long long *) get_zeroed_page(GFP_DMA); | ||
| 756 | if (!facilities) { | ||
| 757 | kvm_exit(); | ||
| 758 | return -ENOMEM; | ||
| 759 | } | ||
| 760 | stfle(facilities, 1); | ||
| 761 | facilities[0] &= 0xff00fff3f0700000ULL; | ||
| 762 | return 0; | ||
| 743 | } | 763 | } |
| 744 | 764 | ||
| 745 | static void __exit kvm_s390_exit(void) | 765 | static void __exit kvm_s390_exit(void) |
| 746 | { | 766 | { |
| 767 | free_page((unsigned long) facilities); | ||
| 747 | kvm_exit(); | 768 | kvm_exit(); |
| 748 | } | 769 | } |
| 749 | 770 | ||
| @@ -158,7 +158,7 @@ static int handle_stfl(struct kvm_vcpu *vcpu) · 157 unmodified lines | |||
| 158 | 158 | ||
| 159 | vcpu->stat.instruction_stfl++; | 159 | vcpu->stat.instruction_stfl++; |
| 160 | /* only pass the facility bits, which we can handle */ | 160 | /* only pass the facility bits, which we can handle */ |
| 161 | facility_list &= 0xfe00fff3; | 161 | facility_list &= 0xff00fff3; |
| 162 | 162 | ||
| 163 | rc = copy_to_guest(vcpu, offsetof(struct _lowcore, stfl_fac_list), | 163 | rc = copy_to_guest(vcpu, offsetof(struct _lowcore, stfl_fac_list), |
| 164 | &facility_list, sizeof(facility_list)); | 164 | &facility_list, sizeof(facility_list)); |
| @@ -109,10 +109,11 @@ swsusp_arch_resume: · 108 unmodified lines | |||
| 109 | aghi %r15,-STACK_FRAME_OVERHEAD | 109 | aghi %r15,-STACK_FRAME_OVERHEAD |
| 110 | stg %r1,__SF_BACKCHAIN(%r15) | 110 | stg %r1,__SF_BACKCHAIN(%r15) |
| 111 | 111 | ||
| 112 | #ifdef CONFIG_SMP | ||
| 112 | /* Save boot cpu number */ | 113 | /* Save boot cpu number */ |
| 113 | brasl %r14,smp_get_phys_cpu_id | 114 | brasl %r14,smp_get_phys_cpu_id |
| 114 | lgr %r10,%r2 | 115 | lgr %r10,%r2 |
| 115 | 116 | #endif | |
| 116 | /* Deactivate DAT */ | 117 | /* Deactivate DAT */ |
| 117 | stnsm __SF_EMPTY(%r15),0xfb | 118 | stnsm __SF_EMPTY(%r15),0xfb |
| 118 | 119 | ||
| @@ -177,11 +178,12 @@ swsusp_arch_resume: · 58 unmodified lines | |||
| 177 | /* Pointer to save arae */ | 178 | /* Pointer to save arae */ |
| 178 | lghi %r13,0x1000 | 179 | lghi %r13,0x1000 |
| 179 | 180 | ||
| 181 | #ifdef CONFIG_SMP | ||
| 180 | /* Switch CPUs */ | 182 | /* Switch CPUs */ |
| 181 | lgr %r2,%r10 /* get cpu id */ | 183 | lgr %r2,%r10 /* get cpu id */ |
| 182 | llgf %r3,0x318(%r13) | 184 | llgf %r3,0x318(%r13) |
| 183 | brasl %r14,smp_switch_boot_cpu_in_resume | 185 | brasl %r14,smp_switch_boot_cpu_in_resume |
| 184 | 186 | #endif | |
| 185 | /* Restore prefix register */ | 187 | /* Restore prefix register */ |
| 186 | spx 0x318(%r13) | 188 | spx 0x318(%r13) |
| 187 | 189 | ||
| @@ -15,7 +15,7 @@ config SUPERH · 14 unmodified lines | |||
| 15 | select HAVE_IOREMAP_PROT if MMU | 15 | select HAVE_IOREMAP_PROT if MMU |
| 16 | select HAVE_ARCH_TRACEHOOK | 16 | select HAVE_ARCH_TRACEHOOK |
| 17 | select HAVE_DMA_API_DEBUG | 17 | select HAVE_DMA_API_DEBUG |
| 18 | select HAVE_PERF_COUNTER | 18 | select HAVE_PERF_COUNTERS |
| 19 | select RTC_LIB | 19 | select RTC_LIB |
| 20 | select GENERIC_ATOMIC64 | 20 | select GENERIC_ATOMIC64 |
| 21 | help | 21 | help |
| @@ -71,6 +71,9 @@ config GENERIC_HARDIRQS_NO__DO_IRQ · 49 unmodified lines | |||
| 71 | config GENERIC_IRQ_PROBE | 71 | config GENERIC_IRQ_PROBE |
| 72 | def_bool y | 72 | def_bool y |
| 73 | 73 | ||
| 74 | config IRQ_PER_CPU | ||
| 75 | def_bool y | ||
| 76 | |||
| 74 | config GENERIC_GPIO | 77 | config GENERIC_GPIO |
| 75 | def_bool n | 78 | def_bool n |
| 76 | 79 | ||
| @@ -151,6 +154,9 @@ config ARCH_NO_VIRT_TO_BUS · 74 unmodified lines | |||
| 151 | config ARCH_HAS_DEFAULT_IDLE | 154 | config ARCH_HAS_DEFAULT_IDLE |
| 152 | def_bool y | 155 | def_bool y |
| 153 | 156 | ||
| 157 | config ARCH_HAS_CPU_IDLE_WAIT | ||
| 158 | def_bool y | ||
| 159 | |||
| 154 | config IO_TRAPPED | 160 | config IO_TRAPPED |
| 155 | bool | 161 | bool |
| 156 | 162 | ||
| @@ -411,6 +417,8 @@ config CPU_SUBTYPE_SH7786 · 254 unmodified lines | |||
| 411 | select CPU_HAS_PTEAEX | 417 | select CPU_HAS_PTEAEX |
| 412 | select ARCH_SPARSEMEM_ENABLE | 418 | select ARCH_SPARSEMEM_ENABLE |
| 413 | select SYS_SUPPORTS_NUMA | 419 | select SYS_SUPPORTS_NUMA |
| 420 | select SYS_SUPPORTS_SMP | ||
| 421 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP | ||
| 414 | 422 | ||
| 415 | config CPU_SUBTYPE_SHX3 | 423 | config CPU_SUBTYPE_SHX3 |
| 416 | bool "Support SH-X3 processor" | 424 | bool "Support SH-X3 processor" |
| @@ -648,7 +656,7 @@ config NR_CPUS · 231 unmodified lines | |||
| 648 | int "Maximum number of CPUs (2-32)" | 656 | int "Maximum number of CPUs (2-32)" |
| 649 | range 2 32 | 657 | range 2 32 |
| 650 | depends on SMP | 658 | depends on SMP |
| 651 | default "4" if CPU_SHX3 | 659 | default "4" if CPU_SUBTYPE_SHX3 |
| 652 | default "2" | 660 | default "2" |
| 653 | help | 661 | help |
| 654 | This allows you to specify the maximum number of CPUs which this | 662 | This allows you to specify the maximum number of CPUs which this |
| @@ -61,10 +61,6 @@ config EARLY_PRINTK · 60 unmodified lines | |||
| 61 | select both the EARLY_SCIF_CONSOLE and SH_STANDARD_BIOS, using | 61 | select both the EARLY_SCIF_CONSOLE and SH_STANDARD_BIOS, using |
| 62 | the kernel command line option to toggle back and forth. | 62 | the kernel command line option to toggle back and forth. |
| 63 | 63 | ||
| 64 | config DEBUG_BOOTMEM | ||
| 65 | depends on DEBUG_KERNEL | ||
| 66 | bool "Debug BOOTMEM initialization" | ||
| 67 | |||
| 68 | config DEBUG_STACKOVERFLOW | 64 | config DEBUG_STACKOVERFLOW |
| 69 | bool "Check for stack overflows" | 65 | bool "Check for stack overflows" |
| 70 | depends on DEBUG_KERNEL && SUPERH32 | 66 | depends on DEBUG_KERNEL && SUPERH32 |
| @@ -50,7 +50,7 @@ unsigned char se7206_inb_p(unsigned long port) · 49 unmodified lines | |||
| 50 | 50 | ||
| 51 | unsigned short se7206_inw(unsigned long port) | 51 | unsigned short se7206_inw(unsigned long port) |
| 52 | { | 52 | { |
| 53 | return *port2adr(port);; | 53 | return *port2adr(port); |
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | void se7206_outb(unsigned char value, unsigned long port) | 56 | void se7206_outb(unsigned char value, unsigned long port) |
| @@ -23,6 +23,8 @@ · 22 unmodified lines | |||
| 23 | #include <media/sh_mobile_ceu.h> | 23 | #include <media/sh_mobile_ceu.h> |
| 24 | #include <asm/io.h> | 24 | #include <asm/io.h> |
| 25 | #include <asm/heartbeat.h> | 25 | #include <asm/heartbeat.h> |
| 26 | #include <asm/sh_eth.h> | ||
| 27 | #include <asm/clock.h> | ||
| 26 | #include <asm/sh_keysc.h> | 28 | #include <asm/sh_keysc.h> |
| 27 | #include <cpu/sh7724.h> | 29 | #include <cpu/sh7724.h> |
| 28 | #include <mach-se/mach/se7724.h> | 30 | #include <mach-se/mach/se7724.h> |
| @@ -272,6 +274,34 @@ static struct platform_device keysc_device = { · 243 unmodified lines | |||
| 272 | }, | 274 | }, |
| 273 | }; | 275 | }; |
| 274 | 276 | ||
| 277 | /* SH Eth */ | ||
| 278 | static struct resource sh_eth_resources[] = { | ||
| 279 | [0] = { | ||
| 280 | .start = SH_ETH_ADDR, | ||
| 281 | .end = SH_ETH_ADDR + 0x1FC, | ||
| 282 | .flags = IORESOURCE_MEM, | ||
| 283 | }, | ||
| 284 | [1] = { | ||
| 285 | .start = 91, | ||
| 286 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
| 287 | }, | ||
| 288 | }; | ||
| 289 | |||
| 290 | struct sh_eth_plat_data sh_eth_plat = { | ||
| 291 | .phy = 0x1f, /* SMSC LAN8187 */ | ||
| 292 | .edmac_endian = EDMAC_LITTLE_ENDIAN, | ||
| 293 | }; | ||
| 294 | |||
| 295 | static struct platform_device sh_eth_device = { | ||
| 296 | .name = "sh-eth", | ||
| 297 | .id = 0, | ||
| 298 | .dev = { | ||
| 299 | .platform_data = &sh_eth_plat, | ||
| 300 | }, | ||
| 301 | .num_resources = ARRAY_SIZE(sh_eth_resources), | ||
| 302 | .resource = sh_eth_resources, | ||
| 303 | }; | ||
| 304 | |||
| 275 | static struct platform_device *ms7724se_devices[] __initdata = { | 305 | static struct platform_device *ms7724se_devices[] __initdata = { |
| 276 | &heartbeat_device, | 306 | &heartbeat_device, |
| 277 | &smc91x_eth_device, | 307 | &smc91x_eth_device, |
| @@ -280,8 +310,57 @@ static struct platform_device *ms7724se_devices[] __initdata = { · 2 unmodified lines | |||
| 280 | &ceu0_device, | 310 | &ceu0_device, |
| 281 | &ceu1_device, | 311 | &ceu1_device, |
| 282 | &keysc_device, | 312 | &keysc_device, |
| 313 | &sh_eth_device, | ||
| 283 | }; | 314 | }; |
| 284 | 315 | ||
| 316 | #define EEPROM_OP 0xBA206000 | ||
| 317 | #define EEPROM_ADR 0xBA206004 | ||
| 318 | #define EEPROM_DATA 0xBA20600C | ||
| 319 | #define EEPROM_STAT 0xBA206010 | ||
| 320 | #define EEPROM_STRT 0xBA206014 | ||
| 321 | static int __init sh_eth_is_eeprom_ready(void) | ||
| 322 | { | ||
| 323 | int t = 10000; | ||
| 324 | |||
| 325 | while (t--) { | ||
| 326 | if (!ctrl_inw(EEPROM_STAT)) | ||
| 327 | return 1; | ||
| 328 | cpu_relax(); | ||
| 329 | } | ||
| 330 | |||
| 331 | printk(KERN_ERR "ms7724se can not access to eeprom\n"); | ||
| 332 | return 0; | ||
| 333 | } | ||
| 334 | |||
| 335 | static void __init sh_eth_init(void) | ||
| 336 | { | ||
| 337 | int i; | ||
| 338 | u16 mac[3]; | ||
| 339 | |||
| 340 | /* check EEPROM status */ | ||
| 341 | if (!sh_eth_is_eeprom_ready()) | ||
| 342 | return; | ||
| 343 | |||
| 344 | /* read MAC addr from EEPROM */ | ||
| 345 | for (i = 0 ; i < 3 ; i++) { | ||
| 346 | ctrl_outw(0x0, EEPROM_OP); /* read */ | ||
| 347 | ctrl_outw(i*2, EEPROM_ADR); | ||
| 348 | ctrl_outw(0x1, EEPROM_STRT); | ||
| 349 | if (!sh_eth_is_eeprom_ready()) | ||
| 350 | return; | ||
| 351 | |||
| 352 | mac[i] = ctrl_inw(EEPROM_DATA); | ||
| 353 | mac[i] = ((mac[i] & 0xFF) << 8) | (mac[i] >> 8); /* swap */ | ||
| 354 | } | ||
| 355 | |||
| 356 | /* reset sh-eth */ | ||
| 357 | ctrl_outl(0x1, SH_ETH_ADDR + 0x0); | ||
| 358 | |||
| 359 | /* set MAC addr */ | ||
| 360 | ctrl_outl(((mac[0] << 16) | (mac[1])), SH_ETH_MAHR); | ||
| 361 | ctrl_outl((mac[2]), SH_ETH_MALR); | ||
| 362 | } | ||
| 363 | |||
| 285 | #define SW4140 0xBA201000 | 364 | #define SW4140 0xBA201000 |
| 286 | #define FPGA_OUT 0xBA200400 | 365 | #define FPGA_OUT 0xBA200400 |
| 287 | #define PORT_HIZA 0xA4050158 | 366 | #define PORT_HIZA 0xA4050158 |
| @@ -302,7 +381,8 @@ static int __init devices_setup(void) · 14 unmodified lines | |||
| 302 | ctrl_outw(ctrl_inw(FPGA_OUT) & | 381 | ctrl_outw(ctrl_inw(FPGA_OUT) & |
| 303 | ~((1 << 1) | /* LAN */ | 382 | ~((1 << 1) | /* LAN */ |
| 304 | (1 << 6) | /* VIDEO DAC */ | 383 | (1 << 6) | /* VIDEO DAC */ |
| 305 | (1 << 12)), /* USB0 */ | 384 | (1 << 12) | /* USB0 */ |
| 385 | (1 << 14)), /* RMII */ | ||
| 306 | FPGA_OUT); | 386 | FPGA_OUT); |
| 307 | 387 | ||
| 308 | /* enable IRQ 0,1,2 */ | 388 | /* enable IRQ 0,1,2 */ |
| @@ -374,7 +454,7 @@ static int __init devices_setup(void) · 65 unmodified lines | |||
| 374 | gpio_request(GPIO_FN_VIO0_CLK, NULL); | 454 | gpio_request(GPIO_FN_VIO0_CLK, NULL); |
| 375 | gpio_request(GPIO_FN_VIO0_FLD, NULL); | 455 | gpio_request(GPIO_FN_VIO0_FLD, NULL); |
| 376 | gpio_request(GPIO_FN_VIO0_HD, NULL); | 456 | gpio_request(GPIO_FN_VIO0_HD, NULL); |
| 377 | platform_resource_setup_memory(&ceu0_device, "ceu", 4 << 20); | 457 | platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); |
| 378 | 458 | ||
| 379 | /* enable CEU1 */ | 459 | /* enable CEU1 */ |
| 380 | gpio_request(GPIO_FN_VIO1_D7, NULL); | 460 | gpio_request(GPIO_FN_VIO1_D7, NULL); |
| @@ -389,7 +469,7 @@ static int __init devices_setup(void) · 8 unmodified lines | |||
| 389 | gpio_request(GPIO_FN_VIO1_HD, NULL); | 469 | gpio_request(GPIO_FN_VIO1_HD, NULL); |
| 390 | gpio_request(GPIO_FN_VIO1_VD, NULL); | 470 | gpio_request(GPIO_FN_VIO1_VD, NULL); |
| 391 | gpio_request(GPIO_FN_VIO1_CLK, NULL); | 471 | gpio_request(GPIO_FN_VIO1_CLK, NULL); |
| 392 | platform_resource_setup_memory(&ceu1_device, "ceu", 4 << 20); | 472 | platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); |
| 393 | 473 | ||
| 394 | /* KEYSC */ | 474 | /* KEYSC */ |
| 395 | gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); | 475 | gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); |
| @@ -404,6 +484,28 @@ static int __init devices_setup(void) · 8 unmodified lines | |||
| 404 | gpio_request(GPIO_FN_KEYOUT1, NULL); | 484 | gpio_request(GPIO_FN_KEYOUT1, NULL); |
| 405 | gpio_request(GPIO_FN_KEYOUT0, NULL); | 485 | gpio_request(GPIO_FN_KEYOUT0, NULL); |
| 406 | 486 | ||
| 487 | /* | ||
| 488 | * enable SH-Eth | ||
| 489 | * | ||
| 490 | * please remove J33 pin from your board !! | ||
| 491 | * | ||
| 492 | * ms7724 board should not use GPIO_FN_LNKSTA pin | ||
| 493 | * So, This time PTX5 is set to input pin | ||
| 494 | */ | ||
| 495 | gpio_request(GPIO_FN_RMII_RXD0, NULL); | ||
| 496 | gpio_request(GPIO_FN_RMII_RXD1, NULL); | ||
| 497 | gpio_request(GPIO_FN_RMII_TXD0, NULL); | ||
| 498 | gpio_request(GPIO_FN_RMII_TXD1, NULL); | ||
| 499 | gpio_request(GPIO_FN_RMII_REF_CLK, NULL); | ||
| 500 | gpio_request(GPIO_FN_RMII_TX_EN, NULL); | ||
| 501 | gpio_request(GPIO_FN_RMII_RX_ER, NULL); | ||
| 502 | gpio_request(GPIO_FN_RMII_CRS_DV, NULL); | ||
| 503 | gpio_request(GPIO_FN_MDIO, NULL); | ||
| 504 | gpio_request(GPIO_FN_MDC, NULL); | ||
| 505 | gpio_request(GPIO_PTX5, NULL); | ||
| 506 | gpio_direction_input(GPIO_PTX5); | ||
| 507 | sh_eth_init(); | ||
| 508 | |||
| 407 | if (sw & SW41_B) { | 509 | if (sw & SW41_B) { |
| 408 | /* SVGA */ | 510 | /* SVGA */ |
| 409 | lcdc_info.ch[0].lcd_cfg.xres = 800; | 511 | lcdc_info.ch[0].lcd_cfg.xres = 800; |
| @@ -437,7 +539,7 @@ static int __init devices_setup(void) · 27 unmodified lines | |||
| 437 | } | 539 | } |
| 438 | 540 | ||
| 439 | return platform_add_devices(ms7724se_devices, | 541 | return platform_add_devices(ms7724se_devices, |
| 440 | ARRAY_SIZE(ms7724se_devices)); | 542 | ARRAY_SIZE(ms7724se_devices)); |
| 441 | } | 543 | } |
| 442 | device_initcall(devices_setup); | 544 | device_initcall(devices_setup); |
| 443 | 545 | ||
| @@ -309,7 +309,7 @@ CONFIG_ZERO_PAGE_OFFSET=0x00001000 · 308 unmodified lines | |||
| 309 | CONFIG_BOOT_LINK_OFFSET=0x00800000 | 309 | CONFIG_BOOT_LINK_OFFSET=0x00800000 |
| 310 | CONFIG_ENTRY_OFFSET=0x00001000 | 310 | CONFIG_ENTRY_OFFSET=0x00001000 |
| 311 | CONFIG_CMDLINE_BOOL=y | 311 | CONFIG_CMDLINE_BOOL=y |
| 312 | CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=serial ip=on root=/dev/nfs ip=dhcp" | 312 | CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 earlyprintk=serial ip=on root=/dev/nfs ip=dhcp" |
| 313 | 313 | ||
| 314 | # | 314 | # |
| 315 | # Bus options | 315 | # Bus options |
| @@ -858,7 +858,35 @@ CONFIG_VIDEO_SH_MOBILE_CEU=y · 542 unmodified lines | |||
| 858 | # | 858 | # |
| 859 | # CONFIG_VGASTATE is not set | 859 | # CONFIG_VGASTATE is not set |
| 860 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | 860 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set |
| 861 | # CONFIG_FB is not set | 861 | CONFIG_FB=y |
| 862 | # CONFIG_FIRMWARE_EDID is not set | ||
| 863 | # CONFIG_FB_DDC is not set | ||
| 864 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 865 | # CONFIG_FB_CFB_FILLRECT is not set | ||
| 866 | # CONFIG_FB_CFB_COPYAREA is not set | ||
| 867 | # CONFIG_FB_CFB_IMAGEBLIT is not set | ||
| 868 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 869 | CONFIG_FB_SYS_FILLRECT=y | ||
| 870 | CONFIG_FB_SYS_COPYAREA=y | ||
| 871 | CONFIG_FB_SYS_IMAGEBLIT=y | ||
| 872 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 873 | CONFIG_FB_SYS_FOPS=y | ||
| 874 | CONFIG_FB_DEFERRED_IO=y | ||
| 875 | # CONFIG_FB_SVGALIB is not set | ||
| 876 | # CONFIG_FB_MACMODES is not set | ||
| 877 | # CONFIG_FB_BACKLIGHT is not set | ||
| 878 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 879 | # CONFIG_FB_TILEBLITTING is not set | ||
| 880 | |||
| 881 | # | ||
| 882 | # Frame buffer hardware drivers | ||
| 883 | # | ||
| 884 | # CONFIG_FB_S1D13XXX is not set | ||
| 885 | CONFIG_FB_SH_MOBILE_LCDC=y | ||
| 886 | # CONFIG_FB_VIRTUAL is not set | ||
| 887 | # CONFIG_FB_METRONOME is not set | ||
| 888 | # CONFIG_FB_MB862XX is not set | ||
| 889 | # CONFIG_FB_BROADSHEET is not set | ||
| 862 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 890 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set |
| 863 | 891 | ||
| 864 | # | 892 | # |
| @@ -870,6 +898,27 @@ CONFIG_VIDEO_SH_MOBILE_CEU=y · 5 unmodified lines | |||
| 870 | # Console display driver support | 898 | # Console display driver support |
| 871 | # | 899 | # |
| 872 | CONFIG_DUMMY_CONSOLE=y | 900 | CONFIG_DUMMY_CONSOLE=y |
| 901 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 902 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y | ||
| 903 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
| 904 | CONFIG_FONTS=y | ||
| 905 | # CONFIG_FONT_8x8 is not set | ||
| 906 | # CONFIG_FONT_8x16 is not set | ||
| 907 | # CONFIG_FONT_6x11 is not set | ||
| 908 | # CONFIG_FONT_7x14 is not set | ||
| 909 | # CONFIG_FONT_PEARL_8x8 is not set | ||
| 910 | # CONFIG_FONT_ACORN_8x8 is not set | ||
| 911 | CONFIG_FONT_MINI_4x6=y | ||
| 912 | # CONFIG_FONT_SUN8x16 is not set | ||
| 913 | # CONFIG_FONT_SUN12x22 is not set | ||
| 914 | # CONFIG_FONT_10x18 is not set | ||
| 915 | CONFIG_LOGO=y | ||
| 916 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 917 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 918 | # CONFIG_LOGO_LINUX_CLUT224 is not set | ||
| 919 | # CONFIG_LOGO_SUPERH_MONO is not set | ||
| 920 | CONFIG_LOGO_SUPERH_VGA16=y | ||
| 921 | # CONFIG_LOGO_SUPERH_CLUT224 is not set | ||
| 873 | # CONFIG_SOUND is not set | 922 | # CONFIG_SOUND is not set |
| 874 | CONFIG_HID_SUPPORT=y | 923 | CONFIG_HID_SUPPORT=y |
| 875 | CONFIG_HID=y | 924 | CONFIG_HID=y |
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.30 | 3 | # Linux kernel version: 2.6.30 |
| 4 | # Thu Jun 18 16:09:05 2009 | 4 | # Mon Jun 29 16:28:43 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_SUPERH=y | 6 | CONFIG_SUPERH=y |
| 7 | CONFIG_SUPERH32=y | 7 | CONFIG_SUPERH32=y |
| @@ -14,6 +14,7 @@ CONFIG_GENERIC_HWEIGHT=y · 6 unmodified lines | |||
| 14 | CONFIG_GENERIC_HARDIRQS=y | 14 | CONFIG_GENERIC_HARDIRQS=y |
| 15 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 15 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 16 | CONFIG_GENERIC_IRQ_PROBE=y | 16 | CONFIG_GENERIC_IRQ_PROBE=y |
| 17 | CONFIG_IRQ_PER_CPU=y | ||
| 17 | CONFIG_GENERIC_GPIO=y | 18 | CONFIG_GENERIC_GPIO=y |
| 18 | CONFIG_GENERIC_TIME=y | 19 | CONFIG_GENERIC_TIME=y |
| 19 | CONFIG_GENERIC_CLOCKEVENTS=y | 20 | CONFIG_GENERIC_CLOCKEVENTS=y |
| @@ -28,7 +29,9 @@ CONFIG_HAVE_LATENCYTOP_SUPPORT=y · 8 unmodified lines | |||
| 28 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | 29 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set |
| 29 | CONFIG_ARCH_NO_VIRT_TO_BUS=y | 30 | CONFIG_ARCH_NO_VIRT_TO_BUS=y |
| 30 | CONFIG_ARCH_HAS_DEFAULT_IDLE=y | 31 | CONFIG_ARCH_HAS_DEFAULT_IDLE=y |
| 32 | CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y | ||
| 31 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 33 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 34 | CONFIG_CONSTRUCTORS=y | ||
| 32 | 35 | ||
| 33 | # | 36 | # |
| 34 | # General setup | 37 | # General setup |
| @@ -88,10 +91,12 @@ CONFIG_TIMERFD=y · 53 unmodified lines | |||
| 88 | CONFIG_EVENTFD=y | 91 | CONFIG_EVENTFD=y |
| 89 | CONFIG_SHMEM=y | 92 | CONFIG_SHMEM=y |
| 90 | CONFIG_AIO=y | 93 | CONFIG_AIO=y |
| 94 | CONFIG_HAVE_PERF_COUNTERS=y | ||
| 91 | 95 | ||
| 92 | # | 96 | # |
| 93 | # Performance Counters | 97 | # Performance Counters |
| 94 | # | 98 | # |
| 99 | # CONFIG_PERF_COUNTERS is not set | ||
| 95 | CONFIG_VM_EVENT_COUNTERS=y | 100 | CONFIG_VM_EVENT_COUNTERS=y |
| 96 | # CONFIG_STRIP_ASM_SYMS is not set | 101 | # CONFIG_STRIP_ASM_SYMS is not set |
| 97 | CONFIG_COMPAT_BRK=y | 102 | CONFIG_COMPAT_BRK=y |
| @@ -107,6 +112,10 @@ CONFIG_HAVE_KRETPROBES=y · 9 unmodified lines | |||
| 107 | CONFIG_HAVE_ARCH_TRACEHOOK=y | 112 | CONFIG_HAVE_ARCH_TRACEHOOK=y |
| 108 | CONFIG_HAVE_CLK=y | 113 | CONFIG_HAVE_CLK=y |
| 109 | CONFIG_HAVE_DMA_API_DEBUG=y | 114 | CONFIG_HAVE_DMA_API_DEBUG=y |
| 115 | |||
| 116 | # | ||
| 117 | # GCOV-based kernel profiling | ||
| 118 | # | ||
| 110 | # CONFIG_SLOW_WORK is not set | 119 | # CONFIG_SLOW_WORK is not set |
| 111 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | 120 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
| 112 | CONFIG_SLABINFO=y | 121 | CONFIG_SLABINFO=y |
| @@ -119,7 +128,7 @@ CONFIG_MODULE_UNLOAD=y · 6 unmodified lines | |||
| 119 | # CONFIG_MODVERSIONS is not set | 128 | # CONFIG_MODVERSIONS is not set |
| 120 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 129 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 121 | CONFIG_BLOCK=y | 130 | CONFIG_BLOCK=y |
| 122 | # CONFIG_LBD is not set | 131 | CONFIG_LBDAF=y |
| 123 | # CONFIG_BLK_DEV_BSG is not set | 132 | # CONFIG_BLK_DEV_BSG is not set |
| 124 | # CONFIG_BLK_DEV_INTEGRITY is not set | 133 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 125 | 134 | ||
| @@ -584,7 +593,6 @@ CONFIG_SCSI_WAIT_SCAN=m · 458 unmodified lines | |||
| 584 | # CONFIG_SCSI_SRP_ATTRS is not set | 593 | # CONFIG_SCSI_SRP_ATTRS is not set |
| 585 | CONFIG_SCSI_LOWLEVEL=y | 594 | CONFIG_SCSI_LOWLEVEL=y |
| 586 | # CONFIG_ISCSI_TCP is not set | 595 | # CONFIG_ISCSI_TCP is not set |
| 587 | # CONFIG_SCSI_BNX2_ISCSI is not set | ||
| 588 | # CONFIG_LIBFC is not set | 596 | # CONFIG_LIBFC is not set |
| 589 | # CONFIG_LIBFCOE is not set | 597 | # CONFIG_LIBFCOE is not set |
| 590 | # CONFIG_SCSI_DEBUG is not set | 598 | # CONFIG_SCSI_DEBUG is not set |
| @@ -624,7 +632,7 @@ CONFIG_NET_ETHERNET=y · 33 unmodified lines | |||
| 624 | CONFIG_MII=y | 632 | CONFIG_MII=y |
| 625 | # CONFIG_AX88796 is not set | 633 | # CONFIG_AX88796 is not set |
| 626 | # CONFIG_STNIC is not set | 634 | # CONFIG_STNIC is not set |
| 627 | # CONFIG_SH_ETH is not set | 635 | CONFIG_SH_ETH=y |
| 628 | CONFIG_SMC91X=y | 636 | CONFIG_SMC91X=y |
| 629 | # CONFIG_ENC28J60 is not set | 637 | # CONFIG_ENC28J60 is not set |
| 630 | # CONFIG_ETHOC is not set | 638 | # CONFIG_ETHOC is not set |
| @@ -801,6 +809,11 @@ CONFIG_SPI_BITBANG=y · 170 unmodified lines | |||
| 801 | # | 809 | # |
| 802 | # CONFIG_SPI_SPIDEV is not set | 810 | # CONFIG_SPI_SPIDEV is not set |
| 803 | # CONFIG_SPI_TLE62X0 is not set | 811 | # CONFIG_SPI_TLE62X0 is not set |
| 812 | |||
| 813 | # | ||
| 814 | # PPS support | ||
| 815 | # | ||
| 816 | # CONFIG_PPS is not set | ||
| 804 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | 817 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
| 805 | CONFIG_GPIOLIB=y | 818 | CONFIG_GPIOLIB=y |
| 806 | # CONFIG_GPIO_SYSFS is not set | 819 | # CONFIG_GPIO_SYSFS is not set |
| @@ -851,6 +864,8 @@ CONFIG_SSB_POSSIBLE=y · 44 unmodified lines | |||
| 851 | # CONFIG_MFD_WM8400 is not set | 864 | # CONFIG_MFD_WM8400 is not set |
| 852 | # CONFIG_MFD_WM8350_I2C is not set | 865 | # CONFIG_MFD_WM8350_I2C is not set |
| 853 | # CONFIG_MFD_PCF50633 is not set | 866 | # CONFIG_MFD_PCF50633 is not set |
| 867 | # CONFIG_AB3100_CORE is not set | ||
| 868 | # CONFIG_EZX_PCAP is not set | ||
| 854 | # CONFIG_REGULATOR is not set | 869 | # CONFIG_REGULATOR is not set |
| 855 | CONFIG_MEDIA_SUPPORT=y | 870 | CONFIG_MEDIA_SUPPORT=y |
| 856 | 871 | ||
| @@ -1196,6 +1211,7 @@ CONFIG_RTC_DRV_PCF8563=y · 339 unmodified lines | |||
| 1196 | # CONFIG_RTC_DRV_S35390A is not set | 1211 | # CONFIG_RTC_DRV_S35390A is not set |
| 1197 | # CONFIG_RTC_DRV_FM3130 is not set | 1212 | # CONFIG_RTC_DRV_FM3130 is not set |
| 1198 | # CONFIG_RTC_DRV_RX8581 is not set | 1213 | # CONFIG_RTC_DRV_RX8581 is not set |
| 1214 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1199 | 1215 | ||
| 1200 | # | 1216 | # |
| 1201 | # SPI RTC drivers | 1217 | # SPI RTC drivers |
| @@ -1260,6 +1276,7 @@ CONFIG_FS_MBCACHE=y · 58 unmodified lines | |||
| 1260 | # CONFIG_JFS_FS is not set | 1276 | # CONFIG_JFS_FS is not set |
| 1261 | CONFIG_FS_POSIX_ACL=y | 1277 | CONFIG_FS_POSIX_ACL=y |
| 1262 | # CONFIG_XFS_FS is not set | 1278 | # CONFIG_XFS_FS is not set |
| 1279 | # CONFIG_GFS2_FS is not set | ||
| 1263 | # CONFIG_OCFS2_FS is not set | 1280 | # CONFIG_OCFS2_FS is not set |
| 1264 | # CONFIG_BTRFS_FS is not set | 1281 | # CONFIG_BTRFS_FS is not set |
| 1265 | CONFIG_FILE_LOCKING=y | 1282 | CONFIG_FILE_LOCKING=y |
| @@ -97,7 +97,7 @@ static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, · 96 unmodified lines | |||
| 97 | dma_unmap_single(dev, dma_address, size, dir); | 97 | dma_unmap_single(dev, dma_address, size, dir); |
| 98 | } | 98 | } |
| 99 | 99 | ||
| 100 | static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle, | 100 | static inline void __dma_sync_single(struct device *dev, dma_addr_t dma_handle, |
| 101 | size_t size, enum dma_data_direction dir) | 101 | size_t size, enum dma_data_direction dir) |
| 102 | { | 102 | { |
| 103 | #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) | 103 | #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) |
| @@ -119,7 +119,7 @@ static inline void dma_sync_single_range(struct device *dev, · 15 unmodified lines | |||
| 119 | dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir); | 119 | dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir); |
| 120 | } | 120 | } |
| 121 | 121 | ||
| 122 | static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg, | 122 | static inline void __dma_sync_sg(struct device *dev, struct scatterlist *sg, |
| 123 | int nelems, enum dma_data_direction dir) | 123 | int nelems, enum dma_data_direction dir) |
| 124 | { | 124 | { |
| 125 | int i; | 125 | int i; |
| @@ -137,7 +137,7 @@ static inline void dma_sync_single_for_cpu(struct device *dev, · 11 unmodified lines | |||
| 137 | dma_addr_t dma_handle, size_t size, | 137 | dma_addr_t dma_handle, size_t size, |
| 138 | enum dma_data_direction dir) | 138 | enum dma_data_direction dir) |
| 139 | { | 139 | { |
| 140 | dma_sync_single(dev, dma_handle, size, dir); | 140 | __dma_sync_single(dev, dma_handle, size, dir); |
| 141 | debug_dma_sync_single_for_cpu(dev, dma_handle, size, dir); | 141 | debug_dma_sync_single_for_cpu(dev, dma_handle, size, dir); |
| 142 | } | 142 | } |
| 143 | 143 | ||
| @@ -146,7 +146,7 @@ static inline void dma_sync_single_for_device(struct device *dev, · 2 unmodified lines | |||
| 146 | size_t size, | 146 | size_t size, |
| 147 | enum dma_data_direction dir) | 147 | enum dma_data_direction dir) |
| 148 | { | 148 | { |
| 149 | dma_sync_single(dev, dma_handle, size, dir); | 149 | __dma_sync_single(dev, dma_handle, size, dir); |
| 150 | debug_dma_sync_single_for_device(dev, dma_handle, size, dir); | 150 | debug_dma_sync_single_for_device(dev, dma_handle, size, dir); |
| 151 | } | 151 | } |
| 152 | 152 | ||
| @@ -177,7 +177,7 @@ static inline void dma_sync_sg_for_cpu(struct device *dev, · 24 unmodified lines | |||
| 177 | struct scatterlist *sg, int nelems, | 177 | struct scatterlist *sg, int nelems, |
| 178 | enum dma_data_direction dir) | 178 | enum dma_data_direction dir) |
| 179 | { | 179 | { |
| 180 | dma_sync_sg(dev, sg, nelems, dir); | 180 | __dma_sync_sg(dev, sg, nelems, dir); |
| 181 | debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); | 181 | debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); |
| 182 | } | 182 | } |
| 183 | 183 | ||
| @@ -185,7 +185,7 @@ static inline void dma_sync_sg_for_device(struct device *dev, · 1 unmodified line | |||
| 185 | struct scatterlist *sg, int nelems, | 185 | struct scatterlist *sg, int nelems, |
| 186 | enum dma_data_direction dir) | 186 | enum dma_data_direction dir) |
| 187 | { | 187 | { |
| 188 | dma_sync_sg(dev, sg, nelems, dir); | 188 | __dma_sync_sg(dev, sg, nelems, dir); |
| 189 | debug_dma_sync_sg_for_device(dev, sg, nelems, dir); | 189 | debug_dma_sync_sg_for_device(dev, sg, nelems, dir); |
| 190 | } | 190 | } |
| 191 | 191 | ||
| @@ -2,6 +2,6 @@ · 1 unmodified line | |||
| 2 | #define __ASM_SH_PERF_COUNTER_H | 2 | #define __ASM_SH_PERF_COUNTER_H |
| 3 | 3 | ||
| 4 | /* SH only supports software counters through this interface. */ | 4 | /* SH only supports software counters through this interface. */ |
| 5 | #define set_perf_counter_pending() do { } while (0) | 5 | static inline void set_perf_counter_pending(void) {} |
| 6 | 6 | ||
| 7 | #endif /* __ASM_SH_PERF_COUNTER_H */ | 7 | #endif /* __ASM_SH_PERF_COUNTER_H */ |
| @@ -3,6 +3,7 @@ · 2 unmodified lines | |||
| 3 | 3 | ||
| 4 | #include <linux/kernel.h> | 4 | #include <linux/kernel.h> |
| 5 | #include <linux/sched.h> | 5 | #include <linux/sched.h> |
| 6 | #include <linux/err.h> | ||
| 6 | #include <asm/ptrace.h> | 7 | #include <asm/ptrace.h> |
| 7 | 8 | ||
| 8 | /* The system call number is given by the user in R3 */ | 9 | /* The system call number is given by the user in R3 */ |
| @@ -154,6 +154,7 @@ extern struct dentry *sh_debugfs_root; · 153 unmodified lines | |||
| 154 | 154 | ||
| 155 | void per_cpu_trap_init(void); | 155 | void per_cpu_trap_init(void); |
| 156 | void default_idle(void); | 156 | void default_idle(void); |
| 157 | void cpu_idle_wait(void); | ||
| 157 | 158 | ||
| 158 | asmlinkage void break_point_trap(void); | 159 | asmlinkage void break_point_trap(void); |
| 159 | 160 | ||
| @@ -20,6 +20,11 @@ · 19 unmodified lines | |||
| 20 | */ | 20 | */ |
| 21 | #include <asm/addrspace.h> | 21 | #include <asm/addrspace.h> |
| 22 | 22 | ||
| 23 | /* SH Eth */ | ||
| 24 | #define SH_ETH_ADDR (0xA4600000) | ||
| 25 | #define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0) | ||
| 26 | #define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8) | ||
| 27 | |||
| 23 | #define PA_LED (0xba203000) /* 8bit LED */ | 28 | #define PA_LED (0xba203000) /* 8bit LED */ |
| 24 | #define IRQ_MODE (0xba200010) | 29 | #define IRQ_MODE (0xba200010) |
| 25 | #define IRQ0_SR (0xba200014) | 30 | #define IRQ0_SR (0xba200014) |
| @@ -16,7 +16,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o · 15 unmodified lines | |||
| 16 | obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o | 16 | obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o |
| 17 | 17 | ||
| 18 | # SMP setup | 18 | # SMP setup |
| 19 | smp-$(CONFIG_CPU_SUBTYPE_SHX3) := smp-shx3.o | 19 | smp-$(CONFIG_CPU_SHX3) := smp-shx3.o |
| 20 | 20 | ||
| 21 | # Primary on-chip clocks (common) | 21 | # Primary on-chip clocks (common) |
| 22 | clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o | 22 | clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o |
| @@ -38,6 +38,6 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o · 15 unmodified lines | |||
| 38 | pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o | 38 | pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o |
| 39 | pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o | 39 | pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o |
| 40 | 40 | ||
| 41 | obj-y += $(clock-y) | 41 | obj-y += $(clock-y) |
| 42 | obj-$(CONFIG_SMP) += $(smp-y) | 42 | obj-$(CONFIG_SMP) += $(smp-y) |
| 43 | obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) | 43 | obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) |
| @@ -595,9 +595,8 @@ enum { · 594 unmodified lines | |||
| 595 | HSPI, | 595 | HSPI, |
| 596 | GPIO0, GPIO1, | 596 | GPIO0, GPIO1, |
| 597 | Thermal, | 597 | Thermal, |
| 598 | INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7, | 598 | INTICI0, INTICI1, INTICI2, INTICI3, |
| 599 | 599 | INTICI4, INTICI5, INTICI6, INTICI7, | |
| 600 | /* interrupt groups */ | ||
| 601 | }; | 600 | }; |
| 602 | 601 | ||
| 603 | static struct intc_vect vectors[] __initdata = { | 602 | static struct intc_vect vectors[] __initdata = { |
| @@ -638,10 +637,12 @@ static struct intc_vect vectors[] __initdata = { · 34 unmodified lines | |||
| 638 | INTC_VECT(HSPI, 0xe80), | 637 | INTC_VECT(HSPI, 0xe80), |
| 639 | INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0), | 638 | INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0), |
| 640 | INTC_VECT(Thermal, 0xee0), | 639 | INTC_VECT(Thermal, 0xee0), |
| 640 | INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20), | ||
| 641 | INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60), | ||
| 642 | INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0), | ||
| 643 | INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0), | ||
| 641 | }; | 644 | }; |
| 642 | 645 | ||
| 643 | /* FIXME: Main CPU support only now */ | ||
| 644 | #if 1 /* Main CPU */ | ||
| 645 | #define CnINTMSK0 0xfe410030 | 646 | #define CnINTMSK0 0xfe410030 |
| 646 | #define CnINTMSK1 0xfe410040 | 647 | #define CnINTMSK1 0xfe410040 |
| 647 | #define CnINTMSKCLR0 0xfe410050 | 648 | #define CnINTMSKCLR0 0xfe410050 |
| @@ -654,21 +655,6 @@ static struct intc_vect vectors[] __initdata = { · 6 unmodified lines | |||
| 654 | #define CnINT2MSKCR1 0xfe410a34 | 655 | #define CnINT2MSKCR1 0xfe410a34 |
| 655 | #define CnINT2MSKCR2 0xfe410a38 | 656 | #define CnINT2MSKCR2 0xfe410a38 |
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