History

Merge tag 'riscv-for-v5.2/fixes-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Paul Walmsley: "Minor RISC-V fixes and one defconfig update. The fixes have no functional impact: - Fix some comment text in the memory management vmalloc_fault path. - Fix some warnings from the DT compiler in our newly-added DT files. - Change the newly-added DT bindings such that SoC IP blocks with external I/O are marked as "disabled" by default, then enable them explicitly in board DT files when the devices are used on the board. This aligns the bindings with existing upstream practice. - Add the MIT license as an option for a minor header file, at the request of one of the U-Boot maintainers. The RISC-V defconfig update builds the SiFive SPI driver and the MMC-SPI driver by default. The intention here is to make v5.2 more usable for testers and users with RISC-V hardware" * tag 'riscv-for-v5.2/fixes-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: mm: Fix code comment dt-bindings: clock: sifive: add MIT license as an option for the header file dt-bindings: riscv: resolve 'make dt_binding_check' warnings riscv: dts: Re-organize the DT nodes RISC-V: defconfig: enable MMC & SPI for RISC-V

Linus Torvalds committed 7 years ago

Commit c57582a2 parents c949c30 0db7f5c6 files · +39 −16Browse files

Unified · Split

6 files
  1. Documentation/devicetree/bindings/riscv/cpus.yaml +14 −12
  2. arch/riscv/boot/dts/sifive/fu540-c000.dtsi +6 −0
  3. arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +13 −0
  4. arch/riscv/configs/defconfig +5 −0
  5. arch/riscv/mm/fault.c +0 −3
  6. include/dt-bindings/clock/sifive-fu540-prci.h +1 −1
Documentation/devicetree/bindings/riscv/cpus.yaml+14−12
@@ -152,17 +152,19 @@ examples: · 151 unmodified lines
152 - |152 - |
153 // Example 2: Spike ISA Simulator with 1 Hart153 // Example 2: Spike ISA Simulator with 1 Hart
154 cpus {154 cpus {
155 cpu@0 {155 #address-cells = <1>;
156 device_type = "cpu";156 #size-cells = <0>;
157 reg = <0>;157 cpu@0 {
158 compatible = "riscv";158 device_type = "cpu";
159 riscv,isa = "rv64imafdc";159 reg = <0>;
160 mmu-type = "riscv,sv48";160 compatible = "riscv";
161 interrupt-controller {161 riscv,isa = "rv64imafdc";
162 #interrupt-cells = <1>;162 mmu-type = "riscv,sv48";
163 interrupt-controller;163 interrupt-controller {
164 compatible = "riscv,cpu-intc";164 #interrupt-cells = <1>;
165 };165 interrupt-controller;
166 };166 compatible = "riscv,cpu-intc";
167 };
168 };
167 };169 };
168...170...
arch/riscv/boot/dts/sifive/fu540-c000.dtsi+6−0
@@ -163,6 +163,7 @@ · 162 unmodified lines
163 interrupt-parent = <&plic0>;163 interrupt-parent = <&plic0>;
164 interrupts = <4>;164 interrupts = <4>;
165 clocks = <&prci PRCI_CLK_TLCLK>;165 clocks = <&prci PRCI_CLK_TLCLK>;
166 status = "disabled";
166 };167 };
167 uart1: serial@10011000 {168 uart1: serial@10011000 {
168 compatible = "sifive,fu540-c000-uart", "sifive,uart0";169 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
@@ -170,6 +171,7 @@ · 1 unmodified line
170 interrupt-parent = <&plic0>;171 interrupt-parent = <&plic0>;
171 interrupts = <5>;172 interrupts = <5>;
172 clocks = <&prci PRCI_CLK_TLCLK>;173 clocks = <&prci PRCI_CLK_TLCLK>;
174 status = "disabled";
173 };175 };
174 i2c0: i2c@10030000 {176 i2c0: i2c@10030000 {
175 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";177 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
@@ -181,6 +183,7 @@ · 5 unmodified lines
181 reg-io-width = <1>;183 reg-io-width = <1>;
182 #address-cells = <1>;184 #address-cells = <1>;
183 #size-cells = <0>;185 #size-cells = <0>;
186 status = "disabled";
184 };187 };
185 qspi0: spi@10040000 {188 qspi0: spi@10040000 {
186 compatible = "sifive,fu540-c000-spi", "sifive,spi0";189 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
@@ -191,6 +194,7 @@ · 4 unmodified lines
191 clocks = <&prci PRCI_CLK_TLCLK>;194 clocks = <&prci PRCI_CLK_TLCLK>;
192 #address-cells = <1>;195 #address-cells = <1>;
193 #size-cells = <0>;196 #size-cells = <0>;
197 status = "disabled";
194 };198 };
195 qspi1: spi@10041000 {199 qspi1: spi@10041000 {
196 compatible = "sifive,fu540-c000-spi", "sifive,spi0";200 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
@@ -201,6 +205,7 @@ · 4 unmodified lines
201 clocks = <&prci PRCI_CLK_TLCLK>;205 clocks = <&prci PRCI_CLK_TLCLK>;
202 #address-cells = <1>;206 #address-cells = <1>;
203 #size-cells = <0>;207 #size-cells = <0>;
208 status = "disabled";
204 };209 };
205 qspi2: spi@10050000 {210 qspi2: spi@10050000 {
206 compatible = "sifive,fu540-c000-spi", "sifive,spi0";211 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
@@ -210,6 +215,7 @@ · 3 unmodified lines
210 clocks = <&prci PRCI_CLK_TLCLK>;215 clocks = <&prci PRCI_CLK_TLCLK>;
211 #address-cells = <1>;216 #address-cells = <1>;
212 #size-cells = <0>;217 #size-cells = <0>;
218 status = "disabled";
213 };219 };
214 };220 };
215};221};
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts+13−0
@@ -42,7 +42,20 @@ · 41 unmodified lines
42 };42 };
43};43};
44 44
45&uart0 {
46 status = "okay";
47};
48
49&uart1 {
50 status = "okay";
51};
52
53&i2c0 {
54 status = "okay";
55};
56
45&qspi0 {57&qspi0 {
58 status = "okay";
46 flash@0 {59 flash@0 {
47 compatible = "issi,is25wp256", "jedec,spi-nor";60 compatible = "issi,is25wp256", "jedec,spi-nor";
48 reg = <0>;61 reg = <0>;
arch/riscv/configs/defconfig+5−0
@@ -69,6 +69,7 @@ CONFIG_VIRTIO_MMIO=y · 68 unmodified lines
69CONFIG_CLK_SIFIVE=y69CONFIG_CLK_SIFIVE=y
70CONFIG_CLK_SIFIVE_FU540_PRCI=y70CONFIG_CLK_SIFIVE_FU540_PRCI=y
71CONFIG_SIFIVE_PLIC=y71CONFIG_SIFIVE_PLIC=y
72CONFIG_SPI_SIFIVE=y
72CONFIG_EXT4_FS=y73CONFIG_EXT4_FS=y
73CONFIG_EXT4_FS_POSIX_ACL=y74CONFIG_EXT4_FS_POSIX_ACL=y
74CONFIG_AUTOFS4_FS=y75CONFIG_AUTOFS4_FS=y
@@ -84,4 +85,8 @@ CONFIG_ROOT_NFS=y · 9 unmodified lines
84CONFIG_CRYPTO_USER_API_HASH=y85CONFIG_CRYPTO_USER_API_HASH=y
85CONFIG_CRYPTO_DEV_VIRTIO=y86CONFIG_CRYPTO_DEV_VIRTIO=y
86CONFIG_PRINTK_TIME=y87CONFIG_PRINTK_TIME=y
88CONFIG_SPI=y
89CONFIG_MMC_SPI=y
90CONFIG_MMC=y
91CONFIG_DEVTMPFS_MOUNT=y
87# CONFIG_RCU_TRACE is not set92# CONFIG_RCU_TRACE is not set
arch/riscv/mm/fault.c+0−3
@@ -272,9 +272,6 @@ vmalloc_fault: · 271 unmodified lines
272 * entries, but in RISC-V, SFENCE.VMA specifies an272 * entries, but in RISC-V, SFENCE.VMA specifies an
273 * ordering constraint, not a cache flush; it is273 * ordering constraint, not a cache flush; it is
274 * necessary even after writing invalid entries.274 * necessary even after writing invalid entries.
275 * Relying on flush_tlb_fix_spurious_fault would
276 * suffice, but the extra traps reduce
277 * performance. So, eagerly SFENCE.VMA.
278 */275 */
279 local_flush_tlb_page(addr);276 local_flush_tlb_page(addr);
280 277
include/dt-bindings/clock/sifive-fu540-prci.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: GPL-2.0 */1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*2/*
3 * Copyright (C) 2018-2019 SiFive, Inc.3 * Copyright (C) 2018-2019 SiFive, Inc.
4 * Wesley Terpstra4 * Wesley Terpstra