Merge tag 'riscv-for-linus-6.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt: - A fix to avoid pt_regs aliasing with idle thread stacks on secondary harts. - HAVE_ARCH_HUGE_VMAP is enabled on XIP kernels, which fixes boot issues on XIP systems with huge pages. - An update to the uABI documentation clarifying that only scalar misaligned accesses were grandfathered in as supported, as the vector extension did not exist at the time the uABI was frozen. - A fix for the recently-added byte/half atomics to avoid losing the fully ordered decorations. * tag 'riscv-for-linus-6.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Fix fully ordered LR/SC xchg[8|16]() implementations Documentation: RISC-V: uabi: Only scalar misaligned loads are supported riscv: enable HAVE_ARCH_HUGE_VMAP for XIP kernel riscv: prevent pt_regs corruption for secondary idle threads

Linus Torvalds committed 2 years ago

Commit c6cc9792 parents ff9bce3 1d84afa5 files · +18 −15Browse files

Unified · Split

5 files

Documentation/arch/riscv/uabi.rst +3 −1
arch/riscv/Kconfig +1 −1
arch/riscv/include/asm/cmpxchg.h +12 −10
arch/riscv/kernel/cpu_ops_sbi.c +1 −1
arch/riscv/kernel/cpu_ops_spinwait.c +1 −2

Documentation/arch/riscv/uabi.rst+3−1

@@ -65,4 +65,6 @@ the extension, or may have deliberately removed it from the listing. · 64 unmodified lines
65	Misaligned accesses	65	Misaligned accesses
66	-------------------	66	-------------------
67		67
68	Misaligned accesses are supported in userspace, but they may perform poorly.	68	Misaligned scalar accesses are supported in userspace, but they may perform
		69	poorly. Misaligned vector accesses are only supported if the Zicclsm extension
		70	is supported.

arch/riscv/Kconfig+1−1

@@ -106,7 +106,7 @@ config RISCV · 105 unmodified lines
106	select HAS_IOPORT if MMU	106	select HAS_IOPORT if MMU
107	select HAVE_ARCH_AUDITSYSCALL	107	select HAVE_ARCH_AUDITSYSCALL
108	select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP	108	select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP
109	select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT && !XIP_KERNEL	109	select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT
110	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL	110	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
111	select HAVE_ARCH_JUMP_LABEL_RELATIVE if !XIP_KERNEL	111	select HAVE_ARCH_JUMP_LABEL_RELATIVE if !XIP_KERNEL
112	select HAVE_ARCH_KASAN if MMU && 64BIT	112	select HAVE_ARCH_KASAN if MMU && 64BIT

arch/riscv/include/asm/cmpxchg.h+12−10

 #include <asm/fence.h>
-#define __arch_xchg_masked(prepend, append, r, p, n)			\
+#define __arch_xchg_masked(sc_sfx, prepend, append, r, p, n)		\
 ({									\
 	u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3);			\
 	ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE;	\
 	       "0:	lr.w %0, %2\n"					\
 	       "	and  %1, %0, %z4\n"				\
 	       "	or   %1, %1, %z3\n"				\
-	       "	sc.w %1, %1, %2\n"				\
+	       "	sc.w" sc_sfx " %1, %1, %2\n"			\
 	       "	bnez %1, 0b\n"					\
 	       append							\
 	       : "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b))	\
 		: "memory");						\
 })
-#define _arch_xchg(ptr, new, sfx, prepend, append)			\
+#define _arch_xchg(ptr, new, sc_sfx, swap_sfx, prepend,			\
+		   sc_append, swap_append)				\
 ({									\
 	__typeof__(ptr) __ptr = (ptr);					\
 	__typeof__(*(__ptr)) __new = (new);				\
 	switch (sizeof(*__ptr)) {					\
 	case 1:								\
 	case 2:								\
-		__arch_xchg_masked(prepend, append,			\
+		__arch_xchg_masked(sc_sfx, prepend, sc_append,		\
 				   __ret, __ptr, __new);		\
 		break;							\
 	case 4:								\
-		__arch_xchg(".w" sfx, prepend, append,			\
+		__arch_xchg(".w" swap_sfx, prepend, swap_append,	\
 			      __ret, __ptr, __new);			\
 		break;							\
 	case 8:								\
-		__arch_xchg(".d" sfx, prepend, append,			\
+		__arch_xchg(".d" swap_sfx, prepend, swap_append,	\
 			      __ret, __ptr, __new);			\
 		break;							\
 	default:							\
 })
 #define arch_xchg_relaxed(ptr, x)					\
-	_arch_xchg(ptr, x, "", "", "")
+	_arch_xchg(ptr, x, "", "", "", "", "")
 #define arch_xchg_acquire(ptr, x)					\
-	_arch_xchg(ptr, x, "", "", RISCV_ACQUIRE_BARRIER)
+	_arch_xchg(ptr, x, "", "", "",					\
+		   RISCV_ACQUIRE_BARRIER, RISCV_ACQUIRE_BARRIER)
 #define arch_xchg_release(ptr, x)					\
-	_arch_xchg(ptr, x, "", RISCV_RELEASE_BARRIER, "")
+	_arch_xchg(ptr, x, "", "", RISCV_RELEASE_BARRIER, "", "")
 #define arch_xchg(ptr, x)						\
-	_arch_xchg(ptr, x, ".aqrl", "", "")
+	_arch_xchg(ptr, x, ".rl", ".aqrl", "", RISCV_FULL_BARRIER, "")
 #define xchg32(ptr, x)							\
 ({									\

arch/riscv/kernel/cpu_ops_sbi.c+1−1

@@ -72,7 +72,7 @@ static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle) · 71 unmodified lines
72	/* Make sure tidle is updated */	72	/* Make sure tidle is updated */
73	smp_mb();	73	smp_mb();
74	bdata->task_ptr = tidle;	74	bdata->task_ptr = tidle;
75	bdata->stack_ptr = task_stack_page(tidle) + THREAD_SIZE;	75	bdata->stack_ptr = task_pt_regs(tidle);
76	/* Make sure boot data is updated */	76	/* Make sure boot data is updated */
77	smp_mb();	77	smp_mb();
78	hsm_data = __pa(bdata);	78	hsm_data = __pa(bdata);

arch/riscv/kernel/cpu_ops_spinwait.c+1−2

@@ -34,8 +34,7 @@ static void cpu_update_secondary_bootdata(unsigned int cpuid, · 33 unmodified lines
34		34
35	/* Make sure tidle is updated */	35	/* Make sure tidle is updated */
36	smp_mb();	36	smp_mb();
37	WRITE_ONCE(__cpu_spinwait_stack_pointer[hartid],	37	WRITE_ONCE(__cpu_spinwait_stack_pointer[hartid], task_pt_regs(tidle));
38	task_stack_page(tidle) + THREAD_SIZE);
39	WRITE_ONCE(__cpu_spinwait_task_pointer[hartid], tidle);	38	WRITE_ONCE(__cpu_spinwait_task_pointer[hartid], tidle);
40	}	39	}
41		40

Merge tag 'riscv-for-linus-6.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

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