| @@ -63,13 +63,19 @@ static DEFINE_MUTEX(spec_ctrl_mutex); · 62 unmodified lines |
| 63 | 63 | * Keep track of the SPEC_CTRL MSR value for the current task, which may differ |
| 64 | 64 | * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update(). |
| 65 | 65 | */ |
| 66 | | −void write_spec_ctrl_current(u64 val) |
| 66 | +void write_spec_ctrl_current(u64 val, bool force) |
| 67 | 67 | { |
| 68 | 68 | if (this_cpu_read(x86_spec_ctrl_current) == val) |
| 69 | 69 | return; |
| 70 | 70 | |
| 71 | 71 | this_cpu_write(x86_spec_ctrl_current, val); |
| 72 | | − wrmsrl(MSR_IA32_SPEC_CTRL, val); |
| 72 | + |
| 73 | + /* |
| 74 | + * When KERNEL_IBRS this MSR is written on return-to-user, unless |
| 75 | + * forced the update can be delayed until that time. |
| 76 | + */ |
| 77 | + if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) |
| 78 | + wrmsrl(MSR_IA32_SPEC_CTRL, val); |
| 73 | 79 | } |
| 74 | 80 | |
| 75 | 81 | /* |
| @@ -1297,7 +1303,7 @@ static void __init spectre_v2_select_mitigation(void) · 1221 unmodified lines |
| 1297 | 1303 | if (spectre_v2_in_eibrs_mode(mode)) { |
| 1298 | 1304 | /* Force it so VMEXIT will restore correctly */ |
| 1299 | 1305 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; |
| 1300 | | − write_spec_ctrl_current(x86_spec_ctrl_base); |
| 1306 | + write_spec_ctrl_current(x86_spec_ctrl_base, true); |
| 1301 | 1307 | } |
| 1302 | 1308 | |
| 1303 | 1309 | switch (mode) { |
| @@ -1352,7 +1358,7 @@ static void __init spectre_v2_select_mitigation(void) · 48 unmodified lines |
| 1352 | 1358 | |
| 1353 | 1359 | static void update_stibp_msr(void * __unused) |
| 1354 | 1360 | { |
| 1355 | | − write_spec_ctrl_current(x86_spec_ctrl_base); |
| 1361 | + write_spec_ctrl_current(x86_spec_ctrl_base, true); |
| 1356 | 1362 | } |
| 1357 | 1363 | |
| 1358 | 1364 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
| @@ -1595,7 +1601,7 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void) · 236 unmodified lines |
| 1595 | 1601 | x86_amd_ssb_disable(); |
| 1596 | 1602 | } else { |
| 1597 | 1603 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
| 1598 | | − write_spec_ctrl_current(x86_spec_ctrl_base); |
| 1604 | + write_spec_ctrl_current(x86_spec_ctrl_base, true); |
| 1599 | 1605 | } |
| 1600 | 1606 | } |
| 1601 | 1607 | |
| @@ -1846,7 +1852,7 @@ int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) · 244 unmodified lines |
| 1846 | 1852 | void x86_spec_ctrl_setup_ap(void) |
| 1847 | 1853 | { |
| 1848 | 1854 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
| 1849 | | − write_spec_ctrl_current(x86_spec_ctrl_base); |
| 1855 | + write_spec_ctrl_current(x86_spec_ctrl_base, true); |
| 1850 | 1856 | |
| 1851 | 1857 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) |
| 1852 | 1858 | x86_amd_ssb_disable(); |