History

Merge tag 'devicetree-fixes-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull Devicetree fixes from Rob Herring: "Fix several warnings/errors in validation of binding schemas" * tag 'devicetree-fixes-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: dt-bindings: pinctrl: stm32: Fix missing 'clocks' property in examples dt-bindings: iio: ad7124: Fix dtc warnings in example dt-bindings: iio: avia-hx711: Fix avdd-supply typo in example dt-bindings: pinctrl: aspeed: Fix AST2500 example errors dt-bindings: pinctrl: aspeed: Fix 'compatible' schema errors dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodes dt-bindings: Ensure child nodes are of type 'object'

Linus Torvalds committed 7 years ago

Commit c7bf0a02 parents d6788eb e2297f711 files · +119 −122Browse files

Unified · Split

11 files
  1. Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml +1 −0
  2. Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml +38 −33
  3. Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml +1 −1
  4. Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml +1 −0
  5. Documentation/devicetree/bindings/mtd/nand-controller.yaml +1 −0
  6. Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml +3 −1
  7. Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +4 −5
  8. Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +7 −0
  9. Documentation/devicetree/bindings/riscv/cpus.yaml +61 −82
  10. Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml +1 −0
  11. Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +1 −0
Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml+1−0
@@ -42,6 +42,7 @@ properties: · 41 unmodified lines
42 42
43patternProperties:43patternProperties:
44 "^.*@[0-9a-fA-F]+$":44 "^.*@[0-9a-fA-F]+$":
45 type: object
45 properties:46 properties:
46 reg:47 reg:
47 maxItems: 148 maxItems: 1
Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml+38−33
@@ -114,42 +114,47 @@ patternProperties: · 113 unmodified lines
114 114
115examples:115examples:
116 - |116 - |
117 adc@0 {117 spi {
118 compatible = "adi,ad7124-4";
119 reg = <0>;
120 spi-max-frequency = <5000000>;
121 interrupts = <25 2>;
122 interrupt-parent = <&gpio>;
123 refin1-supply = <&adc_vref>;
124 clocks = <&ad7124_mclk>;
125 clock-names = "mclk";
126
127 #address-cells = <1>;118 #address-cells = <1>;
128 #size-cells = <0>;119 #size-cells = <0>;
129 120
130 channel@0 {121 adc@0 {
122 compatible = "adi,ad7124-4";
131 reg = <0>;123 reg = <0>;
132 diff-channels = <0 1>;124 spi-max-frequency = <5000000>;
133 adi,reference-select = <0>;125 interrupts = <25 2>;
134 adi,buffered-positive;126 interrupt-parent = <&gpio>;
135 };127 refin1-supply = <&adc_vref>;
136 128 clocks = <&ad7124_mclk>;
137 channel@1 {129 clock-names = "mclk";
138 reg = <1>;130
139 bipolar;131 #address-cells = <1>;
140 diff-channels = <2 3>;132 #size-cells = <0>;
141 adi,reference-select = <0>;133
142 adi,buffered-positive;134 channel@0 {
143 adi,buffered-negative;135 reg = <0>;
144 };136 diff-channels = <0 1>;
145 137 adi,reference-select = <0>;
146 channel@2 {138 adi,buffered-positive;
147 reg = <2>;139 };
148 diff-channels = <4 5>;140
149 };141 channel@1 {
150 142 reg = <1>;
151 channel@3 {143 bipolar;
152 reg = <3>;144 diff-channels = <2 3>;
153 diff-channels = <6 7>;145 adi,reference-select = <0>;
146 adi,buffered-positive;
147 adi,buffered-negative;
148 };
149
150 channel@2 {
151 reg = <2>;
152 diff-channels = <4 5>;
153 };
154
155 channel@3 {
156 reg = <3>;
157 diff-channels = <6 7>;
158 };
154 };159 };
155 };160 };
Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml+1−1
@@ -61,6 +61,6 @@ examples: · 60 unmodified lines
61 compatible = "avia,hx711";61 compatible = "avia,hx711";
62 sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;62 sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
63 dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;63 dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
64 avdd-suppy = <&avdd>;64 avdd-supply = <&avdd>;
65 clock-frequency = <100000>;65 clock-frequency = <100000>;
66 };66 };
Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml+1−0
@@ -55,6 +55,7 @@ patternProperties: · 54 unmodified lines
55 "^pinctrl-[0-9]+$": true55 "^pinctrl-[0-9]+$": true
56 56
57 "^nand@[a-f0-9]+$":57 "^nand@[a-f0-9]+$":
58 type: object
58 properties:59 properties:
59 reg:60 reg:
60 minimum: 061 minimum: 0
Documentation/devicetree/bindings/mtd/nand-controller.yaml+1−0
@@ -40,6 +40,7 @@ properties: · 39 unmodified lines
40 40
41patternProperties:41patternProperties:
42 "^nand@[a-f0-9]$":42 "^nand@[a-f0-9]$":
43 type: object
43 properties:44 properties:
44 reg:45 reg:
45 description:46 description:
Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml+3−1
@@ -22,7 +22,9 @@ description: |+ · 21 unmodified lines
22 22
23properties:23properties:
24 compatible:24 compatible:
25 enum: [ aspeed,ast2400-pinctrl, aspeed,g4-pinctrl ]25 enum:
26 - aspeed,ast2400-pinctrl
27 - aspeed,g4-pinctrl
26 28
27patternProperties:29patternProperties:
28 '^.*$':30 '^.*$':
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml+4−5
@@ -22,7 +22,9 @@ description: |+ · 21 unmodified lines
22 22
23properties:23properties:
24 compatible:24 compatible:
25 enum: [ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl ]25 enum:
26 - aspeed,ast2500-pinctrl
27 - aspeed,g5-pinctrl
26 aspeed,external-nodes:28 aspeed,external-nodes:
27 minItems: 229 minItems: 2
28 maxItems: 230 maxItems: 2
@@ -74,9 +76,6 @@ required: · 45 unmodified lines
74 76
75examples:77examples:
76 - |78 - |
77 compatible = "simple-bus";
78 ranges;
79
80 apb {79 apb {
81 compatible = "simple-bus";80 compatible = "simple-bus";
82 #address-cells = <1>;81 #address-cells = <1>;
@@ -89,7 +88,7 @@ examples: · 6 unmodified lines
89 88
90 pinctrl: pinctrl {89 pinctrl: pinctrl {
91 compatible = "aspeed,g5-pinctrl";90 compatible = "aspeed,g5-pinctrl";
92 aspeed,external-nodes = <&gfx &lhc>;91 aspeed,external-nodes = <&gfx>, <&lhc>;
93 92
94 pinctrl_i2c3_default: i2c3_default {93 pinctrl_i2c3_default: i2c3_default {
95 function = "I2C3";94 function = "I2C3";
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml+7−0
@@ -55,6 +55,7 @@ properties: · 54 unmodified lines
55 55
56patternProperties:56patternProperties:
57 '^gpio@[0-9a-f]*$':57 '^gpio@[0-9a-f]*$':
58 type: object
58 properties:59 properties:
59 gpio-controller: true60 gpio-controller: true
60 '#gpio-cells':61 '#gpio-cells':
@@ -113,8 +114,10 @@ patternProperties: · 52 unmodified lines
113 - st,bank-name114 - st,bank-name
114 115
115 '-[0-9]*$':116 '-[0-9]*$':
117 type: object
116 patternProperties:118 patternProperties:
117 '^pins':119 '^pins':
120 type: object
118 description: |121 description: |
119 A pinctrl node should contain at least one subnode representing the122 A pinctrl node should contain at least one subnode representing the
120 pinctrl group available on the machine. Each subnode will list the123 pinctrl group available on the machine. Each subnode will list the
@@ -194,6 +197,7 @@ required: · 73 unmodified lines
194examples:197examples:
195 - |198 - |
196 #include <dt-bindings/pinctrl/stm32-pinfunc.h>199 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
200 #include <dt-bindings/mfd/stm32f4-rcc.h>
197 //Example 1201 //Example 1
198 pinctrl@40020000 {202 pinctrl@40020000 {
199 #address-cells = <1>;203 #address-cells = <1>;
@@ -207,6 +211,7 @@ examples: · 7 unmodified lines
207 #gpio-cells = <2>;211 #gpio-cells = <2>;
208 reg = <0x0 0x400>;212 reg = <0x0 0x400>;
209 resets = <&reset_ahb1 0>;213 resets = <&reset_ahb1 0>;
214 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
210 st,bank-name = "GPIOA";215 st,bank-name = "GPIOA";
211 };216 };
212 };217 };
@@ -224,6 +229,7 @@ examples: · 11 unmodified lines
224 #gpio-cells = <2>;229 #gpio-cells = <2>;
225 reg = <0x1000 0x400>;230 reg = <0x1000 0x400>;
226 resets = <&reset_ahb1 0>;231 resets = <&reset_ahb1 0>;
232 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
227 st,bank-name = "GPIOB";233 st,bank-name = "GPIOB";
228 gpio-ranges = <&pinctrl 0 0 16>;234 gpio-ranges = <&pinctrl 0 0 16>;
229 };235 };
@@ -233,6 +239,7 @@ examples: · 3 unmodified lines
233 #gpio-cells = <2>;239 #gpio-cells = <2>;
234 reg = <0x2000 0x400>;240 reg = <0x2000 0x400>;
235 resets = <&reset_ahb1 0>;241 resets = <&reset_ahb1 0>;
242 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
236 st,bank-name = "GPIOC";243 st,bank-name = "GPIOC";
237 ngpios = <5>;244 ngpios = <5>;
238 gpio-ranges = <&pinctrl 0 16 3>,245 gpio-ranges = <&pinctrl 0 16 3>,
Documentation/devicetree/bindings/riscv/cpus.yaml+61−82
@@ -10,97 +10,76 @@ maintainers: · 9 unmodified lines
10 - Paul Walmsley <paul.walmsley@sifive.com>10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>
12 12
13allOf:
14 - $ref: /schemas/cpus.yaml#
15
16properties:13properties:
17 $nodename:14 compatible:
18 const: cpus15 items:
19 description: Container of cpu nodes16 - enum:
20 17 - sifive,rocket0
21 '#address-cells':18 - sifive,e5
22 const: 119 - sifive,e51
23 description: |20 - sifive,u54-mc
24 A single unsigned 32-bit integer uniquely identifies each RISC-V21 - sifive,u54
25 hart in a system. (See the "reg" node under the "cpu" node,22 - sifive,u5
26 below).23 - const: riscv
27 24 description:
28 '#size-cells':25 Identifies that the hart uses the RISC-V instruction set
29 const: 026 and identifies the type of the hart.
27
28 mmu-type:
29 allOf:
30 - $ref: "/schemas/types.yaml#/definitions/string"
31 - enum:
32 - riscv,sv32
33 - riscv,sv39
34 - riscv,sv48
35 description:
36 Identifies the MMU address translation mode used on this
37 hart. These values originate from the RISC-V Privileged
38 Specification document, available from
39 https://riscv.org/specifications/
40
41 riscv,isa:
42 allOf:
43 - $ref: "/schemas/types.yaml#/definitions/string"
44 - enum:
45 - rv64imac
46 - rv64imafdc
47 description:
48 Identifies the specific RISC-V instruction set architecture
49 supported by the hart. These are documented in the RISC-V
50 User-Level ISA document, available from
51 https://riscv.org/specifications/
52
53 timebase-frequency:
54 type: integer
55 minimum: 1
56 description:
57 Specifies the clock frequency of the system timer in Hz.
58 This value is common to all harts on a single system image.
59
60 interrupt-controller:
61 type: object
62 description: Describes the CPU's local interrupt controller
30 63
31patternProperties:
32 '^cpu@[0-9a-f]+$':
33 properties:64 properties:
34 compatible:65 '#interrupt-cells':
35 type: array66 const: 1
36 items:
37 - enum:
38 - sifive,rocket0
39 - sifive,e5
40 - sifive,e51
41 - sifive,u54-mc
42 - sifive,u54
43 - sifive,u5
44 - const: riscv
45 description:
46 Identifies that the hart uses the RISC-V instruction set
47 and identifies the type of the hart.
48
49 mmu-type:
50 allOf:
51 - $ref: "/schemas/types.yaml#/definitions/string"
52 - enum:
53 - riscv,sv32
54 - riscv,sv39
55 - riscv,sv48
56 description:
57 Identifies the MMU address translation mode used on this
58 hart. These values originate from the RISC-V Privileged
59 Specification document, available from
60 https://riscv.org/specifications/
61
62 riscv,isa:
63 allOf:
64 - $ref: "/schemas/types.yaml#/definitions/string"
65 - enum:
66 - rv64imac
67 - rv64imafdc
68 description:
69 Identifies the specific RISC-V instruction set architecture
70 supported by the hart. These are documented in the RISC-V
71 User-Level ISA document, available from
72 https://riscv.org/specifications/
73 67
74 timebase-frequency:68 compatible:
75 type: integer69 const: riscv,cpu-intc
76 minimum: 1
77 description:
78 Specifies the clock frequency of the system timer in Hz.
79 This value is common to all harts on a single system image.
80
81 interrupt-controller:
82 type: object
83 description: Describes the CPU's local interrupt controller
84
85 properties:
86 '#interrupt-cells':
87 const: 1
88
89 compatible:
90 const: riscv,cpu-intc
91
92 interrupt-controller: true
93 70
94 required:71 interrupt-controller: true
95 - '#interrupt-cells'
96 - compatible
97 - interrupt-controller
98 72
99 required:73 required:
100 - riscv,isa74 - '#interrupt-cells'
101 - timebase-frequency75 - compatible
102 - interrupt-controller76 - interrupt-controller
103 77
78required:
79 - riscv,isa
80 - timebase-frequency
81 - interrupt-controller
82
104examples:83examples:
105 - |84 - |
106 // Example 1: SiFive Freedom U540G Development Kit85 // Example 1: SiFive Freedom U540G Development Kit
Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml+1−0
@@ -50,6 +50,7 @@ properties: · 49 unmodified lines
50 50
51patternProperties:51patternProperties:
52 "^.*@[0-9a-f]+":52 "^.*@[0-9a-f]+":
53 type: object
53 properties:54 properties:
54 reg:55 reg:
55 items:56 items:
Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml+1−0
@@ -55,6 +55,7 @@ properties: · 54 unmodified lines
55 55
56patternProperties:56patternProperties:
57 "^.*@[0-9a-f]+":57 "^.*@[0-9a-f]+":
58 type: object
58 properties:59 properties:
59 reg:60 reg:
60 items:61 items:

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