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Merge tag 'drm-misc-next-2024-12-05' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next

[airlied: handle module ns conflict] drm-misc-next for 6.14: UAPI Changes: Cross-subsystem Changes: Core Changes: - Remove driver date from drm_driver Driver Changes: - amdxdna: New driver! - ivpu: Fix qemu crash when using passthrough - nouveau: expose GSP-RM logging buffers via debugfs - panfrost: Add MT8188 Mali-G57 MC3 support - panthor: misc improvements, - rockchip: Gamma LUT support - tidss: Misc improvements - virtio: convert to helpers, add prime support for scanout buffers - v3d: Add DRM_IOCTL_V3D_PERFMON_SET_GLOBAL - vc4: Add support for BCM2712 - vkms: Improvements all across the board - panels: - Introduce backlight quirks infrastructure - New panels: KDB KD116N2130B12 Signed-off-by: Dave Airlie <airlied@redhat.com>

Dave Airlie committed 1 year ago

Commit c7d6cb42 parents fac04ef cb2e1c2249 files · +14126 −1203Browse files

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  1. include/uapi/drm/amdxdna_accel.h +436 −0
  2. include/uapi/drm/v3d_drm.h +18 −0
include/uapi/drm/amdxdna_accel.h+436−0
@@ -0,0 +1,436 @@
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
4 */
5
6#ifndef _UAPI_AMDXDNA_ACCEL_H_
7#define _UAPI_AMDXDNA_ACCEL_H_
8
9#include <linux/stddef.h>
10#include "drm.h"
11
12#if defined(__cplusplus)
13extern "C" {
14#endif
15
16#define AMDXDNA_INVALID_CMD_HANDLE (~0UL)
17#define AMDXDNA_INVALID_ADDR (~0UL)
18#define AMDXDNA_INVALID_CTX_HANDLE 0
19#define AMDXDNA_INVALID_BO_HANDLE 0
20#define AMDXDNA_INVALID_FENCE_HANDLE 0
21
22enum amdxdna_device_type {
23 AMDXDNA_DEV_TYPE_UNKNOWN = -1,
24 AMDXDNA_DEV_TYPE_KMQ,
25};
26
27enum amdxdna_drm_ioctl_id {
28 DRM_AMDXDNA_CREATE_HWCTX,
29 DRM_AMDXDNA_DESTROY_HWCTX,
30 DRM_AMDXDNA_CONFIG_HWCTX,
31 DRM_AMDXDNA_CREATE_BO,
32 DRM_AMDXDNA_GET_BO_INFO,
33 DRM_AMDXDNA_SYNC_BO,
34 DRM_AMDXDNA_EXEC_CMD,
35 DRM_AMDXDNA_GET_INFO,
36};
37
38/**
39 * struct qos_info - QoS information for driver.
40 * @gops: Giga operations per second.
41 * @fps: Frames per second.
42 * @dma_bandwidth: DMA bandwidtha.
43 * @latency: Frame response latency.
44 * @frame_exec_time: Frame execution time.
45 * @priority: Request priority.
46 *
47 * User program can provide QoS hints to driver.
48 */
49struct amdxdna_qos_info {
50 __u32 gops;
51 __u32 fps;
52 __u32 dma_bandwidth;
53 __u32 latency;
54 __u32 frame_exec_time;
55 __u32 priority;
56};
57
58/**
59 * struct amdxdna_drm_create_hwctx - Create hardware context.
60 * @ext: MBZ.
61 * @ext_flags: MBZ.
62 * @qos_p: Address of QoS info.
63 * @umq_bo: BO handle for user mode queue(UMQ).
64 * @log_buf_bo: BO handle for log buffer.
65 * @max_opc: Maximum operations per cycle.
66 * @num_tiles: Number of AIE tiles.
67 * @mem_size: Size of AIE tile memory.
68 * @umq_doorbell: Returned offset of doorbell associated with UMQ.
69 * @handle: Returned hardware context handle.
70 * @syncobj_handle: Returned syncobj handle for command completion.
71 */
72struct amdxdna_drm_create_hwctx {
73 __u64 ext;
74 __u64 ext_flags;
75 __u64 qos_p;
76 __u32 umq_bo;
77 __u32 log_buf_bo;
78 __u32 max_opc;
79 __u32 num_tiles;
80 __u32 mem_size;
81 __u32 umq_doorbell;
82 __u32 handle;
83 __u32 syncobj_handle;
84};
85
86/**
87 * struct amdxdna_drm_destroy_hwctx - Destroy hardware context.
88 * @handle: Hardware context handle.
89 * @pad: Structure padding.
90 */
91struct amdxdna_drm_destroy_hwctx {
92 __u32 handle;
93 __u32 pad;
94};
95
96/**
97 * struct amdxdna_cu_config - configuration for one CU
98 * @cu_bo: CU configuration buffer bo handle.
99 * @cu_func: Function of a CU.
100 * @pad: Structure padding.
101 */
102struct amdxdna_cu_config {
103 __u32 cu_bo;
104 __u8 cu_func;
105 __u8 pad[3];
106};
107
108/**
109 * struct amdxdna_hwctx_param_config_cu - configuration for CUs in hardware context
110 * @num_cus: Number of CUs to configure.
111 * @pad: Structure padding.
112 * @cu_configs: Array of CU configurations of struct amdxdna_cu_config.
113 */
114struct amdxdna_hwctx_param_config_cu {
115 __u16 num_cus;
116 __u16 pad[3];
117 struct amdxdna_cu_config cu_configs[] __counted_by(num_cus);
118};
119
120enum amdxdna_drm_config_hwctx_param {
121 DRM_AMDXDNA_HWCTX_CONFIG_CU,
122 DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF,
123 DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF,
124 DRM_AMDXDNA_HWCTX_CONFIG_NUM
125};
126
127/**
128 * struct amdxdna_drm_config_hwctx - Configure hardware context.
129 * @handle: hardware context handle.
130 * @param_type: Value in enum amdxdna_drm_config_hwctx_param. Specifies the
131 * structure passed in via param_val.
132 * @param_val: A structure specified by the param_type struct member.
133 * @param_val_size: Size of the parameter buffer pointed to by the param_val.
134 * If param_val is not a pointer, driver can ignore this.
135 * @pad: Structure padding.
136 *
137 * Note: if the param_val is a pointer pointing to a buffer, the maximum size
138 * of the buffer is 4KiB(PAGE_SIZE).
139 */
140struct amdxdna_drm_config_hwctx {
141 __u32 handle;
142 __u32 param_type;
143 __u64 param_val;
144 __u32 param_val_size;
145 __u32 pad;
146};
147
148enum amdxdna_bo_type {
149 AMDXDNA_BO_INVALID = 0,
150 AMDXDNA_BO_SHMEM,
151 AMDXDNA_BO_DEV_HEAP,
152 AMDXDNA_BO_DEV,
153 AMDXDNA_BO_CMD,
154};
155
156/**
157 * struct amdxdna_drm_create_bo - Create a buffer object.
158 * @flags: Buffer flags. MBZ.
159 * @vaddr: User VA of buffer if applied. MBZ.
160 * @size: Size in bytes.
161 * @type: Buffer type.
162 * @handle: Returned DRM buffer object handle.
163 */
164struct amdxdna_drm_create_bo {
165 __u64 flags;
166 __u64 vaddr;
167 __u64 size;
168 __u32 type;
169 __u32 handle;
170};
171
172/**
173 * struct amdxdna_drm_get_bo_info - Get buffer object information.
174 * @ext: MBZ.
175 * @ext_flags: MBZ.
176 * @handle: DRM buffer object handle.
177 * @pad: Structure padding.
178 * @map_offset: Returned DRM fake offset for mmap().
179 * @vaddr: Returned user VA of buffer. 0 in case user needs mmap().
180 * @xdna_addr: Returned XDNA device virtual address.
181 */
182struct amdxdna_drm_get_bo_info {
183 __u64 ext;
184 __u64 ext_flags;
185 __u32 handle;
186 __u32 pad;
187 __u64 map_offset;
188 __u64 vaddr;
189 __u64 xdna_addr;
190};
191
192/**
193 * struct amdxdna_drm_sync_bo - Sync buffer object.
194 * @handle: Buffer object handle.
195 * @direction: Direction of sync, can be from device or to device.
196 * @offset: Offset in the buffer to sync.
197 * @size: Size in bytes.
198 */
199struct amdxdna_drm_sync_bo {
200 __u32 handle;
201#define SYNC_DIRECT_TO_DEVICE 0U
202#define SYNC_DIRECT_FROM_DEVICE 1U
203 __u32 direction;
204 __u64 offset;
205 __u64 size;
206};
207
208enum amdxdna_cmd_type {
209 AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0,
210 AMDXDNA_CMD_SUBMIT_DEPENDENCY,
211 AMDXDNA_CMD_SUBMIT_SIGNAL,
212};
213
214/**
215 * struct amdxdna_drm_exec_cmd - Execute command.
216 * @ext: MBZ.
217 * @ext_flags: MBZ.
218 * @hwctx: Hardware context handle.
219 * @type: One of command type in enum amdxdna_cmd_type.
220 * @cmd_handles: Array of command handles or the command handle itself
221 * in case of just one.
222 * @args: Array of arguments for all command handles.
223 * @cmd_count: Number of command handles in the cmd_handles array.
224 * @arg_count: Number of arguments in the args array.
225 * @seq: Returned sequence number for this command.
226 */
227struct amdxdna_drm_exec_cmd {
228 __u64 ext;
229 __u64 ext_flags;
230 __u32 hwctx;
231 __u32 type;
232 __u64 cmd_handles;
233 __u64 args;
234 __u32 cmd_count;
235 __u32 arg_count;
236 __u64 seq;
237};
238
239/**
240 * struct amdxdna_drm_query_aie_status - Query the status of the AIE hardware
241 * @buffer: The user space buffer that will return the AIE status.
242 * @buffer_size: The size of the user space buffer.
243 * @cols_filled: A bitmap of AIE columns whose data has been returned in the buffer.
244 */
245struct amdxdna_drm_query_aie_status {
246 __u64 buffer; /* out */
247 __u32 buffer_size; /* in */
248 __u32 cols_filled; /* out */
249};
250
251/**
252 * struct amdxdna_drm_query_aie_version - Query the version of the AIE hardware
253 * @major: The major version number.
254 * @minor: The minor version number.
255 */
256struct amdxdna_drm_query_aie_version {
257 __u32 major; /* out */
258 __u32 minor; /* out */
259};
260
261/**
262 * struct amdxdna_drm_query_aie_tile_metadata - Query the metadata of AIE tile (core, mem, shim)
263 * @row_count: The number of rows.
264 * @row_start: The starting row number.
265 * @dma_channel_count: The number of dma channels.
266 * @lock_count: The number of locks.
267 * @event_reg_count: The number of events.
268 * @pad: Structure padding.
269 */
270struct amdxdna_drm_query_aie_tile_metadata {
271 __u16 row_count;
272 __u16 row_start;
273 __u16 dma_channel_count;
274 __u16 lock_count;
275 __u16 event_reg_count;
276 __u16 pad[3];
277};
278
279/**
280 * struct amdxdna_drm_query_aie_metadata - Query the metadata of the AIE hardware
281 * @col_size: The size of a column in bytes.
282 * @cols: The total number of columns.
283 * @rows: The total number of rows.
284 * @version: The version of the AIE hardware.
285 * @core: The metadata for all core tiles.
286 * @mem: The metadata for all mem tiles.
287 * @shim: The metadata for all shim tiles.
288 */
289struct amdxdna_drm_query_aie_metadata {
290 __u32 col_size;
291 __u16 cols;
292 __u16 rows;
293 struct amdxdna_drm_query_aie_version version;
294 struct amdxdna_drm_query_aie_tile_metadata core;
295 struct amdxdna_drm_query_aie_tile_metadata mem;
296 struct amdxdna_drm_query_aie_tile_metadata shim;
297};
298
299/**
300 * struct amdxdna_drm_query_clock - Metadata for a clock
301 * @name: The clock name.
302 * @freq_mhz: The clock frequency.
303 * @pad: Structure padding.
304 */
305struct amdxdna_drm_query_clock {
306 __u8 name[16];
307 __u32 freq_mhz;
308 __u32 pad;
309};
310
311/**
312 * struct amdxdna_drm_query_clock_metadata - Query metadata for clocks
313 * @mp_npu_clock: The metadata for MP-NPU clock.
314 * @h_clock: The metadata for H clock.
315 */
316struct amdxdna_drm_query_clock_metadata {
317 struct amdxdna_drm_query_clock mp_npu_clock;
318 struct amdxdna_drm_query_clock h_clock;
319};
320
321enum amdxdna_sensor_type {
322 AMDXDNA_SENSOR_TYPE_POWER
323};
324
325/**
326 * struct amdxdna_drm_query_sensor - The data for single sensor.
327 * @label: The name for a sensor.
328 * @input: The current value of the sensor.
329 * @max: The maximum value possible for the sensor.
330 * @average: The average value of the sensor.
331 * @highest: The highest recorded sensor value for this driver load for the sensor.
332 * @status: The sensor status.
333 * @units: The sensor units.
334 * @unitm: Translates value member variables into the correct unit via (pow(10, unitm) * value).
335 * @type: The sensor type from enum amdxdna_sensor_type.
336 * @pad: Structure padding.
337 */
338struct amdxdna_drm_query_sensor {
339 __u8 label[64];
340 __u32 input;
341 __u32 max;
342 __u32 average;
343 __u32 highest;
344 __u8 status[64];
345 __u8 units[16];
346 __s8 unitm;
347 __u8 type;
348 __u8 pad[6];
349};
350
351/**
352 * struct amdxdna_drm_query_hwctx - The data for single context.
353 * @context_id: The ID for this context.
354 * @start_col: The starting column for the partition assigned to this context.
355 * @num_col: The number of columns in the partition assigned to this context.
356 * @pad: Structure padding.
357 * @pid: The Process ID of the process that created this context.
358 * @command_submissions: The number of commands submitted to this context.
359 * @command_completions: The number of commands completed by this context.
360 * @migrations: The number of times this context has been moved to a different partition.
361 * @preemptions: The number of times this context has been preempted by another context in the
362 * same partition.
363 * @errors: The errors for this context.
364 */
365struct amdxdna_drm_query_hwctx {
366 __u32 context_id;
367 __u32 start_col;
368 __u32 num_col;
369 __u32 pad;
370 __s64 pid;
371 __u64 command_submissions;
372 __u64 command_completions;
373 __u64 migrations;
374 __u64 preemptions;
375 __u64 errors;
376};
377
378enum amdxdna_drm_get_param {
379 DRM_AMDXDNA_QUERY_AIE_STATUS,
380 DRM_AMDXDNA_QUERY_AIE_METADATA,
381 DRM_AMDXDNA_QUERY_AIE_VERSION,
382 DRM_AMDXDNA_QUERY_CLOCK_METADATA,
383 DRM_AMDXDNA_QUERY_SENSORS,
384 DRM_AMDXDNA_QUERY_HW_CONTEXTS,
385 DRM_AMDXDNA_NUM_GET_PARAM,
386};
387
388/**
389 * struct amdxdna_drm_get_info - Get some information from the AIE hardware.
390 * @param: Value in enum amdxdna_drm_get_param. Specifies the structure passed in the buffer.
391 * @buffer_size: Size of the input buffer. Size needed/written by the kernel.
392 * @buffer: A structure specified by the param struct member.
393 */
394struct amdxdna_drm_get_info {
395 __u32 param; /* in */
396 __u32 buffer_size; /* in/out */
397 __u64 buffer; /* in/out */
398};
399
400#define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \
401 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \
402 struct amdxdna_drm_create_hwctx)
403
404#define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \
405 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \
406 struct amdxdna_drm_destroy_hwctx)
407
408#define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \
409 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \
410 struct amdxdna_drm_config_hwctx)
411
412#define DRM_IOCTL_AMDXDNA_CREATE_BO \
413 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \
414 struct amdxdna_drm_create_bo)
415
416#define DRM_IOCTL_AMDXDNA_GET_BO_INFO \
417 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \
418 struct amdxdna_drm_get_bo_info)
419
420#define DRM_IOCTL_AMDXDNA_SYNC_BO \
421 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \
422 struct amdxdna_drm_sync_bo)
423
424#define DRM_IOCTL_AMDXDNA_EXEC_CMD \
425 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \
426 struct amdxdna_drm_exec_cmd)
427
428#define DRM_IOCTL_AMDXDNA_GET_INFO \
429 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \
430 struct amdxdna_drm_get_info)
431
432#if defined(__cplusplus)
433} /* extern c end */
434#endif
435
436#endif /* _UAPI_AMDXDNA_ACCEL_H_ */
include/uapi/drm/v3d_drm.h+18−0
@@ -43,6 +43,7 @@ extern "C" { · 42 unmodified lines
43#define DRM_V3D_PERFMON_GET_VALUES 0x0a43#define DRM_V3D_PERFMON_GET_VALUES 0x0a
44#define DRM_V3D_SUBMIT_CPU 0x0b44#define DRM_V3D_SUBMIT_CPU 0x0b
45#define DRM_V3D_PERFMON_GET_COUNTER 0x0c45#define DRM_V3D_PERFMON_GET_COUNTER 0x0c
46#define DRM_V3D_PERFMON_SET_GLOBAL 0x0d
46 47
47#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)48#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
48#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)49#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
@@ -61,6 +62,8 @@ extern "C" { · 12 unmodified lines
61#define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu)62#define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu)
62#define DRM_IOCTL_V3D_PERFMON_GET_COUNTER DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_COUNTER, \63#define DRM_IOCTL_V3D_PERFMON_GET_COUNTER DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_COUNTER, \
63 struct drm_v3d_perfmon_get_counter)64 struct drm_v3d_perfmon_get_counter)
65#define DRM_IOCTL_V3D_PERFMON_SET_GLOBAL DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_PERFMON_SET_GLOBAL, \
66 struct drm_v3d_perfmon_set_global)
64 67
65#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x0168#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
66#define DRM_V3D_SUBMIT_EXTENSION 0x0269#define DRM_V3D_SUBMIT_EXTENSION 0x02
@@ -766,6 +769,21 @@ struct drm_v3d_perfmon_get_counter { · 699 unmodified lines
766 __u8 reserved[7];769 __u8 reserved[7];
767};770};
768 771
772#define DRM_V3D_PERFMON_CLEAR_GLOBAL 0x0001
773
774/**
775 * struct drm_v3d_perfmon_set_global - ioctl to define a global performance
776 * monitor
777 *
778 * The global performance monitor will be used for all jobs. If a global
779 * performance monitor is defined, jobs with a self-defined performance
780 * monitor won't be allowed.
781 */
782struct drm_v3d_perfmon_set_global {
783 __u32 flags;
784 __u32 id;
785};
786
769#if defined(__cplusplus)787#if defined(__cplusplus)
770}788}
771#endif789#endif