RISC-V: Some Svpbmt fixes

Some additionals comments and notes from autobuilders received after the series got applied, warranted some changes. * commit '924cbb8cbe3460ea192e6243017ceb0ceb255b1b': riscv: Improve description for RISCV_ISA_SVPBMT Kconfig symbol riscv: drop cpufeature_apply_feature tracking variable riscv: fix dependency for t-head errata

Palmer Dabbelt committed 4 years ago

Commit c836d9d2 parents a7c1c97 924cbb83 files · +9 −6Browse files

Unified · Split

3 files

arch/riscv/Kconfig +7 −2
arch/riscv/Kconfig.erratas +1 −0
arch/riscv/kernel/cpufeature.c +1 −4

arch/riscv/Kconfig+7−2

 	select RISCV_ALTERNATIVE
 	default y
 	help
-	   Adds support to dynamically detect the presence of the SVPBMT extension
+	   Adds support to dynamically detect the presence of the SVPBMT
-	   (Supervisor-mode: page-based memory types) and enable its usage.
+	   ISA-extension (Supervisor-mode: page-based memory types) and
+	   enable its usage.
+	   The memory type for a page contains a combination of attributes
+	   that indicate the cacheability, idempotency, and ordering
+	   properties for access to that page.
 	   The SVPBMT extension is only available on 64Bit cpus.

arch/riscv/Kconfig.erratas+1−0

@@ -35,6 +35,7 @@ config ERRATA_SIFIVE_CIP_1200 · 34 unmodified lines
35		35
36	config ERRATA_THEAD	36	config ERRATA_THEAD
37	bool "T-HEAD errata"	37	bool "T-HEAD errata"
		38	depends on !XIP_KERNEL
38	select RISCV_ALTERNATIVE	39	select RISCV_ALTERNATIVE
39	help	40	help
40	All T-HEAD errata Kconfig depend on this Kconfig. Disabling	41	All T-HEAD errata Kconfig depend on this Kconfig. Disabling

arch/riscv/kernel/cpufeature.c+1−4

 						  unsigned int stage)
 {
 	u32 cpu_req_feature = cpufeature_probe(stage);
-	u32 cpu_apply_feature = 0;
 	struct alt_entry *alt;
 	u32 tmp;
 		}
 		tmp = (1U << alt->errata_id);
-		if (cpu_req_feature & tmp) {
+		if (cpu_req_feature & tmp)
 			patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
-			cpu_apply_feature |= tmp;
-		}
 	}
 }
 #endif