Pull drm updates from Dave Airlie: "There is a new Qualcomm accel driver for their QAIC, dma-fence got a deadline feature added, lots of refactoring around fbdev emulation, and the usual pre-release hw enablements from AMD and Intel and fixes everywhere. New drivers: - add QAIC acceleration driver dma-buf: - constify kobj_type structs - Reject prime DMA-Buf attachment if get_sg_table is missing. fbdev: - cmdline parser fixes - implement fbdev emulation for GEM DMA drivers - always use shadow buffer in fbdev emulation helpers dma-fence: - add deadline hint to fences - signal private stub fence core: - improve DisplayID 2.0 and EDID parsing - add gem eviction function + callback - prep to convert shmem helper to GEM resv lock - move suballocator from radeon/amdgpu to core for Xe - HPD polling fixes - Documentation improvements - Add atomic enable_plane callback - use tgid instead of pid for client tracking - DP: Add SDP Error Detection Configuration Register - Add prime import/export to vram-helper - use pci aperture helpers in more drivers panel: - Radxa 8/10HD support - Samsung AMD495QA01 support - Elida KD50T048A - Sony TD4353 - Novatek NT36523 - STARRY 2081101QFH032011-53G - B133UAN01.0 - AUO NE135FBM-N41 i915: - More MTL enabling - fix s/r problems with MEI/PXP - Implement fb_dirty for PSR,FBC,DRRS fixes - Fix eDP+DSI dual panel systems - Fix issue #6333: "list_add corruption" and full system lockup from performance monitoring - Don't use stolen memory or BAR for ring buffers on LLC platforms - Make sure DSM size has correct 1MiB granularity on Gen12+ - Whitelist COMMON_SLICE_CHICKEN3 for UMD access on Gen12+ - Add engine TLB invalidation for Meteorlake - Fix GSC races on driver load/unload on Meteorlake+ - Make kobj_type structures constant - Move fd_install after last use of fence - wm/vblank refactoring - display code refactoring - Create GSC submission targeting HDCP and PXP usages on MTL+ - Enable HDCP2.x via GSC CS - Fix context runtime accounting on sysfs fdinfo for heavy workloads - Use i915 instead of dev_priv insied the file_priv structure - Replace fake flex-array with flexible-array member amdgpu: - Make kobj structures const - Generalize dmabuf import to work with KFD - Add capped/uncapped workload handling for supported APUs - Expose additional memory stats via fdinfo - Register vga_switcheroo for apple-gmux - Initial NBIO7.9, GC 9.4.3, GFXHUB 1.2, MMHUB 1.8 support - Initial DC FAM infrastructure - Link DC backlight to connector device rather than PCI device - Add sysfs nodes for secondary VCN clocks amdkfd: - Make kobj structures const - Support for exporting buffers via dmabuf - Multi-VMA page migration fixes - initial GC 9.4.3 support radeon: - iMac fix - convert to client based fbdev emulation habanalabs: - Add opcodes to the CS ioctl to allow user to stall/resume specific engines inside Gaudi2. - INFO ioctl the amount of device memory that the driver and f/w reserve for themselves. - INFO ioctl a bit-mask of the available rotator engines - INFO ioctl the register's address of the f/w that should be used to trigger interrupts - INFO ioctl two new opcodes to fetch information on h/w and f/w events - Enable graceful reset mechanism for compute-reset. - Align to the latest firmware specs. - Enforce the release order of the compute device and dma-buf. msm: - UBWC decoder programming rework - SM8550, SM8450 bindings update - uapi C++ fix - a3xx and a4xx devfreq support - GPU and GEM updates to avoid allocations which could trigger reclaim (shrinker) in fence signaling path - dma-fence deadline hint support and wait-boost - a640/650 speed bin support cirrus: - convert to regular atomic helpers - add damage clipping mediatek: - 10-bit overlay support - mt8195 support - Only trigger DRM HPD events if bridge is attached - Change the aux retries times when receiving AUX_DEFER rockchip: - add 4K support vc4: - use drm_gem_objects virtio: - allow KMS support to be disabled - add damage clipping vmwgfx: - buffer object lifetime fixes exynos: - move MIPI DSI driver to drm bridge for iMX sharing - use kernel fbdev emulation panfrost: - add support for mali MT81xx devices - add speed binning support lima: - add usage stats tegra: - fbdev client conversion vkms: - Add primary plane positioning support" * tag 'drm-next-2023-04-24' of git://anongit.freedesktop.org/drm/drm: (1495 commits) drm/i915/dp_mst: Fix active port PLL selection for secondary MST streams drm/exynos: Implement fbdev emulation as in-kernel client drm/exynos: Initialize fbdev DRM client drm/exynos: Remove fb_helper from struct exynos_drm_private drm/exynos: Remove struct exynos_drm_fbdev drm/exynos: Remove exynos_gem from struct exynos_drm_fbdev drm/i915: Fix memory leaks in i915 selftests drm/i915: Make intel_get_crtc_new_encoder() less oopsy drm/i915/gt: Avoid out-of-bounds access when loading HuC drm/amdgpu: add some basic elements for multiple XCD case drm/amdgpu: move vmhub out of amdgpu_ring_funcs (v4) Revert "drm/amdgpu: enable ras for mp0 v13_0_10 on SRIOV" drm/amdgpu: add common ip block for GC 9.4.3 drm/amd/display: Add logging when DP link training Clock recovery is Successful drm/amdgpu: add common early init support for GC 9.4.3 drm/amdgpu: switch to v9_4_3 gfx_funcs callbacks for GC 9.4.3 drm/amd/display: Add logging when setting DP sink power state fails drm/amdkfd: Add gfx_target_version for GC 9.4.3 drm/amdkfd: Enable HW_UPDATE_RPTR on GC 9.4.3 drm/amdgpu: reserve the old gc_11_0_*_mes.bin ...
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| @@ -972,6 +972,19 @@ extern "C" { · 971 unmodified lines | ||
| 972 | 972 | #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) |
| 973 | 973 | #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) |
| 974 | 974 | #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) |
| 975 | +/** | |
| 976 | + * DRM_IOCTL_GEM_CLOSE - Close a GEM handle. | |
| 977 | + * | |
| 978 | + * GEM handles are not reference-counted by the kernel. User-space is | |
| 979 | + * responsible for managing their lifetime. For example, if user-space imports | |
| 980 | + * the same memory object twice on the same DRM file description, the same GEM | |
| 981 | + * handle is returned by both imports, and user-space needs to ensure | |
| 982 | + * &DRM_IOCTL_GEM_CLOSE is performed once only. The same situation can happen | |
| 983 | + * when a memory object is allocated, then exported and imported again on the | |
| 984 | + * same DRM file description. The &DRM_IOCTL_MODE_GETFB2 IOCTL is an exception | |
| 985 | + * and always returns fresh new GEM handles even if an existing GEM handle | |
| 986 | + * already refers to the same memory object before the IOCTL is performed. | |
| 987 | + */ | |
| 975 | 988 | #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) |
| 976 | 989 | #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) |
| 977 | 990 | #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) |
| @@ -1012,7 +1025,37 @@ extern "C" { · 34 unmodified lines | ||
| 1012 | 1025 | #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) |
| 1013 | 1026 | #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) |
| 1014 | 1027 | |
| 1028 | +/** | |
| 1029 | + * DRM_IOCTL_PRIME_HANDLE_TO_FD - Convert a GEM handle to a DMA-BUF FD. | |
| 1030 | + * | |
| 1031 | + * User-space sets &drm_prime_handle.handle with the GEM handle to export and | |
| 1032 | + * &drm_prime_handle.flags, and gets back a DMA-BUF file descriptor in | |
| 1033 | + * &drm_prime_handle.fd. | |
| 1034 | + * | |
| 1035 | + * The export can fail for any driver-specific reason, e.g. because export is | |
| 1036 | + * not supported for this specific GEM handle (but might be for others). | |
| 1037 | + * | |
| 1038 | + * Support for exporting DMA-BUFs is advertised via &DRM_PRIME_CAP_EXPORT. | |
| 1039 | + */ | |
| 1015 | 1040 | #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) |
| 1041 | +/** | |
| 1042 | + * DRM_IOCTL_PRIME_FD_TO_HANDLE - Convert a DMA-BUF FD to a GEM handle. | |
| 1043 | + * | |
| 1044 | + * User-space sets &drm_prime_handle.fd with a DMA-BUF file descriptor to | |
| 1045 | + * import, and gets back a GEM handle in &drm_prime_handle.handle. | |
| 1046 | + * &drm_prime_handle.flags is unused. | |
| 1047 | + * | |
| 1048 | + * If an existing GEM handle refers to the memory object backing the DMA-BUF, | |
| 1049 | + * that GEM handle is returned. Therefore user-space which needs to handle | |
| 1050 | + * arbitrary DMA-BUFs must have a user-space lookup data structure to manually | |
| 1051 | + * reference-count duplicated GEM handles. For more information see | |
| 1052 | + * &DRM_IOCTL_GEM_CLOSE. | |
| 1053 | + * | |
| 1054 | + * The import can fail for any driver-specific reason, e.g. because import is | |
| 1055 | + * only supported for DMA-BUFs allocated on this DRM device. | |
| 1056 | + * | |
| 1057 | + * Support for importing DMA-BUFs is advertised via &DRM_PRIME_CAP_IMPORT. | |
| 1058 | + */ | |
| 1016 | 1059 | #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) |
| 1017 | 1060 | |
| 1018 | 1061 | #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) |
| @@ -1104,8 +1147,13 @@ extern "C" { · 85 unmodified lines | ||
| 1104 | 1147 | * struct as the output. |
| 1105 | 1148 | * |
| 1106 | 1149 | * If the client is DRM master or has &CAP_SYS_ADMIN, &drm_mode_fb_cmd2.handles |
| 1107 | − * will be filled with GEM buffer handles. Planes are valid until one has a | |
| 1108 | − * zero handle -- this can be used to compute the number of planes. | |
| 1150 | + * will be filled with GEM buffer handles. Fresh new GEM handles are always | |
| 1151 | + * returned, even if another GEM handle referring to the same memory object | |
| 1152 | + * already exists on the DRM file description. The caller is responsible for | |
| 1153 | + * removing the new handles, e.g. via the &DRM_IOCTL_GEM_CLOSE IOCTL. The same | |
| 1154 | + * new handle will be returned for multiple planes in case they use the same | |
| 1155 | + * memory object. Planes are valid until one has a zero handle -- this can be | |
| 1156 | + * used to compute the number of planes. | |
| 1109 | 1157 | * |
| 1110 | 1158 | * Otherwise, &drm_mode_fb_cmd2.handles will be zeroed and planes are valid |
| 1111 | 1159 | * until one has a zero &drm_mode_fb_cmd2.pitches. |
| @@ -1113,6 +1161,11 @@ extern "C" { · 1 unmodified line | ||
| 1113 | 1161 | * If the framebuffer has a format modifier, &DRM_MODE_FB_MODIFIERS will be set |
| 1114 | 1162 | * in &drm_mode_fb_cmd2.flags and &drm_mode_fb_cmd2.modifier will contain the |
| 1115 | 1163 | * modifier. Otherwise, user-space must ignore &drm_mode_fb_cmd2.modifier. |
| 1164 | + * | |
| 1165 | + * To obtain DMA-BUF FDs for each plane without leaking GEM handles, user-space | |
| 1166 | + * can export each handle via &DRM_IOCTL_PRIME_HANDLE_TO_FD, then immediately | |
| 1167 | + * close each unique handle via &DRM_IOCTL_GEM_CLOSE, making sure to not | |
| 1168 | + * double-close handles which are specified multiple times in the array. | |
| 1116 | 1169 | */ |
| 1117 | 1170 | #define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2) |
| 1118 | 1171 | |
| @@ -708,7 +708,8 @@ enum hl_server_type { · 707 unmodified lines | ||
| 708 | 708 | HL_SERVER_GAUDI_HLS1H = 2, |
| 709 | 709 | HL_SERVER_GAUDI_TYPE1 = 3, |
| 710 | 710 | HL_SERVER_GAUDI_TYPE2 = 4, |
| 711 | − HL_SERVER_GAUDI2_HLS2 = 5 | |
| 711 | + HL_SERVER_GAUDI2_HLS2 = 5, | |
| 712 | + HL_SERVER_GAUDI2_TYPE1 = 7 | |
| 712 | 713 | }; |
| 713 | 714 | |
| 714 | 715 | /* |
| @@ -723,6 +724,10 @@ enum hl_server_type { · 8 unmodified lines | ||
| 723 | 724 | * HL_NOTIFIER_EVENT_GENERAL_HW_ERR - Indicates device HW error |
| 724 | 725 | * HL_NOTIFIER_EVENT_RAZWI - Indicates razwi happened |
| 725 | 726 | * HL_NOTIFIER_EVENT_PAGE_FAULT - Indicates page fault happened |
| 727 | + * HL_NOTIFIER_EVENT_CRITICAL_HW_ERR - Indicates a HW error that requires SW abort and | |
| 728 | + * HW reset | |
| 729 | + * HL_NOTIFIER_EVENT_CRITICAL_FW_ERR - Indicates a FW error that requires SW abort and | |
| 730 | + * HW reset | |
| 726 | 731 | */ |
| 727 | 732 | #define HL_NOTIFIER_EVENT_TPC_ASSERT (1ULL << 0) |
| 728 | 733 | #define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1ULL << 1) |
| @@ -733,6 +738,8 @@ enum hl_server_type { · 4 unmodified lines | ||
| 733 | 738 | #define HL_NOTIFIER_EVENT_GENERAL_HW_ERR (1ULL << 6) |
| 734 | 739 | #define HL_NOTIFIER_EVENT_RAZWI (1ULL << 7) |
| 735 | 740 | #define HL_NOTIFIER_EVENT_PAGE_FAULT (1ULL << 8) |
| 741 | +#define HL_NOTIFIER_EVENT_CRITICL_HW_ERR (1ULL << 9) | |
| 742 | +#define HL_NOTIFIER_EVENT_CRITICL_FW_ERR (1ULL << 10) | |
| 736 | 743 | |
| 737 | 744 | /* Opcode for management ioctl |
| 738 | 745 | * |
| @@ -790,6 +797,8 @@ enum hl_server_type { · 51 unmodified lines | ||
| 790 | 797 | * HL_INFO_PAGE_FAULT_EVENT - Retrieve parameters of captured page fault. |
| 791 | 798 | * HL_INFO_USER_MAPPINGS - Retrieve user mappings, captured after page fault event. |
| 792 | 799 | * HL_INFO_FW_GENERIC_REQ - Send generic request to FW. |
| 800 | + * HL_INFO_HW_ERR_EVENT - Retrieve information on the reported HW error. | |
| 801 | + * HL_INFO_FW_ERR_EVENT - Retrieve information on the reported FW error. | |
| 793 | 802 | */ |
| 794 | 803 | #define HL_INFO_HW_IP_INFO 0 |
| 795 | 804 | #define HL_INFO_HW_EVENTS 1 |
| @@ -824,6 +833,8 @@ enum hl_server_type { · 28 unmodified lines | ||
| 824 | 833 | #define HL_INFO_PAGE_FAULT_EVENT 33 |
| 825 | 834 | #define HL_INFO_USER_MAPPINGS 34 |
| 826 | 835 | #define HL_INFO_FW_GENERIC_REQ 35 |
| 836 | +#define HL_INFO_HW_ERR_EVENT 36 | |
| 837 | +#define HL_INFO_FW_ERR_EVENT 37 | |
| 827 | 838 | |
| 828 | 839 | #define HL_INFO_VERSION_MAX_LEN 128 |
| 829 | 840 | #define HL_INFO_CARD_NAME_MAX_LEN 16 |
| @@ -875,6 +886,12 @@ enum hl_server_type { · 45 unmodified lines | ||
| 875 | 886 | * application to use. Relevant for Gaudi2 and later. |
| 876 | 887 | * @device_mem_alloc_default_page_size: default page size used in device memory allocation. |
| 877 | 888 | * @revision_id: PCI revision ID of the ASIC. |
| 889 | + * @tpc_interrupt_id: interrupt id for TPC to use in order to raise events towards the host. | |
| 890 | + * @rotator_enabled_mask: Bit-mask that represents which rotators are enabled. | |
| 891 | + * Relevant for Gaudi3 and later. | |
| 892 | + * @engine_core_interrupt_reg_addr: interrupt register address for engine core to use | |
| 893 | + * in order to raise events toward FW. | |
| 894 | + * @reserved_dram_size: DRAM size reserved for driver and firmware. | |
| 878 | 895 | */ |
| 879 | 896 | struct hl_info_hw_ip_info { |
| 880 | 897 | __u64 sram_base_address; |
| @@ -902,15 +919,20 @@ struct hl_info_hw_ip_info { · 21 unmodified lines | ||
| 902 | 919 | __u64 dram_page_size; |
| 903 | 920 | __u32 edma_enabled_mask; |
| 904 | 921 | __u16 number_of_user_interrupts; |
| 905 | − __u16 pad2; | |
| 906 | − __u64 reserved4; | |
| 922 | + __u8 reserved1; | |
| 923 | + __u8 reserved2; | |
| 924 | + __u64 reserved3; | |
| 907 | 925 | __u64 device_mem_alloc_default_page_size; |
| 926 | + __u64 reserved4; | |
| 908 | 927 | __u64 reserved5; |
| 909 | − __u64 reserved6; | |
| 910 | − __u32 reserved7; | |
| 911 | − __u8 reserved8; | |
| 928 | + __u32 reserved6; | |
| 929 | + __u8 reserved7; | |
| 912 | 930 | __u8 revision_id; |
| 913 | − __u8 pad[2]; | |
| 931 | + __u16 tpc_interrupt_id; | |
| 932 | + __u32 rotator_enabled_mask; | |
| 933 | + __u32 reserved9; | |
| 934 | + __u64 engine_core_interrupt_reg_addr; | |
| 935 | + __u64 reserved_dram_size; | |
| 914 | 936 | }; |
| 915 | 937 | |
| 916 | 938 | struct hl_info_dram_usage { |
| @@ -1161,6 +1183,39 @@ struct hl_info_undefined_opcode_event { · 244 unmodified lines | ||
| 1161 | 1183 | __u32 stream_id; |
| 1162 | 1184 | }; |
| 1163 | 1185 | |
| 1186 | +/** | |
| 1187 | + * struct hl_info_hw_err_event - info about HW error | |
| 1188 | + * @timestamp: timestamp of error occurrence | |
| 1189 | + * @event_id: The async event ID (specific to each device type). | |
| 1190 | + * @pad: size padding for u64 granularity. | |
| 1191 | + */ | |
| 1192 | +struct hl_info_hw_err_event { | |
| 1193 | + __s64 timestamp; | |
| 1194 | + __u16 event_id; | |
| 1195 | + __u16 pad[3]; | |
| 1196 | +}; | |
| 1197 | + | |
| 1198 | +/* FW error definition for event_type in struct hl_info_fw_err_event */ | |
| 1199 | +enum hl_info_fw_err_type { | |
| 1200 | + HL_INFO_FW_HEARTBEAT_ERR, | |
| 1201 | + HL_INFO_FW_REPORTED_ERR, | |
| 1202 | +}; | |
| 1203 | + | |
| 1204 | +/** | |
| 1205 | + * struct hl_info_fw_err_event - info about FW error | |
| 1206 | + * @timestamp: time-stamp of error occurrence | |
| 1207 | + * @err_type: The type of event as defined in hl_info_fw_err_type. | |
| 1208 | + * @event_id: The async event ID (specific to each device type, applicable only when event type is | |
| 1209 | + * HL_INFO_FW_REPORTED_ERR). | |
| 1210 | + * @pad: size padding for u64 granularity. | |
| 1211 | + */ | |
| 1212 | +struct hl_info_fw_err_event { | |
| 1213 | + __s64 timestamp; | |
| 1214 | + __u16 err_type; | |
| 1215 | + __u16 event_id; | |
| 1216 | + __u32 pad; | |
| 1217 | +}; | |
| 1218 | + | |
| 1164 | 1219 | /** |
| 1165 | 1220 | * struct hl_info_dev_memalloc_page_sizes - valid page sizes in device mem alloc information. |
| 1166 | 1221 | * @page_order_bitmask: bitmap in which a set bit represents the order of the supported page size |
| @@ -1486,17 +1541,31 @@ struct hl_cs_chunk { · 319 unmodified lines | ||
| 1486 | 1541 | */ |
| 1487 | 1542 | #define HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES 0x8000 |
| 1488 | 1543 | |
| 1544 | +/* | |
| 1545 | + * The engines CS is merged into the existing CS ioctls. | |
| 1546 | + * Use it to control engines modes. | |
| 1547 | + */ | |
| 1548 | +#define HL_CS_FLAGS_ENGINES_COMMAND 0x10000 | |
| 1549 | + | |
| 1489 | 1550 | #define HL_CS_STATUS_SUCCESS 0 |
| 1490 | 1551 | |
| 1491 | 1552 | #define HL_MAX_JOBS_PER_CS 512 |
| 1492 | 1553 | |
| 1493 | −/* HL_ENGINE_CORE_ values | |
| 1554 | +/* | |
| 1555 | + * enum hl_engine_command - engine command | |
| 1494 | 1556 | * |
| 1495 | − * HL_ENGINE_CORE_HALT: engine core halt | |
| 1496 | − * HL_ENGINE_CORE_RUN: engine core run | |
| 1557 | + * @HL_ENGINE_CORE_HALT: engine core halt | |
| 1558 | + * @HL_ENGINE_CORE_RUN: engine core run | |
| 1559 | + * @HL_ENGINE_STALL: user engine/s stall | |
| 1560 | + * @HL_ENGINE_RESUME: user engine/s resume | |
| 1497 | 1561 | */ |
| 1498 | −#define HL_ENGINE_CORE_HALT (1 << 0) | |
| 1499 | −#define HL_ENGINE_CORE_RUN (1 << 1) | |
| 1562 | +enum hl_engine_command { | |
| 1563 | + HL_ENGINE_CORE_HALT = 1, | |
| 1564 | + HL_ENGINE_CORE_RUN = 2, | |
| 1565 | + HL_ENGINE_STALL = 3, | |
| 1566 | + HL_ENGINE_RESUME = 4, | |
| 1567 | + HL_ENGINE_COMMAND_MAX | |
| 1568 | +}; | |
| 1500 | 1569 | |
| 1501 | 1570 | struct hl_cs_in { |
| 1502 | 1571 | |
| @@ -1520,6 +1589,18 @@ struct hl_cs_in { · 17 unmodified lines | ||
| 1520 | 1589 | /* the core command to be sent towards engine cores */ |
| 1521 | 1590 | __u32 core_command; |
| 1522 | 1591 | }; |
| 1592 | + | |
| 1593 | + /* Valid only when HL_CS_FLAGS_ENGINES_COMMAND is set */ | |
| 1594 | + struct { | |
| 1595 | + /* this holds address of array of uint32 for engines */ | |
| 1596 | + __u64 engines; | |
| 1597 | + | |
| 1598 | + /* number of engines in engines array */ | |
| 1599 | + __u32 num_engines; | |
| 1600 | + | |
| 1601 | + /* the engine command to be sent towards engines */ | |
| 1602 | + __u32 engine_command; | |
| 1603 | + }; | |
| 1523 | 1604 | }; |
| 1524 | 1605 | |
| 1525 | 1606 | union { |
| @@ -2491,7 +2491,7 @@ struct i915_context_param_engines { · 2490 unmodified lines | ||
| 2491 | 2491 | #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ |
| 2492 | 2492 | #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */ |
| 2493 | 2493 | #define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ |
| 2494 | − struct i915_engine_class_instance engines[0]; | |
| 2494 | + struct i915_engine_class_instance engines[]; | |
| 2495 | 2495 | } __attribute__((packed)); |
| 2496 | 2496 | |
| 2497 | 2497 | #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \ |
| @@ -2676,6 +2676,10 @@ enum drm_i915_oa_format { · 178 unmodified lines | ||
| 2676 | 2676 | I915_OAR_FORMAT_A32u40_A4u32_B8_C8, |
| 2677 | 2677 | I915_OA_FORMAT_A24u40_A14u32_B8_C8, |
| 2678 | 2678 | |
| 2679 | + /* MTL OAM */ | |
| 2680 | + I915_OAM_FORMAT_MPEC8u64_B8_C8, | |
| 2681 | + I915_OAM_FORMAT_MPEC8u32_B8_C8, | |
| 2682 | + | |
| 2679 | 2683 | I915_OA_FORMAT_MAX /* non-ABI */ |
| 2680 | 2684 | }; |
| 2681 | 2685 | |
| @@ -2758,6 +2762,25 @@ enum drm_i915_perf_property_id { · 76 unmodified lines | ||
| 2758 | 2762 | */ |
| 2759 | 2763 | DRM_I915_PERF_PROP_POLL_OA_PERIOD, |
| 2760 | 2764 | |
| 2765 | + /** | |
| 2766 | + * Multiple engines may be mapped to the same OA unit. The OA unit is | |
| 2767 | + * identified by class:instance of any engine mapped to it. | |
| 2768 | + * | |
| 2769 | + * This parameter specifies the engine class and must be passed along | |
| 2770 | + * with DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE. | |
| 2771 | + * | |
| 2772 | + * This property is available in perf revision 6. | |
| 2773 | + */ | |
| 2774 | + DRM_I915_PERF_PROP_OA_ENGINE_CLASS, | |
| 2775 | + | |
| 2776 | + /** | |
| 2777 | + * This parameter specifies the engine instance and must be passed along | |
| 2778 | + * with DRM_I915_PERF_PROP_OA_ENGINE_CLASS. | |
| 2779 | + * | |
| 2780 | + * This property is available in perf revision 6. | |
| 2781 | + */ | |
| 2782 | + DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE, | |
| 2783 | + | |
| 2761 | 2784 | DRM_I915_PERF_PROP_MAX /* non-ABI */ |
| 2762 | 2785 | }; |
| 2763 | 2786 | |
| @@ -151,8 +151,13 @@ struct drm_msm_gem_info { · 150 unmodified lines | ||
| 151 | 151 | #define MSM_PREP_READ 0x01 |
| 152 | 152 | #define MSM_PREP_WRITE 0x02 |
| 153 | 153 | #define MSM_PREP_NOSYNC 0x04 |
| 154 | +#define MSM_PREP_BOOST 0x08 | |
| 154 | 155 | |
| 155 | −#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) | |
| 156 | +#define MSM_PREP_FLAGS (MSM_PREP_READ | \ | |
| 157 | + MSM_PREP_WRITE | \ | |
| 158 | + MSM_PREP_NOSYNC | \ | |
| 159 | + MSM_PREP_BOOST | \ | |
| 160 | + 0) | |
| 156 | 161 | |
| 157 | 162 | struct drm_msm_gem_cpu_prep { |
| 158 | 163 | __u32 handle; /* in */ |
| @@ -181,7 +186,11 @@ struct drm_msm_gem_cpu_fini { · 22 unmodified lines | ||
| 181 | 186 | */ |
| 182 | 187 | struct drm_msm_gem_submit_reloc { |
| 183 | 188 | __u32 submit_offset; /* in, offset from submit_bo */ |
| 189 | +#ifdef __cplusplus | |
| 190 | + __u32 _or; /* in, value OR'd with result */ | |
| 191 | +#else | |
| 184 | 192 | __u32 or; /* in, value OR'd with result */ |
| 193 | +#endif | |
| 185 | 194 | __s32 shift; /* in, amount of left shift (can be negative) */ |
| 186 | 195 | __u32 reloc_idx; /* in, index of reloc_bo buffer */ |
| 187 | 196 | __u64 reloc_offset; /* in, offset from start of reloc_bo */ |
| @@ -286,6 +295,11 @@ struct drm_msm_gem_submit { · 98 unmodified lines | ||
| 286 | 295 | |
| 287 | 296 | }; |
| 288 | 297 | |
| 298 | +#define MSM_WAIT_FENCE_BOOST 0x00000001 | |
| 299 | +#define MSM_WAIT_FENCE_FLAGS ( \ | |
| 300 | + MSM_WAIT_FENCE_BOOST | \ | |
| 301 | + 0) | |
| 302 | + | |
| 289 | 303 | /* The normal way to synchronize with the GPU is just to CPU_PREP on |
| 290 | 304 | * a buffer if you need to access it from the CPU (other cmdstream |
| 291 | 305 | * submission from same or other contexts, PAGE_FLIP ioctl, etc, all |
| @@ -295,7 +309,7 @@ struct drm_msm_gem_submit { · 3 unmodified lines | ||
| 295 | 309 | */ |
| 296 | 310 | struct drm_msm_wait_fence { |
| 297 | 311 | __u32 fence; /* in */ |
| 298 | − __u32 pad; | |
| 312 | + __u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */ | |
| 299 | 313 | struct drm_msm_timespec timeout; /* in */ |
| 300 | 314 | __u32 queueid; /* in, submitqueue id */ |
| 301 | 315 | }; |
| @@ -0,0 +1,397 @@ | ||
| 1 | +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note | |
| 2 | + * | |
| 3 | + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. | |
| 4 | + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. | |
| 5 | + */ | |
| 6 | + | |
| 7 | +#ifndef QAIC_ACCEL_H_ | |
| 8 | +#define QAIC_ACCEL_H_ | |
| 9 | + | |
| 10 | +#include "drm.h" | |
| 11 | + | |
| 12 | +#if defined(__cplusplus) | |
| 13 | +extern "C" { | |
| 14 | +#endif | |
| 15 | + | |
| 16 | +/* The length(4K) includes len and count fields of qaic_manage_msg */ | |
| 17 | +#define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K | |
| 18 | + | |
| 19 | +/* semaphore flags */ | |
| 20 | +#define QAIC_SEM_INSYNCFENCE 2 | |
| 21 | +#define QAIC_SEM_OUTSYNCFENCE 1 | |
| 22 | + | |
| 23 | +/* Semaphore commands */ | |
| 24 | +#define QAIC_SEM_NOP 0 | |
| 25 | +#define QAIC_SEM_INIT 1 | |
| 26 | +#define QAIC_SEM_INC 2 | |
| 27 | +#define QAIC_SEM_DEC 3 | |
| 28 | +#define QAIC_SEM_WAIT_EQUAL 4 | |
| 29 | +#define QAIC_SEM_WAIT_GT_EQ 5 /* Greater than or equal */ | |
| 30 | +#define QAIC_SEM_WAIT_GT_0 6 /* Greater than 0 */ | |
| 31 | + | |
| 32 | +#define QAIC_TRANS_UNDEFINED 0 | |
| 33 | +#define QAIC_TRANS_PASSTHROUGH_FROM_USR 1 | |
| 34 | +#define QAIC_TRANS_PASSTHROUGH_TO_USR 2 | |
| 35 | +#define QAIC_TRANS_PASSTHROUGH_FROM_DEV 3 | |
| 36 | +#define QAIC_TRANS_PASSTHROUGH_TO_DEV 4 | |
| 37 | +#define QAIC_TRANS_DMA_XFER_FROM_USR 5 | |
| 38 | +#define QAIC_TRANS_DMA_XFER_TO_DEV 6 | |
| 39 | +#define QAIC_TRANS_ACTIVATE_FROM_USR 7 | |
| 40 | +#define QAIC_TRANS_ACTIVATE_FROM_DEV 8 | |
| 41 | +#define QAIC_TRANS_ACTIVATE_TO_DEV 9 | |
| 42 | +#define QAIC_TRANS_DEACTIVATE_FROM_USR 10 | |
| 43 | +#define QAIC_TRANS_DEACTIVATE_FROM_DEV 11 | |
| 44 | +#define QAIC_TRANS_STATUS_FROM_USR 12 | |
| 45 | +#define QAIC_TRANS_STATUS_TO_USR 13 | |
| 46 | +#define QAIC_TRANS_STATUS_FROM_DEV 14 | |
| 47 | +#define QAIC_TRANS_STATUS_TO_DEV 15 | |
| 48 | +#define QAIC_TRANS_TERMINATE_FROM_DEV 16 | |
| 49 | +#define QAIC_TRANS_TERMINATE_TO_DEV 17 | |
| 50 | +#define QAIC_TRANS_DMA_XFER_CONT 18 | |
| 51 | +#define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV 19 | |
| 52 | +#define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV 20 | |
| 53 | + | |
| 54 | +/** | |
| 55 | + * struct qaic_manage_trans_hdr - Header for a transaction in a manage message. | |
| 56 | + * @type: In. Identifies this transaction. See QAIC_TRANS_* defines. | |
| 57 | + * @len: In. Length of this transaction, including this header. | |
| 58 | + */ | |
| 59 | +struct qaic_manage_trans_hdr { | |
| 60 | + __u32 type; | |
| 61 | + __u32 len; | |
| 62 | +}; | |
| 63 | + | |
| 64 | +/** | |
| 65 | + * struct qaic_manage_trans_passthrough - Defines a passthrough transaction. | |
| 66 | + * @hdr: In. Header to identify this transaction. | |
| 67 | + * @data: In. Payload of this ransaction. Opaque to the driver. Userspace must | |
| 68 | + * encode in little endian and align/pad to 64-bit. | |
| 69 | + */ | |
| 70 | +struct qaic_manage_trans_passthrough { | |
| 71 | + struct qaic_manage_trans_hdr hdr; | |
| 72 | + __u8 data[]; | |
| 73 | +}; | |
| 74 | + | |
| 75 | +/** | |
| 76 | + * struct qaic_manage_trans_dma_xfer - Defines a DMA transfer transaction. | |
| 77 | + * @hdr: In. Header to identify this transaction. | |
| 78 | + * @tag: In. Identified this transfer in other transactions. Opaque to the | |
| 79 | + * driver. | |
| 80 | + * @pad: Structure padding. | |
| 81 | + * @addr: In. Address of the data to DMA to the device. | |
| 82 | + * @size: In. Length of the data to DMA to the device. | |
| 83 | + */ | |
| 84 | +struct qaic_manage_trans_dma_xfer { | |
| 85 | + struct qaic_manage_trans_hdr hdr; | |
| 86 | + __u32 tag; | |
| 87 | + __u32 pad; | |
| 88 | + __u64 addr; | |
| 89 | + __u64 size; | |
| 90 | +}; | |
| 91 | + | |
| 92 | +/** | |
| 93 | + * struct qaic_manage_trans_activate_to_dev - Defines an activate request. | |
| 94 | + * @hdr: In. Header to identify this transaction. | |
| 95 | + * @queue_size: In. Number of elements for DBC request and response queues. | |
| 96 | + * @eventfd: Unused. | |
| 97 | + * @options: In. Device specific options for this activate. | |
| 98 | + * @pad: Structure padding. Must be 0. | |
| 99 | + */ | |
| 100 | +struct qaic_manage_trans_activate_to_dev { | |
| 101 | + struct qaic_manage_trans_hdr hdr; | |
| 102 | + __u32 queue_size; | |
| 103 | + __u32 eventfd; | |
| 104 | + __u32 options; | |
| 105 | + __u32 pad; | |
| 106 | +}; | |
| 107 | + | |
| 108 | +/** | |
| 109 | + * struct qaic_manage_trans_activate_from_dev - Defines an activate response. | |
| 110 | + * @hdr: Out. Header to identify this transaction. | |
| 111 | + * @status: Out. Return code of the request from the device. | |
| 112 | + * @dbc_id: Out. Id of the assigned DBC for successful request. | |
| 113 | + * @options: Out. Device specific options for this activate. | |
| 114 | + */ | |
| 115 | +struct qaic_manage_trans_activate_from_dev { | |
| 116 | + struct qaic_manage_trans_hdr hdr; | |
| 117 | + __u32 status; | |
| 118 | + __u32 dbc_id; | |
| 119 | + __u64 options; | |
| 120 | +}; | |
| 121 | + | |
| 122 | +/** | |
| 123 | + * struct qaic_manage_trans_deactivate - Defines a deactivate request. | |
| 124 | + * @hdr: In. Header to identify this transaction. | |
| 125 | + * @dbc_id: In. Id of assigned DBC. | |
| 126 | + * @pad: Structure padding. Must be 0. | |
| 127 | + */ | |
| 128 | +struct qaic_manage_trans_deactivate { | |
| 129 | + struct qaic_manage_trans_hdr hdr; | |
| 130 | + __u32 dbc_id; | |
| 131 | + __u32 pad; | |
| 132 | +}; | |
| 133 | + | |
| 134 | +/** | |
| 135 | + * struct qaic_manage_trans_status_to_dev - Defines a status request. | |
| 136 | + * @hdr: In. Header to identify this transaction. | |
| 137 | + */ | |
| 138 | +struct qaic_manage_trans_status_to_dev { | |
| 139 | + struct qaic_manage_trans_hdr hdr; | |
| 140 | +}; | |
| 141 | + | |
| 142 | +/** | |
| 143 | + * struct qaic_manage_trans_status_from_dev - Defines a status response. | |
| 144 | + * @hdr: Out. Header to identify this transaction. | |
| 145 | + * @major: Out. NNC protocol version major number. | |
| 146 | + * @minor: Out. NNC protocol version minor number. | |
| 147 | + * @status: Out. Return code from device. | |
| 148 | + * @status_flags: Out. Flags from device. Bit 0 indicates if CRCs are required. | |
| 149 | + */ | |
| 150 | +struct qaic_manage_trans_status_from_dev { | |
| 151 | + struct qaic_manage_trans_hdr hdr; | |
| 152 | + __u16 major; | |
| 153 | + __u16 minor; | |
| 154 | + __u32 status; | |
| 155 | + __u64 status_flags; | |
| 156 | +}; | |
| 157 | + | |
| 158 | +/** | |
| 159 | + * struct qaic_manage_msg - Defines a message to the device. | |
| 160 | + * @len: In. Length of all the transactions contained within this message. | |
| 161 | + * @count: In. Number of transactions in this message. | |
| 162 | + * @data: In. Address to an array where the transactions can be found. | |
| 163 | + */ | |
| 164 | +struct qaic_manage_msg { | |
| 165 | + __u32 len; | |
| 166 | + __u32 count; | |
| 167 | + __u64 data; | |
| 168 | +}; | |
| 169 | + | |
| 170 | +/** | |
| 171 | + * struct qaic_create_bo - Defines a request to create a buffer object. | |
| 172 | + * @size: In. Size of the buffer in bytes. | |
| 173 | + * @handle: Out. GEM handle for the BO. | |
| 174 | + * @pad: Structure padding. Must be 0. | |
| 175 | + */ | |
| 176 | +struct qaic_create_bo { | |
| 177 | + __u64 size; | |
| 178 | + __u32 handle; | |
| 179 | + __u32 pad; | |
| 180 | +}; | |
| 181 | + | |
| 182 | +/** | |
| 183 | + * struct qaic_mmap_bo - Defines a request to prepare a BO for mmap(). | |
| 184 | + * @handle: In. Handle of the GEM BO to prepare for mmap(). | |
| 185 | + * @pad: Structure padding. Must be 0. | |
| 186 | + * @offset: Out. Offset value to provide to mmap(). | |
| 187 | + */ | |
| 188 | +struct qaic_mmap_bo { | |
| 189 | + __u32 handle; | |
| 190 | + __u32 pad; | |
| 191 | + __u64 offset; | |
| 192 | +}; | |
| 193 | + | |
| 194 | +/** | |
| 195 | + * struct qaic_sem - Defines a semaphore command for a BO slice. | |
| 196 | + * @val: In. Only lower 12 bits are valid. | |
| 197 | + * @index: In. Only lower 5 bits are valid. | |
| 198 | + * @presync: In. 1 if presync operation, 0 if postsync. | |
| 199 | + * @cmd: In. One of QAIC_SEM_*. | |
| 200 | + * @flags: In. Bitfield. See QAIC_SEM_INSYNCFENCE and QAIC_SEM_OUTSYNCFENCE | |
| 201 | + * @pad: Structure padding. Must be 0. | |
| 202 | + */ | |
| 203 | +struct qaic_sem { | |
| 204 | + __u16 val; | |
| 205 | + __u8 index; | |
| 206 | + __u8 presync; | |
| 207 | + __u8 cmd; | |
| 208 | + __u8 flags; | |
| 209 | + __u16 pad; | |
| 210 | +}; | |
| 211 | + | |
| 212 | +/** | |
| 213 | + * struct qaic_attach_slice_entry - Defines a single BO slice. | |
| 214 | + * @size: In. Size of this slice in bytes. | |
| 215 | + * @sem0: In. Semaphore command 0. Must be 0 is not valid. | |
| 216 | + * @sem1: In. Semaphore command 1. Must be 0 is not valid. | |
| 217 | + * @sem2: In. Semaphore command 2. Must be 0 is not valid. | |
| 218 | + * @sem3: In. Semaphore command 3. Must be 0 is not valid. | |
| 219 | + * @dev_addr: In. Device address this slice pushes to or pulls from. | |
| 220 | + * @db_addr: In. Address of the doorbell to ring. | |
| 221 | + * @db_data: In. Data to write to the doorbell. | |
| 222 | + * @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for | |
| 223 | + * inactive doorbells. | |
| 224 | + * @offset: In. Start of this slice as an offset from the start of the BO. | |
| 225 | + */ | |
| 226 | +struct qaic_attach_slice_entry { | |
| 227 | + __u64 size; | |
| 228 | + struct qaic_sem sem0; | |
| 229 | + struct qaic_sem sem1; | |
| 230 | + struct qaic_sem sem2; | |
| 231 | + struct qaic_sem sem3; | |
| 232 | + __u64 dev_addr; | |
| 233 | + __u64 db_addr; | |
| 234 | + __u32 db_data; | |
| 235 | + __u32 db_len; | |
| 236 | + __u64 offset; | |
| 237 | +}; | |
| 238 | + | |
| 239 | +/** | |
| 240 | + * struct qaic_attach_slice_hdr - Defines metadata for a set of BO slices. | |
| 241 | + * @count: In. Number of slices for this BO. | |
| 242 | + * @dbc_id: In. Associate the sliced BO with this DBC. | |
| 243 | + * @handle: In. GEM handle of the BO to slice. | |
| 244 | + * @dir: In. Direction of data flow. 1 = DMA_TO_DEVICE, 2 = DMA_FROM_DEVICE | |
| 245 | + * @size: In. Total length of the BO. | |
| 246 | + * If BO is imported (DMABUF/PRIME) then this size | |
| 247 | + * should not exceed the size of DMABUF provided. | |
| 248 | + * If BO is allocated using DRM_IOCTL_QAIC_CREATE_BO | |
| 249 | + * then this size should be exactly same as the size | |
| 250 | + * provided during DRM_IOCTL_QAIC_CREATE_BO. | |
| 251 | + * @dev_addr: In. Device address this slice pushes to or pulls from. | |
| 252 | + * @db_addr: In. Address of the doorbell to ring. | |
| 253 | + * @db_data: In. Data to write to the doorbell. | |
| 254 | + * @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for | |
| 255 | + * inactive doorbells. | |
| 256 | + * @offset: In. Start of this slice as an offset from the start of the BO. | |
| 257 | + */ | |
| 258 | +struct qaic_attach_slice_hdr { | |
| 259 | + __u32 count; | |
| 260 | + __u32 dbc_id; | |
| 261 | + __u32 handle; | |
| 262 | + __u32 dir; | |
| 263 | + __u64 size; | |
| 264 | +}; | |
| 265 | + | |
| 266 | +/** | |
| 267 | + * struct qaic_attach_slice - Defines a set of BO slices. | |
| 268 | + * @hdr: In. Metadata of the set of slices. | |
| 269 | + * @data: In. Pointer to an array containing the slice definitions. | |
| 270 | + */ | |
| 271 | +struct qaic_attach_slice { | |
| 272 | + struct qaic_attach_slice_hdr hdr; | |
| 273 | + __u64 data; | |
| 274 | +}; | |
| 275 | + | |
| 276 | +/** | |
| 277 | + * struct qaic_execute_entry - Defines a BO to submit to the device. | |
| 278 | + * @handle: In. GEM handle of the BO to commit to the device. | |
| 279 | + * @dir: In. Direction of data. 1 = to device, 2 = from device. | |
| 280 | + */ | |
| 281 | +struct qaic_execute_entry { | |
| 282 | + __u32 handle; | |
| 283 | + __u32 dir; | |
| 284 | +}; | |
| 285 | + | |
| 286 | +/** | |
| 287 | + * struct qaic_partial_execute_entry - Defines a BO to resize and submit. | |
| 288 | + * @handle: In. GEM handle of the BO to commit to the device. | |
| 289 | + * @dir: In. Direction of data. 1 = to device, 2 = from device. | |
| 290 | + * @resize: In. New size of the BO. Must be <= the original BO size. 0 is | |
| 291 | + * short for no resize. | |
| 292 | + */ | |
| 293 | +struct qaic_partial_execute_entry { | |
| 294 | + __u32 handle; | |
| 295 | + __u32 dir; | |
| 296 | + __u64 resize; | |
| 297 | +}; | |
| 298 | + | |
| 299 | +/** | |
| 300 | + * struct qaic_execute_hdr - Defines metadata for BO submission. | |
| 301 | + * @count: In. Number of BOs to submit. | |
| 302 | + * @dbc_id: In. DBC to submit the BOs on. | |
| 303 | + */ | |
| 304 | +struct qaic_execute_hdr { | |
| 305 | + __u32 count; | |
| 306 | + __u32 dbc_id; | |
| 307 | +}; | |
| 308 | + | |
| 309 | +/** | |
| 310 | + * struct qaic_execute - Defines a list of BOs to submit to the device. | |
| 311 | + * @hdr: In. BO list metadata. | |
| 312 | + * @data: In. Pointer to an array of BOs to submit. | |
| 313 | + */ | |
| 314 | +struct qaic_execute { | |
| 315 | + struct qaic_execute_hdr hdr; | |
| 316 | + __u64 data; | |
| 317 | +}; | |
| 318 | + | |
| 319 | +/** | |
| 320 | + * struct qaic_wait - Defines a blocking wait for BO execution. | |
| 321 | + * @handle: In. GEM handle of the BO to wait on. | |
| 322 | + * @timeout: In. Maximum time in ms to wait for the BO. | |
| 323 | + * @dbc_id: In. DBC the BO is submitted to. | |
| 324 | + * @pad: Structure padding. Must be 0. | |
| 325 | + */ | |
| 326 | +struct qaic_wait { | |
| 327 | + __u32 handle; | |
| 328 | + __u32 timeout; | |
| 329 | + __u32 dbc_id; | |
| 330 | + __u32 pad; | |
| 331 | +}; | |
| 332 | + | |
| 333 | +/** | |
| 334 | + * struct qaic_perf_stats_hdr - Defines metadata for getting BO perf info. | |
| 335 | + * @count: In. Number of BOs requested. | |
| 336 | + * @pad: Structure padding. Must be 0. | |
| 337 | + * @dbc_id: In. DBC the BO are associated with. | |
| 338 | + */ | |
| 339 | +struct qaic_perf_stats_hdr { | |
| 340 | + __u16 count; | |
| 341 | + __u16 pad; | |
| 342 | + __u32 dbc_id; | |
| 343 | +}; | |
| 344 | + | |
| 345 | +/** | |
| 346 | + * struct qaic_perf_stats - Defines a request for getting BO perf info. | |
| 347 | + * @hdr: In. Request metadata | |
| 348 | + * @data: In. Pointer to array of stats structures that will receive the data. | |
| 349 | + */ | |
| 350 | +struct qaic_perf_stats { | |
| 351 | + struct qaic_perf_stats_hdr hdr; | |
| 352 | + __u64 data; | |
| 353 | +}; | |
| 354 | + | |
| 355 | +/** | |
| 356 | + * struct qaic_perf_stats_entry - Defines a BO perf info. | |
| 357 | + * @handle: In. GEM handle of the BO to get perf stats for. | |
| 358 | + * @queue_level_before: Out. Number of elements in the queue before this BO | |
| 359 | + * was submitted. | |
| 360 | + * @num_queue_element: Out. Number of elements added to the queue to submit | |
| 361 | + * this BO. | |
| 362 | + * @submit_latency_us: Out. Time taken by the driver to submit this BO. | |
| 363 | + * @device_latency_us: Out. Time taken by the device to execute this BO. | |
| 364 | + * @pad: Structure padding. Must be 0. | |
| 365 | + */ | |
| 366 | +struct qaic_perf_stats_entry { | |
| 367 | + __u32 handle; | |
| 368 | + __u32 queue_level_before; | |
| 369 | + __u32 num_queue_element; | |
| 370 | + __u32 submit_latency_us; | |
| 371 | + __u32 device_latency_us; | |
| 372 | + __u32 pad; | |
| 373 | +}; | |
| 374 | + | |
| 375 | +#define DRM_QAIC_MANAGE 0x00 | |
| 376 | +#define DRM_QAIC_CREATE_BO 0x01 | |
| 377 | +#define DRM_QAIC_MMAP_BO 0x02 | |
| 378 | +#define DRM_QAIC_ATTACH_SLICE_BO 0x03 | |
| 379 | +#define DRM_QAIC_EXECUTE_BO 0x04 | |
| 380 | +#define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05 | |
| 381 | +#define DRM_QAIC_WAIT_BO 0x06 | |
| 382 | +#define DRM_QAIC_PERF_STATS_BO 0x07 | |
| 383 | + | |
| 384 | +#define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg) | |
| 385 | +#define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo) | |
| 386 | +#define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo) | |
| 387 | +#define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice) | |
| 388 | +#define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute) | |
| 389 | +#define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute) | |
| 390 | +#define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait) | |
| 391 | +#define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats) | |
| 392 | + | |
| 393 | +#if defined(__cplusplus) | |
| 394 | +} | |
| 395 | +#endif | |
| 396 | + | |
| 397 | +#endif /* QAIC_ACCEL_H_ */ | |
| @@ -37,9 +37,10 @@ · 36 unmodified lines | ||
| 37 | 37 | * - 1.9 - Add available memory ioctl |
| 38 | 38 | * - 1.10 - Add SMI profiler event log |
| 39 | 39 | * - 1.11 - Add unified memory for ctx save/restore area |
| 40 | + * - 1.12 - Add DMA buf export ioctl | |
| 40 | 41 | */ |
| 41 | 42 | #define KFD_IOCTL_MAJOR_VERSION 1 |
| 42 | −#define KFD_IOCTL_MINOR_VERSION 11 | |
| 43 | +#define KFD_IOCTL_MINOR_VERSION 12 | |
| 43 | 44 | |
| 44 | 45 | struct kfd_ioctl_get_version_args { |
| 45 | 46 | __u32 major_version; /* from KFD */ |
| @@ -463,6 +464,12 @@ struct kfd_ioctl_import_dmabuf_args { · 417 unmodified lines | ||
| 463 | 464 | __u32 dmabuf_fd; /* to KFD */ |
| 464 | 465 | }; |
| 465 | 466 | |
| 467 | +struct kfd_ioctl_export_dmabuf_args { | |
| 468 | + __u64 handle; /* to KFD */ | |
| 469 | + __u32 flags; /* to KFD */ | |
| 470 | + __u32 dmabuf_fd; /* from KFD */ | |
| 471 | +}; | |
| 472 | + | |
| 466 | 473 | /* |
| 467 | 474 | * KFD SMI(System Management Interface) events |
| 468 | 475 | */ |
| @@ -877,7 +884,10 @@ struct kfd_ioctl_set_xnack_mode_args { · 408 unmodified lines | ||
| 877 | 884 | #define AMDKFD_IOC_AVAILABLE_MEMORY \ |
| 878 | 885 | AMDKFD_IOWR(0x23, struct kfd_ioctl_get_available_memory_args) |
| 879 | 886 | |
| 887 | +#define AMDKFD_IOC_EXPORT_DMABUF \ | |
| 888 | + AMDKFD_IOWR(0x24, struct kfd_ioctl_export_dmabuf_args) | |
| 889 | + | |
| 880 | 890 | #define AMDKFD_COMMAND_START 0x01 |
| 881 | −#define AMDKFD_COMMAND_END 0x24 | |
| 891 | +#define AMDKFD_COMMAND_END 0x25 | |
| 882 | 892 | |
| 883 | 893 | #endif |
| @@ -16,12 +16,16 @@ · 15 unmodified lines | ||
| 16 | 16 | #include <linux/types.h> |
| 17 | 17 | |
| 18 | 18 | /** |
| 19 | − * struct sync_merge_data - data passed to merge ioctl | |
| 19 | + * struct sync_merge_data - SYNC_IOC_MERGE: merge two fences | |
| 20 | 20 | * @name: name of new fence |
| 21 | 21 | * @fd2: file descriptor of second fence |
| 22 | 22 | * @fence: returns the fd of the new fence to userspace |
| 23 | 23 | * @flags: merge_data flags |
| 24 | 24 | * @pad: padding for 64-bit alignment, should always be zero |
| 25 | + * | |
| 26 | + * Creates a new fence containing copies of the sync_pts in both | |
| 27 | + * the calling fd and sync_merge_data.fd2. Returns the new fence's | |
| 28 | + * fd in sync_merge_data.fence | |
| 25 | 29 | */ |
| 26 | 30 | struct sync_merge_data { |
| 27 | 31 | char name[32]; |
| @@ -34,8 +38,8 @@ struct sync_merge_data { · 6 unmodified lines | ||
| 34 | 38 | /** |
| 35 | 39 | * struct sync_fence_info - detailed fence information |
| 36 | 40 | * @obj_name: name of parent sync_timeline |
| 37 | −* @driver_name: name of driver implementing the parent | |
| 38 | −* @status: status of the fence 0:active 1:signaled <0:error | |
| 41 | + * @driver_name: name of driver implementing the parent | |
| 42 | + * @status: status of the fence 0:active 1:signaled <0:error | |
| 39 | 43 | * @flags: fence_info flags |
| 40 | 44 | * @timestamp_ns: timestamp of status change in nanoseconds |
| 41 | 45 | */ |
| @@ -48,14 +52,19 @@ struct sync_fence_info { · 6 unmodified lines | ||
| 48 | 52 | }; |
| 49 | 53 | |
| 50 | 54 | /** |
| 51 | − * struct sync_file_info - data returned from fence info ioctl | |
| 55 | + * struct sync_file_info - SYNC_IOC_FILE_INFO: get detailed information on a sync_file | |
| 52 | 56 | * @name: name of fence |
| 53 | 57 | * @status: status of fence. 1: signaled 0:active <0:error |
| 54 | 58 | * @flags: sync_file_info flags |
| 55 | 59 | * @num_fences number of fences in the sync_file |
| 56 | 60 | * @pad: padding for 64-bit alignment, should always be zero |
| 57 | − * @sync_fence_info: pointer to array of structs sync_fence_info with all | |
| 61 | + * @sync_fence_info: pointer to array of struct &sync_fence_info with all | |
| 58 | 62 | * fences in the sync_file |
| 63 | + * | |
| 64 | + * Takes a struct sync_file_info. If num_fences is 0, the field is updated | |
| 65 | + * with the actual number of fences. If num_fences is > 0, the system will | |
| 66 | + * use the pointer provided on sync_fence_info to return up to num_fences of | |
| 67 | + * struct sync_fence_info, with detailed fence information. | |
| 59 | 68 | */ |
| 60 | 69 | struct sync_file_info { |
| 61 | 70 | char name[32]; |
| @@ -69,30 +78,14 @@ struct sync_file_info { · 7 unmodified lines | ||
| 69 | 78 | |
| 70 | 79 | #define SYNC_IOC_MAGIC '>' |
| 71 | 80 | |
| 72 | −/** | |
| 81 | +/* | |
| 73 | 82 | * Opcodes 0, 1 and 2 were burned during a API change to avoid users of the |
| 74 | 83 | * old API to get weird errors when trying to handling sync_files. The API |
| 75 | 84 | * change happened during the de-stage of the Sync Framework when there was |
| 76 | 85 | * no upstream users available. |
| 77 | 86 | */ |
| 78 | 87 | |
| 79 | −/** | |
| 80 | − * DOC: SYNC_IOC_MERGE - merge two fences | |
| 81 | − * | |
| 82 | − * Takes a struct sync_merge_data. Creates a new fence containing copies of | |
| 83 | − * the sync_pts in both the calling fd and sync_merge_data.fd2. Returns the | |
| 84 | − * new fence's fd in sync_merge_data.fence | |
| 85 | − */ | |
| 86 | 88 | #define SYNC_IOC_MERGE _IOWR(SYNC_IOC_MAGIC, 3, struct sync_merge_data) |
| 87 | − | |
| 88 | −/** | |
| 89 | − * DOC: SYNC_IOC_FILE_INFO - get detailed information on a sync_file | |
| 90 | − * | |
| 91 | − * Takes a struct sync_file_info. If num_fences is 0, the field is updated | |
| 92 | − * with the actual number of fences. If num_fences is > 0, the system will | |
| 93 | − * use the pointer provided on sync_fence_info to return up to num_fences of | |
| 94 | − * struct sync_fence_info, with detailed fence information. | |
| 95 | − */ | |
| 96 | 89 | #define SYNC_IOC_FILE_INFO _IOWR(SYNC_IOC_MAGIC, 4, struct sync_file_info) |
| 97 | 90 | |
| 98 | 91 | #endif /* _UAPI_LINUX_SYNC_H */ |