Currently when WoL is supported but disabled, ethtool reports: "Supports Wake-on: d". Fix the indication of Wol support, so that the indication remains "g" all the time if the NIC supports WoL. Tested: As accepted, when NIC supports WoL- ethtool reports: Supports Wake-on: g Wake-on: d when NIC doesn't support WoL- ethtool reports: Supports Wake-on: d Wake-on: d
Unified · Split
| @@ -223,6 +223,7 @@ static void mlx4_en_get_wol(struct net_device *netdev, · 222 unmodified lines | |||
| 223 | struct ethtool_wolinfo *wol) | 223 | struct ethtool_wolinfo *wol) |
| 224 | { | 224 | { |
| 225 | struct mlx4_en_priv *priv = netdev_priv(netdev); | 225 | struct mlx4_en_priv *priv = netdev_priv(netdev); |
| 226 | struct mlx4_caps *caps = &priv->mdev->dev->caps; | ||
| 226 | int err = 0; | 227 | int err = 0; |
| 227 | u64 config = 0; | 228 | u64 config = 0; |
| 228 | u64 mask; | 229 | u64 mask; |
| @@ -235,24 +236,24 @@ static void mlx4_en_get_wol(struct net_device *netdev, · 6 unmodified lines | |||
| 235 | mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : | 236 | mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : |
| 236 | MLX4_DEV_CAP_FLAG_WOL_PORT2; | 237 | MLX4_DEV_CAP_FLAG_WOL_PORT2; |
| 237 | 238 | ||
| 238 | if (!(priv->mdev->dev->caps.flags & mask)) { | 239 | if (!(caps->flags & mask)) { |
| 239 | wol->supported = 0; | 240 | wol->supported = 0; |
| 240 | wol->wolopts = 0; | 241 | wol->wolopts = 0; |
| 241 | return; | 242 | return; |
| 242 | } | 243 | } |
| 243 | 244 | ||
| 245 | if (caps->wol_port[priv->port]) | ||
| 246 | wol->supported = WAKE_MAGIC; | ||
| 247 | else | ||
| 248 | wol->supported = 0; | ||
| 249 | |||
| 244 | err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); | 250 | err = mlx4_wol_read(priv->mdev->dev, &config, priv->port); |
| 245 | if (err) { | 251 | if (err) { |
| 246 | en_err(priv, "Failed to get WoL information\n"); | 252 | en_err(priv, "Failed to get WoL information\n"); |
| 247 | return; | 253 | return; |
| 248 | } | 254 | } |
| 249 | 255 | ||
| 250 | if (config & MLX4_EN_WOL_MAGIC) | 256 | if ((config & MLX4_EN_WOL_ENABLED) && (config & MLX4_EN_WOL_MAGIC)) |
| 251 | wol->supported = WAKE_MAGIC; | ||
| 252 | else | ||
| 253 | wol->supported = 0; | ||
| 254 | |||
| 255 | if (config & MLX4_EN_WOL_ENABLED) | ||
| 256 | wol->wolopts = WAKE_MAGIC; | 257 | wol->wolopts = WAKE_MAGIC; |
| 257 | else | 258 | else |
| 258 | wol->wolopts = 0; | 259 | wol->wolopts = 0; |
| @@ -764,6 +764,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) · 763 unmodified lines | |||
| 764 | #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e | 764 | #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e |
| 765 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f | 765 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f |
| 766 | #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 | 766 | #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 |
| 767 | #define QUERY_DEV_CAP_WOL_OFFSET 0x43 | ||
| 767 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 | 768 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 |
| 768 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 | 769 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 |
| 769 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 | 770 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 |
| @@ -920,6 +921,9 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) · 150 unmodified lines | |||
| 920 | MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); | 921 | MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 921 | MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); | 922 | MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); |
| 922 | dev_cap->flags = flags | (u64)ext_flags << 32; | 923 | dev_cap->flags = flags | (u64)ext_flags << 32; |
| 924 | MLX4_GET(field, outbox, QUERY_DEV_CAP_WOL_OFFSET); | ||
| 925 | dev_cap->wol_port[1] = !!(field & 0x20); | ||
| 926 | dev_cap->wol_port[2] = !!(field & 0x40); | ||
| 923 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); | 927 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); |
| 924 | dev_cap->reserved_uars = field >> 4; | 928 | dev_cap->reserved_uars = field >> 4; |
| 925 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); | 929 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); |
| @@ -129,6 +129,7 @@ struct mlx4_dev_cap { · 128 unmodified lines | |||
| 129 | u32 dmfs_high_rate_qpn_range; | 129 | u32 dmfs_high_rate_qpn_range; |
| 130 | struct mlx4_rate_limit_caps rl_caps; | 130 | struct mlx4_rate_limit_caps rl_caps; |
| 131 | struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1]; | 131 | struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1]; |
| 132 | bool wol_port[MLX4_MAX_PORTS + 1]; | ||
| 132 | }; | 133 | }; |
| 133 | 134 | ||
| 134 | struct mlx4_func_cap { | 135 | struct mlx4_func_cap { |
| @@ -424,6 +424,8 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) · 423 unmodified lines | |||
| 424 | dev->caps.stat_rate_support = dev_cap->stat_rate_support; | 424 | dev->caps.stat_rate_support = dev_cap->stat_rate_support; |
| 425 | dev->caps.max_gso_sz = dev_cap->max_gso_sz; | 425 | dev->caps.max_gso_sz = dev_cap->max_gso_sz; |
| 426 | dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; | 426 | dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; |
| 427 | dev->caps.wol_port[1] = dev_cap->wol_port[1]; | ||
| 428 | dev->caps.wol_port[2] = dev_cap->wol_port[2]; | ||
| 427 | 429 | ||
| 428 | /* Save uar page shift */ | 430 | /* Save uar page shift */ |
| 429 | if (!mlx4_is_slave(dev)) { | 431 | if (!mlx4_is_slave(dev)) { |
| @@ -620,6 +620,7 @@ struct mlx4_caps { · 619 unmodified lines | |||
| 620 | u32 dmfs_high_rate_qpn_base; | 620 | u32 dmfs_high_rate_qpn_base; |
| 621 | u32 dmfs_high_rate_qpn_range; | 621 | u32 dmfs_high_rate_qpn_range; |
| 622 | u32 vf_caps; | 622 | u32 vf_caps; |
| 623 | bool wol_port[MLX4_MAX_PORTS + 1]; | ||
| 623 | struct mlx4_rate_limit_caps rl_caps; | 624 | struct mlx4_rate_limit_caps rl_caps; |
| 624 | }; | 625 | }; |
| 625 | 626 | ||