Pull x86 cpuid updates from Borislav Petkov: - Make sure the "svm" feature flag is cleared from /proc/cpuinfo when virtualization support is disabled in the BIOS on AMD and Hygon platforms - A minor cleanup * tag 'x86_cpu_for_6.7_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpu/amd: Remove redundant 'break' statement x86/cpu: Clear SVM feature if disabled by BIOS
Unified · Split
| @@ -1117,12 +1117,16 @@ · 1116 unmodified lines | ||
| 1117 | 1117 | #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) |
| 1118 | 1118 | #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) |
| 1119 | 1119 | #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F |
| 1120 | −/* AMD-V MSRs */ | |
| 1121 | 1120 | |
| 1121 | +/* AMD-V MSRs */ | |
| 1122 | 1122 | #define MSR_VM_CR 0xc0010114 |
| 1123 | 1123 | #define MSR_VM_IGNNE 0xc0010115 |
| 1124 | 1124 | #define MSR_VM_HSAVE_PA 0xc0010117 |
| 1125 | 1125 | |
| 1126 | +#define SVM_VM_CR_VALID_MASK 0x001fULL | |
| 1127 | +#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL | |
| 1128 | +#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL | |
| 1129 | + | |
| 1126 | 1130 | /* Hardware Feedback Interface */ |
| 1127 | 1131 | #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 |
| 1128 | 1132 | #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 |
| @@ -229,10 +229,6 @@ struct __attribute__ ((__packed__)) vmcb_control_area { · 228 unmodified lines | ||
| 229 | 229 | #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) |
| 230 | 230 | #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) |
| 231 | 231 | |
| 232 | −#define SVM_VM_CR_VALID_MASK 0x001fULL | |
| 233 | −#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL | |
| 234 | −#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL | |
| 235 | − | |
| 236 | 232 | #define SVM_NESTED_CTL_NP_ENABLE BIT(0) |
| 237 | 233 | #define SVM_NESTED_CTL_SEV_ENABLE BIT(1) |
| 238 | 234 | #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2) |
| @@ -572,8 +568,6 @@ struct vmcb { · 333 unmodified lines | ||
| 572 | 568 | |
| 573 | 569 | #define SVM_CPUID_FUNC 0x8000000a |
| 574 | 570 | |
| 575 | −#define SVM_VM_CR_SVM_DISABLE 4 | |
| 576 | − | |
| 577 | 571 | #define SVM_SELECTOR_S_SHIFT 4 |
| 578 | 572 | #define SVM_SELECTOR_DPL_SHIFT 5 |
| 579 | 573 | #define SVM_SELECTOR_P_SHIFT 7 |
| @@ -1014,7 +1014,6 @@ static bool cpu_has_zenbleed_microcode(void) · 1013 unmodified lines | ||
| 1014 | 1014 | |
| 1015 | 1015 | default: |
| 1016 | 1016 | return false; |
| 1017 | − break; | |
| 1018 | 1017 | } |
| 1019 | 1018 | |
| 1020 | 1019 | if (boot_cpu_data.microcode < good_rev) |
| @@ -1044,6 +1043,8 @@ static void zenbleed_check(struct cpuinfo_x86 *c) · 23 unmodified lines | ||
| 1044 | 1043 | |
| 1045 | 1044 | static void init_amd(struct cpuinfo_x86 *c) |
| 1046 | 1045 | { |
| 1046 | + u64 vm_cr; | |
| 1047 | + | |
| 1047 | 1048 | early_init_amd(c); |
| 1048 | 1049 | |
| 1049 | 1050 | /* |
| @@ -1095,6 +1096,14 @@ static void init_amd(struct cpuinfo_x86 *c) · 45 unmodified lines | ||
| 1095 | 1096 | |
| 1096 | 1097 | init_amd_cacheinfo(c); |
| 1097 | 1098 | |
| 1099 | + if (cpu_has(c, X86_FEATURE_SVM)) { | |
| 1100 | + rdmsrl(MSR_VM_CR, vm_cr); | |
| 1101 | + if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { | |
| 1102 | + pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); | |
| 1103 | + clear_cpu_cap(c, X86_FEATURE_SVM); | |
| 1104 | + } | |
| 1105 | + } | |
| 1106 | + | |
| 1098 | 1107 | if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { |
| 1099 | 1108 | /* |
| 1100 | 1109 | * Use LFENCE for execution serialization. On families which |
| @@ -290,6 +290,8 @@ static void early_init_hygon(struct cpuinfo_x86 *c) · 289 unmodified lines | ||
| 290 | 290 | |
| 291 | 291 | static void init_hygon(struct cpuinfo_x86 *c) |
| 292 | 292 | { |
| 293 | + u64 vm_cr; | |
| 294 | + | |
| 293 | 295 | early_init_hygon(c); |
| 294 | 296 | |
| 295 | 297 | /* |
| @@ -320,6 +322,14 @@ static void init_hygon(struct cpuinfo_x86 *c) · 24 unmodified lines | ||
| 320 | 322 | |
| 321 | 323 | init_hygon_cacheinfo(c); |
| 322 | 324 | |
| 325 | + if (cpu_has(c, X86_FEATURE_SVM)) { | |
| 326 | + rdmsrl(MSR_VM_CR, vm_cr); | |
| 327 | + if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { | |
| 328 | + pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); | |
| 329 | + clear_cpu_cap(c, X86_FEATURE_SVM); | |
| 330 | + } | |
| 331 | + } | |
| 332 | + | |
| 323 | 333 | if (cpu_has(c, X86_FEATURE_XMM2)) { |
| 324 | 334 | /* |
| 325 | 335 | * Use LFENCE for execution serialization. On families which |
| @@ -531,8 +531,6 @@ static bool __kvm_is_svm_supported(void) · 530 unmodified lines | ||
| 531 | 531 | int cpu = smp_processor_id(); |
| 532 | 532 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
| 533 | 533 | |
| 534 | − u64 vm_cr; | |
| 535 | − | |
| 536 | 534 | if (c->x86_vendor != X86_VENDOR_AMD && |
| 537 | 535 | c->x86_vendor != X86_VENDOR_HYGON) { |
| 538 | 536 | pr_err("CPU %d isn't AMD or Hygon\n", cpu); |
| @@ -549,12 +547,6 @@ static bool __kvm_is_svm_supported(void) · 10 unmodified lines | ||
| 549 | 547 | return false; |
| 550 | 548 | } |
| 551 | 549 | |
| 552 | − rdmsrl(MSR_VM_CR, vm_cr); | |
| 553 | − if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) { | |
| 554 | − pr_err("SVM disabled (by BIOS) in MSR_VM_CR on CPU %d\n", cpu); | |
| 555 | − return false; | |
| 556 | − } | |
| 557 | − | |
| 558 | 550 | return true; |
| 559 | 551 | } |
| 560 | 552 | |