Merge tag 'drm-etnaviv-fixes-2024-04-25' of https://git.pengutronix.de/git/lst/linux into drm-fixes

- fix GC7000 TX clock gating - revert NPU UAPI changes Signed-off-by: Dave Airlie <airlied@redhat.com>

Dave Airlie committed 2 years ago

Commit ca382d62 parents 86ab998 e877d704 files · +2 −73Browse files

Unified · Split

4 files

drivers/gpu/drm/etnaviv/etnaviv_gpu.c +2 −22
drivers/gpu/drm/etnaviv/etnaviv_gpu.h +0 −12
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c +0 −34
include/uapi/drm/etnaviv_drm.h +0 −5

drivers/gpu/drm/etnaviv/etnaviv_gpu.c+2−22

@@ -164,26 +164,6 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu gpu, u32 param, u64 value) · 163 unmodified lines
164	164	*value = gpu->identity.eco_id;
165	165	break;
166	166
167		− case ETNAVIV_PARAM_GPU_NN_CORE_COUNT:
168		− *value = gpu->identity.nn_core_count;
169		− break;
170		−
171		− case ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE:
172		− *value = gpu->identity.nn_mad_per_core;
173		− break;
174		−
175		− case ETNAVIV_PARAM_GPU_TP_CORE_COUNT:
176		− *value = gpu->identity.tp_core_count;
177		− break;
178		−
179		− case ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE:
180		− *value = gpu->identity.on_chip_sram_size;
181		− break;
182		−
183		− case ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE:
184		− *value = gpu->identity.axi_sram_size;
185		− break;
186		−
187	167	default:
188	168	DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
189	169	return -EINVAL;
@@ -663,8 +643,8 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) · 473 unmodified lines
663	643	/* Disable TX clock gating on affected core revisions. */
664	644	if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) \|\|
665	645	etnaviv_is_model_rev(gpu, GC2000, 0x5108) \|\|
666		− etnaviv_is_model_rev(gpu, GC2000, 0x6202) \|\|
667		− etnaviv_is_model_rev(gpu, GC2000, 0x6203))
	646	+ etnaviv_is_model_rev(gpu, GC7000, 0x6202) \|\|
	647	+ etnaviv_is_model_rev(gpu, GC7000, 0x6203))
668	648	pmc \|= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
669	649
670	650	/* Disable SE and RA clock gating on affected core revisions. */

drivers/gpu/drm/etnaviv/etnaviv_gpu.h+0−12

@@ -54,18 +54,6 @@ struct etnaviv_chip_identity { · 53 unmodified lines
54	54	/* Number of Neural Network cores. */
55	55	u32 nn_core_count;
56	56
57		− /* Number of MAD units per Neural Network core. */
58		− u32 nn_mad_per_core;
59		−
60		− /* Number of Tensor Processing cores. */
61		− u32 tp_core_count;
62		−
63		− /* Size in bytes of the SRAM inside the NPU. */
64		− u32 on_chip_sram_size;
65		−
66		− /* Size in bytes of the SRAM across the AXI bus. */
67		− u32 axi_sram_size;
68		−
69	57	/* Size of the vertex cache. */
70	58	u32 vertex_cache_size;
71	59

drivers/gpu/drm/etnaviv/etnaviv_hwdb.c+0−34

@@ -17,10 +17,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = { · 16 unmodified lines
17	17	.thread_count = 128,
18	18	.shader_core_count = 1,
19	19	.nn_core_count = 0,
20		− .nn_mad_per_core = 0,
21		− .tp_core_count = 0,
22		− .on_chip_sram_size = 0,
23		− .axi_sram_size = 0,
24	20	.vertex_cache_size = 8,
25	21	.vertex_output_buffer_size = 1024,
26	22	.pixel_pipes = 1,
@@ -52,11 +48,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = { · 25 unmodified lines
52	48	.register_max = 64,
53	49	.thread_count = 256,
54	50	.shader_core_count = 1,
55		− .nn_core_count = 0,
56		− .nn_mad_per_core = 0,
57		− .tp_core_count = 0,
58		− .on_chip_sram_size = 0,
59		− .axi_sram_size = 0,
60	51	.vertex_cache_size = 8,
61	52	.vertex_output_buffer_size = 512,
62	53	.pixel_pipes = 1,
@@ -89,10 +80,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = { · 26 unmodified lines
89	80	.thread_count = 512,
90	81	.shader_core_count = 2,
91	82	.nn_core_count = 0,
92		− .nn_mad_per_core = 0,
93		− .tp_core_count = 0,
94		− .on_chip_sram_size = 0,
95		− .axi_sram_size = 0,
96	83	.vertex_cache_size = 16,
97	84	.vertex_output_buffer_size = 1024,
98	85	.pixel_pipes = 1,
@@ -125,10 +112,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = { · 26 unmodified lines
125	112	.thread_count = 512,
126	113	.shader_core_count = 2,
127	114	.nn_core_count = 0,
128		− .nn_mad_per_core = 0,
129		− .tp_core_count = 0,
130		− .on_chip_sram_size = 0,
131		− .axi_sram_size = 0,
132	115	.vertex_cache_size = 16,
133	116	.vertex_output_buffer_size = 1024,
134	117	.pixel_pipes = 1,
@@ -160,11 +143,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = { · 25 unmodified lines
160	143	.register_max = 64,
161	144	.thread_count = 512,
162	145	.shader_core_count = 2,
163		− .nn_core_count = 0,
164		− .nn_mad_per_core = 0,
165		− .tp_core_count = 0,
166		− .on_chip_sram_size = 0,
167		− .axi_sram_size = 0,
168	146	.vertex_cache_size = 16,
169	147	.vertex_output_buffer_size = 1024,
170	148	.pixel_pipes = 1,
@@ -197,10 +175,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = { · 26 unmodified lines
197	175	.thread_count = 1024,
198	176	.shader_core_count = 4,
199	177	.nn_core_count = 0,
200		− .nn_mad_per_core = 0,
201		− .tp_core_count = 0,
202		− .on_chip_sram_size = 0,
203		− .axi_sram_size = 0,
204	178	.vertex_cache_size = 16,
205	179	.vertex_output_buffer_size = 1024,
206	180	.pixel_pipes = 2,
@@ -233,10 +207,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = { · 26 unmodified lines
233	207	.thread_count = 256,
234	208	.shader_core_count = 1,
235	209	.nn_core_count = 8,
236		− .nn_mad_per_core = 64,
237		− .tp_core_count = 4,
238		− .on_chip_sram_size = 524288,
239		− .axi_sram_size = 1048576,
240	210	.vertex_cache_size = 16,
241	211	.vertex_output_buffer_size = 1024,
242	212	.pixel_pipes = 1,
@@ -269,10 +239,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = { · 26 unmodified lines
269	239	.thread_count = 256,
270	240	.shader_core_count = 1,
271	241	.nn_core_count = 6,
272		− .nn_mad_per_core = 64,
273		− .tp_core_count = 3,
274		− .on_chip_sram_size = 262144,
275		− .axi_sram_size = 0,
276	242	.vertex_cache_size = 16,
277	243	.vertex_output_buffer_size = 1024,
278	244	.pixel_pipes = 1,

include/uapi/drm/etnaviv_drm.h+0−5

@@ -77,11 +77,6 @@ struct drm_etnaviv_timespec { · 76 unmodified lines
77	77	#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
78	78	#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
79	79	#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
80		−#define ETNAVIV_PARAM_GPU_NN_CORE_COUNT 0x1f
81		−#define ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE 0x20
82		−#define ETNAVIV_PARAM_GPU_TP_CORE_COUNT 0x21
83		−#define ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE 0x22
84		−#define ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE 0x23
85	80
86	81	#define ETNA_MAX_PIPES 4
87	82