Merge tag 'drm-fixes-2020-01-03' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie: "New Years fixes! Mostly amdgpu with a light smattering of arm graphics, and two AGP warning fixes. Quiet as expected, hopefully we don't get a post holiday rush. agp: - two unused variable removed amdgpu: - ATPX regression fix - SMU metrics table locking fixes - gfxoff fix for raven - RLC firmware loading stability fix mediatek: - external display fix - dsi timing fix sun4i: - Fix double-free in connector/encoder cleanup (Stefan) maildp: - Make vtable static (Ben)" * tag 'drm-fixes-2020-01-03' of git://anongit.freedesktop.org/drm/drm: agp: remove unused variable arqsz in agp_3_5_enable() agp: remove unused variable mcapndx drm/amdgpu: correct RLC firmwares loading sequence drm/amdgpu: enable gfxoff for raven1 refresh drm/amdgpu/smu: add metrics table lock for vega20 (v2) drm/amdgpu/smu: add metrics table lock for navi (v2) drm/amdgpu/smu: add metrics table lock for arcturus (v2) drm/amdgpu/smu: add metrics table lock Revert "drm/amdgpu: simplify ATPX detection" drm/arm/mali: make malidp_mw_connector_helper_funcs static drm/sun4i: hdmi: Remove duplicate cleanup calls drm/mediatek: reduce the hbp and hfp for phy timing drm/mediatek: Fix can't get component for external display plane. drm/mediatek: Check return value of mtk_drm_ddp_comp_for_plane.

Linus Torvalds committed 6 years ago

Commit ca78fde2 parents 15f0ec9 a6204fc14 files · +80 −60Browse files

Unified · Split

14 files

drivers/char/agp/isoch.c +1 −8
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +11 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +1 −1
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +1 −1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +4 −11
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +1 −0
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +3 −0
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +1 −0
drivers/gpu/drm/amd/powerplay/navi10_ppt.c +3 −0
drivers/gpu/drm/amd/powerplay/vega20_ppt.c +3 −0
drivers/gpu/drm/arm/malidp_mw.c +1 −1
drivers/gpu/drm/mediatek/mtk_drm_crtc.c +12 −6
drivers/gpu/drm/mediatek/mtk_dsi.c +38 −29
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +0 −2

drivers/char/agp/isoch.c+1−8

 	unsigned int cdev = 0;
 	u32 mnistat, tnistat, tstatus, mcmd;
 	u16 tnicmd, mnicmd;
-	u8 mcapndx;
 	u32 tot_bw = 0, tot_n = 0, tot_rq = 0, y_max, rq_isoch, rq_async;
 	u32 step, rem, rem_isoch, rem_async;
 	int ret = 0;
 		cur = list_entry(pos, struct agp_3_5_dev, list);
 		dev = cur->dev;
-		mcapndx = cur->capndx;
 		pci_read_config_dword(dev, cur->capndx+AGPNISTAT, &mnistat);
 		master[cdev].maxbw = (mnistat >> 16) & 0xff;
 		cur = master[cdev].dev;
 		dev = cur->dev;
-		mcapndx = cur->capndx;
 		master[cdev].rq += (cdev == ndevs - 1)
 		              ? (rem_async + rem_isoch) : step;
 {
 	struct pci_dev *td = bridge->dev, *dev = NULL;
 	u8 mcapndx;
-	u32 isoch, arqsz;
+	u32 isoch;
 	u32 tstatus, mstatus, ncapid;
 	u32 mmajor;
 	u16 mpstat;
 	if (isoch == 0)	/* isoch xfers not available, bail out. */
 		return -ENODEV;
-	arqsz     = (tstatus >> 13) & 0x7;
 	/*
 	 * Allocate a head for our AGP 3.5 device list
 	 * (multiple AGP v3 devices are allowed behind a single bridge).

drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c+11−1

@@ -613,7 +613,17 @@ static bool amdgpu_atpx_detect(void) · 612 unmodified lines
613	bool d3_supported = false;	613	bool d3_supported = false;
614	struct pci_dev *parent_pdev;	614	struct pci_dev *parent_pdev;
615		615
616	while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) != NULL) {	616	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
		617	vga_count++;
		618
		619	has_atpx \|= (amdgpu_atpx_pci_probe_handle(pdev) == true);
		620
		621	parent_pdev = pci_upstream_bridge(pdev);
		622	d3_supported \|= parent_pdev && parent_pdev->bridge_d3;
		623	amdgpu_atpx_get_quirks(pdev);
		624	}
		625
		626	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
617	vga_count++;	627	vga_count++;
618		628
619	has_atpx \|= (amdgpu_atpx_pci_probe_handle(pdev) == true);	629	has_atpx \|= (amdgpu_atpx_pci_probe_handle(pdev) == true);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+1−1

@@ -1488,7 +1488,7 @@ out: · 1487 unmodified lines
1488		1488
1489	/* Start rlc autoload after psp recieved all the gfx firmware */	1489	/* Start rlc autoload after psp recieved all the gfx firmware */
1490	if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?	1490	if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
1491	AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {	1491	AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
1492	ret = psp_rlc_autoload(psp);	1492	ret = psp_rlc_autoload(psp);
1493	if (ret) {	1493	if (ret) {
1494	DRM_ERROR("Failed to start rlc autoload\n");	1494	DRM_ERROR("Failed to start rlc autoload\n");

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h+1−1

 	AMDGPU_UCODE_ID_CP_MEC2_JT,
 	AMDGPU_UCODE_ID_CP_MES,
 	AMDGPU_UCODE_ID_CP_MES_DATA,
-	AMDGPU_UCODE_ID_RLC_G,
 	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
 	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
 	AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
+	AMDGPU_UCODE_ID_RLC_G,
 	AMDGPU_UCODE_ID_STORAGE,
 	AMDGPU_UCODE_ID_SMC,
 	AMDGPU_UCODE_ID_UVD,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+4−11

 	case CHIP_VEGA20:
 		break;
 	case CHIP_RAVEN:
-		/* Disable GFXOFF on original raven.  There are combinations
+		if (!(adev->rev_id >= 0x8 ||
-		 * of sbios and platforms that are not stable.
+		      adev->pdev->device == 0x15d8) &&
-		 */
+		    (adev->pm.fw_version < 0x41e2b || /* not raven1 fresh */
-		if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8))
+		     !adev->gfx.rlc.is_rlc_v2_1)) /* without rlc save restore ucodes */
-			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
-		else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
-			 &&((adev->gfx.rlc_fw_version != 106 &&
-			     adev->gfx.rlc_fw_version < 531) ||
-			    (adev->gfx.rlc_fw_version == 53815) ||
-			    (adev->gfx.rlc_feature_version < 1) ||
-			    !adev->gfx.rlc.is_rlc_v2_1))
 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		if (adev->pm.pp_feature & PP_GFXOFF_MASK)

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c+1−0

@@ -866,6 +866,7 @@ static int smu_sw_init(void *handle) · 865 unmodified lines
866	smu->smu_baco.platform_support = false;	866	smu->smu_baco.platform_support = false;
867		867
868	mutex_init(&smu->sensor_lock);	868	mutex_init(&smu->sensor_lock);
		869	mutex_init(&smu->metrics_lock);
869		870
870	smu->watermarks_bitmap = 0;	871	smu->watermarks_bitmap = 0;
871	smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;	872	smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;

drivers/gpu/drm/amd/powerplay/arcturus_ppt.c+3−0

 	struct smu_table_context *smu_table= &smu->smu_table;
 	int ret = 0;
+	mutex_lock(&smu->metrics_lock);
 	if (!smu_table->metrics_time ||
 	     time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
 		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 				(void *)smu_table->metrics_table, false);
 		if (ret) {
 			pr_info("Failed to export SMU metrics table!\n");
+			mutex_unlock(&smu->metrics_lock);
 			return ret;
 		}
 		smu_table->metrics_time = jiffies;
 	}
 	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
+	mutex_unlock(&smu->metrics_lock);
 	return ret;
 }

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h+1−0

@@ -349,6 +349,7 @@ struct smu_context · 348 unmodified lines
349	const struct pptable_funcs *ppt_funcs;	349	const struct pptable_funcs *ppt_funcs;
350	struct mutex mutex;	350	struct mutex mutex;
351	struct mutex sensor_lock;	351	struct mutex sensor_lock;
		352	struct mutex metrics_lock;
352	uint64_t pool_size;	353	uint64_t pool_size;
353		354
354	struct smu_table_context smu_table;	355	struct smu_table_context smu_table;

drivers/gpu/drm/amd/powerplay/navi10_ppt.c+3−0

 	struct smu_table_context *smu_table= &smu->smu_table;
 	int ret = 0;
+	mutex_lock(&smu->metrics_lock);
 	if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
 		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 				(void *)smu_table->metrics_table, false);
 		if (ret) {
 			pr_info("Failed to export SMU metrics table!\n");
+			mutex_unlock(&smu->metrics_lock);
 			return ret;
 		}
 		smu_table->metrics_time = jiffies;
 	}
 	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
+	mutex_unlock(&smu->metrics_lock);
 	return ret;
 }

drivers/gpu/drm/amd/powerplay/vega20_ppt.c+3−0

 	struct smu_table_context *smu_table= &smu->smu_table;
 	int ret = 0;
+	mutex_lock(&smu->metrics_lock);
 	if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
 		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 				(void *)smu_table->metrics_table, false);
 		if (ret) {
 			pr_info("Failed to export SMU metrics table!\n");
+			mutex_unlock(&smu->metrics_lock);
 			return ret;
 		}
 		smu_table->metrics_time = jiffies;
 	}
 	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
+	mutex_unlock(&smu->metrics_lock);
 	return ret;
 }

drivers/gpu/drm/arm/malidp_mw.c+1−1

@@ -56,7 +56,7 @@ malidp_mw_connector_mode_valid(struct drm_connector *connector, · 55 unmodified lines
56	return MODE_OK;	56	return MODE_OK;
57	}	57	}
58		58
59	const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = {	59	static const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = {
60	.get_modes = malidp_mw_connector_get_modes,	60	.get_modes = malidp_mw_connector_get_modes,
61	.mode_valid = malidp_mw_connector_mode_valid,	61	.mode_valid = malidp_mw_connector_mode_valid,
62	};	62	};

drivers/gpu/drm/mediatek/mtk_drm_crtc.c+12−6

 	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
 	struct mtk_ddp_comp *comp;
 	int i, count = 0;
+	unsigned int local_index = plane - mtk_crtc->planes;
 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
 		comp = mtk_crtc->ddp_comp[i];
-		if (plane->index < (count + mtk_ddp_comp_layer_nr(comp))) {
+		if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
-			*local_layer = plane->index - count;
+			*local_layer = local_index - count;
 			return comp;
 		}
 		count += mtk_ddp_comp_layer_nr(comp);
 		plane_state = to_mtk_plane_state(plane->state);
 		comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
-		mtk_ddp_comp_layer_config(comp, local_layer, plane_state);
+		if (comp)
+			mtk_ddp_comp_layer_config(comp, local_layer,
+						  plane_state);
 	}
 	return 0;
 			comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
 							  &local_layer);
-			mtk_ddp_comp_layer_config(comp, local_layer,
+			if (comp)
-						  plane_state);
+				mtk_ddp_comp_layer_config(comp, local_layer,
+							  plane_state);
 			plane_state->pending.config = false;
 		}
 		mtk_crtc->pending_planes = false;
 	struct mtk_ddp_comp *comp;
 	comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
-	return mtk_ddp_comp_layer_check(comp, local_layer, state);
+	if (comp)
+		return mtk_ddp_comp_layer_check(comp, local_layer, state);
+	return 0;
 }
 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,

drivers/gpu/drm/mediatek/mtk_dsi.c+38−29

@@ -230,28 +230,25 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) · 229 unmodified lines
230	static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)	230	static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
231	{	231	{
232	u32 timcon0, timcon1, timcon2, timcon3;	232	u32 timcon0, timcon1, timcon2, timcon3;
233	u32 ui, cycle_time;	233	u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
234	struct mtk_phy_timing *timing = &dsi->phy_timing;	234	struct mtk_phy_timing *timing = &dsi->phy_timing;
235		235
236	ui = DIV_ROUND_UP(1000000000, dsi->data_rate);	236	timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
237	cycle_time = div_u64(8000000000ULL, dsi->data_rate);	237	timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
		238	timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
		239	timing->da_hs_prepare;
		240	timing->da_hs_trail = timing->da_hs_prepare + 1;
238		241
239	timing->lpx = NS_TO_CYCLE(60, cycle_time);	242	timing->ta_go = 4 * timing->lpx - 2;
240	timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);	243	timing->ta_sure = timing->lpx + 2;
241	timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);	244	timing->ta_get = 4 * timing->lpx;
242	timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);	245	timing->da_hs_exit = 2 * timing->lpx + 1;
243		246
244	timing->ta_go = 4 * timing->lpx;	247	timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
245	timing->ta_sure = 3 * timing->lpx / 2;	248	timing->clk_hs_post = timing->clk_hs_prepare + 8;
246	timing->ta_get = 5 * timing->lpx;	249	timing->clk_hs_trail = timing->clk_hs_prepare;
247	timing->da_hs_exit = 2 * timing->lpx;	250	timing->clk_hs_zero = timing->clk_hs_trail * 4;
248		251	timing->clk_hs_exit = 2 * timing->clk_hs_trail;
249	timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
250	timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
251
252	timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
253	timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
254	timing->clk_hs_exit = 2 * timing->lpx;
255		252
256	timcon0 = timing->lpx \| timing->da_hs_prepare << 8 \|	253	timcon0 = timing->lpx \| timing->da_hs_prepare << 8 \|
257	timing->da_hs_zero << 16 \| timing->da_hs_trail << 24;	254	timing->da_hs_zero << 16 \| timing->da_hs_trail << 24;
@@ -482,27 +479,39 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) · 224 unmodified lines
482	dsi_tmp_buf_bpp - 10);	479	dsi_tmp_buf_bpp - 10);
483		480
484	data_phy_cycles = timing->lpx + timing->da_hs_prepare +	481	data_phy_cycles = timing->lpx + timing->da_hs_prepare +
485	timing->da_hs_zero + timing->da_hs_exit + 2;	482	timing->da_hs_zero + timing->da_hs_exit + 3;
486		483
487	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {	484	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
488	if (vm->hfront_porch * dsi_tmp_buf_bpp >	485	if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
489	data_phy_cycles * dsi->lanes + 18) {	486	data_phy_cycles * dsi->lanes + 18) {
490	horizontal_frontporch_byte = vm->hfront_porch *	487	horizontal_frontporch_byte =
491	dsi_tmp_buf_bpp -	488	vm->hfront_porch * dsi_tmp_buf_bpp -
492	data_phy_cycles *	489	(data_phy_cycles * dsi->lanes + 18) *
493	dsi->lanes - 18;	490	vm->hfront_porch /
		491	(vm->hfront_porch + vm->hback_porch);
		492
		493	horizontal_backporch_byte =
		494	horizontal_backporch_byte -
		495	(data_phy_cycles * dsi->lanes + 18) *
		496	vm->hback_porch /
		497	(vm->hfront_porch + vm->hback_porch);
494	} else {	498	} else {
495	DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");	499	DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
496	horizontal_frontporch_byte = vm->hfront_porch *	500	horizontal_frontporch_byte = vm->hfront_porch *
497	dsi_tmp_buf_bpp;	501	dsi_tmp_buf_bpp;
498	}	502	}
499	} else {	503	} else {
500	if (vm->hfront_porch * dsi_tmp_buf_bpp >	504	if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
501	data_phy_cycles * dsi->lanes + 12) {	505	data_phy_cycles * dsi->lanes + 12) {
502	horizontal_frontporch_byte = vm->hfront_porch *	506	horizontal_frontporch_byte =
503	dsi_tmp_buf_bpp -	507	vm->hfront_porch * dsi_tmp_buf_bpp -
504	data_phy_cycles *	508	(data_phy_cycles * dsi->lanes + 12) *
505	dsi->lanes - 12;	509	vm->hfront_porch /
		510	(vm->hfront_porch + vm->hback_porch);
		511	horizontal_backporch_byte = horizontal_backporch_byte -
		512	(data_phy_cycles * dsi->lanes + 12) *
		513	vm->hback_porch /
		514	(vm->hfront_porch + vm->hback_porch);
506	} else {	515	} else {
507	DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");	516	DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
508	horizontal_frontporch_byte = vm->hfront_porch *	517	horizontal_frontporch_byte = vm->hfront_porch *

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c+0−2

@@ -685,8 +685,6 @@ static void sun4i_hdmi_unbind(struct device dev, struct device master, · 684 unmodified lines
685	struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);	685	struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
686		686
687	cec_unregister_adapter(hdmi->cec_adap);	687	cec_unregister_adapter(hdmi->cec_adap);
688	drm_connector_cleanup(&hdmi->connector);
689	drm_encoder_cleanup(&hdmi->encoder);
690	i2c_del_adapter(hdmi->i2c);	688	i2c_del_adapter(hdmi->i2c);
691	i2c_put_adapter(hdmi->ddc_i2c);	689	i2c_put_adapter(hdmi->ddc_i2c);
692	clk_disable_unprepare(hdmi->mod_clk);	690	clk_disable_unprepare(hdmi->mod_clk);

Merge tag 'drm-fixes-2020-01-03' of git://anongit.freedesktop.org/drm/drm

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