lael-labs/linux

drivers/gpu/drm/amd/amdgpu/amdgpu.h+2−1

 #define AMDGPU_RESET_MAGIC_NUM 64
 #define AMDGPU_MAX_DF_PERFMONS 4
+#define AMDGPU_PRODUCT_NAME_LEN 64
 struct amdgpu_device {
 	struct device			*dev;
 	struct pci_dev			*pdev;
 	/* Chip product information */
 	char				product_number[16];
-	char				product_name[32];
+	char				product_name[AMDGPU_PRODUCT_NAME_LEN];
 	char				serial[20];
 	atomic_t			throttling_logging_enabled;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c+3−3

@@ -721,13 +721,13 @@ bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) · 720 unmodified lines
721	return adev->have_atomics_support;	721	return adev->have_atomics_support;
722	}	722	}
723		723
724	void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev)	724	void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset)
725	{	725	{
726	struct ras_err_data err_data = {0, 0, 0, NULL};	726	struct ras_err_data err_data = {0, 0, 0, NULL};
727		727
728	/* CPU MCA will handle page retirement if connected_to_cpu is 1 */	728	/* CPU MCA will handle page retirement if connected_to_cpu is 1 */
729	if (!adev->gmc.xgmi.connected_to_cpu)	729	if (!adev->gmc.xgmi.connected_to_cpu)
730	amdgpu_umc_process_ras_data_cb(adev, &err_data, NULL);	730	amdgpu_umc_poison_handler(adev, &err_data, reset);
731	else	731	else if (reset)
732	amdgpu_amdkfd_gpu_reset(adev);	732	amdgpu_amdkfd_gpu_reset(adev);
733	}	733	}

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h+2−1

 				      uint64_t *mmap_offset);
 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
 				struct tile_config *config);
-void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev);
+void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
+				bool reset);
 #if IS_ENABLED(CONFIG_HSA_AMD)
 void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c+13−14

 	lock_srbm(adev, mec, pipe, 0, 0);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
+	WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
 		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
 		CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
 		       lower_32_bits((uintptr_t)wptr));
 		WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
 		       upper_32_bits((uintptr_t)wptr));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
+		WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
 		       (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
 	}
 	uint32_t low, high;
 	acquire_queue(adev, pipe_id, queue_id);
-	act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+	act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
 	if (act) {
 		low = lower_32_bits(queue_address >> 8);
 		high = upper_32_bits(queue_address >> 8);
-		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
+		if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
-		   high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
+		   high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
 			retval = true;
 	}
 	release_queue(adev);
 	end_jiffies = (utimeout * HZ / 1000) + jiffies;
 	while (true) {
-		temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+		temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
 		if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 			break;
 		if (time_after(jiffies, end_jiffies)) {
 	mutex_lock(&adev->grbm_idx_mutex);
 	WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
+	WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd);
 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 		INSTANCE_BROADCAST_WRITES, 1);
 	pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe;
 	queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe;
 	soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0);
-	reg_val = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +
+	reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +
 			 queue_slot);
 	*wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK;
 	if (*wave_cnt != 0)
 		for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) {
 			gfx_v9_0_select_se_sh(adev, se_idx, sh_idx, 0xffffffff);
-			queue_map = RREG32(SOC15_REG_OFFSET(GC, 0,
+			queue_map = RREG32_SOC15(GC, 0, mmSPI_CSQ_WF_ACTIVE_STATUS);
-					   mmSPI_CSQ_WF_ACTIVE_STATUS));
 			/*
 			 * Assumption: queue map encodes following schema: four
 	/*
 	 * Program TBA registers
 	 */
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
+	WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_LO,
                         lower_32_bits(tba_addr >> 8));
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
+	WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_HI,
                         upper_32_bits(tba_addr >> 8));
 	/*
 	 * Program TMA registers
 	 */
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
+	WREG32_SOC15(GC, 0, mmSQ_SHADER_TMA_LO,
 			lower_32_bits(tma_addr >> 8));
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
+	WREG32_SOC15(GC, 0, mmSQ_SHADER_TMA_HI,
 			upper_32_bits(tma_addr >> 8));
 	unlock_srbm(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+29−17

 		/* need to do gmc hw init early so we can allocate gpu mem */
 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
+			/* Try to reserve bad pages early */
+			if (amdgpu_sriov_vf(adev))
+				amdgpu_virt_exchange_data(adev);
 			r = amdgpu_device_vram_scratch_init(adev);
 			if (r) {
 				DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
 	}
 	if (amdgpu_sriov_vf(adev))
-		amdgpu_virt_init_data_exchange(adev);
+		amdgpu_virt_exchange_data(adev);
 	r = amdgpu_ib_pool_init(adev);
 	if (r) {
 	if (r)
 		DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
-	/* For XGMI + passthrough configuration on arcturus, enable light SBR */
+	/* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
-	if (adev->asic_type == CHIP_ARCTURUS &&
+	if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)||
-	    amdgpu_passthrough(adev) &&
+			       adev->asic_type == CHIP_ALDEBARAN ))
-	    adev->gmc.xgmi.num_physical_nodes > 1)
+		smu_handle_passthrough_sbr(&adev->smu, true);
-		smu_set_light_sbr(&adev->smu, true);
 	if (adev->gmc.xgmi.num_physical_nodes > 1) {
 		mutex_lock(&mgpu_info.mutex);
 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
 {
 	switch (asic_type) {
+#ifdef CONFIG_DRM_AMDGPU_SI
+	case CHIP_HAINAN:
+#endif
+	case CHIP_TOPAZ:
+		/* chips with no display hardware */
+		return false;
 #if defined(CONFIG_DRM_AMD_DC)
 	case CHIP_TAHITI:
 	case CHIP_PITCAIRN:
 	if (r)
 		return r;
+	/* Need to get xgmi info early to decide the reset behavior*/
+	if (adev->gmc.xgmi.supported) {
+		r = adev->gfxhub.funcs->get_xgmi_info(adev);
+		if (r)
+			return r;
+	}
 	/* enable PCIE atomic ops */
 	if (amdgpu_sriov_vf(adev))
 		adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
 	amdgpu_irq_fini_hw(adev);
-	ttm_device_clear_dma_mappings(&adev->mman.bdev);
+	if (adev->mman.initialized)
+		ttm_device_clear_dma_mappings(&adev->mman.bdev);
 	amdgpu_gart_dummy_page_fini(adev);
-	amdgpu_device_unmap_mmio(adev);
+	if (drm_dev_is_unplugged(adev_to_drm(adev)))
+		amdgpu_device_unmap_mmio(adev);
 }
 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
 				 struct amdgpu_reset_context *reset_context)
 {
-	int i, j, r = 0;
+	int i, r = 0;
 	struct amdgpu_job *job = NULL;
 	bool need_full_reset =
 		test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
 		/*clear job fence from fence drv to avoid force_completion
 		 *leave NULL and vm flush fence in fence drv */
-		for (j = 0; j <= ring->fence_drv.num_fences_mask; j++) {
+		amdgpu_fence_driver_clear_job_fences(ring);
-			struct dma_fence *old, **ptr;
-			ptr = &ring->fence_drv.fences[j];
-			old = rcu_dereference_protected(*ptr, 1);
-			if (old && test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &old->flags)) {
-				RCU_INIT_POINTER(*ptr, NULL);
-			}
-		}
 		/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
 		amdgpu_fence_driver_force_completion(ring);
 	}

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c+55−23

@@ -565,10 +565,15 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) · 564 unmodified lines
565	}	565	}
566	}	566	}
567		567
		568	union gc_info {
		569	struct gc_info_v1_0 v1;
		570	struct gc_info_v2_0 v2;
		571	};
		572
568	int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)	573	int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
569	{	574	{
570	struct binary_header *bhdr;	575	struct binary_header *bhdr;
571	struct gc_info_v1_0 *gc_info;	576	union gc_info *gc_info;
572		577
573	if (!adev->mman.discovery_bin) {	578	if (!adev->mman.discovery_bin) {
574	DRM_ERROR("ip discovery uninitialized\n");	579	DRM_ERROR("ip discovery uninitialized\n");
@@ -576,28 +581,55 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) · 1 unmodified line
576	}	581	}
577		582
578	bhdr = (struct binary_header *)adev->mman.discovery_bin;	583	bhdr = (struct binary_header *)adev->mman.discovery_bin;
579	gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin +	584	gc_info = (union gc_info *)(adev->mman.discovery_bin +
580	le16_to_cpu(bhdr->table_list[GC].offset));	585	le16_to_cpu(bhdr->table_list[GC].offset));
581		586	switch (gc_info->v1.header.version_major) {
582	adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);	587	case 1:
583	adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +	588	adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
584	le32_to_cpu(gc_info->gc_num_wgp1_per_sa));	589	adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
585	adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);	590	le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
586	adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);	591	adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
587	adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);	592	adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
588	adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);	593	adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
589	adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);	594	adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
590	adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);	595	adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
591	adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);	596	adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
592	adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);	597	adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
593	adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);	598	adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
594	adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);	599	adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
595	adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);	600	adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
596	adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);	601	adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
597	adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /	602	adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
598	le32_to_cpu(gc_info->gc_num_sa_per_se);	603	adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
599	adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);	604	le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
600		605	adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
		606	break;
		607	case 2:
		608	adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
		609	adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
		610	adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
		611	adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
		612	adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
		613	adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
		614	adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
		615	adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
		616	adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
		617	adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
		618	adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
		619	adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
		620	adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
		621	adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
		622	adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
		623	le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
		624	adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
		625	break;
		626	default:
		627	dev_err(adev->dev,
		628	"Unhandled GC info table %d.%d\n",
		629	gc_info->v1.header.version_major,
		630	gc_info->v1.header.version_minor);
		631	return -EINVAL;
		632	}
601	return 0;	633	return 0;
602	}	634	}
603		635
@@ -992,7 +1024,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) · 388 unmodified lines
992	amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);	1024	amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
993	break;	1025	break;
994	default:	1026	default:
995	break;;	1027	break;
996	}	1028	}
997	return 0;	1029	return 0;
998	}	1030	}

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+23−4

@@ -330,10 +330,11 @@ module_param_named(aspm, amdgpu_aspm, int, 0444); · 329 unmodified lines
330		330
331	/**	331	/**
332	* DOC: runpm (int)	332	* DOC: runpm (int)
333	* Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down	333	* Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
334	* the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.	334	* the dGPUs when they are idle if supported. The default is -1 (auto enable).
		335	* Setting the value to 0 disables this functionality.
335	*/	336	*/
336	MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)");	337	MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
337	module_param_named(runpm, amdgpu_runtime_pm, int, 0444);	338	module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
338		339
339	/**	340	/**
@@ -2168,7 +2169,10 @@ static int amdgpu_pmops_suspend(struct device *dev) · 1828 unmodified lines
2168	adev->in_s3 = true;	2169	adev->in_s3 = true;
2169	r = amdgpu_device_suspend(drm_dev, true);	2170	r = amdgpu_device_suspend(drm_dev, true);
2170	adev->in_s3 = false;	2171	adev->in_s3 = false;
2171		2172	if (r)
		2173	return r;
		2174	if (!adev->in_s0ix)
		2175	r = amdgpu_asic_reset(adev);
2172	return r;	2176	return r;
2173	}	2177	}
2174		2178
@@ -2249,12 +2253,27 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev) · 74 unmodified lines
2249	if (amdgpu_device_supports_px(drm_dev))	2253	if (amdgpu_device_supports_px(drm_dev))
2250	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;	2254	drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2251		2255
		2256	/*
		2257	* By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
		2258	* proper cleanups and put itself into a state ready for PNP. That
		2259	* can address some random resuming failure observed on BOCO capable
		2260	* platforms.
		2261	* TODO: this may be also needed for PX capable platform.
		2262	*/
		2263	if (amdgpu_device_supports_boco(drm_dev))
		2264	adev->mp1_state = PP_MP1_STATE_UNLOAD;
		2265
2252	ret = amdgpu_device_suspend(drm_dev, false);	2266	ret = amdgpu_device_suspend(drm_dev, false);
2253	if (ret) {	2267	if (ret) {
2254	adev->in_runpm = false;	2268	adev->in_runpm = false;
		2269	if (amdgpu_device_supports_boco(drm_dev))
		2270	adev->mp1_state = PP_MP1_STATE_NONE;
2255	return ret;	2271	return ret;
2256	}	2272	}
2257		2273
		2274	if (amdgpu_device_supports_boco(drm_dev))
		2275	adev->mp1_state = PP_MP1_STATE_NONE;
		2276
2258	if (amdgpu_device_supports_px(drm_dev)) {	2277	if (amdgpu_device_supports_px(drm_dev)) {
2259	/* Only need to handle PCI state in the driver for ATPX	2278	/* Only need to handle PCI state in the driver for ATPX
2260	* PCI core handles it for _PR3.	2279	* PCI core handles it for _PR3.

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c+87−39

@@ -77,11 +77,13 @@ void amdgpu_fence_slab_fini(void) · 76 unmodified lines
77	* Cast helper	77	* Cast helper
78	*/	78	*/
79	static const struct dma_fence_ops amdgpu_fence_ops;	79	static const struct dma_fence_ops amdgpu_fence_ops;
		80	static const struct dma_fence_ops amdgpu_job_fence_ops;
80	static inline struct amdgpu_fence to_amdgpu_fence(struct dma_fence f)	81	static inline struct amdgpu_fence to_amdgpu_fence(struct dma_fence f)
81	{	82	{
82	struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);	83	struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
83		84
84	if (__f->base.ops == &amdgpu_fence_ops)	85	if (__f->base.ops == &amdgpu_fence_ops \|\|
		86	__f->base.ops == &amdgpu_job_fence_ops)
85	return __f;	87	return __f;
86		88
87	return NULL;	89	return NULL;
@@ -158,19 +160,18 @@ int amdgpu_fence_emit(struct amdgpu_ring ring, struct dma_fence *f, struct amd · 70 unmodified lines
158	}	160	}
159		161
160	seq = ++ring->fence_drv.sync_seq;	162	seq = ++ring->fence_drv.sync_seq;
161	if (job != NULL && job->job_run_counter) {	163	if (job && job->job_run_counter) {
162	/* reinit seq for resubmitted jobs */	164	/* reinit seq for resubmitted jobs */
163	fence->seqno = seq;	165	fence->seqno = seq;
164	} else {	166	} else {
165	dma_fence_init(fence, &amdgpu_fence_ops,	167	if (job)
166	&ring->fence_drv.lock,	168	dma_fence_init(fence, &amdgpu_job_fence_ops,
167	adev->fence_context + ring->idx,	169	&ring->fence_drv.lock,
168	seq);	170	adev->fence_context + ring->idx, seq);
169	}	171	else
170		172	dma_fence_init(fence, &amdgpu_fence_ops,
171	if (job != NULL) {	173	&ring->fence_drv.lock,
172	/* mark this fence has a parent job */	174	adev->fence_context + ring->idx, seq);
173	set_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &fence->flags);
174	}	175	}
175		176
176	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,	177	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
@@ -620,6 +621,25 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev) · 443 unmodified lines
620	}	621	}
621	}	622	}
622		623
		624	/**
		625	* amdgpu_fence_driver_clear_job_fences - clear job embedded fences of ring
		626	*
		627	* @ring: fence of the ring to be cleared
		628	*
		629	*/
		630	void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring)
		631	{
		632	int i;
		633	struct dma_fence old, *ptr;
		634
		635	for (i = 0; i <= ring->fence_drv.num_fences_mask; i++) {
		636	ptr = &ring->fence_drv.fences[i];
		637	old = rcu_dereference_protected(*ptr, 1);
		638	if (old && old->ops == &amdgpu_job_fence_ops)
		639	RCU_INIT_POINTER(*ptr, NULL);
		640	}
		641	}
		642
623	/**	643	/**
624	* amdgpu_fence_driver_force_completion - force signal latest fence of ring	644	* amdgpu_fence_driver_force_completion - force signal latest fence of ring
625	*	645	*
@@ -643,16 +663,14 @@ static const char amdgpu_fence_get_driver_name(struct dma_fence fence) · 17 unmodified lines
643		663
644	static const char amdgpu_fence_get_timeline_name(struct dma_fence f)	664	static const char amdgpu_fence_get_timeline_name(struct dma_fence f)
645	{	665	{
646	struct amdgpu_ring *ring;	666	return (const char *)to_amdgpu_fence(f)->ring->name;
		667	}
647		668
648	if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {	669	static const char amdgpu_job_fence_get_timeline_name(struct dma_fence f)
649	struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);	670	{
		671	struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
650		672
651	ring = to_amdgpu_ring(job->base.sched);	673	return (const char *)to_amdgpu_ring(job->base.sched)->name;
652	} else {
653	ring = to_amdgpu_fence(f)->ring;
654	}
655	return (const char *)ring->name;
656	}	674	}
657		675
658	/**	676	/**
@@ -665,18 +683,25 @@ static const char amdgpu_fence_get_timeline_name(struct dma_fence f) · 6 unmodified lines
665	*/	683	*/
666	static bool amdgpu_fence_enable_signaling(struct dma_fence *f)	684	static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
667	{	685	{
668	struct amdgpu_ring *ring;	686	if (!timer_pending(&to_amdgpu_fence(f)->ring->fence_drv.fallback_timer))
		687	amdgpu_fence_schedule_fallback(to_amdgpu_fence(f)->ring);
669		688
670	if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {	689	return true;
671	struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);	690	}
672		691
673	ring = to_amdgpu_ring(job->base.sched);	692	/**
674	} else {	693	* amdgpu_job_fence_enable_signaling - enable signalling on job fence
675	ring = to_amdgpu_fence(f)->ring;	694	* @f: fence
676	}	695	*
		696	* This is the simliar function with amdgpu_fence_enable_signaling above, it
		697	* only handles the job embedded fence.
		698	*/
		699	static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)
		700	{
		701	struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
677		702
678	if (!timer_pending(&ring->fence_drv.fallback_timer))	703	if (!timer_pending(&to_amdgpu_ring(job->base.sched)->fence_drv.fallback_timer))
679	amdgpu_fence_schedule_fallback(ring);	704	amdgpu_fence_schedule_fallback(to_amdgpu_ring(job->base.sched));
680		705
681	return true;	706	return true;
682	}	707	}
@@ -692,19 +717,23 @@ static void amdgpu_fence_free(struct rcu_head *rcu) · 9 unmodified lines
692	{	717	{
693	struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);	718	struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
694		719
695	if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {
696	/* free job if fence has a parent job */
697	struct amdgpu_job *job;
698
699	job = container_of(f, struct amdgpu_job, hw_fence);
700	kfree(job);
701	} else {
702	/* free fence_slab if it's separated fence*/	720	/* free fence_slab if it's separated fence*/
703	struct amdgpu_fence *fence;	721	kmem_cache_free(amdgpu_fence_slab, to_amdgpu_fence(f));
		722	}
704		723
705	fence = to_amdgpu_fence(f);	724	/**
706	kmem_cache_free(amdgpu_fence_slab, fence);	725	* amdgpu_job_fence_free - free up the job with embedded fence
707	}	726	*
		727	* @rcu: RCU callback head
		728	*
		729	* Free up the job with embedded fence after the RCU grace period.
		730	*/
		731	static void amdgpu_job_fence_free(struct rcu_head *rcu)
		732	{
		733	struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
		734
		735	/* free job if fence has a parent job */
		736	kfree(container_of(f, struct amdgpu_job, hw_fence));
708	}	737	}
709		738
710	/**	739	/**
@@ -720,6 +749,19 @@ static void amdgpu_fence_release(struct dma_fence *f) · 9 unmodified lines
720	call_rcu(&f->rcu, amdgpu_fence_free);	749	call_rcu(&f->rcu, amdgpu_fence_free);
721	}	750	}
722		751
		752	/**
		753	* amdgpu_job_fence_release - callback that job embedded fence can be freed
		754	*
		755	* @f: fence
		756	*
		757	* This is the simliar function with amdgpu_fence_release above, it
		758	* only handles the job embedded fence.
		759	*/
		760	static void amdgpu_job_fence_release(struct dma_fence *f)
		761	{
		762	call_rcu(&f->rcu, amdgpu_job_fence_free);
		763	}
		764
723	static const struct dma_fence_ops amdgpu_fence_ops = {	765	static const struct dma_fence_ops amdgpu_fence_ops = {
724	.get_driver_name = amdgpu_fence_get_driver_name,	766	.get_driver_name = amdgpu_fence_get_driver_name,
725	.get_timeline_name = amdgpu_fence_get_timeline_name,	767	.get_timeline_name = amdgpu_fence_get_timeline_name,
@@ -727,6 +769,12 @@ static const struct dma_fence_ops amdgpu_fence_ops = { · 1 unmodified line
727	.release = amdgpu_fence_release,	769	.release = amdgpu_fence_release,
728	};	770	};
729		771
		772	static const struct dma_fence_ops amdgpu_job_fence_ops = {
		773	.get_driver_name = amdgpu_fence_get_driver_name,
		774	.get_timeline_name = amdgpu_job_fence_get_timeline_name,
		775	.enable_signaling = amdgpu_job_fence_enable_signaling,
		776	.release = amdgpu_job_fence_release,
		777	};
730		778
731	/*	779	/*
732	* Fence debugfs	780	* Fence debugfs

drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c+15−10

 			return true;
 		else
 			return false;
+	case CHIP_ALDEBARAN:
+		/* All Aldebaran SKUs have the FRU */
+		return true;
 	default:
 		return false;
 	}
 int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
 {
-	unsigned char buff[34];
+	unsigned char buff[AMDGPU_PRODUCT_NAME_LEN+2];
 	u32 addrptr;
 	int size, len;
+	int offset = 2;
 	if (!is_fru_eeprom_supported(adev))
 		return 0;
+	if (adev->asic_type == CHIP_ALDEBARAN)
+		offset = 0;
 	/* If algo exists, it means that the i2c_adapter's initialized */
 	if (!adev->pm.smu_i2c.algo) {
 		DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");
 	}
 	len = size;
-	/* Product name should only be 32 characters. Any more,
+	if (len >= AMDGPU_PRODUCT_NAME_LEN) {
-	 * and something could be wrong. Cap it at 32 to be safe
+		DRM_WARN("FRU Product Name is larger than %d characters. This is likely a mistake",
-	 */
+				AMDGPU_PRODUCT_NAME_LEN);
-	if (len >= sizeof(adev->product_name)) {
+		len = AMDGPU_PRODUCT_NAME_LEN - 1;
-		DRM_WARN("FRU Product Number is larger than 32 characters. This is likely a mistake");
-		len = sizeof(adev->product_name) - 1;
 	}
 	/* Start at 2 due to buff using fields 0 and 1 for the address */
-	memcpy(adev->product_name, &buff[2], len);
+	memcpy(adev->product_name, &buff[offset], len);
 	adev->product_name[len] = '\0';
 	addrptr += size + 1;
 		DRM_WARN("FRU Product Number is larger than 16 characters. This is likely a mistake");
 		len = sizeof(adev->product_number) - 1;
 	}
-	memcpy(adev->product_number, &buff[2], len);
+	memcpy(adev->product_number, &buff[offset], len);
 	adev->product_number[len] = '\0';
 	addrptr += size + 1;
 		DRM_WARN("FRU Serial Number is larger than 16 characters. This is likely a mistake");
 		len = sizeof(adev->serial) - 1;
 	}
-	memcpy(adev->serial, &buff[2], len);
+	memcpy(adev->serial, &buff[offset], len);
 	adev->serial[len] = '\0';
 	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+3−0

@@ -264,6 +264,9 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str · 263 unmodified lines
264	!(vma->vm_flags & (VM_READ \| VM_WRITE \| VM_EXEC)))	264	!(vma->vm_flags & (VM_READ \| VM_WRITE \| VM_EXEC)))
265	vma->vm_flags &= ~VM_MAYWRITE;	265	vma->vm_flags &= ~VM_MAYWRITE;
266		266
		267	if (bo->kfd_bo)
		268	vma->vm_flags \|= VM_DONTCOPY;
		269
267	return drm_gem_ttm_mmap(obj, vma);	270	return drm_gem_ttm_mmap(obj, vma);
268	}	271	}
269		272

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h+1−3

 #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)
-/* fence flag bit to indicate the face is embedded in job*/
-#define AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT		(DMA_FENCE_FLAG_USER_BITS + 1)
 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
 #define AMDGPU_IB_POOL_SIZE	(1024 * 1024)
 	struct dma_fence		**fences;
 };
+void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c+99−68

@@ -23,74 +23,10 @@ · 22 unmodified lines
23		23
24	#include "amdgpu_ras.h"	24	#include "amdgpu_ras.h"
25		25
26	int amdgpu_umc_ras_late_init(struct amdgpu_device *adev)	26	static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,
27	{
28	int r;
29	struct ras_fs_if fs_info = {
30	.sysfs_name = "umc_err_count",
31	};
32	struct ras_ih_if ih_info = {
33	.cb = amdgpu_umc_process_ras_data_cb,
34	};
35
36	if (!adev->umc.ras_if) {
37	adev->umc.ras_if =
38	kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
39	if (!adev->umc.ras_if)
40	return -ENOMEM;
41	adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC;
42	adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
43	adev->umc.ras_if->sub_block_index = 0;
44	}
45	ih_info.head = fs_info.head = *adev->umc.ras_if;
46
47	r = amdgpu_ras_late_init(adev, adev->umc.ras_if,
48	&fs_info, &ih_info);
49	if (r)
50	goto free;
51
52	if (amdgpu_ras_is_supported(adev, adev->umc.ras_if->block)) {
53	r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
54	if (r)
55	goto late_fini;
56	} else {
57	r = 0;
58	goto free;
59	}
60
61	/* ras init of specific umc version */
62	if (adev->umc.ras_funcs &&
63	adev->umc.ras_funcs->err_cnt_init)
64	adev->umc.ras_funcs->err_cnt_init(adev);
65
66	return 0;
67
68	late_fini:
69	amdgpu_ras_late_fini(adev, adev->umc.ras_if, &ih_info);
70	free:
71	kfree(adev->umc.ras_if);
72	adev->umc.ras_if = NULL;
73	return r;
74	}
75
76	void amdgpu_umc_ras_fini(struct amdgpu_device *adev)
77	{
78	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
79	adev->umc.ras_if) {
80	struct ras_common_if *ras_if = adev->umc.ras_if;
81	struct ras_ih_if ih_info = {
82	.head = *ras_if,
83	.cb = amdgpu_umc_process_ras_data_cb,
84	};
85
86	amdgpu_ras_late_fini(adev, ras_if, &ih_info);
87	kfree(ras_if);
88	}
89	}
90
91	int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
92	void *ras_error_status,	27	void *ras_error_status,
93	struct amdgpu_iv_entry *entry)	28	struct amdgpu_iv_entry *entry,
		29	bool reset)
94	{	30	{
95	struct ras_err_data err_data = (struct ras_err_data )ras_error_status;	31	struct ras_err_data err_data = (struct ras_err_data )ras_error_status;
96	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);	32	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
@@ -164,13 +100,108 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, · 67 unmodified lines
164	adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);	100	adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
165	}	101	}
166		102
167	amdgpu_ras_reset_gpu(adev);	103	if (reset)
		104	amdgpu_ras_reset_gpu(adev);
168	}	105	}
169		106
170	kfree(err_data->err_addr);	107	kfree(err_data->err_addr);
171	return AMDGPU_RAS_SUCCESS;	108	return AMDGPU_RAS_SUCCESS;
172	}	109	}
173		110
		111	int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
		112	void *ras_error_status,
		113	bool reset)
		114	{
		115	int ret;
		116	struct ras_err_data err_data = (struct ras_err_data )ras_error_status;
		117	struct ras_common_if head = {
		118	.block = AMDGPU_RAS_BLOCK__UMC,
		119	};
		120	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);
		121
		122	ret =
		123	amdgpu_umc_do_page_retirement(adev, ras_error_status, NULL, reset);
		124
		125	if (ret == AMDGPU_RAS_SUCCESS && obj) {
		126	obj->err_data.ue_count += err_data->ue_count;
		127	obj->err_data.ce_count += err_data->ce_count;
		128	}
		129
		130	return ret;
		131	}
		132
		133	static int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
		134	void *ras_error_status,
		135	struct amdgpu_iv_entry *entry)
		136	{
		137	return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry, true);
		138	}
		139
		140	int amdgpu_umc_ras_late_init(struct amdgpu_device *adev)
		141	{
		142	int r;
		143	struct ras_fs_if fs_info = {
		144	.sysfs_name = "umc_err_count",
		145	};
		146	struct ras_ih_if ih_info = {
		147	.cb = amdgpu_umc_process_ras_data_cb,
		148	};
		149
		150	if (!adev->umc.ras_if) {
		151	adev->umc.ras_if =
		152	kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
		153	if (!adev->umc.ras_if)
		154	return -ENOMEM;
		155	adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC;
		156	adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
		157	adev->umc.ras_if->sub_block_index = 0;
		158	}
		159	ih_info.head = fs_info.head = *adev->umc.ras_if;
		160
		161	r = amdgpu_ras_late_init(adev, adev->umc.ras_if,
		162	&fs_info, &ih_info);
		163	if (r)
		164	goto free;
		165
		166	if (amdgpu_ras_is_supported(adev, adev->umc.ras_if->block)) {
		167	r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
		168	if (r)
		169	goto late_fini;
		170	} else {
		171	r = 0;
		172	goto free;
		173	}
		174
		175	/* ras init of specific umc version */
		176	if (adev->umc.ras_funcs &&
		177	adev->umc.ras_funcs->err_cnt_init)
		178	adev->umc.ras_funcs->err_cnt_init(adev);
		179
		180	return 0;
		181
		182	late_fini:
		183	amdgpu_ras_late_fini(adev, adev->umc.ras_if, &ih_info);
		184	free:
		185	kfree(adev->umc.ras_if);
		186	adev->umc.ras_if = NULL;
		187	return r;
		188	}
		189
		190	void amdgpu_umc_ras_fini(struct amdgpu_device *adev)
		191	{
		192	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
		193	adev->umc.ras_if) {
		194	struct ras_common_if *ras_if = adev->umc.ras_if;
		195	struct ras_ih_if ih_info = {
		196	.head = *ras_if,
		197	.cb = amdgpu_umc_process_ras_data_cb,
		198	};
		199
		200	amdgpu_ras_late_fini(adev, ras_if, &ih_info);
		201	kfree(ras_if);
		202	}
		203	}
		204
174	int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,	205	int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
175	struct amdgpu_irq_src *source,	206	struct amdgpu_irq_src *source,
176	struct amdgpu_iv_entry *entry)	207	struct amdgpu_iv_entry *entry)

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h+2−2

@@ -78,9 +78,9 @@ struct amdgpu_umc { · 77 unmodified lines
78		78
79	int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);	79	int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
80	void amdgpu_umc_ras_fini(struct amdgpu_device *adev);	80	void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
81	int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,	81	int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
82	void *ras_error_status,	82	void *ras_error_status,
83	struct amdgpu_iv_entry *entry);	83	bool reset);
84	int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,	84	int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
85	struct amdgpu_irq_src *source,	85	struct amdgpu_irq_src *source,
86	struct amdgpu_iv_entry *entry);	86	struct amdgpu_iv_entry *entry);

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c+24−12

 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
 {
-	uint64_t bp_block_offset = 0;
-	uint32_t bp_block_size = 0;
-	struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
 	adev->virt.fw_reserve.p_pf2vf = NULL;
 	adev->virt.fw_reserve.p_vf2pf = NULL;
 	adev->virt.vf2pf_update_interval_ms = 0;
-	if (adev->mman.fw_vram_usage_va != NULL) {
+	if (adev->bios != NULL) {
 		adev->virt.vf2pf_update_interval_ms = 2000;
+		adev->virt.fw_reserve.p_pf2vf =
+			(struct amd_sriov_msg_pf2vf_info_header *)
+			(adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
+		amdgpu_virt_read_pf2vf_data(adev);
+	}
+	if (adev->virt.vf2pf_update_interval_ms != 0) {
+		INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
+		schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms));
+	}
+}
+void amdgpu_virt_exchange_data(struct amdgpu_device *adev)
+{
+	uint64_t bp_block_offset = 0;
+	uint32_t bp_block_size = 0;
+	struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
+	if (adev->mman.fw_vram_usage_va != NULL) {
 		adev->virt.fw_reserve.p_pf2vf =
 			(struct amd_sriov_msg_pf2vf_info_header *)
 			(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
 			(adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
 		amdgpu_virt_read_pf2vf_data(adev);
-		return;
-	}
-	if (adev->virt.vf2pf_update_interval_ms != 0) {
-		INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
-		schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);
 	}
 }
 void amdgpu_detect_virtualization(struct amdgpu_device *adev)
 {
 	uint32_t reg;

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h+1−0

@@ -308,6 +308,7 @@ int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); · 307 unmodified lines
308	void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);	308	void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
309	void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);	309	void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
310	void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);	310	void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
		311	void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
311	void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);	312	void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
312	void amdgpu_detect_virtualization(struct amdgpu_device *adev);	313	void amdgpu_detect_virtualization(struct amdgpu_device *adev);
313		314

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+89−28

@@ -63,6 +63,13 @@ · 62 unmodified lines
63	#define mmGCEA_PROBE_MAP 0x070c	63	#define mmGCEA_PROBE_MAP 0x070c
64	#define mmGCEA_PROBE_MAP_BASE_IDX 0	64	#define mmGCEA_PROBE_MAP_BASE_IDX 0
65		65
		66	#define GFX9_RLCG_GC_WRITE_OLD (0x8 << 28)
		67	#define GFX9_RLCG_GC_WRITE (0x0 << 28)
		68	#define GFX9_RLCG_GC_READ (0x1 << 28)
		69	#define GFX9_RLCG_VFGATE_DISABLED 0x4000000
		70	#define GFX9_RLCG_WRONG_OPERATION_TYPE 0x2000000
		71	#define GFX9_RLCG_NOT_IN_RANGE 0x1000000
		72
66	MODULE_FIRMWARE("amdgpu/vega10_ce.bin");	73	MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
67	MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");	74	MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
68	MODULE_FIRMWARE("amdgpu/vega10_me.bin");	75	MODULE_FIRMWARE("amdgpu/vega10_me.bin");
@@ -739,7 +746,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = · 670 unmodified lines
739	mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,	746	mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
740	};	747	};
741		748
742	static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)	749	static u32 gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
743	{	750	{
744	static void *scratch_reg0;	751	static void *scratch_reg0;
745	static void *scratch_reg1;	752	static void *scratch_reg1;
@@ -748,21 +755,20 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 f · 2 unmodified lines
748	static void *spare_int;	755	static void *spare_int;
749	static uint32_t grbm_cntl;	756	static uint32_t grbm_cntl;
750	static uint32_t grbm_idx;	757	static uint32_t grbm_idx;
		758	uint32_t i = 0;
		759	uint32_t retries = 50000;
		760	u32 ret = 0;
		761	u32 tmp;
751		762
752	scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;	763	scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
753	scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;	764	scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
754	scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;	765	scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG2_BASE_IDX] + mmSCRATCH_REG2)*4;
755	scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;	766	scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG3_BASE_IDX] + mmSCRATCH_REG3)*4;
756	spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;	767	spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
757		768
758	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;	769	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
759	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;	770	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
760		771
761	if (amdgpu_sriov_runtime(adev)) {
762	pr_err("shouldn't call rlcg write register during runtime\n");
763	return;
764	}
765
766	if (offset == grbm_cntl \|\| offset == grbm_idx) {	772	if (offset == grbm_cntl \|\| offset == grbm_idx) {
767	if (offset == grbm_cntl)	773	if (offset == grbm_cntl)
768	writel(v, scratch_reg2);	774	writel(v, scratch_reg2);
@@ -771,41 +777,95 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 f · 2 unmodified lines
771		777
772	writel(v, ((void __iomem )adev->rmmio) + (offset 4));	778	writel(v, ((void __iomem )adev->rmmio) + (offset 4));
773	} else {	779	} else {
774	uint32_t i = 0;	780	/*
775	uint32_t retries = 50000;	781	* SCRATCH_REG0 = read/write value
776		782	* SCRATCH_REG1[30:28] = command
		783	* SCRATCH_REG1[19:0] = address in dword
		784	* SCRATCH_REG1[26:24] = Error reporting
		785	*/
777	writel(v, scratch_reg0);	786	writel(v, scratch_reg0);
778	writel(offset \| 0x80000000, scratch_reg1);	787	writel(offset \| flag, scratch_reg1);
779	writel(1, spare_int);	788	writel(1, spare_int);
780	for (i = 0; i < retries; i++) {
781	u32 tmp;
782		789
		790	for (i = 0; i < retries; i++) {
783	tmp = readl(scratch_reg1);	791	tmp = readl(scratch_reg1);
784	if (!(tmp & 0x80000000))	792	if (!(tmp & flag))
785	break;	793	break;
786		794
787	udelay(10);	795	udelay(10);
788	}	796	}
789	if (i >= retries)	797
790	pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);	798	if (i >= retries) {
		799	if (amdgpu_sriov_reg_indirect_gc(adev)) {
		800	if (tmp & GFX9_RLCG_VFGATE_DISABLED)
		801	pr_err("The vfgate is disabled, program reg:0x%05x failed!\n", offset);
		802	else if (tmp & GFX9_RLCG_WRONG_OPERATION_TYPE)
		803	pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset);
		804	else if (tmp & GFX9_RLCG_NOT_IN_RANGE)
		805	pr_err("The register is not in range, program reg:0x%05x failed!\n", offset);
		806	else
		807	pr_err("Unknown error type, program reg:0x%05x failed!\n", offset);
		808	} else
		809	pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
		810	}
791	}	811	}
792		812
		813	ret = readl(scratch_reg0);
		814
		815	return ret;
		816	}
		817
		818	static bool gfx_v9_0_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip,
		819	int write, u32 *rlcg_flag)
		820	{
		821
		822	switch (hwip) {
		823	case GC_HWIP:
		824	if (amdgpu_sriov_reg_indirect_gc(adev)) {
		825	*rlcg_flag = write ? GFX9_RLCG_GC_WRITE : GFX9_RLCG_GC_READ;
		826
		827	return true;
		828	/* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */
		829	} else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) {
		830	*rlcg_flag = GFX9_RLCG_GC_WRITE_OLD;
		831	return true;
		832	}
		833
		834	break;
		835	default:
		836	return false;
		837	}
		838
		839	return false;
		840	}
		841
		842	static u32 gfx_v9_0_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
		843	{
		844	u32 rlcg_flag;
		845
		846	if (!amdgpu_sriov_runtime(adev) && gfx_v9_0_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
		847	return gfx_v9_0_rlcg_rw(adev, offset, 0, rlcg_flag);
		848
		849	if (acc_flags & AMDGPU_REGS_NO_KIQ)
		850	return RREG32_NO_KIQ(offset);
		851	else
		852	return RREG32(offset);
793	}	853	}
794		854
795	static void gfx_v9_0_sriov_wreg(struct amdgpu_device *adev, u32 offset,	855	static void gfx_v9_0_sriov_wreg(struct amdgpu_device *adev, u32 offset,
796	u32 v, u32 acc_flags, u32 hwip)	856	u32 value, u32 acc_flags, u32 hwip)
797	{	857	{
798	if ((acc_flags & AMDGPU_REGS_RLC) &&	858	u32 rlcg_flag;
799	amdgpu_sriov_fullaccess(adev)) {
800	gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
801		859
		860	if (!amdgpu_sriov_runtime(adev) && gfx_v9_0_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
		861	gfx_v9_0_rlcg_rw(adev, offset, value, rlcg_flag);
802	return;	862	return;
803	}	863	}
804		864
805	if (acc_flags & AMDGPU_REGS_NO_KIQ)	865	if (acc_flags & AMDGPU_REGS_NO_KIQ)
806	WREG32_NO_KIQ(offset, v);	866	WREG32_NO_KIQ(offset, value);
807	else	867	else
808	WREG32(offset, v);	868	WREG32(offset, value);
809	}	869	}
810		870
811	#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042	871	#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
@@ -5135,7 +5195,7 @@ static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) · 4323 unmodified lines
5135	if (amdgpu_sriov_is_pp_one_vf(adev))	5195	if (amdgpu_sriov_is_pp_one_vf(adev))
5136	data = RREG32_NO_KIQ(reg);	5196	data = RREG32_NO_KIQ(reg);
5137	else	5197	else
5138	data = RREG32(reg);	5198	data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
5139		5199
5140	data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;	5200	data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
5141	data \|= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;	5201	data \|= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
@@ -5191,6 +5251,7 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { · 49 unmodified lines
5191	.start = gfx_v9_0_rlc_start,	5251	.start = gfx_v9_0_rlc_start,
5192	.update_spm_vmid = gfx_v9_0_update_spm_vmid,	5252	.update_spm_vmid = gfx_v9_0_update_spm_vmid,
5193	.sriov_wreg = gfx_v9_0_sriov_wreg,	5253	.sriov_wreg = gfx_v9_0_sriov_wreg,
		5254	.sriov_rreg = gfx_v9_0_sriov_rreg,
5194	.is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,	5255	.is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
5195	};	5256	};
5196		5257
@@ -5796,16 +5857,16 @@ static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, · 599 unmodified lines
5796		5857
5797	switch (state) {	5858	switch (state) {
5798	case AMDGPU_IRQ_STATE_DISABLE:	5859	case AMDGPU_IRQ_STATE_DISABLE:
5799	mec_int_cntl = RREG32(mec_int_cntl_reg);	5860	mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg);
5800	mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,	5861	mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5801	TIME_STAMP_INT_ENABLE, 0);	5862	TIME_STAMP_INT_ENABLE, 0);
5802	WREG32(mec_int_cntl_reg, mec_int_cntl);	5863	WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5803	break;	5864	break;
5804	case AMDGPU_IRQ_STATE_ENABLE:	5865	case AMDGPU_IRQ_STATE_ENABLE:
5805	mec_int_cntl = RREG32(mec_int_cntl_reg);	5866	mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5806	mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,	5867	mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5807	TIME_STAMP_INT_ENABLE, 1);	5868	TIME_STAMP_INT_ENABLE, 1);
5808	WREG32(mec_int_cntl_reg, mec_int_cntl);	5869	WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5809	break;	5870	break;
5810	default:	5871	default:
5811	break;	5872	break;

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c+0−6

 		return r;
 	}
-	if (adev->gmc.xgmi.supported) {
-		r = adev->gfxhub.funcs->get_xgmi_info(adev);
-		if (r)
-			return r;
-	}
 	r = gmc_v10_0_mc_init(adev);
 	if (r)
 		return r;

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c+10−3

 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 {
 	int r;
+	u32 tmp;
 	adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
 	if (!adev->gmc.vram_width) {
-		u32 tmp;
 		int chansize, numchan;
 		/* Get VRAM informations */
 		adev->gmc.vram_width = numchan * chansize;
 	}
 	/* size in MB on si */
-	adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
+	tmp = RREG32(mmCONFIG_MEMSIZE);
-	adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
+	/* some boards may have garbage in the upper 16 bits */
+	if (tmp & 0xffff0000) {
+		DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
+		if (tmp & 0xffff)
+			tmp &= 0xffff;
+	}
+	adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;
+	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 	if (!(adev->flags & AMD_IS_APU)) {
 		r = amdgpu_device_resize_fb_bar(adev);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+43−20

@@ -478,9 +478,18 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, · 477 unmodified lines
478	hub = &adev->vmhub[j];	478	hub = &adev->vmhub[j];
479	for (i = 0; i < 16; i++) {	479	for (i = 0; i < 16; i++) {
480	reg = hub->vm_context0_cntl + i;	480	reg = hub->vm_context0_cntl + i;
481	tmp = RREG32(reg);	481
		482	if (j == AMDGPU_GFXHUB_0)
		483	tmp = RREG32_SOC15_IP(GC, reg);
		484	else
		485	tmp = RREG32_SOC15_IP(MMHUB, reg);
		486
482	tmp &= ~bits;	487	tmp &= ~bits;
483	WREG32(reg, tmp);	488
		489	if (j == AMDGPU_GFXHUB_0)
		490	WREG32_SOC15_IP(GC, reg, tmp);
		491	else
		492	WREG32_SOC15_IP(MMHUB, reg, tmp);
484	}	493	}
485	}	494	}
486	break;	495	break;
@@ -489,9 +498,18 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, · 2 unmodified lines
489	hub = &adev->vmhub[j];	498	hub = &adev->vmhub[j];
490	for (i = 0; i < 16; i++) {	499	for (i = 0; i < 16; i++) {
491	reg = hub->vm_context0_cntl + i;	500	reg = hub->vm_context0_cntl + i;
492	tmp = RREG32(reg);	501
		502	if (j == AMDGPU_GFXHUB_0)
		503	tmp = RREG32_SOC15_IP(GC, reg);
		504	else
		505	tmp = RREG32_SOC15_IP(MMHUB, reg);
		506
493	tmp \|= bits;	507	tmp \|= bits;
494	WREG32(reg, tmp);	508
		509	if (j == AMDGPU_GFXHUB_0)
		510	WREG32_SOC15_IP(GC, reg, tmp);
		511	else
		512	WREG32_SOC15_IP(MMHUB, reg, tmp);
495	}	513	}
496	}	514	}
497	break;	515	break;
@@ -788,9 +806,12 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 290 unmodified lines
788	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */	806	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
789	if (use_semaphore) {	807	if (use_semaphore) {
790	for (j = 0; j < adev->usec_timeout; j++) {	808	for (j = 0; j < adev->usec_timeout; j++) {
791	/* a read return value of 1 means semaphore acuqire */	809	/* a read return value of 1 means semaphore acquire */
792	tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +	810	if (vmhub == AMDGPU_GFXHUB_0)
793	hub->eng_distance * eng);	811	tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
		812	else
		813	tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng);
		814
794	if (tmp & 0x1)	815	if (tmp & 0x1)
795	break;	816	break;
796	udelay(1);	817	udelay(1);
@@ -801,8 +822,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 4 unmodified lines
801	}	822	}
802		823
803	do {	824	do {
804	WREG32_NO_KIQ(hub->vm_inv_eng0_req +	825	if (vmhub == AMDGPU_GFXHUB_0)
805	hub->eng_distance * eng, inv_req);	826	WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
		827	else
		828	WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
806		829
807	/*	830	/*
808	* Issue a dummy read to wait for the ACK register to	831	* Issue a dummy read to wait for the ACK register to
@@ -815,8 +838,11 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 6 unmodified lines
815	hub->eng_distance * eng);	838	hub->eng_distance * eng);
816		839
817	for (j = 0; j < adev->usec_timeout; j++) {	840	for (j = 0; j < adev->usec_timeout; j++) {
818	tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +	841	if (vmhub == AMDGPU_GFXHUB_0)
819	hub->eng_distance * eng);	842	tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
		843	else
		844	tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng);
		845
820	if (tmp & (1 << vmid))	846	if (tmp & (1 << vmid))
821	break;	847	break;
822	udelay(1);	848	udelay(1);
@@ -827,13 +853,16 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 4 unmodified lines
827	} while (inv_req);	853	} while (inv_req);
828		854
829	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */	855	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
830	if (use_semaphore)	856	if (use_semaphore) {
831	/*	857	/*
832	* add semaphore release after invalidation,	858	* add semaphore release after invalidation,
833	* write with 0 means semaphore release	859	* write with 0 means semaphore release
834	*/	860	*/
835	WREG32_NO_KIQ(hub->vm_inv_eng0_sem +	861	if (vmhub == AMDGPU_GFXHUB_0)
836	hub->eng_distance * eng, 0);	862	WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0);
		863	else
		864	WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0);
		865	}
837		866
838	spin_unlock(&adev->gmc.invalidate_lock);	867	spin_unlock(&adev->gmc.invalidate_lock);
839		868
@@ -1599,12 +1628,6 @@ static int gmc_v9_0_sw_init(void *handle) · 759 unmodified lines
1599	}	1628	}
1600	adev->need_swiotlb = drm_need_swiotlb(44);	1629	adev->need_swiotlb = drm_need_swiotlb(44);
1601		1630
1602	if (adev->gmc.xgmi.supported) {
1603	r = adev->gfxhub.funcs->get_xgmi_info(adev);
1604	if (r)
1605	return r;
1606	}
1607
1608	r = gmc_v9_0_mc_init(adev);	1631	r = gmc_v9_0_mc_init(adev);
1609	if (r)	1632	if (r)
1610	return r;	1633	return r;

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c+15−63

@@ -277,13 +277,15 @@ static bool psp_v11_0_is_sos_alive(struct psp_context *psp) · 276 unmodified lines
277	return sol_reg != 0x0;	277	return sol_reg != 0x0;
278	}	278	}
279		279
280	static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)	280	static int psp_v11_0_bootloader_load_component(struct psp_context *psp,
		281	struct psp_bin_desc *bin_desc,
		282	enum psp_bootloader_cmd bl_cmd)
281	{	283	{
282	int ret;	284	int ret;
283	uint32_t psp_gfxdrv_command_reg = 0;	285	uint32_t psp_gfxdrv_command_reg = 0;
284	struct amdgpu_device *adev = psp->adev;	286	struct amdgpu_device *adev = psp->adev;
285		287
286	/* Check tOS sign of life register to confirm sys driver and sOS	288	/* Check sOS sign of life register to confirm sys driver and sOS
287	* are already been loaded.	289	* are already been loaded.
288	*/	290	*/
289	if (psp_v11_0_is_sos_alive(psp))	291	if (psp_v11_0_is_sos_alive(psp))
@@ -293,13 +295,13 @@ static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) · 3 unmodified lines
293	if (ret)	295	if (ret)
294	return ret;	296	return ret;
295		297
296	/* Copy PSP KDB binary to memory */	298	/* Copy PSP System Driver binary to memory */
297	psp_copy_fw(psp, psp->kdb.start_addr, psp->kdb.size_bytes);	299	psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes);
298		300
299	/* Provide the PSP KDB to bootloader */	301	/* Provide the sys driver to bootloader */
300	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,	302	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
301	(uint32_t)(psp->fw_pri_mc_addr >> 20));	303	(uint32_t)(psp->fw_pri_mc_addr >> 20));
302	psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;	304	psp_gfxdrv_command_reg = bl_cmd;
303	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,	305	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
304	psp_gfxdrv_command_reg);	306	psp_gfxdrv_command_reg);
305		307
@@ -308,69 +310,19 @@ static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) · 2 unmodified lines
308	return ret;	310	return ret;
309	}	311	}
310		312
311	static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)	313	static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
312	{	314	{
313	int ret;	315	return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
314	uint32_t psp_gfxdrv_command_reg = 0;	316	}
315	struct amdgpu_device *adev = psp->adev;
316
317	/* Check tOS sign of life register to confirm sys driver and sOS
318	* are already been loaded.
319	*/
320	if (psp_v11_0_is_sos_alive(psp))
321	return 0;
322
323	ret = psp_v11_0_wait_for_bootloader(psp);
324	if (ret)
325	return ret;
326
327	/* Copy PSP SPL binary to memory */
328	psp_copy_fw(psp, psp->spl.start_addr, psp->spl.size_bytes);
329
330	/* Provide the PSP SPL to bootloader */
331	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
332	(uint32_t)(psp->fw_pri_mc_addr >> 20));
333	psp_gfxdrv_command_reg = PSP_BL__LOAD_TOS_SPL_TABLE;
334	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
335	psp_gfxdrv_command_reg);
336
337	ret = psp_v11_0_wait_for_bootloader(psp);
338		317
339	return ret;	318	static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
		319	{
		320	return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE);
340	}	321	}
341		322
342	static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)	323	static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
343	{	324	{
344	int ret;	325	return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
345	uint32_t psp_gfxdrv_command_reg = 0;
346	struct amdgpu_device *adev = psp->adev;
347
348	/* Check sOS sign of life register to confirm sys driver and sOS
349	* are already been loaded.
350	*/
351	if (psp_v11_0_is_sos_alive(psp))
352	return 0;
353
354	ret = psp_v11_0_wait_for_bootloader(psp);
355	if (ret)
356	return ret;
357
358	/* Copy PSP System Driver binary to memory */
359	psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
360
361	/* Provide the sys driver to bootloader */
362	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
363	(uint32_t)(psp->fw_pri_mc_addr >> 20));
364	psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
365	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
366	psp_gfxdrv_command_reg);
367
368	/* there might be handshake issue with hardware which needs delay */
369	mdelay(20);
370
371	ret = psp_v11_0_wait_for_bootloader(psp);
372
373	return ret;
374	}	326	}
375		327
376	static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)	328	static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c+46−37

@@ -542,9 +542,6 @@ static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) · 541 unmodified lines
542	}	542	}
543		543
544	for (i = 0; i < adev->sdma.num_instances; i++) {	544	for (i = 0; i < adev->sdma.num_instances; i++) {
545	f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
546	f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
547	AUTO_CTXSW_ENABLE, enable ? 1 : 0);
548	if (enable && amdgpu_sdma_phase_quantum) {	545	if (enable && amdgpu_sdma_phase_quantum) {
549	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),	546	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
550	phase_quantum);	547	phase_quantum);
@@ -553,7 +550,13 @@ static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) · 2 unmodified lines
553	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),	550	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
554	phase_quantum);	551	phase_quantum);
555	}	552	}
556	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);	553
		554	if (!amdgpu_sriov_vf(adev)) {
		555	f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
		556	f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
		557	AUTO_CTXSW_ENABLE, enable ? 1 : 0);
		558	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
		559	}
557	}	560	}
558		561
559	}	562	}
@@ -576,10 +579,12 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) · 16 unmodified lines
576	sdma_v5_2_rlc_stop(adev);	579	sdma_v5_2_rlc_stop(adev);
577	}	580	}
578		581
579	for (i = 0; i < adev->sdma.num_instances; i++) {	582	if (!amdgpu_sriov_vf(adev)) {
580	f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));	583	for (i = 0; i < adev->sdma.num_instances; i++) {
581	f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);	584	f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
582	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);	585	f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
		586	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
		587	}
583	}	588	}
584	}	589	}
585		590
@@ -608,7 +613,8 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) · 22 unmodified lines
608	ring = &adev->sdma.instance[i].ring;	613	ring = &adev->sdma.instance[i].ring;
609	wb_offset = (ring->rptr_offs * 4);	614	wb_offset = (ring->rptr_offs * 4);
610		615
611	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);	616	if (!amdgpu_sriov_vf(adev))
		617	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
612		618
613	/* Set ring buffer size in dwords */	619	/* Set ring buffer size in dwords */
614	rb_bufsz = order_base_2(ring->ring_size / 4);	620	rb_bufsz = order_base_2(ring->ring_size / 4);
@@ -683,32 +689,34 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) · 68 unmodified lines
683	sdma_v5_2_ring_set_wptr(ring);	689	sdma_v5_2_ring_set_wptr(ring);
684		690
685	/* set minor_ptr_update to 0 after wptr programed */	691	/* set minor_ptr_update to 0 after wptr programed */
686	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
687		692
688	/* set utc l1 enable flag always to 1 */	693	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
689	temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
690	temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
691
692	/* enable MCBP */
693	temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
694	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
695
696	/* Set up RESP_MODE to non-copy addresses */
697	temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
698	temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
699	temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
700	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
701
702	/* program default cache read and write policy */
703	temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
704	/* clean read policy and write policy bits */
705	temp &= 0xFF0FFF;
706	temp \|= ((CACHE_READ_POLICY_L2__DEFAULT << 12) \|
707	(CACHE_WRITE_POLICY_L2__DEFAULT << 14) \|
708	SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
709	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
710		694
		695	/* SRIOV VF has no control of any of registers below */
711	if (!amdgpu_sriov_vf(adev)) {	696	if (!amdgpu_sriov_vf(adev)) {
		697	/* set utc l1 enable flag always to 1 */
		698	temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
		699	temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
		700
		701	/* enable MCBP */
		702	temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
		703	WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
		704
		705	/* Set up RESP_MODE to non-copy addresses */
		706	temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
		707	temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
		708	temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
		709	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
		710
		711	/* program default cache read and write policy */
		712	temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
		713	/* clean read policy and write policy bits */
		714	temp &= 0xFF0FFF;
		715	temp \|= ((CACHE_READ_POLICY_L2__DEFAULT << 12) \|
		716	(CACHE_WRITE_POLICY_L2__DEFAULT << 14) \|
		717	SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
		718	WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
		719
712	/* unhalt engine */	720	/* unhalt engine */
713	temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));	721	temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
714	temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);	722	temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
@@ -1436,13 +1444,14 @@ static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, · 721 unmodified lines
1436	enum amdgpu_interrupt_state state)	1444	enum amdgpu_interrupt_state state)
1437	{	1445	{
1438	u32 sdma_cntl;	1446	u32 sdma_cntl;
1439
1440	u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);	1447	u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1441		1448
1442	sdma_cntl = RREG32(reg_offset);	1449	if (!amdgpu_sriov_vf(adev)) {
1443	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,	1450	sdma_cntl = RREG32(reg_offset);
1444	state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);	1451	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1445	WREG32(reg_offset, sdma_cntl);	1452	state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
		1453	WREG32(reg_offset, sdma_cntl);
		1454	}
1446		1455
1447	return 0;	1456	return 0;
1448	}	1457	}

drivers/gpu/drm/amd/amdgpu/soc15_common.h+5−0

 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)
+#define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
 	__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
 			 AMDGPU_REGS_NO_KIQ, ip##_HWIP)
 #define WREG32_SOC15_IP(ip, reg, value) \
 	 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
+#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \
+	 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
 	__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
 			     value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c+7−0

@@ -246,6 +246,13 @@ static int vcn_v1_0_suspend(void *handle) · 245 unmodified lines
246	{	246	{
247	int r;	247	int r;
248	struct amdgpu_device adev = (struct amdgpu_device )handle;	248	struct amdgpu_device adev = (struct amdgpu_device )handle;
		249	bool idle_work_unexecuted;
		250
		251	idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
		252	if (idle_work_unexecuted) {
		253	if (adev->pm.dpm_enabled)
		254	amdgpu_dpm_enable_uvd(adev, false);
		255	}
249		256
250	r = vcn_v1_0_hw_fini(adev);	257	r = vcn_v1_0_hw_fini(adev);
251	if (r)	258	if (r)

drivers/gpu/drm/amd/amdkfd/kfd_device.c+71−9

@@ -59,11 +59,78 @@ static void kfd_gtt_sa_fini(struct kfd_dev *kfd); · 58 unmodified lines
59		59
60	static int kfd_resume(struct kfd_dev *kfd);	60	static int kfd_resume(struct kfd_dev *kfd);
61		61
		62	static void kfd_device_info_set_sdma_queue_num(struct kfd_dev *kfd)
		63	{
		64	uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0];
		65
		66	switch (sdma_version) {
		67	case IP_VERSION(4, 0, 0):/* VEGA10 */
		68	case IP_VERSION(4, 0, 1):/* VEGA12 */
		69	case IP_VERSION(4, 1, 0):/* RAVEN */
		70	case IP_VERSION(4, 1, 1):/* RAVEN */
		71	case IP_VERSION(4, 1, 2):/* RENIOR */
		72	case IP_VERSION(5, 2, 1):/* VANGOGH */
		73	case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
		74	kfd->device_info.num_sdma_queues_per_engine = 2;
		75	break;
		76	case IP_VERSION(4, 2, 0):/* VEGA20 */
		77	case IP_VERSION(4, 2, 2):/* ARCTUTUS */
		78	case IP_VERSION(4, 4, 0):/* ALDEBARAN */
		79	case IP_VERSION(5, 0, 0):/* NAVI10 */
		80	case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
		81	case IP_VERSION(5, 0, 2):/* NAVI14 */
		82	case IP_VERSION(5, 0, 5):/* NAVI12 */
		83	case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
		84	case IP_VERSION(5, 2, 2):/* NAVY_FLOUDER */
		85	case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
		86	case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
		87	kfd->device_info.num_sdma_queues_per_engine = 8;
		88	break;
		89	default:
		90	dev_warn(kfd_device,
		91	"Default sdma queue per engine(8) is set due to "
		92	"mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
		93	sdma_version);
		94	kfd->device_info.num_sdma_queues_per_engine = 8;
		95	}
		96	}
		97
		98	static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
		99	{
		100	uint32_t gc_version = KFD_GC_VERSION(kfd);
		101
		102	switch (gc_version) {
		103	case IP_VERSION(9, 0, 1): /* VEGA10 */
		104	case IP_VERSION(9, 1, 0): /* RAVEN */
		105	case IP_VERSION(9, 2, 1): /* VEGA12 */
		106	case IP_VERSION(9, 2, 2): /* RAVEN */
		107	case IP_VERSION(9, 3, 0): /* RENOIR */
		108	case IP_VERSION(9, 4, 0): /* VEGA20 */
		109	case IP_VERSION(9, 4, 1): /* ARCTURUS */
		110	case IP_VERSION(9, 4, 2): /* ALDEBARAN */
		111	case IP_VERSION(10, 3, 1): /* VANGOGH */
		112	case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
		113	case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
		114	case IP_VERSION(10, 1, 10): /* NAVI10 */
		115	case IP_VERSION(10, 1, 2): /* NAVI12 */
		116	case IP_VERSION(10, 1, 1): /* NAVI14 */
		117	case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */
		118	case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */
		119	case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */
		120	case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */
		121	kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
		122	break;
		123	default:
		124	dev_warn(kfd_device, "v9 event interrupt handler is set due to "
		125	"mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version);
		126	kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
		127	}
		128	}
		129
62	static void kfd_device_info_init(struct kfd_dev *kfd,	130	static void kfd_device_info_init(struct kfd_dev *kfd,
63	bool vf, uint32_t gfx_target_version)	131	bool vf, uint32_t gfx_target_version)
64	{	132	{
65	uint32_t gc_version = KFD_GC_VERSION(kfd);	133	uint32_t gc_version = KFD_GC_VERSION(kfd);
66	uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0];
67	uint32_t asic_type = kfd->adev->asic_type;	134	uint32_t asic_type = kfd->adev->asic_type;
68		135
69	kfd->device_info.max_pasid_bits = 16;	136	kfd->device_info.max_pasid_bits = 16;
@@ -75,16 +142,11 @@ static void kfd_device_info_init(struct kfd_dev *kfd, · 5 unmodified lines
75	if (KFD_IS_SOC15(kfd)) {	142	if (KFD_IS_SOC15(kfd)) {
76	kfd->device_info.doorbell_size = 8;	143	kfd->device_info.doorbell_size = 8;
77	kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);	144	kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
78	kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
79	kfd->device_info.supports_cwsr = true;	145	kfd->device_info.supports_cwsr = true;
80		146
81	if ((sdma_version >= IP_VERSION(4, 0, 0) &&	147	kfd_device_info_set_sdma_queue_num(kfd);
82	sdma_version <= IP_VERSION(4, 2, 0)) \|\|	148
83	sdma_version == IP_VERSION(5, 2, 1) \|\|	149	kfd_device_info_set_event_interrupt_class(kfd);
84	sdma_version == IP_VERSION(5, 2, 3))
85	kfd->device_info.num_sdma_queues_per_engine = 2;
86	else
87	kfd->device_info.num_sdma_queues_per_engine = 8;
88		150
89	/* Raven */	151	/* Raven */
90	if (gc_version == IP_VERSION(9, 1, 0) \|\|	152	if (gc_version == IP_VERSION(9, 1, 0) \|\|

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+22−6

 				uint32_t filter_param);
 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
 				enum kfd_unmap_queues_filter filter,
-				uint32_t filter_param);
+				uint32_t filter_param, bool reset);
 static int map_queues_cpsch(struct device_queue_manager *dqm);
 	/* Make sure the queue is unmapped before updating the MQD */
 	if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
 		retval = unmap_queues_cpsch(dqm,
-				KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
+				KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false);
 		if (retval) {
 			pr_err("unmap queue failed\n");
 			goto out_unlock;
 	}
 	if (!dqm->is_hws_hang)
-		unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
+		unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, false);
 	hanging = dqm->is_hws_hang || dqm->is_resetting;
 	dqm->sched_running = false;
 /* dqm->lock mutex has to be locked before calling this function */
 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
 				enum kfd_unmap_queues_filter filter,
-				uint32_t filter_param)
+				uint32_t filter_param, bool reset)
 {
 	int retval = 0;
 	struct mqd_manager *mqd_mgr;
 		return retval;
 	retval = pm_send_unmap_queue(&dqm->packet_mgr, KFD_QUEUE_TYPE_COMPUTE,
-			filter, filter_param, false, 0);
+			filter, filter_param, reset, 0);
 	if (retval)
 		return retval;
 	return retval;
 }
+/* only for compute queue */
+static int reset_queues_cpsch(struct device_queue_manager *dqm,
+			uint16_t pasid)
+{
+	int retval;
+	dqm_lock(dqm);
+	retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID,
+			pasid, true);
+	dqm_unlock(dqm);
+	return retval;
+}
 /* dqm->lock mutex has to be locked before calling this function */
 static int execute_queues_cpsch(struct device_queue_manager *dqm,
 				enum kfd_unmap_queues_filter filter,
 	if (dqm->is_hws_hang)
 		return -EIO;
-	retval = unmap_queues_cpsch(dqm, filter, filter_param);
+	retval = unmap_queues_cpsch(dqm, filter, filter_param, false);
 	if (retval)
 		return retval;
 		dqm->ops.evict_process_queues = evict_process_queues_cpsch;
 		dqm->ops.restore_process_queues = restore_process_queues_cpsch;
 		dqm->ops.get_wave_state = get_wave_state;
+		dqm->ops.reset_queues = reset_queues_cpsch;
 		break;
 	case KFD_SCHED_POLICY_NO_HWS:
 		/* initialize dqm for no cp scheduling */

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h+5−0

  *
  * @get_wave_state: Retrieves context save state and optionally copies the
  * control stack, if kept in the MQD, to the given userspace address.
+ *
+ * @reset_queues: reset queues which consume RAS poison
  */
 struct device_queue_manager_ops {
 				  void __user *ctl_stack,
 				  u32 *ctl_stack_used_size,
 				  u32 *save_area_used_size);
+	int (*reset_queues)(struct device_queue_manager *dqm,
+					uint16_t pasid);
 };
 struct device_queue_manager_asic_ops {

drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c+40−4

@@ -89,6 +89,44 @@ enum SQ_INTERRUPT_ERROR_TYPE { · 88 unmodified lines
89	#define KFD_SQ_INT_DATA__ERR_TYPE_MASK 0xF00000	89	#define KFD_SQ_INT_DATA__ERR_TYPE_MASK 0xF00000
90	#define KFD_SQ_INT_DATA__ERR_TYPE__SHIFT 20	90	#define KFD_SQ_INT_DATA__ERR_TYPE__SHIFT 20
91		91
		92	static void event_interrupt_poison_consumption(struct kfd_dev *dev,
		93	uint16_t pasid, uint16_t source_id)
		94	{
		95	int ret = -EINVAL;
		96	struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
		97
		98	if (!p)
		99	return;
		100
		101	/* all queues of a process will be unmapped in one time */
		102	if (atomic_read(&p->poison)) {
		103	kfd_unref_process(p);
		104	return;
		105	}
		106
		107	atomic_set(&p->poison, 1);
		108	kfd_unref_process(p);
		109
		110	switch (source_id) {
		111	case SOC15_INTSRC_SQ_INTERRUPT_MSG:
		112	if (dev->dqm->ops.reset_queues)
		113	ret = dev->dqm->ops.reset_queues(dev->dqm, pasid);
		114	break;
		115	case SOC15_INTSRC_SDMA_ECC:
		116	default:
		117	break;
		118	}
		119
		120	kfd_signal_poison_consumed_event(dev, pasid);
		121
		122	/* resetting queue passes, do page retirement without gpu reset
		123	resetting queue fails, fallback to gpu reset solution */
		124	if (!ret)
		125	amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false);
		126	else
		127	amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, true);
		128	}
		129
92	static bool event_interrupt_isr_v9(struct kfd_dev *dev,	130	static bool event_interrupt_isr_v9(struct kfd_dev *dev,
93	const uint32_t *ih_ring_entry,	131	const uint32_t *ih_ring_entry,
94	uint32_t *patched_ihre,	132	uint32_t *patched_ihre,
@@ -230,8 +268,7 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev, · 135 unmodified lines
230	sq_intr_err);	268	sq_intr_err);
231	if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &&	269	if (sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST &&
232	sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {	270	sq_intr_err != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) {
233	kfd_signal_poison_consumed_event(dev, pasid);	271	event_interrupt_poison_consumption(dev, pasid, source_id);
234	amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev);
235	return;	272	return;
236	}	273	}
237	break;	274	break;
@@ -252,8 +289,7 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev, · 14 unmodified lines
252	if (source_id == SOC15_INTSRC_SDMA_TRAP) {	289	if (source_id == SOC15_INTSRC_SDMA_TRAP) {
253	kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);	290	kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);
254	} else if (source_id == SOC15_INTSRC_SDMA_ECC) {	291	} else if (source_id == SOC15_INTSRC_SDMA_ECC) {
255	kfd_signal_poison_consumed_event(dev, pasid);	292	event_interrupt_poison_consumption(dev, pasid, source_id);
256	amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev);
257	return;	293	return;
258	}	294	}
259	} else if (client_id == SOC15_IH_CLIENTID_VMC \|\|	295	} else if (client_id == SOC15_IH_CLIENTID_VMC \|\|

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c+1−1

@@ -549,7 +549,7 @@ static void svm_migrate_page_free(struct page *page) · 548 unmodified lines
549		549
550	if (svm_bo) {	550	if (svm_bo) {
551	pr_debug_ratelimited("ref: %d\n", kref_read(&svm_bo->kref));	551	pr_debug_ratelimited("ref: %d\n", kref_read(&svm_bo->kref));
552	svm_range_bo_unref(svm_bo);	552	svm_range_bo_unref_async(svm_bo);
553	}	553	}
554	}	554	}
555		555

drivers/gpu/drm/amd/amdkfd/kfd_priv.h+2−0

@@ -856,6 +856,8 @@ struct kfd_process { · 855 unmodified lines
856	struct svm_range_list svms;	856	struct svm_range_list svms;
857		857
858	bool xnack_enabled;	858	bool xnack_enabled;
		859
		860	atomic_t poison;
859	};	861	};
860		862
861	#define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */	863	#define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */

drivers/gpu/drm/amd/amdkfd/kfd_svm.c+29−6

@@ -332,6 +332,8 @@ static void svm_range_bo_release(struct kref *kref) · 331 unmodified lines
332	struct svm_range_bo *svm_bo;	332	struct svm_range_bo *svm_bo;
333		333
334	svm_bo = container_of(kref, struct svm_range_bo, kref);	334	svm_bo = container_of(kref, struct svm_range_bo, kref);
		335	pr_debug("svm_bo 0x%p\n", svm_bo);
		336
335	spin_lock(&svm_bo->list_lock);	337	spin_lock(&svm_bo->list_lock);
336	while (!list_empty(&svm_bo->range_list)) {	338	while (!list_empty(&svm_bo->range_list)) {
337	struct svm_range *prange =	339	struct svm_range *prange =
@@ -365,12 +367,33 @@ static void svm_range_bo_release(struct kref *kref) · 27 unmodified lines
365	kfree(svm_bo);	367	kfree(svm_bo);
366	}	368	}
367		369
368	void svm_range_bo_unref(struct svm_range_bo *svm_bo)	370	static void svm_range_bo_wq_release(struct work_struct *work)
369	{	371	{
370	if (!svm_bo)	372	struct svm_range_bo *svm_bo;
371	return;	373
		374	svm_bo = container_of(work, struct svm_range_bo, release_work);
		375	svm_range_bo_release(&svm_bo->kref);
		376	}
		377
		378	static void svm_range_bo_release_async(struct kref *kref)
		379	{
		380	struct svm_range_bo *svm_bo;
		381
		382	svm_bo = container_of(kref, struct svm_range_bo, kref);
		383	pr_debug("svm_bo 0x%p\n", svm_bo);
		384	INIT_WORK(&svm_bo->release_work, svm_range_bo_wq_release);
		385	schedule_work(&svm_bo->release_work);
		386	}
372		387
373	kref_put(&svm_bo->kref, svm_range_bo_release);	388	void svm_range_bo_unref_async(struct svm_range_bo *svm_bo)
		389	{
		390	kref_put(&svm_bo->kref, svm_range_bo_release_async);
		391	}
		392
		393	static void svm_range_bo_unref(struct svm_range_bo *svm_bo)
		394	{
		395	if (svm_bo)
		396	kref_put(&svm_bo->kref, svm_range_bo_release);
374	}	397	}
375		398
376	static bool	399	static bool
@@ -2254,8 +2277,8 @@ svm_range_cpu_invalidate_pagetables(struct mmu_interval_notifier *mni, · 1877 unmodified lines
2254		2277
2255	start = mni->interval_tree.start;	2278	start = mni->interval_tree.start;
2256	last = mni->interval_tree.last;	2279	last = mni->interval_tree.last;
2257	start = (start > range->start ? start : range->start) >> PAGE_SHIFT;	2280	start = max(start, range->start) >> PAGE_SHIFT;
2258	last = (last < (range->end - 1) ? last : range->end - 1) >> PAGE_SHIFT;	2281	last = min(last, range->end - 1) >> PAGE_SHIFT;
2259	pr_debug("[0x%lx 0x%lx] range[0x%lx 0x%lx] notifier[0x%lx 0x%lx] %d\n",	2282	pr_debug("[0x%lx 0x%lx] range[0x%lx 0x%lx] notifier[0x%lx 0x%lx] %d\n",
2260	start, last, range->start >> PAGE_SHIFT,	2283	start, last, range->start >> PAGE_SHIFT,
2261	(range->end - 1) >> PAGE_SHIFT,	2284	(range->end - 1) >> PAGE_SHIFT,

drivers/gpu/drm/amd/amdkfd/kfd_svm.h+2−1

 	struct work_struct		eviction_work;
 	struct svm_range_list		*svms;
 	uint32_t			evicting;
+	struct work_struct		release_work;
 };
 enum svm_work_list_ops {
  */
 #define KFD_IS_SVM_API_SUPPORTED(dev) ((dev)->pgmap.type != 0)
-void svm_range_bo_unref(struct svm_range_bo *svm_bo);
+void svm_range_bo_unref_async(struct svm_range_bo *svm_bo);
 #else
 struct kfd_process;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c+1−1

@@ -741,7 +741,7 @@ void vg_clk_mgr_construct( · 740 unmodified lines
741	sizeof(struct watermarks),	741	sizeof(struct watermarks),
742	&clk_mgr->smu_wm_set.mc_address.quad_part);	742	&clk_mgr->smu_wm_set.mc_address.quad_part);
743		743
744	if (clk_mgr->smu_wm_set.wm_set == 0) {	744	if (!clk_mgr->smu_wm_set.wm_set) {
745	clk_mgr->smu_wm_set.wm_set = &dummy_wms;	745	clk_mgr->smu_wm_set.wm_set = &dummy_wms;
746	clk_mgr->smu_wm_set.mc_address.quad_part = 0;	746	clk_mgr->smu_wm_set.mc_address.quad_part = 0;
747	}	747	}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c+1−0

@@ -158,6 +158,7 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, · 157 unmodified lines
158	union display_idle_optimization_u idle_info = { 0 };	158	union display_idle_optimization_u idle_info = { 0 };
159	idle_info.idle_info.df_request_disabled = 1;	159	idle_info.idle_info.df_request_disabled = 1;
160	idle_info.idle_info.phy_ref_clk_off = 1;	160	idle_info.idle_info.phy_ref_clk_off = 1;
		161	idle_info.idle_info.s0i2_rdy = 1;
161	dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);	162	dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
162	/* update power state */	163	/* update power state */
163	clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;	164	clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;

drivers/gpu/drm/amd/display/dc/core/dc.c+0−18

@@ -274,24 +274,6 @@ static bool create_links( · 273 unmodified lines
274	goto failed_alloc;	274	goto failed_alloc;
275	}	275	}
276		276
277	#if defined(CONFIG_DRM_AMD_DC_DCN)
278	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
279	dc->caps.dp_hpo &&
280	link->dc->res_pool->res_cap->num_hpo_dp_link_encoder > 0) {
281	/* FPGA case - Allocate HPO DP link encoder */
282	if (i < link->dc->res_pool->res_cap->num_hpo_dp_link_encoder) {
283	link->hpo_dp_link_enc = link->dc->res_pool->hpo_dp_link_enc[i];
284
285	if (link->hpo_dp_link_enc == NULL) {
286	BREAK_TO_DEBUGGER();
287	goto failed_alloc;
288	}
289	link->hpo_dp_link_enc->hpd_source = link->link_enc->hpd_source;
290	link->hpo_dp_link_enc->transmitter = link->link_enc->transmitter;
291	}
292	}
293	#endif
294
295	link->link_status.dpcd_caps = &link->dpcd_caps;	277	link->link_status.dpcd_caps = &link->dpcd_caps;
296		278
297	enc_init.ctx = dc->ctx;	279	enc_init.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc_debug.c+2−0

 		return "The operation is not supported.";
 	case DC_UNSUPPORTED_VALUE:
 		return "The value specified is not supported.";
+	case DC_NO_LINK_ENC_RESOURCE:
+		return "No link encoder resource";
 	case DC_ERROR_UNEXPECTED:
 		return "Unexpected error";
 	}

drivers/gpu/drm/amd/display/dc/core/dc_link.c+173−68

@@ -66,31 +66,6 @@ · 65 unmodified lines
66	/*******************************************************************************	66	/*******************************************************************************
67	* Private functions	67	* Private functions
68	******************************************************************************/	68	******************************************************************************/
69	#if defined(CONFIG_DRM_AMD_DC_DCN)
70	static bool add_dp_hpo_link_encoder_to_link(struct dc_link *link)
71	{
72	struct hpo_dp_link_encoder *enc = resource_get_unused_hpo_dp_link_encoder(
73	link->dc->res_pool);
74
75	if (!link->hpo_dp_link_enc && enc) {
76	link->hpo_dp_link_enc = enc;
77	link->hpo_dp_link_enc->transmitter = link->link_enc->transmitter;
78	link->hpo_dp_link_enc->hpd_source = link->link_enc->hpd_source;
79	}
80
81	return (link->hpo_dp_link_enc != NULL);
82	}
83
84	static void remove_dp_hpo_link_encoder_from_link(struct dc_link *link)
85	{
86	if (link->hpo_dp_link_enc) {
87	link->hpo_dp_link_enc->hpd_source = HPD_SOURCEID_UNKNOWN;
88	link->hpo_dp_link_enc->transmitter = TRANSMITTER_UNKNOWN;
89	link->hpo_dp_link_enc = NULL;
90	}
91	}
92	#endif
93
94	static void dc_link_destruct(struct dc_link *link)	69	static void dc_link_destruct(struct dc_link *link)
95	{	70	{
96	int i;	71	int i;
@@ -118,12 +93,6 @@ static void dc_link_destruct(struct dc_link *link) · 21 unmodified lines
118	link->link_enc->funcs->destroy(&link->link_enc);	93	link->link_enc->funcs->destroy(&link->link_enc);
119	}	94	}
120		95
121	#if defined(CONFIG_DRM_AMD_DC_DCN)
122	if (link->hpo_dp_link_enc) {
123	remove_dp_hpo_link_encoder_from_link(link);
124	}
125	#endif
126
127	if (link->local_sink)	96	if (link->local_sink)
128	dc_sink_release(link->local_sink);	97	dc_sink_release(link->local_sink);
129		98
@@ -881,6 +850,7 @@ static bool dc_link_detect_helper(struct dc_link *link, · 751 unmodified lines
881	enum dc_connection_type pre_connection_type = dc_connection_none;	850	enum dc_connection_type pre_connection_type = dc_connection_none;
882	bool perform_dp_seamless_boot = false;	851	bool perform_dp_seamless_boot = false;
883	const uint32_t post_oui_delay = 30; // 30ms	852	const uint32_t post_oui_delay = 30; // 30ms
		853	struct link_resource link_res = { 0 };
884		854
885	DC_LOGGER_INIT(link->ctx->logger);	855	DC_LOGGER_INIT(link->ctx->logger);
886		856
@@ -975,7 +945,10 @@ static bool dc_link_detect_helper(struct dc_link *link, · 88 unmodified lines
975		945
976	#if defined(CONFIG_DRM_AMD_DC_DCN)	946	#if defined(CONFIG_DRM_AMD_DC_DCN)
977	if (dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING)	947	if (dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING)
978	add_dp_hpo_link_encoder_to_link(link);	948	link_res.hpo_dp_link_enc = resource_get_hpo_dp_link_enc_for_det_lt(
		949	&link->dc->current_state->res_ctx,
		950	link->dc->res_pool,
		951	link);
979	#endif	952	#endif
980		953
981	if (link->type == dc_connection_mst_branch) {	954	if (link->type == dc_connection_mst_branch) {
@@ -986,7 +959,7 @@ static bool dc_link_detect_helper(struct dc_link *link, · 4 unmodified lines
986	* empty which leads to allocate_mst_payload() has "0"	959	* empty which leads to allocate_mst_payload() has "0"
987	* pbn_per_slot value leading to exception on dc_fixpt_div()	960	* pbn_per_slot value leading to exception on dc_fixpt_div()
988	*/	961	*/
989	dp_verify_mst_link_cap(link);	962	dp_verify_mst_link_cap(link, &link_res);
990		963
991	/*	964	/*
992	* This call will initiate MST topology discovery. Which	965	* This call will initiate MST topology discovery. Which
@@ -1150,6 +1123,7 @@ static bool dc_link_detect_helper(struct dc_link *link, · 157 unmodified lines
1150	// verify link cap for SST non-seamless boot	1123	// verify link cap for SST non-seamless boot
1151	if (!perform_dp_seamless_boot)	1124	if (!perform_dp_seamless_boot)
1152	dp_verify_link_cap_with_retries(link,	1125	dp_verify_link_cap_with_retries(link,
		1126	&link_res,
1153	&link->reported_link_cap,	1127	&link->reported_link_cap,
1154	LINK_TRAINING_MAX_VERIFY_RETRY);	1128	LINK_TRAINING_MAX_VERIFY_RETRY);
1155	} else {	1129	} else {
@@ -1844,6 +1818,8 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) · 688 unmodified lines
1844	union down_spread_ctrl old_downspread;	1818	union down_spread_ctrl old_downspread;
1845	union down_spread_ctrl new_downspread;	1819	union down_spread_ctrl new_downspread;
1846		1820
		1821	memset(&old_downspread, 0, sizeof(old_downspread));
		1822
1847	core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,	1823	core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1848	&old_downspread.raw, sizeof(old_downspread));	1824	&old_downspread.raw, sizeof(old_downspread));
1849		1825
@@ -2503,7 +2479,8 @@ static void write_i2c_redriver_setting( · 653 unmodified lines
2503	DC_LOG_DEBUG("Set redriver failed");	2479	DC_LOG_DEBUG("Set redriver failed");
2504	}	2480	}
2505		2481
2506	static void disable_link(struct dc_link *link, enum signal_type signal)	2482	static void disable_link(struct dc_link link, const struct link_resource link_res,
		2483	enum signal_type signal)
2507	{	2484	{
2508	/*	2485	/*
2509	* TODO: implement call for dp_set_hw_test_pattern	2486	* TODO: implement call for dp_set_hw_test_pattern
@@ -2522,20 +2499,20 @@ static void disable_link(struct dc_link *link, enum signal_type signal) · 12 unmodified lines
2522	struct dc_link_settings link_settings = link->cur_link_settings;	2499	struct dc_link_settings link_settings = link->cur_link_settings;
2523	#endif	2500	#endif
2524	if (dc_is_dp_sst_signal(signal))	2501	if (dc_is_dp_sst_signal(signal))
2525	dp_disable_link_phy(link, signal);	2502	dp_disable_link_phy(link, link_res, signal);
2526	else	2503	else
2527	dp_disable_link_phy_mst(link, signal);	2504	dp_disable_link_phy_mst(link, link_res, signal);
2528		2505
2529	if (dc_is_dp_sst_signal(signal) \|\|	2506	if (dc_is_dp_sst_signal(signal) \|\|
2530	link->mst_stream_alloc_table.stream_count == 0) {	2507	link->mst_stream_alloc_table.stream_count == 0) {
2531	#if defined(CONFIG_DRM_AMD_DC_DCN)	2508	#if defined(CONFIG_DRM_AMD_DC_DCN)
2532	if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {	2509	if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2533	dp_set_fec_enable(link, false);	2510	dp_set_fec_enable(link, false);
2534	dp_set_fec_ready(link, false);	2511	dp_set_fec_ready(link, link_res, false);
2535	}	2512	}
2536	#else	2513	#else
2537	dp_set_fec_enable(link, false);	2514	dp_set_fec_enable(link, false);
2538	dp_set_fec_ready(link, false);	2515	dp_set_fec_ready(link, link_res, false);
2539	#endif	2516	#endif
2540	}	2517	}
2541	} else {	2518	} else {
@@ -2646,7 +2623,7 @@ static enum dc_status enable_link( · 104 unmodified lines
2646	* new link settings.	2623	* new link settings.
2647	*/	2624	*/
2648	if (link->link_status.link_active) {	2625	if (link->link_status.link_active) {
2649	disable_link(link, pipe_ctx->stream->signal);	2626	disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
2650	}	2627	}
2651		2628
2652	switch (pipe_ctx->stream->signal) {	2629	switch (pipe_ctx->stream->signal) {
@@ -3421,7 +3398,7 @@ static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, · 768 unmodified lines
3421	{	3398	{
3422	struct dc_stream_state *stream = pipe_ctx->stream;	3399	struct dc_stream_state *stream = pipe_ctx->stream;
3423	struct dc_link *link = stream->link;	3400	struct dc_link *link = stream->link;
3424	struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;	3401	struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
3425	struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;	3402	struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3426	struct link_mst_stream_allocation_table proposed_table = {0};	3403	struct link_mst_stream_allocation_table proposed_table = {0};
3427	struct fixed31_32 avg_time_slots_per_mtp;	3404	struct fixed31_32 avg_time_slots_per_mtp;
@@ -3503,7 +3480,7 @@ enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx) · 75 unmodified lines
3503	struct link_encoder *link_encoder = NULL;	3480	struct link_encoder *link_encoder = NULL;
3504	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;	3481	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3505	#if defined(CONFIG_DRM_AMD_DC_DCN)	3482	#if defined(CONFIG_DRM_AMD_DC_DCN)
3506	struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;	3483	struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
3507	struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;	3484	struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3508	#endif	3485	#endif
3509	struct dp_mst_stream_allocation_table proposed_table = {0};	3486	struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -3833,7 +3810,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) · 323 unmodified lines
3833	struct link_encoder *link_encoder = NULL;	3810	struct link_encoder *link_encoder = NULL;
3834	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;	3811	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3835	#if defined(CONFIG_DRM_AMD_DC_DCN)	3812	#if defined(CONFIG_DRM_AMD_DC_DCN)
3836	struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;	3813	struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
3837	struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;	3814	struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3838	#endif	3815	#endif
3839	struct dp_mst_stream_allocation_table proposed_table = {0};	3816	struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -4009,12 +3986,9 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) · 169 unmodified lines
4009	config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;	3986	config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
4010	#if defined(CONFIG_DRM_AMD_DC_DCN)	3987	#if defined(CONFIG_DRM_AMD_DC_DCN)
4011	config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;	3988	config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
4012		3989
4013	if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY \|\|	3990	if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY \|\|
4014	pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {	3991	pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
4015	link_enc = pipe_ctx->stream->link->link_enc;
4016	config.dio_output_type = pipe_ctx->stream->link->ep_type;
4017	config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4018	if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY)	3992	if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY)
4019	link_enc = pipe_ctx->stream->link->link_enc;	3993	link_enc = pipe_ctx->stream->link->link_enc;
4020	else if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)	3994	else if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
@@ -4081,7 +4055,8 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) · 60 unmodified lines
4081	config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;	4055	config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4082	if (is_dp_128b_132b_signal(pipe_ctx)) {	4056	if (is_dp_128b_132b_signal(pipe_ctx)) {
4083	config.stream_enc_idx = pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;	4057	config.stream_enc_idx = pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
4084	config.link_enc_idx = pipe_ctx->stream->link->hpo_dp_link_enc->inst;	4058
		4059	config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
4085	config.dp2_enabled = 1;	4060	config.dp2_enabled = 1;
4086	}	4061	}
4087	#endif	4062	#endif
@@ -4112,7 +4087,7 @@ static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pi · 24 unmodified lines
4112	stream->link->cur_link_settings = link_settings;	4087	stream->link->cur_link_settings = link_settings;
4113		4088
4114	/* Enable clock, Configure lane count, and Enable Link Encoder*/	4089	/* Enable clock, Configure lane count, and Enable Link Encoder*/
4115	enable_dp_hpo_output(stream->link, &stream->link->cur_link_settings);	4090	enable_dp_hpo_output(stream->link, &pipe_ctx->link_res, &stream->link->cur_link_settings);
4116		4091
4117	#ifdef DIAGS_BUILD	4092	#ifdef DIAGS_BUILD
4118	/* Workaround for FPGA HPO capture DP link data:	4093	/* Workaround for FPGA HPO capture DP link data:
@@ -4162,12 +4137,12 @@ static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pi · 43 unmodified lines
4162	proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;	4137	proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
4163	}	4138	}
4164		4139
4165	stream->link->hpo_dp_link_enc->funcs->update_stream_allocation_table(	4140	pipe_ctx->link_res.hpo_dp_link_enc->funcs->update_stream_allocation_table(
4166	stream->link->hpo_dp_link_enc,	4141	pipe_ctx->link_res.hpo_dp_link_enc,
4167	&proposed_table);	4142	&proposed_table);
4168		4143
4169	stream->link->hpo_dp_link_enc->funcs->set_throttled_vcp_size(	4144	pipe_ctx->link_res.hpo_dp_link_enc->funcs->set_throttled_vcp_size(
4170	stream->link->hpo_dp_link_enc,	4145	pipe_ctx->link_res.hpo_dp_link_enc,
4171	pipe_ctx->stream_res.hpo_dp_stream_enc->inst,	4146	pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
4172	avg_time_slots_per_mtp);	4147	avg_time_slots_per_mtp);
4173		4148
@@ -4356,7 +4331,8 @@ void core_link_enable_stream( · 182 unmodified lines
4356	if (status != DC_FAIL_DP_LINK_TRAINING \|\|	4331	if (status != DC_FAIL_DP_LINK_TRAINING \|\|
4357	pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {	4332	pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
4358	if (false == stream->link->link_status.link_active)	4333	if (false == stream->link->link_status.link_active)
4359	disable_link(stream->link, pipe_ctx->stream->signal);	4334	disable_link(stream->link, &pipe_ctx->link_res,
		4335	pipe_ctx->stream->signal);
4360	BREAK_TO_DEBUGGER();	4336	BREAK_TO_DEBUGGER();
4361	return;	4337	return;
4362	}	4338	}
@@ -4505,14 +4481,14 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx) · 142 unmodified lines
4505	* state machine.	4481	* state machine.
4506	* In DP2 or MST mode, our encoder will stay video active	4482	* In DP2 or MST mode, our encoder will stay video active
4507	*/	4483	*/
4508	disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);	4484	disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4509	dc->hwss.disable_stream(pipe_ctx);	4485	dc->hwss.disable_stream(pipe_ctx);
4510	} else {	4486	} else {
4511	dc->hwss.disable_stream(pipe_ctx);	4487	dc->hwss.disable_stream(pipe_ctx);
4512	disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);	4488	disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4513	}	4489	}
4514	#else	4490	#else
4515	disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);	4491	disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4516		4492
4517	dc->hwss.disable_stream(pipe_ctx);	4493	dc->hwss.disable_stream(pipe_ctx);
4518	#endif	4494	#endif
@@ -4595,16 +4571,22 @@ void dc_link_set_drive_settings(struct dc *dc, · 76 unmodified lines
4595	{	4571	{
4596		4572
4597	int i;	4573	int i;
		4574	struct pipe_ctx *pipe = NULL;
		4575	const struct link_resource *link_res;
4598		4576
4599	for (i = 0; i < dc->link_count; i++) {	4577	link_res = dc_link_get_cur_link_res(link);
4600	if (dc->links[i] == link)
4601	break;
4602	}
4603		4578
4604	if (i >= dc->link_count)	4579	for (i = 0; i < MAX_PIPES; i++) {
		4580	pipe = &dc->current_state->res_ctx.pipe_ctx[i];
		4581	if (pipe->stream && pipe->stream->link) {
		4582	if (pipe->stream->link == link)
		4583	break;
		4584	}
		4585	}
		4586	if (pipe && link_res)
		4587	dc_link_dp_set_drive_settings(pipe->stream->link, link_res, lt_settings);
		4588	else
4605	ASSERT_CRITICAL(false);	4589	ASSERT_CRITICAL(false);
4606
4607	dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
4608	}	4590	}
4609		4591
4610	void dc_link_set_preferred_link_settings(struct dc *dc,	4592	void dc_link_set_preferred_link_settings(struct dc *dc,
@@ -4665,11 +4647,9 @@ void dc_link_set_preferred_training_settings(struct dc *dc, · 54 unmodified lines
4665	if (link_setting != NULL) {	4647	if (link_setting != NULL) {
4666	link->preferred_link_setting = *link_setting;	4648	link->preferred_link_setting = *link_setting;
4667	#if defined(CONFIG_DRM_AMD_DC_DCN)	4649	#if defined(CONFIG_DRM_AMD_DC_DCN)
4668	if (dp_get_link_encoding_format(link_setting) ==	4650	if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
4669	DP_128b_132b_ENCODING && !link->hpo_dp_link_enc) {	4651	/* TODO: add dc update for acquiring link res */
4670	if (!add_dp_hpo_link_encoder_to_link(link))	4652	skip_immediate_retrain = true;
4671	memset(&link->preferred_link_setting, 0, sizeof(link->preferred_link_setting));
4672	}
4673	#endif	4653	#endif
4674	} else {	4654	} else {
4675	link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;	4655	link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
@@ -4796,6 +4776,9 @@ void dc_link_overwrite_extended_receiver_cap( · 120 unmodified lines
4796		4776
4797	bool dc_link_is_fec_supported(const struct dc_link *link)	4777	bool dc_link_is_fec_supported(const struct dc_link *link)
4798	{	4778	{
		4779	/* TODO - use asic cap instead of link_enc->features
		4780	* we no longer know which link enc to use for this link before commit
		4781	*/
4799	struct link_encoder *link_enc = NULL;	4782	struct link_encoder *link_enc = NULL;
4800		4783
4801	/* Links supporting dynamically assigned link encoder will be assigned next	4784	/* Links supporting dynamically assigned link encoder will be assigned next
@@ -4890,3 +4873,125 @@ uint32_t dc_bandwidth_in_kbps_from_timing( · 88 unmodified lines
4890	return kbps;	4873	return kbps;
4891		4874
4892	}	4875	}
		4876
		4877	const struct link_resource dc_link_get_cur_link_res(const struct dc_link link)
		4878	{
		4879	int i;
		4880	struct pipe_ctx *pipe = NULL;
		4881	const struct link_resource *link_res = NULL;
		4882
		4883	for (i = 0; i < MAX_PIPES; i++) {
		4884	pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
		4885	if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) {
		4886	if (pipe->stream->link == link) {
		4887	link_res = &pipe->link_res;
		4888	break;
		4889	}
		4890	}
		4891	}
		4892
		4893	return link_res;
		4894	}
		4895
		4896	/**
		4897	* dc_get_cur_link_res_map() - take a snapshot of current link resource allocation state
		4898	* @dc: pointer to dc of the dm calling this
		4899	* @map: a dc link resource snapshot defined internally to dc.
		4900	*
		4901	* DM needs to capture a snapshot of current link resource allocation mapping
		4902	* and store it in its persistent storage.
		4903	*
		4904	* Some of the link resource is using first come first serve policy.
		4905	* The allocation mapping depends on original hotplug order. This information
		4906	* is lost after driver is loaded next time. The snapshot is used in order to
		4907	* restore link resource to its previous state so user will get consistent
		4908	* link capability allocation across reboot.
		4909	*
		4910	* Return: none (void function)
		4911	*
		4912	*/
		4913	void dc_get_cur_link_res_map(const struct dc dc, uint32_t map)
		4914	{
		4915	#if defined(CONFIG_DRM_AMD_DC_DCN)
		4916	struct dc_link *link;
		4917	uint8_t i;
		4918	uint32_t hpo_dp_recycle_map = 0;
		4919
		4920	*map = 0;
		4921
		4922	if (dc->caps.dp_hpo) {
		4923	for (i = 0; i < dc->caps.max_links; i++) {
		4924	link = dc->links[i];
		4925	if (link->link_status.link_active &&
		4926	dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING &&
		4927	dp_get_link_encoding_format(&link->cur_link_settings) != DP_128b_132b_ENCODING)
		4928	/* hpo dp link encoder is considered as recycled, when RX reports 128b/132b encoding capability
		4929	* but current link doesn't use it.
		4930	*/
		4931	hpo_dp_recycle_map \|= (1 << i);
		4932	}
		4933	*map \|= (hpo_dp_recycle_map << LINK_RES_HPO_DP_REC_MAP__SHIFT);
		4934	}
		4935	#endif
		4936	}
		4937
		4938	/**
		4939	* dc_restore_link_res_map() - restore link resource allocation state from a snapshot
		4940	* @dc: pointer to dc of the dm calling this
		4941	* @map: a dc link resource snapshot defined internally to dc.
		4942	*
		4943	* DM needs to call this function after initial link detection on boot and
		4944	* before first commit streams to restore link resource allocation state
		4945	* from previous boot session.
		4946	*
		4947	* Some of the link resource is using first come first serve policy.
		4948	* The allocation mapping depends on original hotplug order. This information
		4949	* is lost after driver is loaded next time. The snapshot is used in order to
		4950	* restore link resource to its previous state so user will get consistent
		4951	* link capability allocation across reboot.
		4952	*
		4953	* Return: none (void function)
		4954	*
		4955	*/
		4956	void dc_restore_link_res_map(const struct dc dc, uint32_t map)
		4957	{
		4958	#if defined(CONFIG_DRM_AMD_DC_DCN)
		4959	struct dc_link *link;
		4960	uint8_t i;
		4961	unsigned int available_hpo_dp_count;
		4962	uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK)
		4963	>> LINK_RES_HPO_DP_REC_MAP__SHIFT;
		4964
		4965	if (dc->caps.dp_hpo) {
		4966	available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;
		4967	/* remove excess 128b/132b encoding support for not recycled links */
		4968	for (i = 0; i < dc->caps.max_links; i++) {
		4969	if ((hpo_dp_recycle_map & (1 << i)) == 0) {
		4970	link = dc->links[i];
		4971	if (link->type != dc_connection_none &&
		4972	dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
		4973	if (available_hpo_dp_count > 0)
		4974	available_hpo_dp_count--;
		4975	else
		4976	/* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
		4977	link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
		4978	}
		4979	}
		4980	}
		4981	/* remove excess 128b/132b encoding support for recycled links */
		4982	for (i = 0; i < dc->caps.max_links; i++) {
		4983	if ((hpo_dp_recycle_map & (1 << i)) != 0) {
		4984	link = dc->links[i];
		4985	if (link->type != dc_connection_none &&
		4986	dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
		4987	if (available_hpo_dp_count > 0)
		4988	available_hpo_dp_count--;
		4989	else
		4990	/* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
		4991	link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
		4992	}
		4993	}
		4994	}
		4995	}
		4996	#endif
		4997	}

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+434−67

 static bool perform_post_lt_adj_req_sequence(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	struct link_training_settings *lt_settings)
 {
 	enum dc_lane_count lane_count =
 						lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
 				dc_link_dp_set_drive_settings(link,
+						link_res,
 						lt_settings);
 				break;
 			}
 static enum link_training_result perform_channel_equalization_sequence(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	struct link_training_settings *lt_settings,
 	uint32_t offset)
 {
 		tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 #endif
-	dp_set_hw_training_pattern(link, tr_pattern, offset);
+	dp_set_hw_training_pattern(link, link_res, tr_pattern, offset);
 	for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 		retries_ch_eq++) {
-		dp_set_hw_lane_settings(link, lt_settings, offset);
+		dp_set_hw_lane_settings(link, link_res, lt_settings, offset);
 		/* 2. update DPCD*/
 		if (!retries_ch_eq)
 }
 static void start_clock_recovery_pattern_early(struct dc_link *link,
+		const struct link_resource *link_res,
 		struct link_training_settings *lt_settings,
 		uint32_t offset)
 {
 	DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
 			__func__);
-	dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
+	dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, offset);
-	dp_set_hw_lane_settings(link, lt_settings, offset);
+	dp_set_hw_lane_settings(link, link_res, lt_settings, offset);
 	udelay(400);
 }
 static enum link_training_result perform_clock_recovery_sequence(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	struct link_training_settings *lt_settings,
 	uint32_t offset)
 {
 	retry_count = 0;
 	if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
-		dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
+		dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, offset);
 	/* najeeb - The synaptics MST hub can put the LT in
 	* infinite loop by switching the VS
 		/* 1. call HWSS to set lane settings*/
 		dp_set_hw_lane_settings(
 				link,
+				link_res,
 				lt_settings,
 				offset);
 		/* 3. wait receiver to lock-on*/
 		wait_time_microsec = lt_settings->cr_pattern_time;
-		if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
-			wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
 		if (link->dc->debug.apply_vendor_specific_lttpr_wa &&
 				(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)) {
 			wait_time_microsec = 16000;
 static inline enum link_training_result dp_transition_to_video_idle(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	struct link_training_settings *lt_settings,
 	enum link_training_result status)
 {
 	union lane_count_set lane_count_set = {0};
 	/* 4. mainlink output idle pattern*/
-	dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
+	dp_set_hw_test_pattern(link, link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
 	/*
 	 * 5. post training adjust if required
 	}
 	if (status == LINK_TRAINING_SUCCESS &&
-		perform_post_lt_adj_req_sequence(link, lt_settings) == false)
+		perform_post_lt_adj_req_sequence(link, link_res, lt_settings) == false)
 		status = LINK_TRAINING_LQA_FAIL;
 	lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
 void dc_link_dp_set_drive_settings(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	struct link_training_settings *lt_settings)
 {
 	/* program ASIC PHY settings*/
-	dp_set_hw_lane_settings(link, lt_settings, DPRX);
+	dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
 	dp_hw_to_dpcd_lane_settings(lt_settings,
 			lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
 bool dc_link_dp_perform_link_training_skip_aux(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	const struct dc_link_settings *link_setting)
 {
 	struct link_training_settings lt_settings = {0};
 	/* 1. Perform_clock_recovery_sequence. */
 	/* transmit training pattern for clock recovery */
-	dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
+	dp_set_hw_training_pattern(link, link_res, lt_settings.pattern_for_cr, DPRX);
 	/* call HWSS to set lane settings*/
-	dp_set_hw_lane_settings(link, &lt_settings, DPRX);
+	dp_set_hw_lane_settings(link, link_res, &lt_settings, DPRX);
 	/* wait receiver to lock-on*/
 	dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
 	/* 2. Perform_channel_equalization_sequence. */
 	/* transmit training pattern for channel equalization. */
-	dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
+	dp_set_hw_training_pattern(link, link_res, lt_settings.pattern_for_eq, DPRX);
 	/* call HWSS to set lane settings*/
-	dp_set_hw_lane_settings(link, &lt_settings, DPRX);
+	dp_set_hw_lane_settings(link, link_res, &lt_settings, DPRX);
 	/* wait receiver to lock-on. */
 	dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
 	/* 3. Perform_link_training_int. */
 	/* Mainlink output idle pattern. */
-	dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
+	dp_set_hw_test_pattern(link, link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
 	print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
 static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
 		struct dc_link *link,
+		const struct link_resource *link_res,
 		struct link_training_settings *lt_settings)
 {
 	uint8_t loop_count;
 	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
 	/* Transmit 128b/132b_TPS1 over Main-Link */
-	dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, DPRX);
+	dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, DPRX);
 	/* Set TRAINING_PATTERN_SET to 01h */
 	dpcd_set_training_pattern(link, lt_settings->pattern_for_cr);
 			&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);
 	dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
 			lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
-	dp_set_hw_lane_settings(link, lt_settings, DPRX);
+	dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
-	dp_set_hw_training_pattern(link, lt_settings->pattern_for_eq, DPRX);
+	dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_eq, DPRX);
 	/* Set loop counter to start from 1 */
 	loop_count = 1;
 		} else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) {
 			status = DP_128b_132b_LT_FAILED;
 		} else {
-			dp_set_hw_lane_settings(link, lt_settings, DPRX);
+			dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);
 			dpcd_set_lane_settings(link, lt_settings, DPRX);
 		}
 		loop_count++;
 static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
 		struct dc_link *link,
+		const struct link_resource *link_res,
 		struct link_training_settings *lt_settings)
 {
 	/* Assumption: assume hardware has transmitted eq pattern */
 static enum link_training_result dp_perform_8b_10b_link_training(
 		struct dc_link *link,
+		const struct link_resource *link_res,
 		struct link_training_settings *lt_settings)
 {
 	enum link_training_result status = LINK_TRAINING_SUCCESS;
 	uint8_t lane = 0;
 	if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
-		start_clock_recovery_pattern_early(link, lt_settings, DPRX);
+		start_clock_recovery_pattern_early(link, link_res, lt_settings, DPRX);
 	/* 1. set link rate, lane count and spread. */
 	dpcd_set_link_settings(link, lt_settings);
 		for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
 				repeater_id--) {
-			status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
+			status = perform_clock_recovery_sequence(link, link_res, lt_settings, repeater_id);
 			if (status != LINK_TRAINING_SUCCESS)
 				break;
 			status = perform_channel_equalization_sequence(link,
+					link_res,
 					lt_settings,
 					repeater_id);
 	}
 	if (status == LINK_TRAINING_SUCCESS) {
-		status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
+		status = perform_clock_recovery_sequence(link, link_res, lt_settings, DPRX);
 	if (status == LINK_TRAINING_SUCCESS) {
 		status = perform_channel_equalization_sequence(link,
+					link_res,
 					lt_settings,
 					DPRX);
 		}
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 static enum link_training_result dp_perform_128b_132b_link_training(
 		struct dc_link *link,
+		const struct link_resource *link_res,
 		struct link_training_settings *lt_settings)
 {
 	enum link_training_result result = LINK_TRAINING_SUCCESS;
 		decide_8b_10b_training_settings(link,
 				&lt_settings->link_settings,
 				&legacy_settings);
-		return dp_perform_8b_10b_link_training(link, &legacy_settings);
+		return dp_perform_8b_10b_link_training(link, link_res, &legacy_settings);
 	}
 	dpcd_set_link_settings(link, lt_settings);
 	if (result == LINK_TRAINING_SUCCESS)
-		result = dp_perform_128b_132b_channel_eq_done_sequence(link, lt_settings);
+		result = dp_perform_128b_132b_channel_eq_done_sequence(link, link_res, lt_settings);
 	if (result == LINK_TRAINING_SUCCESS)
-		result = dp_perform_128b_132b_cds_done_sequence(link, lt_settings);
+		result = dp_perform_128b_132b_cds_done_sequence(link, link_res, lt_settings);
 	return result;
 }
 #endif
+static enum link_training_result dc_link_dp_perform_fixed_vs_pe_training_sequence(
+	struct dc_link *link,
+	const struct link_resource *link_res,
+	struct link_training_settings *lt_settings)
+{
+	const uint8_t vendor_lttpr_write_data_reset[4] = {0x1, 0x50, 0x63, 0xFF};
+	const uint8_t offset = dp_convert_to_count(
+			link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
+	const uint8_t vendor_lttpr_write_data_intercept_en[4] = {0x1, 0x55, 0x63, 0x0};
+	const uint8_t vendor_lttpr_write_data_intercept_dis[4] = {0x1, 0x55, 0x63, 0x68};
+	uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};
+	uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};
+	uint32_t vendor_lttpr_write_address = 0xF004F;
+	enum link_training_result status = LINK_TRAINING_SUCCESS;
+	uint8_t lane = 0;
+	union down_spread_ctrl downspread = {0};
+	union lane_count_set lane_count_set = {0};
+	uint8_t toggle_rate;
+	uint8_t rate;
+	/* Only 8b/10b is supported */
+	ASSERT(dp_get_link_encoding_format(&lt_settings->link_settings) ==
+			DP_8b_10b_ENCODING);
+	if (offset != 0xFF) {
+		vendor_lttpr_write_address +=
+				((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
+	}
+	/* Vendor specific: Reset lane settings */
+	core_link_write_dpcd(
+			link,
+			vendor_lttpr_write_address,
+			&vendor_lttpr_write_data_reset[0],
+			sizeof(vendor_lttpr_write_data_reset));
+	core_link_write_dpcd(
+			link,
+			vendor_lttpr_write_address,
+			&vendor_lttpr_write_data_vs[0],
+			sizeof(vendor_lttpr_write_data_vs));
+	core_link_write_dpcd(
+			link,
+			vendor_lttpr_write_address,
+			&vendor_lttpr_write_data_pe[0],
+			sizeof(vendor_lttpr_write_data_pe));
+	/* Vendor specific: Enable intercept */
+	core_link_write_dpcd(
+			link,
+			vendor_lttpr_write_address,
+			&vendor_lttpr_write_data_intercept_en[0],
+			sizeof(vendor_lttpr_write_data_intercept_en));
+	/* 1. set link rate, lane count and spread. */
+	downspread.raw = (uint8_t)(lt_settings->link_settings.link_spread);
+	lane_count_set.bits.LANE_COUNT_SET =
+	lt_settings->link_settings.lane_count;
+	lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
+	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
+	if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
+		lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
+				link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
+	}
+	core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
+		&downspread.raw, sizeof(downspread));
+	core_link_write_dpcd(link, DP_LANE_COUNT_SET,
+		&lane_count_set.raw, 1);
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	rate = get_dpcd_link_rate(&lt_settings->link_settings);
+#else
+	rate = (uint8_t) (lt_settings->link_settings.link_rate);
+#endif
+	/* Vendor specific: Toggle link rate */
+	toggle_rate = (rate == 0x6) ? 0xA : 0x6;
+	if (link->vendor_specific_lttpr_link_rate_wa == rate) {
+		core_link_write_dpcd(
+				link,
+				DP_LINK_BW_SET,
+				&toggle_rate,
+				1);
+	}
+	link->vendor_specific_lttpr_link_rate_wa = rate;
+	core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
+	DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
+		__func__,
+		DP_LINK_BW_SET,
+		lt_settings->link_settings.link_rate,
+		DP_LANE_COUNT_SET,
+		lt_settings->link_settings.lane_count,
+		lt_settings->enhanced_framing,
+		DP_DOWNSPREAD_CTRL,
+		lt_settings->link_settings.link_spread);
+	/* 2. Perform link training */
+	/* Perform Clock Recovery Sequence */
+	if (status == LINK_TRAINING_SUCCESS) {
+		uint32_t retries_cr;
+		uint32_t retry_count;
+		uint32_t wait_time_microsec;
+		enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
+		union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
+		union lane_align_status_updated dpcd_lane_status_updated;
+		union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
+		retries_cr = 0;
+		retry_count = 0;
+		while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
+			(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
+			memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
+			memset(&dpcd_lane_status_updated, '\0',
+			sizeof(dpcd_lane_status_updated));
+			/* 1. call HWSS to set lane settings */
+			dp_set_hw_lane_settings(
+					link,
+					link_res,
+					lt_settings,
+					0);
+			/* 2. update DPCD of the receiver */
+			if (!retry_count) {
+				/* EPR #361076 - write as a 5-byte burst,
+				 * but only for the 1-st iteration.
+				 */
+				dpcd_set_lt_pattern_and_lane_settings(
+						link,
+						lt_settings,
+						lt_settings->pattern_for_cr,
+						0);
+				/* Vendor specific: Disable intercept */
+				core_link_write_dpcd(
+						link,
+						vendor_lttpr_write_address,
+						&vendor_lttpr_write_data_intercept_dis[0],
+						sizeof(vendor_lttpr_write_data_intercept_dis));
+			} else {
+				vendor_lttpr_write_data_vs[3] = 0;
+				vendor_lttpr_write_data_pe[3] = 0;
+				for (lane = 0; lane < lane_count; lane++) {
+					vendor_lttpr_write_data_vs[3] |=
+							lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET << (2 * lane);
+					vendor_lttpr_write_data_pe[3] |=
+							lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET << (2 * lane);
+				}
+				/* Vendor specific: Update VS and PE to DPRX requested value */
+				core_link_write_dpcd(
+						link,
+						vendor_lttpr_write_address,
+						&vendor_lttpr_write_data_vs[0],
+						sizeof(vendor_lttpr_write_data_vs));
+				core_link_write_dpcd(
+						link,
+						vendor_lttpr_write_address,
+						&vendor_lttpr_write_data_pe[0],
+						sizeof(vendor_lttpr_write_data_pe));
+				dpcd_set_lane_settings(
+						link,
+						lt_settings,
+						0);
+			}
+			/* 3. wait receiver to lock-on*/
+			wait_time_microsec = lt_settings->cr_pattern_time;
+			dp_wait_for_training_aux_rd_interval(
+					link,
+					wait_time_microsec);
+			/* 4. Read lane status and requested drive
+			 * settings as set by the sink
+			 */
+			dp_get_lane_status_and_lane_adjust(
+					link,
+					lt_settings,
+					dpcd_lane_status,
+					&dpcd_lane_status_updated,
+					dpcd_lane_adjust,
+					0);
+			/* 5. check CR done*/
+			if (dp_is_cr_done(lane_count, dpcd_lane_status)) {
+				status = LINK_TRAINING_SUCCESS;
+				break;
+			}
+			/* 6. max VS reached*/
+			if (dp_is_max_vs_reached(lt_settings))
+				break;
+			/* 7. same lane settings */
+			/* Note: settings are the same for all lanes,
+			 * so comparing first lane is sufficient
+			 */
+			if (lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET ==
+					dpcd_lane_adjust[0].bits.VOLTAGE_SWING_LANE)
+				retries_cr++;
+			else
+				retries_cr = 0;
+			/* 8. update VS/PE/PC2 in lt_settings*/
+			dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
+					lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
+			retry_count++;
+		}
+		if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
+			ASSERT(0);
+			DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
+				__func__,
+				LINK_TRAINING_MAX_CR_RETRY);
+		}
+		status = dp_get_cr_failure(lane_count, dpcd_lane_status);
+	}
+	/* Perform Channel EQ Sequence */
+	if (status == LINK_TRAINING_SUCCESS) {
+		enum dc_dp_training_pattern tr_pattern;
+		uint32_t retries_ch_eq;
+		uint32_t wait_time_microsec;
+		enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
+		union lane_align_status_updated dpcd_lane_status_updated = {0};
+		union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
+		union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
+		/* Note: also check that TPS4 is a supported feature*/
+		tr_pattern = lt_settings->pattern_for_eq;
+		dp_set_hw_training_pattern(link, link_res, tr_pattern, 0);
+		status = LINK_TRAINING_EQ_FAIL_EQ;
+		for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
+			retries_ch_eq++) {
+			dp_set_hw_lane_settings(link, link_res, lt_settings, 0);
+			vendor_lttpr_write_data_vs[3] = 0;
+			vendor_lttpr_write_data_pe[3] = 0;
+			for (lane = 0; lane < lane_count; lane++) {
+				vendor_lttpr_write_data_vs[3] |=
+						lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET << (2 * lane);
+				vendor_lttpr_write_data_pe[3] |=
+						lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET << (2 * lane);
+			}
+			/* Vendor specific: Update VS and PE to DPRX requested value */
+			core_link_write_dpcd(
+					link,
+					vendor_lttpr_write_address,
+					&vendor_lttpr_write_data_vs[0],
+					sizeof(vendor_lttpr_write_data_vs));
+			core_link_write_dpcd(
+					link,
+					vendor_lttpr_write_address,
+					&vendor_lttpr_write_data_pe[0],
+					sizeof(vendor_lttpr_write_data_pe));
+			/* 2. update DPCD*/
+			if (!retries_ch_eq)
+				/* EPR #361076 - write as a 5-byte burst,
+				 * but only for the 1-st iteration
+				 */
+				dpcd_set_lt_pattern_and_lane_settings(
+					link,
+					lt_settings,
+					tr_pattern, 0);
+			else
+				dpcd_set_lane_settings(link, lt_settings, 0);
+			/* 3. wait for receiver to lock-on*/
+			wait_time_microsec = lt_settings->eq_pattern_time;
+			dp_wait_for_training_aux_rd_interval(
+					link,
+					wait_time_microsec);
+			/* 4. Read lane status and requested
+			 * drive settings as set by the sink
+			 */
+			dp_get_lane_status_and_lane_adjust(
+				link,
+				lt_settings,
+				dpcd_lane_status,
+				&dpcd_lane_status_updated,
+				dpcd_lane_adjust,
+				0);
+			/* 5. check CR done*/
+			if (!dp_is_cr_done(lane_count, dpcd_lane_status)) {
+				status = LINK_TRAINING_EQ_FAIL_CR;
+				break;
+			}
+			/* 6. check CHEQ done*/
+			if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
+					dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
+					dp_is_interlane_aligned(dpcd_lane_status_updated)) {
+				status = LINK_TRAINING_SUCCESS;
+				break;
+			}
+			/* 7. update VS/PE/PC2 in lt_settings*/
+			dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
+					lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
+		}
+	}
+	return status;
+}
 enum link_training_result dc_link_dp_perform_link_training(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	const struct dc_link_settings *link_settings,
 	bool skip_video_pattern)
 {
 	/* configure link prior to entering training mode */
 	dpcd_configure_lttpr_mode(link, &lt_settings);
-	dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
+	dp_set_fec_ready(link, link_res, lt_settings.should_set_fec_ready);
 	dpcd_configure_channel_coding(link, &lt_settings);
 	/* enter training mode:
 	 * Per DP specs starting from here, DPTX device shall not issue
 	 * Non-LT AUX transactions inside training mode.
 	 */
-	if (encoding == DP_8b_10b_ENCODING)
+	if (!link->dc->debug.apply_vendor_specific_lttpr_wa &&
-		status = dp_perform_8b_10b_link_training(link, &lt_settings);
+			(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
+			link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
+		status = dc_link_dp_perform_fixed_vs_pe_training_sequence(link, link_res, &lt_settings);
+	else if (encoding == DP_8b_10b_ENCODING)
+		status = dp_perform_8b_10b_link_training(link, link_res, &lt_settings);
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	else if (encoding == DP_128b_132b_ENCODING)
-		status = dp_perform_128b_132b_link_training(link, &lt_settings);
+		status = dp_perform_128b_132b_link_training(link, link_res, &lt_settings);
 #endif
 	else
 		ASSERT(0);
 	/* switch to video idle */
 	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
 		status = dp_transition_to_video_idle(link,
+				link_res,
 				&lt_settings,
 				status);
 		dp_enable_link_phy(
 			link,
+			&pipe_ctx->link_res,
 			signal,
 			pipe_ctx->clock_source->id,
 			&current_setting);
 		dp_set_panel_mode(link, panel_mode);
 		if (link->aux_access_disabled) {
-			dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
+			dc_link_dp_perform_link_training_skip_aux(link, &pipe_ctx->link_res, &current_setting);
 			return true;
 		} else {
 			/** @todo Consolidate USB4 DP and DPx.x training. */
 			if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
 				status = dc_link_dpia_perform_link_training(link,
-									    &current_setting,
+						&pipe_ctx->link_res,
-									    skip_video_pattern);
+						&current_setting,
+						skip_video_pattern);
 				/* Transmit idle pattern once training successful. */
 				if (status == LINK_TRAINING_SUCCESS)
-					dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE,
+					dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
-							       NULL, 0);
 			} else {
 				status = dc_link_dp_perform_link_training(link,
-									  &current_setting,
+						&pipe_ctx->link_res,
-									  skip_video_pattern);
+						&current_setting,
+						skip_video_pattern);
 			}
 			if (status == LINK_TRAINING_SUCCESS)
 		DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
 			__func__, (unsigned int)j + 1, attempts);
-		dp_disable_link_phy(link, signal);
+		dp_disable_link_phy(link, &pipe_ctx->link_res, signal);
 		/* Abort link training if failure due to sink being unplugged. */
 		if (status == LINK_TRAINING_ABORT) {
 	return dp_cs_id;
 }
-static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
+static void set_dp_mst_mode(struct dc_link *link, const struct link_resource *link_res,
+		bool mst_enable)
 {
 	if (mst_enable == false &&
 		link->type == dc_connection_mst_branch) {
 		/* Disable MST on link. Use only local sink. */
-		dp_disable_link_phy_mst(link, link->connector_signal);
+		dp_disable_link_phy_mst(link, link_res, link->connector_signal);
 		link->type = dc_connection_single;
 		link->local_sink = link->remote_sinks[0];
 			link->type == dc_connection_single &&
 			link->remote_sinks[0] != NULL) {
 		/* Re-enable MST on link. */
-		dp_disable_link_phy(link, link->connector_signal);
+		dp_disable_link_phy(link, link_res, link->connector_signal);
 		dp_enable_mst_on_sink(link, true);
 		link->type = dc_connection_mst_branch;
 enum link_training_result dc_link_dp_sync_lt_attempt(
     struct dc_link *link,
+    const struct link_resource *link_res,
     struct dc_link_settings *link_settings,
     struct dc_link_training_overrides *lt_overrides)
 {
 			&lt_settings);
 	/* Setup MST Mode */
 	if (lt_overrides->mst_enable)
-		set_dp_mst_mode(link, *lt_overrides->mst_enable);
+		set_dp_mst_mode(link, link_res, *lt_overrides->mst_enable);
 	/* Disable link */
-	dp_disable_link_phy(link, link->connector_signal);
+	dp_disable_link_phy(link, link_res, link->connector_signal);
 	/* Enable link */
 	dp_cs_id = get_clock_source_id(link);
-	dp_enable_link_phy(link, link->connector_signal,
+	dp_enable_link_phy(link, link_res, link->connector_signal,
 		dp_cs_id, link_settings);
 	/* Set FEC enable */
 	if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
 #endif
 		fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
-		dp_set_fec_ready(link, fec_enable);
+		dp_set_fec_ready(link, NULL, fec_enable);
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	}
 #endif
 	/* Attempt to train with given link training settings */
 	if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
-		start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
+		start_clock_recovery_pattern_early(link, link_res, &lt_settings, DPRX);
 	/* Set link rate, lane count and spread. */
 	dpcd_set_link_settings(link, &lt_settings);
 	/* 2. perform link training (set link training done
 	 *  to false is done as well)
 	 */
-	lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
+	lt_status = perform_clock_recovery_sequence(link, link_res, &lt_settings, DPRX);
 	if (lt_status == LINK_TRAINING_SUCCESS) {
 		lt_status = perform_channel_equalization_sequence(link,
+						link_res,
 						&lt_settings,
 						DPRX);
 	}
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 		struct dc_link_settings link_settings = link->cur_link_settings;
 #endif
-		dp_disable_link_phy(link, link->connector_signal);
+		dp_disable_link_phy(link, NULL, link->connector_signal);
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 		if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING)
 #endif
-			dp_set_fec_ready(link, false);
+			dp_set_fec_ready(link, NULL, false);
 	}
 	link->sync_lt_in_progress = false;
 	return false;
 }
-static struct dc_link_settings get_max_link_cap(struct dc_link *link)
+static struct dc_link_settings get_max_link_cap(struct dc_link *link,
+		const struct link_resource *link_res)
 {
 	struct dc_link_settings max_link_cap = {0};
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	if (link_enc)
 		link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-	if (max_link_cap.link_rate >= LINK_RATE_UHBR10 &&
+	if (max_link_cap.link_rate >= LINK_RATE_UHBR10) {
-			!link->hpo_dp_link_enc)
+		if (!link_res->hpo_dp_link_enc ||
-		max_link_cap.link_rate = LINK_RATE_HIGH3;
+				link->dc->debug.disable_uhbr)
+			max_link_cap.link_rate = LINK_RATE_HIGH3;
+	}
 #endif
 	/* Lower link settings based on sink's link cap */
 	 * account for lttpr repeaters cap
 	 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
 	 */
-	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
+	if (link->lttpr_mode != LTTPR_MODE_NON_LTTPR) {
 		if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
 			max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
 bool dp_verify_link_cap(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	struct dc_link_settings *known_limit_link_setting,
 	int *fail_count)
 {
 	/* link training starts with the maximum common settings
 	 * supported by both sink and ASIC.
 	 */
-	max_link_cap = get_max_link_cap(link);
+	max_link_cap = get_max_link_cap(link, link_res);
 	initial_link_settings = get_common_supported_link_settings(
 			*known_limit_link_setting,
 			max_link_cap);
 	 * find the physical link capability
 	 */
 	/* disable PHY done possible by BIOS, will be done by driver itself */
-	dp_disable_link_phy(link, link->connector_signal);
+	dp_disable_link_phy(link, link_res, link->connector_signal);
 	dp_cs_id = get_clock_source_id(link);
 	 */
 	if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C &&
 			link->dc->debug.usbc_combo_phy_reset_wa) {
-		dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
+		dp_enable_link_phy(link, link_res, link->connector_signal, dp_cs_id, cur);
-		dp_disable_link_phy(link, link->connector_signal);
+		dp_disable_link_phy(link, link_res, link->connector_signal);
 	}
 	do {
 		dp_enable_link_phy(
 				link,
+				link_res,
 				link->connector_signal,
 				dp_cs_id,
 				cur);
 		else {
 			status = dc_link_dp_perform_link_training(
 							link,
+							link_res,
 							cur,
 							skip_video_pattern);
 			if (status == LINK_TRAINING_SUCCESS)
 		 * setting or before returning we'll enable it later
 		 * based on the actual mode we're driving
 		 */
-		dp_disable_link_phy(link, link->connector_signal);
+		dp_disable_link_phy(link, link_res, link->connector_signal);
 	} while (!success && decide_fallback_link_setting(link,
 			initial_link_settings, cur, status));
 bool dp_verify_link_cap_with_retries(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	struct dc_link_settings *known_limit_link_setting,
 	int attempts)
 {
 			link->verified_link_cap.link_rate = LINK_RATE_LOW;
 			link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
 			break;
-		} else if (dp_verify_link_cap(link,
+		} else if (dp_verify_link_cap(link, link_res,
 				known_limit_link_setting,
 				&fail_count) && fail_count == 0) {
 			success = true;
 }
 bool dp_verify_mst_link_cap(
-	struct dc_link *link)
+	struct dc_link *link, const struct link_resource *link_res)
 {
 	struct dc_link_settings max_link_cap = {0};
 	if (dp_get_link_encoding_format(&link->reported_link_cap) ==
 			DP_8b_10b_ENCODING) {
-		max_link_cap = get_max_link_cap(link);
+		max_link_cap = get_max_link_cap(link, link_res);
 		link->verified_link_cap = get_common_supported_link_settings(
 				link->reported_link_cap,
 				max_link_cap);
 	else if (dp_get_link_encoding_format(&link->reported_link_cap) ==
 			DP_128b_132b_ENCODING) {
 		dp_verify_link_cap_with_retries(link,
+				link_res,
 				&link->reported_link_cap,
 				LINK_TRAINING_MAX_VERIFY_RETRY);
 	}
 			DP_TEST_PATTERN_VIDEO_MODE) {
 		/* Set CRTC Test Pattern */
 		set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
-		dp_set_hw_test_pattern(link, test_pattern,
+		dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,
 				(uint8_t *)p_custom_pattern,
 				(uint32_t)cust_pattern_size);
 						p_link_settings->dpcd_lane_settings,
 						p_link_settings->link_settings.lane_count);
 			} else {
-				dp_set_hw_lane_settings(link, p_link_settings, DPRX);
+				dp_set_hw_lane_settings(link, &pipe_ctx->link_res, p_link_settings, DPRX);
 				dpcd_set_lane_settings(link, p_link_settings, DPRX);
 			}
 		}
 			pipes->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
 		}
-		dp_set_hw_test_pattern(link, test_pattern,
+		dp_set_hw_test_pattern(link, &pipe_ctx->link_res, test_pattern,
 				(uint8_t *)p_custom_pattern,
 				(uint32_t)cust_pattern_size);
 	return DP_PANEL_MODE_DEFAULT;
 }
-enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
+enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready)
 {
 	/* FEC has to be "set ready" before the link training.
 	 * The policy is to always train with FEC
 bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx)
 {
+	/* If this assert is hit then we have a link encoder dynamic management issue */
+	ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
 	return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
-			pipe_ctx->stream->link->hpo_dp_link_enc &&
+			pipe_ctx->link_res.hpo_dp_link_enc &&
 			dc_is_dp_signal(pipe_ctx->stream->signal));
 }
 #endif

drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c+32−16

  * @param[in] link_setting Lane count, link rate and downspread control.
  * @param[out] lt_settings Link settings and drive settings (voltage swing and pre-emphasis).
  */
-static enum link_training_result dpia_configure_link(struct dc_link *link,
+static enum link_training_result dpia_configure_link(
+		struct dc_link *link,
+		const struct link_resource *link_res,
 		const struct dc_link_settings *link_setting,
 		struct link_training_settings *lt_settings)
 {
 		fec_enable = *link->preferred_training_settings.fec_enable;
 	else
 		fec_enable = true;
-	status = dp_set_fec_ready(link, fec_enable);
+	status = dp_set_fec_ready(link, link_res, fec_enable);
 	if (status != DC_OK && link->is_hpd_pending)
 		return LINK_TRAINING_ABORT;
  * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
  * @param hop The Hop in display path. DPRX = 0.
  */
-static enum link_training_result dpia_training_cr_non_transparent(struct dc_link *link,
+static enum link_training_result dpia_training_cr_non_transparent(
+		struct dc_link *link,
+		const struct link_resource *link_res,
 		struct link_training_settings *lt_settings,
 		uint32_t hop)
 {
  * @param link DPIA link being trained.
  * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
  */
-static enum link_training_result dpia_training_cr_transparent(struct dc_link *link,
+static enum link_training_result dpia_training_cr_transparent(
+		struct dc_link *link,
+		const struct link_resource *link_res,
 		struct link_training_settings *lt_settings)
 {
 	enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
  * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
  * @param hop The Hop in display path. DPRX = 0.
  */
-static enum link_training_result dpia_training_cr_phase(struct dc_link *link,
+static enum link_training_result dpia_training_cr_phase(
+		struct dc_link *link,
+		const struct link_resource *link_res,
 		struct link_training_settings *lt_settings,
 		uint32_t hop)
 {
 	enum link_training_result result = LINK_TRAINING_CR_FAIL_LANE0;
 	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
-		result = dpia_training_cr_non_transparent(link, lt_settings, hop);
+		result = dpia_training_cr_non_transparent(link, link_res, lt_settings, hop);
 	else
-		result = dpia_training_cr_transparent(link, lt_settings);
+		result = dpia_training_cr_transparent(link, link_res, lt_settings);
 	return result;
 }
  * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
  * @param hop The Hop in display path. DPRX = 0.
  */
-static enum link_training_result dpia_training_eq_non_transparent(struct dc_link *link,
+static enum link_training_result dpia_training_eq_non_transparent(
+		struct dc_link *link,
+		const struct link_resource *link_res,
 		struct link_training_settings *lt_settings,
 		uint32_t hop)
 {
  * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
  * @param hop The Hop in display path. DPRX = 0.
  */
-static enum link_training_result dpia_training_eq_transparent(struct dc_link *link,
+static enum link_training_result dpia_training_eq_transparent(
+		struct dc_link *link,
+		const struct link_resource *link_res,
 		struct link_training_settings *lt_settings)
 {
 	enum link_training_result result = LINK_TRAINING_EQ_FAIL_EQ;
  * @param lt_settings link_setting and drive settings (voltage swing and pre-emphasis).
  * @param hop The Hop in display path. DPRX = 0.
  */
-static enum link_training_result dpia_training_eq_phase(struct dc_link *link,
+static enum link_training_result dpia_training_eq_phase(
+		struct dc_link *link,
+		const struct link_resource *link_res,
 		struct link_training_settings *lt_settings,
 		uint32_t hop)
 {
 	enum link_training_result result;
 	if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
-		result = dpia_training_eq_non_transparent(link, lt_settings, hop);
+		result = dpia_training_eq_non_transparent(link, link_res, lt_settings, hop);
 	else
-		result = dpia_training_eq_transparent(link, lt_settings);
+		result = dpia_training_eq_transparent(link, link_res, lt_settings);
 	return result;
 }
 	core_link_send_set_config(link, DPIA_SET_CFG_SET_LINK, data);
 }
-enum link_training_result dc_link_dpia_perform_link_training(struct dc_link *link,
+enum link_training_result dc_link_dpia_perform_link_training(
+	struct dc_link *link,
+	const struct link_resource *link_res,
 	const struct dc_link_settings *link_setting,
 	bool skip_video_pattern)
 {
 	int8_t repeater_id; /* Current hop. */
 	/* Configure link as prescribed in link_setting and set LTTPR mode. */
-	result = dpia_configure_link(link, link_setting, &lt_settings);
+	result = dpia_configure_link(link, link_res, link_setting, &lt_settings);
 	if (result != LINK_TRAINING_SUCCESS)
 		return result;
 	 */
 	for (repeater_id = repeater_cnt; repeater_id >= 0; repeater_id--) {
 		/* Clock recovery. */
-		result = dpia_training_cr_phase(link, &lt_settings, repeater_id);
+		result = dpia_training_cr_phase(link, link_res, &lt_settings, repeater_id);
 		if (result != LINK_TRAINING_SUCCESS)
 			break;
 		/* Equalization. */
-		result = dpia_training_eq_phase(link, &lt_settings, repeater_id);
+		result = dpia_training_eq_phase(link, link_res, &lt_settings, repeater_id);
 		if (result != LINK_TRAINING_SUCCESS)
 			break;

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c+37−26

 void dp_enable_link_phy(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	enum signal_type signal,
 	enum clock_source_id clock_source,
 	const struct dc_link_settings *link_settings)
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
-		enable_dp_hpo_output(link, link_settings);
+		enable_dp_hpo_output(link, link_res, link_settings);
 	} else if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
 		if (dc_is_dp_sst_signal(signal)) {
 			link_enc->funcs->enable_dp_output(
 	return result;
 }
-void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
+void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_res,
+		enum signal_type signal)
 {
 	struct dc  *dc = link->ctx->dc;
 	struct dmcu *dmcu = dc->res_pool->dmcu;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-	struct hpo_dp_link_encoder *hpo_link_enc = link->hpo_dp_link_enc;
+	struct hpo_dp_link_encoder *hpo_link_enc = link_res->hpo_dp_link_enc;
 #endif
 	struct link_encoder *link_enc;
 			link->dc->hwss.edp_backlight_control(link, false);
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 		if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING)
-			disable_dp_hpo_output(link, signal);
+			disable_dp_hpo_output(link, link_res, signal);
 		else
 			link_enc->funcs->disable_output(link_enc, signal);
 #else
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 		if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING &&
 				hpo_link_enc)
-			disable_dp_hpo_output(link, signal);
+			disable_dp_hpo_output(link, link_res, signal);
 		else
 			link_enc->funcs->disable_output(link_enc, signal);
 #else
 		dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
 }
-void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
+void dp_disable_link_phy_mst(struct dc_link *link, const struct link_resource *link_res,
+		enum signal_type signal)
 {
 	/* MST disable link only when no stream use the link */
 	if (link->mst_stream_alloc_table.stream_count > 0)
 		return;
-	dp_disable_link_phy(link, signal);
+	dp_disable_link_phy(link, link_res, signal);
 	/* set the sink to SST mode after disabling the link */
 	dp_enable_mst_on_sink(link, false);
 bool dp_set_hw_training_pattern(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	enum dc_dp_training_pattern pattern,
 	uint32_t offset)
 {
 		break;
 	}
-	dp_set_hw_test_pattern(link, test_pattern, NULL, 0);
+	dp_set_hw_test_pattern(link, link_res, test_pattern, NULL, 0);
 	return true;
 }
 #endif
 void dp_set_hw_lane_settings(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	const struct link_training_settings *link_settings,
 	uint32_t offset)
 {
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	if (dp_get_link_encoding_format(&link_settings->link_settings) ==
 			DP_128b_132b_ENCODING) {
-		link->hpo_dp_link_enc->funcs->set_ffe(
+		link_res->hpo_dp_link_enc->funcs->set_ffe(
-				link->hpo_dp_link_enc,
+				link_res->hpo_dp_link_enc,
 				&link_settings->link_settings,
 				link_settings->lane_settings[0].FFE_PRESET.raw);
 	} else if (dp_get_link_encoding_format(&link_settings->link_settings)
 void dp_set_hw_test_pattern(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	enum dp_test_pattern test_pattern,
 	uint8_t *custom_pattern,
 	uint32_t custom_pattern_size)
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	switch (link_encoding_format) {
 	case DP_128b_132b_ENCODING:
-		link->hpo_dp_link_enc->funcs->set_link_test_pattern(
+		link_res->hpo_dp_link_enc->funcs->set_link_test_pattern(
-				link->hpo_dp_link_enc, &pattern_param);
+				link_res->hpo_dp_link_enc, &pattern_param);
 		break;
 	case DP_8b_10b_ENCODING:
 		ASSERT(encoder);
 					pipes[i].stream_res.stream_enc);
 			/* disable any test pattern that might be active */
-			dp_set_hw_test_pattern(link,
+			dp_set_hw_test_pattern(link, &pipes[i].link_res,
 					DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
 			dp_receiver_power_ctrl(link, false);
 	}
 }
-void enable_dp_hpo_output(struct dc_link *link, const struct dc_link_settings *link_settings)
+void enable_dp_hpo_output(struct dc_link *link,
+		const struct link_resource *link_res,
+		const struct dc_link_settings *link_settings)
 {
 	const struct dc *dc = link->dc;
 	enum phyd32clk_clock_source phyd32clk;
 		}
 	} else {
 		/* DP2.0 HW: call transmitter control to enable PHY */
-		link->hpo_dp_link_enc->funcs->enable_link_phy(
+		link_res->hpo_dp_link_enc->funcs->enable_link_phy(
-				link->hpo_dp_link_enc,
+				link_res->hpo_dp_link_enc,
 				link_settings,
-				link->link_enc->transmitter);
+				link->link_enc->transmitter,
+				link->link_enc->hpd_source);
 	}
 	/* DCCG muxing and DTBCLK DTO */
 		phyd32clk = get_phyd32clk_src(link);
 		dc->res_pool->dccg->funcs->enable_symclk32_le(
 				dc->res_pool->dccg,
-				link->hpo_dp_link_enc->inst,
+				link_res->hpo_dp_link_enc->inst,
 				phyd32clk);
-		link->hpo_dp_link_enc->funcs->link_enable(
+		link_res->hpo_dp_link_enc->funcs->link_enable(
-					link->hpo_dp_link_enc,
+				link_res->hpo_dp_link_enc,
-					link_settings->lane_count);
+				link_settings->lane_count);
 	}
 }
-void disable_dp_hpo_output(struct dc_link *link, enum signal_type signal)
+void disable_dp_hpo_output(struct dc_link *link,
+		const struct link_resource *link_res,
+		enum signal_type signal)
 {
 	const struct dc *dc = link->dc;
-	link->hpo_dp_link_enc->funcs->link_disable(link->hpo_dp_link_enc);
+	link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc);
 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 		dc->res_pool->dccg->funcs->disable_symclk32_le(
 					dc->res_pool->dccg,
-					link->hpo_dp_link_enc->inst);
+					link_res->hpo_dp_link_enc->inst);
 		dc->res_pool->dccg->funcs->set_physymclk(
 					dc->res_pool->dccg,
 		dm_set_phyd32clk(dc->ctx, 0);
 	} else {
 		/* DP2.0 HW: call transmitter control to disable PHY */
-		link->hpo_dp_link_enc->funcs->disable_link_phy(
+		link_res->hpo_dp_link_enc->funcs->disable_link_phy(
-				link->hpo_dp_link_enc,
+				link_res->hpo_dp_link_enc,
 				signal);
 	}
 }

drivers/gpu/drm/amd/display/dc/core/dc_resource.c+127−72

@@ -734,10 +734,6 @@ static void calculate_split_count_and_index(struct pipe_ctx pipe_ctx, int spli · 733 unmodified lines
734	(*split_idx)++;	734	(*split_idx)++;
735	split_pipe = split_pipe->top_pipe;	735	split_pipe = split_pipe->top_pipe;
736	}	736	}
737
738	/* MPO window on right side of ODM split */
739	if (split_pipe && split_pipe->prev_odm_pipe && !pipe_ctx->prev_odm_pipe)
740	(*split_idx)++;
741	} else {	737	} else {
742	/Get odm split index/	738	/Get odm split index/
743	struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;	739	struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
@@ -784,11 +780,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) · 40 unmodified lines
784	/*	780	/*
785	* Only the leftmost ODM pipe should be offset by a nonzero distance	781	* Only the leftmost ODM pipe should be offset by a nonzero distance
786	*/	782	*/
787	if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->prev_odm_pipe && !pipe_ctx->prev_odm_pipe) {	783	if (!pipe_ctx->prev_odm_pipe \|\| split_idx == split_count) {
788	/* MPO window on right side of ODM split */
789	data->recout.x = stream->dst.x + (surf_clip.x - stream->dst.width/2) *
790	stream->dst.width / stream->src.width;
791	} else if (!pipe_ctx->prev_odm_pipe \|\| split_idx == split_count) {
792	data->recout.x = stream->dst.x;	784	data->recout.x = stream->dst.x;
793	if (stream->src.x < surf_clip.x)	785	if (stream->src.x < surf_clip.x)
794	data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width	786	data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
@@ -986,8 +978,6 @@ static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx) · 191 unmodified lines
986	* stream->dst.height / stream->src.height;	978	* stream->dst.height / stream->src.height;
987	if (pipe_ctx->prev_odm_pipe && split_idx)	979	if (pipe_ctx->prev_odm_pipe && split_idx)
988	ro_lb = data->h_active * split_idx - recout_full_x;	980	ro_lb = data->h_active * split_idx - recout_full_x;
989	else if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->prev_odm_pipe)
990	ro_lb = data->h_active * split_idx - recout_full_x + data->recout.x;
991	else	981	else
992	ro_lb = data->recout.x - recout_full_x;	982	ro_lb = data->recout.x - recout_full_x;
993	ro_tb = data->recout.y - recout_full_y;	983	ro_tb = data->recout.y - recout_full_y;
@@ -1086,9 +1076,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 92 unmodified lines
1086	timing->v_border_top + timing->v_border_bottom;	1076	timing->v_border_top + timing->v_border_bottom;
1087	if (pipe_ctx->next_odm_pipe \|\| pipe_ctx->prev_odm_pipe)	1077	if (pipe_ctx->next_odm_pipe \|\| pipe_ctx->prev_odm_pipe)
1088	pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;	1078	pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
1089	/* ODM + windows MPO, where window is on either right or left ODM half */
1090	else if (pipe_ctx->top_pipe && (pipe_ctx->top_pipe->next_odm_pipe \|\| pipe_ctx->top_pipe->prev_odm_pipe))
1091	pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx->top_pipe) + 1;
1092		1079
1093	/* depends on h_active */	1080	/* depends on h_active */
1094	calculate_recout(pipe_ctx);	1081	calculate_recout(pipe_ctx);
@@ -1097,6 +1084,11 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) · 2 unmodified lines
1097	/* depends on scaling ratios and recout, does not calculate offset yet */	1084	/* depends on scaling ratios and recout, does not calculate offset yet */
1098	calculate_viewport_size(pipe_ctx);	1085	calculate_viewport_size(pipe_ctx);
1099		1086
		1087	/* Stopgap for validation of ODM + MPO on one side of screen case */
		1088	if (pipe_ctx->plane_res.scl_data.viewport.height < 1 \|\|
		1089	pipe_ctx->plane_res.scl_data.viewport.width < 1)
		1090	return false;
		1091
1100	/*	1092	/*
1101	* LB calculations depend on vp size, h/v_active and scaling ratios	1093	* LB calculations depend on vp size, h/v_active and scaling ratios
1102	* Setting line buffer pixel depth to 24bpp yields banding	1094	* Setting line buffer pixel depth to 24bpp yields banding
@@ -1445,54 +1437,23 @@ bool dc_add_plane_to_context( · 342 unmodified lines
1445	if (head_pipe != free_pipe) {	1437	if (head_pipe != free_pipe) {
1446	tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);	1438	tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1447	ASSERT(tail_pipe);	1439	ASSERT(tail_pipe);
1448		1440	free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1449	/* ODM + window MPO, where MPO window is on right half only */	1441	free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1450	if (free_pipe->plane_state &&	1442	free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1451	(free_pipe->plane_state->clip_rect.x >= free_pipe->stream->src.width/2) &&	1443	free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1452	tail_pipe->next_odm_pipe) {	1444	free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1453	free_pipe->stream_res.tg = tail_pipe->next_odm_pipe->stream_res.tg;	1445	free_pipe->clock_source = tail_pipe->clock_source;
1454	free_pipe->stream_res.abm = tail_pipe->next_odm_pipe->stream_res.abm;	1446	free_pipe->top_pipe = tail_pipe;
1455	free_pipe->stream_res.opp = tail_pipe->next_odm_pipe->stream_res.opp;	1447	tail_pipe->bottom_pipe = free_pipe;
1456	free_pipe->stream_res.stream_enc = tail_pipe->next_odm_pipe->stream_res.stream_enc;	1448	if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
1457	free_pipe->stream_res.audio = tail_pipe->next_odm_pipe->stream_res.audio;	1449	free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe;
1458	free_pipe->clock_source = tail_pipe->next_odm_pipe->clock_source;	1450	tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe;
1459		1451	}
1460	free_pipe->top_pipe = tail_pipe->next_odm_pipe;	1452	if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) {
1461	tail_pipe->next_odm_pipe->bottom_pipe = free_pipe;	1453	free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
1462	} else {	1454	tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe;
1463	free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1464	free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1465	free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1466	free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1467	free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1468	free_pipe->clock_source = tail_pipe->clock_source;
1469
1470	free_pipe->top_pipe = tail_pipe;
1471	tail_pipe->bottom_pipe = free_pipe;
1472
1473	if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
1474	free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe;
1475	tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe;
1476	}
1477	if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) {
1478	free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
1479	tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe;
1480	}
1481	}	1455	}
1482	}	1456	}
1483
1484	/* ODM + window MPO, where MPO window is on left half only */
1485	if (free_pipe->plane_state &&
1486	(free_pipe->plane_state->clip_rect.x + free_pipe->plane_state->clip_rect.width <=
1487	free_pipe->stream->src.x + free_pipe->stream->src.width/2)) {
1488	break;
1489	}
1490	/* ODM + window MPO, where MPO window is on right half only */
1491	if (free_pipe->plane_state &&
1492	(free_pipe->plane_state->clip_rect.x >= free_pipe->stream->src.width/2)) {
1493	break;
1494	}
1495
1496	head_pipe = head_pipe->next_odm_pipe;	1457	head_pipe = head_pipe->next_odm_pipe;
1497	}	1458	}
1498	/* assign new surfaces*/	1459	/* assign new surfaces*/
@@ -1763,6 +1724,94 @@ static void update_hpo_dp_stream_engine_usage( · 264 unmodified lines
1763	res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;	1724	res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;
1764	}	1725	}
1765	}	1726	}
		1727
		1728	static inline int find_acquired_hpo_dp_link_enc_for_link(
		1729	const struct resource_context *res_ctx,
		1730	const struct dc_link *link)
		1731	{
		1732	int i;
		1733
		1734	for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)
		1735	if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 &&
		1736	res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index)
		1737	return i;
		1738
		1739	return -1;
		1740	}
		1741
		1742	static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx,
		1743	const struct resource_pool *pool)
		1744	{
		1745	int i;
		1746
		1747	for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)
		1748	if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0)
		1749	break;
		1750
		1751	return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&
		1752	i < pool->hpo_dp_link_enc_count) ? i : -1;
		1753	}
		1754
		1755	static inline void acquire_hpo_dp_link_enc(
		1756	struct resource_context *res_ctx,
		1757	unsigned int link_index,
		1758	int enc_index)
		1759	{
		1760	res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index;
		1761	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1;
		1762	}
		1763
		1764	static inline void retain_hpo_dp_link_enc(
		1765	struct resource_context *res_ctx,
		1766	int enc_index)
		1767	{
		1768	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
		1769	}
		1770
		1771	static inline void release_hpo_dp_link_enc(
		1772	struct resource_context *res_ctx,
		1773	int enc_index)
		1774	{
		1775	ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
		1776	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
		1777	}
		1778
		1779	static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
		1780	const struct resource_pool *pool,
		1781	struct pipe_ctx *pipe_ctx,
		1782	struct dc_stream_state *stream)
		1783	{
		1784	int enc_index;
		1785
		1786	enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
		1787
		1788	if (enc_index >= 0) {
		1789	retain_hpo_dp_link_enc(res_ctx, enc_index);
		1790	} else {
		1791	enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
		1792	if (enc_index >= 0)
		1793	acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index);
		1794	}
		1795
		1796	if (enc_index >= 0)
		1797	pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
		1798
		1799	return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
		1800	}
		1801
		1802	static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
		1803	struct pipe_ctx *pipe_ctx,
		1804	struct dc_stream_state *stream)
		1805	{
		1806	int enc_index;
		1807
		1808	enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
		1809
		1810	if (enc_index >= 0) {
		1811	release_hpo_dp_link_enc(res_ctx, enc_index);
		1812	pipe_ctx->link_res.hpo_dp_link_enc = NULL;
		1813	}
		1814	}
1766	#endif	1815	#endif
1767		1816
1768	/* TODO: release audio object */	1817	/* TODO: release audio object */
@@ -1925,6 +1974,7 @@ enum dc_status dc_remove_stream_from_ctx( · 156 unmodified lines
1925	&new_ctx->res_ctx, dc->res_pool,	1974	&new_ctx->res_ctx, dc->res_pool,
1926	del_pipe->stream_res.hpo_dp_stream_enc,	1975	del_pipe->stream_res.hpo_dp_stream_enc,
1927	false);	1976	false);
		1977	remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
1928	}	1978	}
1929	#endif	1979	#endif
1930		1980
@@ -2200,6 +2250,8 @@ enum dc_status resource_map_pool_resources( · 269 unmodified lines
2200	&context->res_ctx, pool,	2250	&context->res_ctx, pool,
2201	pipe_ctx->stream_res.hpo_dp_stream_enc,	2251	pipe_ctx->stream_res.hpo_dp_stream_enc,
2202	true);	2252	true);
		2253	if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))
		2254	return DC_NO_LINK_ENC_RESOURCE;
2203	}	2255	}
2204	}	2256	}
2205	#endif	2257	#endif
@@ -2875,6 +2927,8 @@ bool pipe_need_reprogram( · 669 unmodified lines
2875	#if defined(CONFIG_DRM_AMD_DC_DCN)	2927	#if defined(CONFIG_DRM_AMD_DC_DCN)
2876	if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)	2928	if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)
2877	return true;	2929	return true;
		2930	if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)
		2931	return true;
2878	#endif	2932	#endif
2879		2933
2880	/* DIG link encoder resource assignment for stream changed. */	2934	/* DIG link encoder resource assignment for stream changed. */
@@ -3143,22 +3197,23 @@ void get_audio_check(struct audio_info *aud_modes, · 262 unmodified lines
3143	}	3197	}
3144		3198
3145	#if defined(CONFIG_DRM_AMD_DC_DCN)	3199	#if defined(CONFIG_DRM_AMD_DC_DCN)
3146	struct hpo_dp_link_encoder *resource_get_unused_hpo_dp_link_encoder(	3200	struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
3147	const struct resource_pool *pool)	3201	const struct resource_context *res_ctx,
		3202	const struct resource_pool *pool,
		3203	const struct dc_link *link)
3148	{	3204	{
3149	uint8_t i;	3205	struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL;
3150	struct hpo_dp_link_encoder *enc = NULL;	3206	int enc_index;
3151		3207
3152	ASSERT(pool->hpo_dp_link_enc_count <= MAX_HPO_DP2_LINK_ENCODERS);	3208	enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link);
3153		3209
3154	for (i = 0; i < pool->hpo_dp_link_enc_count; i++) {	3210	if (enc_index < 0)
3155	if (pool->hpo_dp_link_enc[i]->transmitter == TRANSMITTER_UNKNOWN) {	3211	enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
3156	enc = pool->hpo_dp_link_enc[i];	3212
3157	break;	3213	if (enc_index >= 0)
3158	}	3214	hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
3159	}
3160		3215
3161	return enc;	3216	return hpo_dp_link_enc;
3162	}	3217	}
3163	#endif	3218	#endif
3164		3219

drivers/gpu/drm/amd/display/dc/dc.h+2−1

 struct set_config_cmd_payload;
 struct dmub_notification;
-#define DC_VER "3.2.166"
+#define DC_VER "3.2.167"
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
 	/* TODO - remove once tested */
 	bool legacy_dp2_lt;
 	bool set_mst_en_for_sst;
+	bool disable_uhbr;
 	bool force_dp2_lt_fallback_method;
 #endif
 	union mem_low_power_enable_options enable_mem_low_power;

drivers/gpu/drm/amd/display/dc/dc_link.h+12−3

 #include "dc_types.h"
 #include "grph_object_defs.h"
+struct link_resource;
 enum dc_link_fec_state {
 	dc_link_fec_not_ready,
 	dc_link_fec_ready,
 	struct panel_cntl *panel_cntl;
 	struct link_encoder *link_enc;
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-	struct hpo_dp_link_encoder *hpo_dp_link_enc;
-#endif
 	struct graphics_object_id link_id;
 	/* Endpoint type distinguishes display endpoints which do not have entries
 	 * in the BIOS connector table from those that do. Helps when tracking link
 void dc_link_dp_set_drive_settings(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	struct link_training_settings *lt_settings);
 bool dc_link_dp_perform_link_training_skip_aux(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	const struct dc_link_settings *link_setting);
 enum link_training_result dc_link_dp_perform_link_training(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	const struct dc_link_settings *link_settings,
 	bool skip_video_pattern);
 enum link_training_result dc_link_dp_sync_lt_attempt(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	struct dc_link_settings *link_setting,
 	struct dc_link_training_overrides *lt_settings);
 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw);
 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(const struct dc_link *link);
 #endif
+const struct link_resource *dc_link_get_cur_link_res(const struct dc_link *link);
+/* take a snapshot of current link resource allocation state */
+void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
+/* restore link resource allocation state from a snapshot */
+void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
 #endif /* DC_LINK_H_ */

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c+4−10

 	log_mpc_crc(dc, log_ctx);
 	{
-		int hpo_dp_link_enc_count = 0;
 		if (pool->hpo_dp_stream_enc_count > 0) {
 			DTN_INFO("DP HPO S_ENC:  Enabled  OTG   Format   Depth   Vid   SDP   Compressed  Link\n");
 			for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
 		}
 		/* log DP HPO L_ENC section if any hpo_dp_link_enc exists */
-		for (i = 0; i < dc->link_count; i++)
+		if (pool->hpo_dp_link_enc_count) {
-			if (dc->links[i]->hpo_dp_link_enc)
-				hpo_dp_link_enc_count++;
-		if (hpo_dp_link_enc_count) {
 			DTN_INFO("DP HPO L_ENC:  Enabled  Mode   Lanes   Stream  Slots   VC Rate X    VC Rate Y\n");
-			for (i = 0; i < dc->link_count; i++) {
+			for (i = 0; i < pool->hpo_dp_link_enc_count; i++) {
-				struct hpo_dp_link_encoder *hpo_dp_link_enc = dc->links[i]->hpo_dp_link_enc;
+				struct hpo_dp_link_encoder *hpo_dp_link_enc = pool->hpo_dp_link_enc[i];
 				struct hpo_dp_link_enc_state hpo_dp_le_state = {0};
-				if (hpo_dp_link_enc && hpo_dp_link_enc->funcs->read_state) {
+				if (hpo_dp_link_enc->funcs->read_state) {
 					hpo_dp_link_enc->funcs->read_state(hpo_dp_link_enc, &hpo_dp_le_state);
 					DTN_INFO("[%d]:                 %d  %6s     %d        %d      %d     %d     %d\n",
 							hpo_dp_link_enc->inst,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c+1−0

@@ -78,6 +78,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { · 77 unmodified lines
78	.get_clock = dcn10_get_clock,	78	.get_clock = dcn10_get_clock,
79	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,	79	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
80	.calc_vupdate_position = dcn10_calc_vupdate_position,	80	.calc_vupdate_position = dcn10_calc_vupdate_position,
		81	.power_down = dce110_power_down,
81	.set_backlight_level = dce110_set_backlight_level,	82	.set_backlight_level = dce110_set_backlight_level,
82	.set_abm_immediate_disable = dce110_set_abm_immediate_disable,	83	.set_abm_immediate_disable = dce110_set_abm_immediate_disable,
83	.set_pipe = dce110_set_pipe,	84	.set_pipe = dce110_set_pipe,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c+1−1

@@ -2414,7 +2414,7 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) · 2413 unmodified lines
2414	pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->map_stream_to_link(	2414	pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->map_stream_to_link(
2415	pipe_ctx->stream_res.hpo_dp_stream_enc,	2415	pipe_ctx->stream_res.hpo_dp_stream_enc,
2416	pipe_ctx->stream_res.hpo_dp_stream_enc->inst,	2416	pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
2417	link->hpo_dp_link_enc->inst);	2417	pipe_ctx->link_res.hpo_dp_link_enc->inst);
2418	}	2418	}
2419		2419
2420	if (!is_dp_128b_132b_signal(pipe_ctx) && link_enc)	2420	if (!is_dp_128b_132b_signal(pipe_ctx) && link_enc)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c+2−3

 		.timing_trace = false,
 		.clock_trace = true,
 		.disable_pplib_clock_request = true,
-		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
 		.force_single_disp_pipe_split = false,
 		.disable_dcc = DCC_ENABLE,
 		.vsr_support = true,
 	else if (context->stream_count == 1 &&  context->streams[0]->signal == SIGNAL_TYPE_EDP) {
 		struct dc_link *link = context->streams[0]->sink->link;
-		if ((link->link_index == 0 && link->psr_settings.psr_feature_enabled)
+		if (link->link_index == 0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
-				|| context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
 			return DCN_ZSTATE_SUPPORT_ALLOW;
 		else
 			return DCN_ZSTATE_SUPPORT_DISALLOW;

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c+2−1

 	PHYSICAL_ADDRESS_LOC addr;
 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 	struct dce_hwseq *hws = dc->hwseq;
-	struct dc_plane_address uma = plane_state->address;
+	struct dc_plane_address uma;
 	if (plane_state == NULL)
 		return;
+	uma = plane_state->address;
 	addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
 	plane_address_in_gpu_space_to_uma(hws, &uma);

drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c+1−1

@@ -603,7 +603,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 602 unmodified lines
603	.timing_trace = false,	603	.timing_trace = false,
604	.clock_trace = true,	604	.clock_trace = true,
605	.disable_pplib_clock_request = true,	605	.disable_pplib_clock_request = true,
606	.pipe_split_policy = MPC_SPLIT_AVOID,	606	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
607	.force_single_disp_pipe_split = false,	607	.force_single_disp_pipe_split = false,
608	.disable_dcc = DCC_ENABLE,	608	.disable_dcc = DCC_ENABLE,
609	.vsr_support = true,	609	.vsr_support = true,

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c+1−1

@@ -873,7 +873,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 872 unmodified lines
873	.clock_trace = true,	873	.clock_trace = true,
874	.disable_pplib_clock_request = true,	874	.disable_pplib_clock_request = true,
875	.min_disp_clk_khz = 100000,	875	.min_disp_clk_khz = 100000,
876	.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,	876	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
877	.force_single_disp_pipe_split = false,	877	.force_single_disp_pipe_split = false,
878	.disable_dcc = DCC_ENABLE,	878	.disable_dcc = DCC_ENABLE,
879	.vsr_support = true,	879	.vsr_support = true,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c+1−12

 	.timing_trace = false,
 	.clock_trace = true,
 	.disable_pplib_clock_request = true,
-	.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
 	.force_single_disp_pipe_split = false,
 	.disable_dcc = DCC_ENABLE,
 	.vsr_support = true,
 	int pipe_idx = sec_pipe->pipe_idx;
 	const struct resource_pool *pool = dc->res_pool;
-	if (pri_pipe->plane_state) {
-		/* ODM + window MPO, where MPO window is on left half only */
-		if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
-				pri_pipe->stream->src.x + pri_pipe->stream->src.width/2)
-			return true;
-		/* ODM + window MPO, where MPO window is on right half only */
-		if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.width/2)
-			return true;
-	}
 	*sec_pipe = *pri_pipe;
 	sec_pipe->pipe_idx = pipe_idx;

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c+1−1

@@ -686,7 +686,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 685 unmodified lines
686	.disable_clock_gate = true,	686	.disable_clock_gate = true,
687	.disable_pplib_clock_request = true,	687	.disable_pplib_clock_request = true,
688	.disable_pplib_wm_range = true,	688	.disable_pplib_wm_range = true,
689	.pipe_split_policy = MPC_SPLIT_AVOID,	689	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
690	.force_single_disp_pipe_split = false,	690	.force_single_disp_pipe_split = false,
691	.disable_dcc = DCC_ENABLE,	691	.disable_dcc = DCC_ENABLE,
692	.vsr_support = true,	692	.vsr_support = true,

drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c+1−1

@@ -211,7 +211,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 210 unmodified lines
211	.timing_trace = false,	211	.timing_trace = false,
212	.clock_trace = true,	212	.clock_trace = true,
213	.disable_pplib_clock_request = true,	213	.disable_pplib_clock_request = true,
214	.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,	214	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
215	.force_single_disp_pipe_split = false,	215	.force_single_disp_pipe_split = false,
216	.disable_dcc = DCC_ENABLE,	216	.disable_dcc = DCC_ENABLE,
217	.vsr_support = true,	217	.vsr_support = true,

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h+18−2

@@ -15,7 +15,11 @@ · 14 unmodified lines
15	SR(DPPCLK_DTO_CTRL),\	15	SR(DPPCLK_DTO_CTRL),\
16	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\	16	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
17	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\	17	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
18	SR(REFCLK_CNTL)	18	SR(REFCLK_CNTL),\
		19	SR(DISPCLK_FREQ_CHANGE_CNTL),\
		20	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
		21	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1)
		22
19		23
20	#define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \	24	#define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \
21	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\	25	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
@@ -25,6 +29,18 @@ · 3 unmodified lines
25	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\	29	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
26	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\	30	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
27	DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\	31	DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
28	DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)	32	DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
		33	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
		34	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
		35	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
		36	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
		37	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
		38	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
		39	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
		40	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
		41	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
		42	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
		43	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
		44	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
29		45
30	#endif //__DCN303_DCCG_H__	46	#endif //__DCN303_DCCG_H__

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c+1−1

@@ -193,7 +193,7 @@ static const struct dc_debug_options debug_defaults_drv = { · 192 unmodified lines
193	.timing_trace = false,	193	.timing_trace = false,
194	.clock_trace = true,	194	.clock_trace = true,
195	.disable_pplib_clock_request = true,	195	.disable_pplib_clock_request = true,
196	.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,	196	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
197	.force_single_disp_pipe_split = false,	197	.force_single_disp_pipe_split = false,
198	.disable_dcc = DCC_ENABLE,	198	.disable_dcc = DCC_ENABLE,
199	.vsr_support = true,	199	.vsr_support = true,

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c+5−1

 void dcn31_hpo_dp_link_enc_enable_dp_output(
 	struct hpo_dp_link_encoder *enc,
 	const struct dc_link_settings *link_settings,
-	enum transmitter transmitter)
+	enum transmitter transmitter,
+	enum hpd_source_id hpd_source)
 {
 	struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
 	struct bp_transmitter_control cntl = { 0 };
 	/* Set the transmitter */
 	enc3->base.transmitter = transmitter;
+	/* Set the hpd source */
+	enc3->base.hpd_source = hpd_source;
 	/* Enable the PHY */
 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
 	cntl.engine_id = ENGINE_ID_UNKNOWN;

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.h+2−1

@@ -184,7 +184,8 @@ void hpo_dp_link_encoder31_construct(struct dcn31_hpo_dp_link_encoder *enc31, · 183 unmodified lines
184	void dcn31_hpo_dp_link_enc_enable_dp_output(	184	void dcn31_hpo_dp_link_enc_enable_dp_output(
185	struct hpo_dp_link_encoder *enc,	185	struct hpo_dp_link_encoder *enc,
186	const struct dc_link_settings *link_settings,	186	const struct dc_link_settings *link_settings,
187	enum transmitter transmitter);	187	enum transmitter transmitter,
		188	enum hpd_source_id hpd_source);
188		189
189	void dcn31_hpo_dp_link_enc_disable_output(	190	void dcn31_hpo_dp_link_enc_disable_output(
190	struct hpo_dp_link_encoder *enc,	191	struct hpo_dp_link_encoder *enc,

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c+1−0

@@ -103,6 +103,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = { · 102 unmodified lines
103	.z10_restore = dcn31_z10_restore,	103	.z10_restore = dcn31_z10_restore,
104	.z10_save_init = dcn31_z10_save_init,	104	.z10_save_init = dcn31_z10_save_init,
105	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,	105	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
		106	.optimize_pwr_state = dcn21_optimize_pwr_state,
106	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,	107	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
107	.update_visual_confirm_color = dcn20_update_visual_confirm_color,	108	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
108	};	109	};

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c+24−3

 	clk_src_regs(3, D),
 	clk_src_regs(4, E)
 };
+/*pll_id being rempped in dmub, in driver it is logical instance*/
+static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
+	clk_src_regs(0, A),
+	clk_src_regs(1, B),
+	clk_src_regs(2, F),
+	clk_src_regs(3, G),
+	clk_src_regs(4, E)
+};
 static const struct dce110_clk_src_shift cs_shift = {
 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 	.timing_trace = false,
 	.clock_trace = true,
 	.disable_pplib_clock_request = false,
-	.pipe_split_policy = MPC_SPLIT_AVOID,
+	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
 	.force_single_disp_pipe_split = false,
 	.disable_dcc = DCC_ENABLE,
 	.vsr_support = true,
 			dcn30_clock_source_create(ctx, ctx->dc_bios,
 				CLOCK_SOURCE_COMBO_PHY_PLL1,
 				&clk_src_regs[1], false);
-	pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
+	/*move phypllx_pixclk_resync to dmub next*/
+	if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
+		pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL2,
+				&clk_src_regs_b0[2], false);
+		pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL3,
+				&clk_src_regs_b0[3], false);
+	} else {
+		pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
 			dcn30_clock_source_create(ctx, ctx->dc_bios,
 				CLOCK_SOURCE_COMBO_PHY_PLL2,
 				&clk_src_regs[2], false);
-	pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
+		pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
 			dcn30_clock_source_create(ctx, ctx->dc_bios,
 				CLOCK_SOURCE_COMBO_PHY_PLL3,
 				&clk_src_regs[3], false);
+	}
 	pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
 			dcn30_clock_source_create(ctx, ctx->dc_bios,
 				CLOCK_SOURCE_COMBO_PHY_PLL4,

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h+31−0

@@ -49,4 +49,35 @@ struct resource_pool *dcn31_create_resource_pool( · 48 unmodified lines
49	const struct dc_init_data *init_data,	49	const struct dc_init_data *init_data,
50	struct dc *dc);	50	struct dc *dc);
51		51
		52	/temp: B0 specific before switch to dcn313 headers/
		53	#ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL
		54	#define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
		55	#define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
		56	#define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
		57	#define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
		58
		59	//PHYPLLF_PIXCLK_RESYNC_CNTL
		60	#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
		61	#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
		62	#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
		63	#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8
		64	#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
		65	#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
		66	#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
		67	#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
		68	#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L
		69	#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
		70
		71	//PHYPLLG_PIXCLK_RESYNC_CNTL
		72	#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
		73	#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
		74	#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
		75	#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8
		76	#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
		77	#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
		78	#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
		79	#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
		80	#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L
		81	#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
		82	#endif
52	#endif /* _DCN31_RESOURCE_H_ */	83	#endif /* _DCN31_RESOURCE_H_ */

drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c+1−1

@@ -1274,7 +1274,7 @@ static void dcn20_adjust_adaptive_sync_v_startup( · 1273 unmodified lines
1274	static bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx)	1274	static bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx)
1275	{	1275	{
1276	return (pipe_ctx->stream_res.hpo_dp_stream_enc &&	1276	return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
1277	pipe_ctx->stream->link->hpo_dp_link_enc &&	1277	pipe_ctx->link_res.hpo_dp_link_enc &&
1278	dc_is_dp_signal(pipe_ctx->stream->signal));	1278	dc_is_dp_signal(pipe_ctx->stream->signal));
1279	}	1279	}
1280		1280

drivers/gpu/drm/amd/display/dc/inc/core_status.h+2−0

@@ -53,6 +53,8 @@ enum dc_status { · 52 unmodified lines
53	DC_NOT_SUPPORTED = 24,	53	DC_NOT_SUPPORTED = 24,
54	DC_UNSUPPORTED_VALUE = 25,	54	DC_UNSUPPORTED_VALUE = 25,
55		55
		56	DC_NO_LINK_ENC_RESOURCE = 26,
		57
56	DC_ERROR_UNEXPECTED = -1	58	DC_ERROR_UNEXPECTED = -1
57	};	59	};
58		60

drivers/gpu/drm/amd/display/dc/inc/core_types.h+17−0

 	struct dcn_fe_bandwidth bw;
 };
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+#define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF
+#define LINK_RES_HPO_DP_REC_MAP__SHIFT 0
+#endif
+/* all mappable hardware resources used to enable a link */
+struct link_resource {
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	struct hpo_dp_link_encoder *hpo_dp_link_enc;
+#else
+	void *dummy;
+#endif
+};
 union pipe_update_flags {
 	struct {
 		uint32_t enable : 1;
 	struct plane_resource plane_res;
 	struct stream_resource stream_res;
+	struct link_resource link_res;
 	struct clock_source *clock_source;
 	struct link_enc_cfg_context link_enc_cfg_ctx;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
+	unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];
+	int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];
 #endif
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool is_mpc_3dlut_acquired[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h+11−4

 bool dp_verify_link_cap(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	struct dc_link_settings *known_limit_link_setting,
 	int *fail_count);
 bool dp_verify_link_cap_with_retries(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	struct dc_link_settings *known_limit_link_setting,
 	int attempts);
 bool dp_verify_mst_link_cap(
-	struct dc_link *link);
+	struct dc_link *link,
+	const struct link_resource *link_res);
 bool dp_validate_mode_timing(
 	struct dc_link *link,
 	struct dc_link *link,
 	enum dc_dp_training_pattern pattern);
-enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready);
+enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready);
 void dp_set_fec_enable(struct dc_link *link, bool enable);
 struct link_encoder *dp_get_link_enc(struct dc_link *link);
 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
 struct fixed31_32 calculate_sst_avg_time_slots_per_mtp(
 		const struct dc_stream_state *stream,
 		const struct dc_link *link);
-void enable_dp_hpo_output(struct dc_link *link, const struct dc_link_settings *link_settings);
+void enable_dp_hpo_output(struct dc_link *link,
-void disable_dp_hpo_output(struct dc_link *link, enum signal_type signal);
+		const struct link_resource *link_res,
+		const struct dc_link_settings *link_settings);
+void disable_dp_hpo_output(struct dc_link *link,
+		const struct link_resource *link_res,
+		enum signal_type signal);
 void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable);
 bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx);
 void reset_dp_hpo_stream_encoders_for_link(struct dc_link *link);

drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h+3−2

  * DPIA equivalent of dc_link_dp_perfrorm_link_training.
  * Aborts link training upon detection of sink unplug.
  */
-enum link_training_result
+enum link_training_result dc_link_dpia_perform_link_training(
-dc_link_dpia_perform_link_training(struct dc_link *link,
+	struct dc_link *link,
+	const struct link_resource *link_res,
 	const struct dc_link_settings *link_setting,
 	bool skip_video_pattern);

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h+2−1

@@ -268,7 +268,8 @@ struct hpo_dp_link_encoder_funcs { · 267 unmodified lines
268		268
269	void (enable_link_phy)(struct hpo_dp_link_encoder enc,	269	void (enable_link_phy)(struct hpo_dp_link_encoder enc,
270	const struct dc_link_settings *link_settings,	270	const struct dc_link_settings *link_settings,
271	enum transmitter transmitter);	271	enum transmitter transmitter,
		272	enum hpd_source_id hpd_source);
272		273
273	void (disable_link_phy)(struct hpo_dp_link_encoder link_enc,	274	void (disable_link_phy)(struct hpo_dp_link_encoder link_enc,
274	enum signal_type signal);	275	enum signal_type signal);

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h+8−2

 void dp_enable_link_phy(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	enum signal_type signal,
 	enum clock_source_id clock_source,
 	const struct dc_link_settings *link_settings);
 bool edp_receiver_ready_T9(struct dc_link *link);
 bool edp_receiver_ready_T7(struct dc_link *link);
-void dp_disable_link_phy(struct dc_link *link, enum signal_type signal);
+void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_res,
+		enum signal_type signal);
-void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal);
+void dp_disable_link_phy_mst(struct dc_link *link, const struct link_resource *link_res,
+		enum signal_type signal);
 bool dp_set_hw_training_pattern(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	enum dc_dp_training_pattern pattern,
 	uint32_t offset);
 void dp_set_hw_lane_settings(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	const struct link_training_settings *link_settings,
 	uint32_t offset);
 void dp_set_hw_test_pattern(
 	struct dc_link *link,
+	const struct link_resource *link_res,
 	enum dp_test_pattern test_pattern,
 	uint8_t *custom_pattern,
 	uint32_t custom_pattern_size);

drivers/gpu/drm/amd/display/dc/inc/resource.h+4−2

 int get_num_odm_splits(struct pipe_ctx *pipe);
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-struct hpo_dp_link_encoder *resource_get_unused_hpo_dp_link_encoder(
+struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
-		const struct resource_pool *pool);
+		const struct resource_context *res_ctx,
+		const struct resource_pool *pool,
+		const struct dc_link *link);
 #endif
 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h+2−2

@@ -46,10 +46,10 @@ · 45 unmodified lines
46		46
47	/* Firmware versioning. */	47	/* Firmware versioning. */
48	#ifdef DMUB_EXPOSE_VERSION	48	#ifdef DMUB_EXPOSE_VERSION
49	#define DMUB_FW_VERSION_GIT_HASH 0xc99a4517	49	#define DMUB_FW_VERSION_GIT_HASH 0xbaf06b95
50	#define DMUB_FW_VERSION_MAJOR 0	50	#define DMUB_FW_VERSION_MAJOR 0
51	#define DMUB_FW_VERSION_MINOR 0	51	#define DMUB_FW_VERSION_MINOR 0
52	#define DMUB_FW_VERSION_REVISION 97	52	#define DMUB_FW_VERSION_REVISION 98
53	#define DMUB_FW_VERSION_TEST 0	53	#define DMUB_FW_VERSION_TEST 0
54	#define DMUB_FW_VERSION_VBIOS 0	54	#define DMUB_FW_VERSION_VBIOS 0
55	#define DMUB_FW_VERSION_HOTFIX 0	55	#define DMUB_FW_VERSION_HOTFIX 0

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c+2−2

@@ -852,7 +852,7 @@ bool dmub_srv_should_detect(struct dmub_srv *dmub) · 851 unmodified lines
852		852
853	enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)	853	enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)
854	{	854	{
855	if (!dmub->hw_init \|\| dmub->hw_funcs.clear_inbox0_ack_register)	855	if (!dmub->hw_init \|\| !dmub->hw_funcs.clear_inbox0_ack_register)
856	return DMUB_STATUS_INVALID;	856	return DMUB_STATUS_INVALID;
857		857
858	dmub->hw_funcs.clear_inbox0_ack_register(dmub);	858	dmub->hw_funcs.clear_inbox0_ack_register(dmub);
@@ -878,7 +878,7 @@ enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t ti · 19 unmodified lines
878	enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,	878	enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,
879	union dmub_inbox0_data_register data)	879	union dmub_inbox0_data_register data)
880	{	880	{
881	if (!dmub->hw_init \|\| dmub->hw_funcs.send_inbox0_cmd)	881	if (!dmub->hw_init \|\| !dmub->hw_funcs.send_inbox0_cmd)
882	return DMUB_STATUS_INVALID;	882	return DMUB_STATUS_INVALID;
883		883
884	dmub->hw_funcs.send_inbox0_cmd(dmub, data);	884	dmub->hw_funcs.send_inbox0_cmd(dmub, data);

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_offset.h+0−2

@@ -20753,8 +20753,6 @@ · 20752 unmodified lines
20753		20753
20754	// addressBlock: nbio_nbif0_gdc_GDCDEC	20754	// addressBlock: nbio_nbif0_gdc_GDCDEC
20755	// base address: 0xd0000000	20755	// base address: 0xd0000000
20756	#define regGDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL 0x2ffc0eda
20757	#define regGDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL_BASE_IDX 5
20758	#define regGDC1_NGDC_SDP_PORT_CTRL 0x2ffc0ee2	20756	#define regGDC1_NGDC_SDP_PORT_CTRL 0x2ffc0ee2
20759	#define regGDC1_NGDC_SDP_PORT_CTRL_BASE_IDX 5	20757	#define regGDC1_NGDC_SDP_PORT_CTRL_BASE_IDX 5
20760	#define regGDC1_SHUB_REGS_IF_CTL 0x2ffc0ee3	20758	#define regGDC1_SHUB_REGS_IF_CTL 0x2ffc0ee3

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h+0−12

@@ -1,4 +1,3 @@
1
2	/*	1	/*
3	* Copyright (C) 2020 Advanced Micro Devices, Inc.	2	* Copyright (C) 2020 Advanced Micro Devices, Inc.
4	*	3	*
@@ -108541,17 +108540,6 @@ · 108536 unmodified lines
108541		108540
108542		108541
108543	// addressBlock: nbio_nbif0_gdc_GDCDEC	108542	// addressBlock: nbio_nbif0_gdc_GDCDEC
108544	//GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL
108545	#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN0_FAST_WRITE_RESPONSE_EN__SHIFT 0x0
108546	#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN1_FAST_WRITE_RESPONSE_EN__SHIFT 0x1
108547	#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN2_FAST_WRITE_RESPONSE_EN__SHIFT 0x2
108548	#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN3_FAST_WRITE_RESPONSE_EN__SHIFT 0x3
108549	#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__FWR_NORMAL_ARB_MODE__SHIFT 0x10
108550	#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN0_FAST_WRITE_RESPONSE_EN_MASK 0x00000001L
108551	#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN1_FAST_WRITE_RESPONSE_EN_MASK 0x00000002L
108552	#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN2_FAST_WRITE_RESPONSE_EN_MASK 0x00000004L
108553	#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN3_FAST_WRITE_RESPONSE_EN_MASK 0x00000008L
108554	#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__FWR_NORMAL_ARB_MODE_MASK 0x00010000L
108555	//GDC1_NGDC_SDP_PORT_CTRL	108543	//GDC1_NGDC_SDP_PORT_CTRL
108556	#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0	108544	#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
108557	#define GDC1_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT 0xf	108545	#define GDC1_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT 0xf

drivers/gpu/drm/amd/include/discovery.h+49−0

@@ -143,6 +143,55 @@ struct gc_info_v1_0 { · 142 unmodified lines
143	uint32_t gc_num_gl2a;	143	uint32_t gc_num_gl2a;
144	};	144	};
145		145
		146	struct gc_info_v1_1 {
		147	struct gpu_info_header header;
		148
		149	uint32_t gc_num_se;
		150	uint32_t gc_num_wgp0_per_sa;
		151	uint32_t gc_num_wgp1_per_sa;
		152	uint32_t gc_num_rb_per_se;
		153	uint32_t gc_num_gl2c;
		154	uint32_t gc_num_gprs;
		155	uint32_t gc_num_max_gs_thds;
		156	uint32_t gc_gs_table_depth;
		157	uint32_t gc_gsprim_buff_depth;
		158	uint32_t gc_parameter_cache_depth;
		159	uint32_t gc_double_offchip_lds_buffer;
		160	uint32_t gc_wave_size;
		161	uint32_t gc_max_waves_per_simd;
		162	uint32_t gc_max_scratch_slots_per_cu;
		163	uint32_t gc_lds_size;
		164	uint32_t gc_num_sc_per_se;
		165	uint32_t gc_num_sa_per_se;
		166	uint32_t gc_num_packer_per_sc;
		167	uint32_t gc_num_gl2a;
		168	uint32_t gc_num_tcp_per_sa;
		169	uint32_t gc_num_sdp_interface;
		170	uint32_t gc_num_tcps;
		171	};
		172
		173	struct gc_info_v2_0 {
		174	struct gpu_info_header header;
		175
		176	uint32_t gc_num_se;
		177	uint32_t gc_num_cu_per_sh;
		178	uint32_t gc_num_sh_per_se;
		179	uint32_t gc_num_rb_per_se;
		180	uint32_t gc_num_tccs;
		181	uint32_t gc_num_gprs;
		182	uint32_t gc_num_max_gs_thds;
		183	uint32_t gc_gs_table_depth;
		184	uint32_t gc_gsprim_buff_depth;
		185	uint32_t gc_parameter_cache_depth;
		186	uint32_t gc_double_offchip_lds_buffer;
		187	uint32_t gc_wave_size;
		188	uint32_t gc_max_waves_per_simd;
		189	uint32_t gc_max_scratch_slots_per_cu;
		190	uint32_t gc_lds_size;
		191	uint32_t gc_num_sc_per_se;
		192	uint32_t gc_num_packer_per_sc;
		193	};
		194
146	typedef struct harvest_info_header {	195	typedef struct harvest_info_header {
147	uint32_t signature; /* Table Signature */	196	uint32_t signature; /* Table Signature */
148	uint32_t version; /* Table Version */	197	uint32_t version; /* Table Version */

drivers/gpu/drm/amd/pm/amdgpu_pm.c+8−1

 	} else if (DEVICE_ATTR_IS(unique_id)) {
 		if (asic_type != CHIP_VEGA10 &&
 		    asic_type != CHIP_VEGA20 &&
-		    asic_type != CHIP_ARCTURUS)
+		    asic_type != CHIP_ARCTURUS &&
+		    asic_type != CHIP_ALDEBARAN)
 			*states = ATTR_STATE_UNSUPPORTED;
 	} else if (DEVICE_ATTR_IS(pp_features)) {
 		if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
 		}
 	}
+	/* setting should not be allowed from VF */
+	if (amdgpu_sriov_vf(adev)) {
+		dev_attr->attr.mode &= ~S_IWUGO;
+		dev_attr->store = NULL;
+	}
 #undef DEVICE_ATTR_IS
 	return 0;

drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h+3−1

@@ -102,7 +102,9 @@ · 101 unmodified lines
102		102
103	#define PPSMC_MSG_GfxDriverResetRecovery 0x42	103	#define PPSMC_MSG_GfxDriverResetRecovery 0x42
104	#define PPSMC_MSG_BoardPowerCalibration 0x43	104	#define PPSMC_MSG_BoardPowerCalibration 0x43
105	#define PPSMC_Message_Count 0x44	105	#define PPSMC_MSG_HeavySBR 0x45
		106	#define PPSMC_Message_Count 0x46
		107
106		108
107	//PPSMC Reset Types	109	//PPSMC Reset Types
108	#define PPSMC_RESET_TYPE_WARM_RESET 0x00	110	#define PPSMC_RESET_TYPE_WARM_RESET 0x00

drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h+3−3

@@ -1257,9 +1257,9 @@ struct pptable_funcs { · 1256 unmodified lines
1257	int (set_fine_grain_gfx_freq_parameters)(struct smu_context smu);	1257	int (set_fine_grain_gfx_freq_parameters)(struct smu_context smu);
1258		1258
1259	/**	1259	/**
1260	* @set_light_sbr: Set light sbr mode for the SMU.	1260	* @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR.
1261	*/	1261	*/
1262	int (set_light_sbr)(struct smu_context smu, bool enable);	1262	int (smu_handle_passthrough_sbr)(struct smu_context smu, bool enable);
1263		1263
1264	/**	1264	/**
1265	* @wait_for_event: Wait for events from SMU.	1265	* @wait_for_event: Wait for events from SMU.
@@ -1415,7 +1415,7 @@ int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); · 149 unmodified lines
1415		1415
1416	int smu_get_status_gfxoff(struct amdgpu_device adev, uint32_t value);	1416	int smu_get_status_gfxoff(struct amdgpu_device adev, uint32_t value);
1417		1417
1418	int smu_set_light_sbr(struct smu_context *smu, bool enable);	1418	int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);
1419		1419
1420	int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,	1420	int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
1421	uint64_t event_arg);	1421	uint64_t event_arg);

drivers/gpu/drm/amd/pm/inc/smu_types.h+2−1

@@ -229,7 +229,8 @@ · 228 unmodified lines
229	__SMU_DUMMY_MAP(BoardPowerCalibration), \	229	__SMU_DUMMY_MAP(BoardPowerCalibration), \
230	__SMU_DUMMY_MAP(RequestGfxclk), \	230	__SMU_DUMMY_MAP(RequestGfxclk), \
231	__SMU_DUMMY_MAP(ForceGfxVid), \	231	__SMU_DUMMY_MAP(ForceGfxVid), \
232	__SMU_DUMMY_MAP(UnforceGfxVid),	232	__SMU_DUMMY_MAP(UnforceGfxVid), \
		233	__SMU_DUMMY_MAP(HeavySBR),
233		234
234	#undef __SMU_DUMMY_MAP	235	#undef __SMU_DUMMY_MAP
235	#define __SMU_DUMMY_MAP(type) SMU_MSG_##type	236	#define __SMU_DUMMY_MAP(type) SMU_MSG_##type

drivers/gpu/drm/amd/pm/inc/smu_v11_0.h+1−1

@@ -312,7 +312,7 @@ int smu_v11_0_deep_sleep_control(struct smu_context *smu, · 311 unmodified lines
312		312
313	void smu_v11_0_interrupt_work(struct smu_context *smu);	313	void smu_v11_0_interrupt_work(struct smu_context *smu);
314		314
315	int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable);	315	int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
316		316
317	int smu_v11_0_restore_user_od_settings(struct smu_context *smu);	317	int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
318		318

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c+5−8

 	smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
-	/* skip CGPG when in S0ix */
+	smu_set_gfx_cgpg(&adev->smu, false);
-	if (smu->is_apu && !adev->in_s0ix)
-		smu_set_gfx_cgpg(&adev->smu, false);
 	return 0;
 }
 		return ret;
 	}
-	if (smu->is_apu)
+	smu_set_gfx_cgpg(&adev->smu, true);
-		smu_set_gfx_cgpg(&adev->smu, true);
 	smu->disable_uclk_switch = 0;
 	return ret;
 }
-int smu_set_light_sbr(struct smu_context *smu, bool enable)
+int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
 {
 	int ret = 0;
 	mutex_lock(&smu->mutex);
-	if (smu->ppt_funcs->set_light_sbr)
+	if (smu->ppt_funcs->smu_handle_passthrough_sbr)
-		ret = smu->ppt_funcs->set_light_sbr(smu, enable);
+		ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
 	mutex_unlock(&smu->mutex);
 	return ret;

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c+1−1

@@ -2472,7 +2472,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = { · 2471 unmodified lines
2472	.deep_sleep_control = smu_v11_0_deep_sleep_control,	2472	.deep_sleep_control = smu_v11_0_deep_sleep_control,
2473	.get_fan_parameters = arcturus_get_fan_parameters,	2473	.get_fan_parameters = arcturus_get_fan_parameters,
2474	.interrupt_work = smu_v11_0_interrupt_work,	2474	.interrupt_work = smu_v11_0_interrupt_work,
2475	.set_light_sbr = smu_v11_0_set_light_sbr,	2475	.smu_handle_passthrough_sbr = smu_v11_0_handle_passthrough_sbr,
2476	.set_mp1_state = smu_cmn_set_mp1_state,	2476	.set_mp1_state = smu_cmn_set_mp1_state,
2477	};	2477	};
2478		2478

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c+1−1

@@ -1724,7 +1724,7 @@ int smu_v11_0_mode1_reset(struct smu_context *smu) · 1723 unmodified lines
1724	return ret;	1724	return ret;
1725	}	1725	}
1726		1726
1727	int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable)	1727	int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1728	{	1728	{
1729	int ret = 0;	1729	int ret = 0;
1730		1730

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c+2−1

@@ -120,7 +120,8 @@ int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate) · 119 unmodified lines
120		120
121	int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)	121	int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
122	{	122	{
123	if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))	123	/* Until now the SMU12 only implemented for Renoir series so here neen't do APU check. */
		124	if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) \|\| smu->adev->in_s0ix)
124	return 0;	125	return 0;
125		126
126	return smu_cmn_send_smc_msg_with_param(smu,	127	return smu_cmn_send_smc_msg_with_param(smu,

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c+13−2

 	MSG_MAP(SetUclkDpmMode,			     PPSMC_MSG_SetUclkDpmMode,			0),
 	MSG_MAP(GfxDriverResetRecovery,		     PPSMC_MSG_GfxDriverResetRecovery,		0),
 	MSG_MAP(BoardPowerCalibration,		     PPSMC_MSG_BoardPowerCalibration,		0),
+	MSG_MAP(HeavySBR,                            PPSMC_MSG_HeavySBR,                        0),
 };
 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
 	mutex_unlock(&smu->metrics_lock);
 	adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
-	sprintf(adev->serial, "%016llx", adev->unique_id);
+	if (adev->serial[0] == '\0')
+		sprintf(adev->serial, "%016llx", adev->unique_id);
 }
 static bool aldebaran_is_baco_supported(struct smu_context *smu)
 {
 	return smu_cmn_send_smc_msg_with_param(smu,
 					       SMU_MSG_GmiPwrDnControl,
-					       en ? 1 : 0,
+					       en ? 0 : 1,
 					       NULL);
 }
 	return ret;
 }
+static int aldebaran_smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
+{
+	int ret = 0;
+	ret =  smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_HeavySBR, enable ? 1 : 0, NULL);
+	return ret;
+}
 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
 {
 #if 0
 	.get_gpu_metrics = aldebaran_get_gpu_metrics,
 	.mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
 	.mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
+	.smu_handle_passthrough_sbr = aldebaran_smu_handle_passthrough_sbr,
 	.mode1_reset = aldebaran_mode1_reset,
 	.set_mp1_state = aldebaran_set_mp1_state,
 	.mode2_reset = aldebaran_mode2_reset,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c+10−5

 	if (smu->is_apu)
 		adev->pm.fw_version = smu_version;
-	switch (smu->adev->ip_versions[MP1_HWIP][0]) {
+	switch (adev->ip_versions[MP1_HWIP][0]) {
 	case IP_VERSION(13, 0, 2):
 		smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
 		break;
 		smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
 		break;
 	default:
-		dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
+		dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
-			smu->adev->ip_versions[MP1_HWIP][0]);
+			adev->ip_versions[MP1_HWIP][0]);
 		smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
 		break;
 	}
+	/* only for dGPU w/ SMU13*/
+	if (adev->pm.fw)
+		dev_dbg(adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
+			 smu_version, smu_major, smu_minor, smu_debug);
 	/*
 	 * 1. if_version mismatch is not critical as our fw is designed
 	 * to be backward compatible.
 	 * of halt driver loading.
 	 */
 	if (if_version != smu->smc_driver_if_version) {
-		dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
+		dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 			 "smu fw version = 0x%08x (%d.%d.%d)\n",
 			 smu->smc_driver_if_version, if_version,
 			 smu_version, smu_major, smu_minor, smu_debug);
-		dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
+		dev_warn(adev->dev, "SMU driver if version not matched\n");
 	}
 	return ret;